orbit_boot_800.c 26 KB

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  1. /**
  2. ******************************************************************************
  3. * @file orbit_boot_800.c
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 07/20/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #include <regconfig.h.sim_PI.h>
  21. #include <regconfig.h.sim_PHY.h>
  22. #include <sys.h>
  23. #include <clkgen_ctrl_macro.h>
  24. #include <comdef.h>
  25. #include <timer.h>
  26. void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
  27. {
  28. u32 tmp = 0;
  29. int count = 0;
  30. int i = 0;
  31. //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
  32. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  33. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
  34. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
  35. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);
  36. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);
  37. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
  38. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
  39. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
  40. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
  41. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
  42. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
  43. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
  44. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
  45. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
  46. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  47. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
  48. // Memory frequency should be changed below 50MHz somewhere before here
  49. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
  50. udelay(300);
  51. //cdns_dll_rst_deassert()
  52. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  53. //printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  54. while((tmp & 0x80000000) != 0x80000000) {
  55. udelay(1);
  56. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  57. }
  58. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
  59. // tINIT0 is controlled by System
  60. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
  61. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  62. udelay(300);
  63. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
  64. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  65. udelay(3000);
  66. // Drive CKE high
  67. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
  68. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  69. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  70. udelay(4);
  71. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
  72. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
  73. // Write down RCLK-related CRs
  74. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
  75. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  76. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  77. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  78. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  79. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  80. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  81. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
  82. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
  83. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);
  84. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
  85. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
  86. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
  87. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  88. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  89. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00110000);
  90. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  91. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);
  92. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00080c00);
  93. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0040007);
  94. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  95. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);
  96. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  97. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  98. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  99. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
  100. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  101. //apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);
  102. //apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
  103. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);
  104. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
  105. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
  106. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  107. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  108. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  109. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  110. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  111. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  112. //while(1)
  113. {
  114. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  115. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  116. //printf("write 05\r\n");
  117. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  118. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  119. //printf("write 00\r\n");
  120. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  121. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  122. //printf("write 31\r\n");
  123. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0000);
  124. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  125. //printf("write 66\r\n");
  126. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160000);
  127. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  128. //printf("write 00****\r\n");
  129. }
  130. /*read MR4 reg*/
  131. //apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  132. //apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  133. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
  134. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  135. // Waits tZQCAL (1 us)
  136. udelay(4);
  137. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
  138. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  139. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
  140. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  141. // Waits tZQCAL (1 us)
  142. udelay(4);
  143. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
  144. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  145. #if 0
  146. //while(1)
  147. {
  148. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  149. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  150. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  151. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  152. }
  153. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  154. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  155. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  156. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  157. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0000);
  158. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  159. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  160. printf("ddr ctrl 0xc = 0x%x\n", tmp);
  161. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  162. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  163. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  164. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  165. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  166. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  167. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  168. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  169. #endif
  170. #if 0
  171. for(i = 0; i< 363; i++)
  172. {
  173. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 +i) << 2));
  174. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((2048 +i) << 2)), tmp);
  175. }
  176. for(i = 0; i< 1931; i++)
  177. {
  178. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 +i) << 2));
  179. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((4096 +i) << 2)), tmp);
  180. }
  181. tmp = apb_read(OMC_APB_BASE_ADDR + 0x0);
  182. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x0), tmp);
  183. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf00);
  184. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf00), tmp);
  185. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf04);
  186. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf04), tmp);
  187. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf10);
  188. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf10), tmp);
  189. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf14);
  190. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf14), tmp);
  191. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf18);
  192. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf18), tmp);
  193. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf30);
  194. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf30), tmp);
  195. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf34);
  196. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf34), tmp);
  197. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x110);
  198. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x110), tmp);
  199. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x114);
  200. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x114), tmp);
  201. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10c);
  202. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10c), tmp);
  203. tmp = apb_read(OMC_APB_BASE_ADDR + 0x11c);
  204. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x11c), tmp);
  205. tmp = apb_read(OMC_APB_BASE_ADDR + 0x500);
  206. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x500), tmp);
  207. tmp = apb_read(OMC_APB_BASE_ADDR + 0x514);
  208. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x514), tmp);
  209. tmp = apb_read(OMC_APB_BASE_ADDR + 0x6a8);
  210. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x6a8), tmp);
  211. tmp = apb_read(OMC_APB_BASE_ADDR + 0xea8);
  212. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xea8), tmp);
  213. tmp = // Mread frequency should be changed below 50MHz somewhere before here
  214. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  215. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  216. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  217. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  218. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  219. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  220. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  221. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  222. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  223. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  224. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  225. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  226. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  227. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  228. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  229. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  230. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  231. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  232. tmp = apb_read(OMC_APB_BASE_ADDR + 0x600);
  233. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x600), tmp);
  234. tmp = apb_read(OMC_APB_BASE_ADDR + 0x604);
  235. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x604), tmp);
  236. for(i = 0x600; i < 0x6ac;)
  237. {
  238. tmp = apb_read(OMC_APB_BASE_ADDR + i);
  239. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + i),tmp);
  240. i +=4;
  241. }
  242. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  243. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  244. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  245. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  246. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  247. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  248. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  249. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  250. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  251. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  252. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  253. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  254. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  255. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  256. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  257. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  258. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  259. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  260. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  261. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  262. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  263. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  264. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  265. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  266. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  267. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  268. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  269. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  270. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  271. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  272. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  273. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  274. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  275. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  276. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  277. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  278. #endif
  279. #if 1
  280. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  281. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  282. while((tmp & 0x00000002) != 0x00000002) {
  283. udelay(1);
  284. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  285. }
  286. //------ training start ------
  287. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  288. while((tmp & 0x00000002) != 0x00000000) {
  289. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  290. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  291. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  292. case 0:
  293. if(ddr_num == 0) //ddrc_clock=12.5M
  294. {
  295. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  296. udelay(100);
  297. }
  298. else
  299. {
  300. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  301. udelay(100);
  302. }
  303. break;
  304. case 1:
  305. if(ddr_num == 0) //ddrc_clock=200M
  306. {
  307. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_;
  308. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  309. udelay(100);
  310. }
  311. else
  312. {
  313. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_;
  314. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  315. udelay(100);
  316. }
  317. break;
  318. case 2:
  319. if(ddr_num == 0) //ddrc_clock=400M
  320. {
  321. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  322. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  323. udelay(100);
  324. }
  325. else
  326. {
  327. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
  328. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  329. udelay(100);
  330. }
  331. break;
  332. default:
  333. break;
  334. }
  335. //printf("tmp = 0x%x\r\n", (u32)tmp);
  336. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  337. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  338. #if 0
  339. if(count == 4)
  340. {
  341. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  342. printf("start phy %d = 0x%x\r\n", i,(u32)tmp);
  343. udelay(100);
  344. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  345. printf("post phy %d = 0x%x\r\n", i,(u32)tmp);
  346. }
  347. #endif
  348. count++;
  349. //printf("count = 0x%x\r\n", count);
  350. while((tmp & 0x00000001) != 0x00000000) {
  351. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  352. }
  353. #if 0
  354. if(count == 5)
  355. {
  356. for(i = 0; i < 1913; i++)
  357. {
  358. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  359. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  360. }
  361. for(i = 0; i < 362; i++)
  362. {
  363. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 + i) << 2));
  364. printf("pi phy %d = 0x%x\r\n", i,(u32)tmp);
  365. }
  366. }
  367. #endif
  368. }
  369. udelay(1);
  370. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  371. }
  372. #if 0
  373. //if(count == 5)
  374. {
  375. for(i = 0; i < 1913; i++)
  376. {
  377. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  378. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  379. }
  380. }
  381. #endif
  382. //------ training end --------
  383. //cdns_pi_end( 3);
  384. //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);//`DENALI_PI_11_DATA
  385. //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp & ~4'hF | 4'h3);//set PI_CS_MAP=3
  386. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA //read PI_INT_STATUS
  387. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  388. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  389. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  390. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), tmp & 0xF8000000);
  391. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  392. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  393. DEBUG_INFO("PI_46_DATA = 0x%x\r\n", tmp);
  394. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<24) | (0x3 <<24));
  395. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  396. DEBUG_INFO("PI_33_DATA = 0x%x\r\n", tmp);
  397. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<24));
  398. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  399. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  400. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<16));
  401. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  402. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  403. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<24));
  404. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  405. DEBUG_INFO("PI_45_DATA = 0x%x\r\n", tmp);
  406. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), tmp | 0x1);
  407. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  408. DEBUG_INFO("PI_146_DATA = 0x%x\r\n", tmp);
  409. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<24));
  410. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  411. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  412. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<8));
  413. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  414. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  415. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<24));
  416. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  417. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | (0x1 <<8));
  418. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  419. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  420. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<16) | (0x3 <<16));
  421. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  422. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<16));
  423. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  424. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<16));
  425. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  426. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<24));
  427. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  428. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | 0x1);
  429. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  430. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<16));
  431. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  432. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | 0x3);
  433. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  434. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<16));
  435. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  436. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), tmp | (0x3 <<24));
  437. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  438. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), tmp | (0x3 <<24));
  439. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  440. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), tmp | (0x3 <<24));
  441. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  442. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp | (0x1 <<8));
  443. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  444. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  445. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp & ~(0xF <<8) | (0x3 <<8));
  446. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  447. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), tmp & ~(0x1<<8));
  448. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  449. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<16));
  450. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  451. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<24));
  452. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  453. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), tmp | (0x1 <<8));
  454. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  455. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), tmp | (0x3 <<8));
  456. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  457. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), tmp | (0x3 <<8));
  458. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  459. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
  460. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
  461. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030f11);
  462. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x060c0506);
  463. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x3022088f);
  464. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x20190820);
  465. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x21190e08);
  466. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001a0000);
  467. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200c0c08);
  468. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x2131fa06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
  469. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00e61866);
  470. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x507000e0);
  471. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  472. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00082110);
  473. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x1033240a);
  474. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00001310);
  475. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  476. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00480018);
  477. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  478. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x0600040a);//trdcslat=0x8->0x6;trddata_en=0x8->0xa
  479. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000404);//twrcslat=0x2->0x1;twrlat=0x4;twrdata=0x4
  480. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040d);
  481. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002920);
  482. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  483. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  484. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  485. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20290c00);
  486. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  487. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010026);
  488. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  489. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020012);
  490. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  491. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  492. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  493. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
  494. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  495. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  496. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  497. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
  498. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  499. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  500. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  501. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  502. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  503. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
  504. apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
  505. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
  506. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
  507. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
  508. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
  509. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  510. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
  511. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
  512. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
  513. #endif
  514. }
  515. //cdns_per_tr_longcnt_set( 16);
  516. // Initialization done