orbit_boot_800.c 25 KB

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  1. #include <regconfig.h.sim_PI.h>
  2. #include <regconfig.h.sim_PHY.h>
  3. #include <sys.h>
  4. #include <clkgen_ctrl_macro.h>
  5. #include <comdef.h>
  6. #include <timer.h>
  7. void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
  8. {
  9. u32 tmp = 0;
  10. int count = 0;
  11. int i = 0;
  12. //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
  13. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  14. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
  15. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
  16. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);
  17. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);
  18. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
  19. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
  20. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
  21. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
  22. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
  23. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
  24. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
  25. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
  26. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
  27. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  28. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
  29. // Memory frequency should be changed below 50MHz somewhere before here
  30. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
  31. udelay(300);
  32. //cdns_dll_rst_deassert()
  33. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  34. //printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  35. while((tmp & 0x80000000) != 0x80000000) {
  36. udelay(1);
  37. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  38. }
  39. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
  40. // tINIT0 is controlled by System
  41. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
  42. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  43. udelay(300);
  44. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
  45. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  46. udelay(3000);
  47. // Drive CKE high
  48. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
  49. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  50. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  51. udelay(4);
  52. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
  53. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
  54. // Write down RCLK-related CRs
  55. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
  56. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  57. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  58. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  59. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  60. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  61. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  62. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
  63. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
  64. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);
  65. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
  66. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
  67. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
  68. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  69. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  70. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00110000);
  71. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  72. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);
  73. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00080c00);
  74. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0040007);
  75. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  76. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);
  77. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  78. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  79. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  80. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
  81. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  82. //apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);
  83. //apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
  84. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);
  85. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
  86. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
  87. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  88. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  89. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  90. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  91. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  92. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  93. //while(1)
  94. {
  95. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  96. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  97. //printf("write 05\r\n");
  98. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  99. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  100. //printf("write 00\r\n");
  101. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  102. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  103. //printf("write 31\r\n");
  104. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0000);
  105. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  106. //printf("write 66\r\n");
  107. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160000);
  108. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  109. //printf("write 00****\r\n");
  110. }
  111. /*read MR4 reg*/
  112. //apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  113. //apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  114. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
  115. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  116. // Waits tZQCAL (1 us)
  117. udelay(4);
  118. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
  119. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  120. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
  121. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  122. // Waits tZQCAL (1 us)
  123. udelay(4);
  124. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
  125. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  126. #if 0
  127. //while(1)
  128. {
  129. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  130. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  131. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  132. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  133. }
  134. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  135. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  136. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  137. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  138. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0000);
  139. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  140. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  141. printf("ddr ctrl 0xc = 0x%x\n", tmp);
  142. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  143. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  144. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  145. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  146. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  147. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  148. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  149. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  150. #endif
  151. #if 0
  152. for(i = 0; i< 363; i++)
  153. {
  154. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 +i) << 2));
  155. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((2048 +i) << 2)), tmp);
  156. }
  157. for(i = 0; i< 1931; i++)
  158. {
  159. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 +i) << 2));
  160. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((4096 +i) << 2)), tmp);
  161. }
  162. tmp = apb_read(OMC_APB_BASE_ADDR + 0x0);
  163. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x0), tmp);
  164. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf00);
  165. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf00), tmp);
  166. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf04);
  167. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf04), tmp);
  168. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf10);
  169. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf10), tmp);
  170. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf14);
  171. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf14), tmp);
  172. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf18);
  173. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf18), tmp);
  174. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf30);
  175. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf30), tmp);
  176. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf34);
  177. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf34), tmp);
  178. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x110);
  179. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x110), tmp);
  180. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x114);
  181. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x114), tmp);
  182. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10c);
  183. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10c), tmp);
  184. tmp = apb_read(OMC_APB_BASE_ADDR + 0x11c);
  185. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x11c), tmp);
  186. tmp = apb_read(OMC_APB_BASE_ADDR + 0x500);
  187. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x500), tmp);
  188. tmp = apb_read(OMC_APB_BASE_ADDR + 0x514);
  189. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x514), tmp);
  190. tmp = apb_read(OMC_APB_BASE_ADDR + 0x6a8);
  191. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x6a8), tmp);
  192. tmp = apb_read(OMC_APB_BASE_ADDR + 0xea8);
  193. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xea8), tmp);
  194. tmp = // Mread frequency should be changed below 50MHz somewhere before here
  195. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  196. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  197. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  198. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  199. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  200. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  201. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  202. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  203. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  204. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  205. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  206. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  207. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  208. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  209. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  210. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  211. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  212. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  213. tmp = apb_read(OMC_APB_BASE_ADDR + 0x600);
  214. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x600), tmp);
  215. tmp = apb_read(OMC_APB_BASE_ADDR + 0x604);
  216. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x604), tmp);
  217. for(i = 0x600; i < 0x6ac;)
  218. {
  219. tmp = apb_read(OMC_APB_BASE_ADDR + i);
  220. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + i),tmp);
  221. i +=4;
  222. }
  223. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  224. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  225. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  226. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  227. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  228. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  229. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  230. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  231. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  232. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  233. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  234. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  235. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  236. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  237. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  238. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  239. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  240. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  241. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  242. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  243. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  244. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  245. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  246. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  247. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  248. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  249. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  250. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  251. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  252. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  253. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  254. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  255. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  256. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  257. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  258. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  259. #endif
  260. #if 1
  261. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  262. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  263. while((tmp & 0x00000002) != 0x00000002) {
  264. udelay(1);
  265. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  266. }
  267. //------ training start ------
  268. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  269. while((tmp & 0x00000002) != 0x00000000) {
  270. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  271. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  272. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  273. case 0:
  274. if(ddr_num == 0) //ddrc_clock=12.5M
  275. {
  276. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  277. udelay(100);
  278. }
  279. else
  280. {
  281. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  282. udelay(100);
  283. }
  284. break;
  285. case 1:
  286. if(ddr_num == 0) //ddrc_clock=200M
  287. {
  288. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_;
  289. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  290. udelay(100);
  291. }
  292. else
  293. {
  294. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_;
  295. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  296. udelay(100);
  297. }
  298. break;
  299. case 2:
  300. if(ddr_num == 0) //ddrc_clock=400M
  301. {
  302. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  303. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  304. udelay(100);
  305. }
  306. else
  307. {
  308. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
  309. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  310. udelay(100);
  311. }
  312. break;
  313. default:
  314. break;
  315. }
  316. //printf("tmp = 0x%x\r\n", (u32)tmp);
  317. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  318. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  319. #if 0
  320. if(count == 4)
  321. {
  322. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  323. printf("start phy %d = 0x%x\r\n", i,(u32)tmp);
  324. udelay(100);
  325. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  326. printf("post phy %d = 0x%x\r\n", i,(u32)tmp);
  327. }
  328. #endif
  329. count++;
  330. //printf("count = 0x%x\r\n", count);
  331. while((tmp & 0x00000001) != 0x00000000) {
  332. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  333. }
  334. #if 0
  335. if(count == 5)
  336. {
  337. for(i = 0; i < 1913; i++)
  338. {
  339. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  340. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  341. }
  342. for(i = 0; i < 362; i++)
  343. {
  344. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 + i) << 2));
  345. printf("pi phy %d = 0x%x\r\n", i,(u32)tmp);
  346. }
  347. }
  348. #endif
  349. }
  350. udelay(1);
  351. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  352. }
  353. #if 0
  354. //if(count == 5)
  355. {
  356. for(i = 0; i < 1913; i++)
  357. {
  358. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  359. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  360. }
  361. }
  362. #endif
  363. //------ training end --------
  364. //cdns_pi_end( 3);
  365. //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);//`DENALI_PI_11_DATA
  366. //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp & ~4'hF | 4'h3);//set PI_CS_MAP=3
  367. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA //read PI_INT_STATUS
  368. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  369. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  370. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  371. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), tmp & 0xF8000000);
  372. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  373. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  374. DEBUG_INFO("PI_46_DATA = 0x%x\r\n", tmp);
  375. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<24) | (0x3 <<24));
  376. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  377. DEBUG_INFO("PI_33_DATA = 0x%x\r\n", tmp);
  378. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<24));
  379. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  380. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  381. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<16));
  382. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  383. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  384. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<24));
  385. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  386. DEBUG_INFO("PI_45_DATA = 0x%x\r\n", tmp);
  387. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), tmp | 0x1);
  388. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  389. DEBUG_INFO("PI_146_DATA = 0x%x\r\n", tmp);
  390. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<24));
  391. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  392. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  393. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<8));
  394. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  395. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  396. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<24));
  397. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  398. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | (0x1 <<8));
  399. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  400. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  401. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<16) | (0x3 <<16));
  402. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  403. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<16));
  404. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  405. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<16));
  406. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  407. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<24));
  408. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  409. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | 0x1);
  410. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  411. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<16));
  412. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  413. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | 0x3);
  414. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  415. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<16));
  416. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  417. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), tmp | (0x3 <<24));
  418. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  419. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), tmp | (0x3 <<24));
  420. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  421. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), tmp | (0x3 <<24));
  422. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  423. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp | (0x1 <<8));
  424. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  425. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  426. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp & ~(0xF <<8) | (0x3 <<8));
  427. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  428. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), tmp & ~(0x1<<8));
  429. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  430. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<16));
  431. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  432. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<24));
  433. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  434. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), tmp | (0x1 <<8));
  435. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  436. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), tmp | (0x3 <<8));
  437. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  438. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), tmp | (0x3 <<8));
  439. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  440. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
  441. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
  442. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030f11);
  443. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x060c0506);
  444. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x3022088f);
  445. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x20190820);
  446. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x21190e08);
  447. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001a0000);
  448. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200c0c08);
  449. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x2131fa06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
  450. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00e61866);
  451. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x507000e0);
  452. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  453. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00082110);
  454. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x1033240a);
  455. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00001310);
  456. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  457. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00480018);
  458. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  459. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x0600040a);//trdcslat=0x8->0x6;trddata_en=0x8->0xa
  460. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000404);//twrcslat=0x2->0x1;twrlat=0x4;twrdata=0x4
  461. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040d);
  462. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002920);
  463. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  464. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  465. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  466. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20290c00);
  467. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  468. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010026);
  469. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  470. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020012);
  471. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  472. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  473. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  474. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
  475. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  476. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  477. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  478. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
  479. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  480. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  481. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  482. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  483. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  484. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
  485. apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
  486. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
  487. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
  488. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
  489. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
  490. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  491. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
  492. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
  493. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
  494. #endif
  495. }
  496. //cdns_per_tr_longcnt_set( 16);
  497. // Initialization done