sys.h 2.9 KB

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  1. #ifndef SYS_H_
  2. #define SYS_H_
  3. /*********************************** sys clock************************/
  4. #define E32_ADDR_REMAP_OFFSET 0
  5. #define U74_SYS_PORT_DDRC_BASE_ADDR 0x1000000000LL
  6. #define OMC_CFG0_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011000000LL)
  7. #define OMC_CFG1_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011010000LL)
  8. #define DDRPHY0_CSR_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011820000LL)
  9. #define DDRPHY1_CSR_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011830000LL)
  10. #define QSPI_CLK 100000000
  11. #define QSPI_REF_CLK 250000000
  12. #define TIMER_CLK_HZ 6250000
  13. #define DEFAULT_SD_BOOT_LOAD_BLOCK 1000
  14. #define DEFAULT_SPI_BOOT_START_ADDR 1
  15. #define DEFAULT_SPI_BOOT_SIZE_ADDR 0x0
  16. #define DEFAULT_SPI_BOOT_LOAD_PAGES 512
  17. // QSPI
  18. #define QSPI_BASE_ADDR 0x11860000
  19. //CADENCE QSPI AHB
  20. #define QSPI_BASE_AHB_ADDR 0x20000000
  21. // TIMER --WDT
  22. #define TIMER_BASE_ADDR 0x12480000
  23. // SDIO0
  24. #define SDIO0_BASE_ADDR 0x10000000
  25. // SDIO1
  26. #define SDIO1_BASE_ADDR 0x10010000
  27. // GPIO
  28. #define GPIO_BASE_ADDR 0x11910000///0xA9060000
  29. #define EZGPIO_FULLMUX_BASE_ADDR 0x11910000
  30. #define RSTGEN_BASE_ADDR 0x11840000
  31. #define CLKGEN_BASE_ADDR 0x11800000
  32. // CLKGEN
  33. #define VIC_CLKGEN_TOP_SV_BASE_ADDR 0x11800000///0xA9090000
  34. // RSTGEN
  35. #define VIC_RSTGEN_BASE_ADDR 0x11840000///0xA90A0000
  36. #define SYSCON_IOPAD_CTRL_BASE_ADDR 0x11858000
  37. // SYSCON
  38. #define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x11850000
  39. // HS-UART0
  40. #define UART0_HS_BASE_ADDR 0x11870000
  41. // HS-UART1
  42. #define UART1_HS_BASE_ADDR 0x11880000
  43. // UART2
  44. #define UART2_BASE_ADDR 0x12430000
  45. // UART3
  46. #define UART3_BASE_ADDR 0x12440000
  47. /*Reserved information:
  48. *second boot:64K 0x0 - 0xffff
  49. *ddr init:64K 0x10000 - 0x1ffff
  50. *uboot:1M 0x20000 - 0x11ffff
  51. *kernel:25M 0x120000 - 0x1a1ffff
  52. */
  53. /*Reserved information:
  54. *second boot:32K 0x0 - 0x7fff
  55. *ddr init:50K 0x8000 - 0x147ff
  56. *uboot:500K 0x14800 - 0x917ff
  57. *kernel:25M 0x130000 - 0x1a3ffff
  58. */
  59. #define UBOOT_EXEC_AT_NBDLA_2M 0
  60. #define UBOOT_EXEC_AT_SYS_PORT 0
  61. /*DDR bin file */
  62. #define DEFAULT_DDR_ADDR 0x18080000
  63. #define DEFAULT_DDR_OFFSET 0x100
  64. /*uboot bin file*/
  65. #if (UBOOT_EXEC_AT_NBDLA_2M == 1)
  66. #define DEFAULT_UBOOT_ADDR 0x19c00000
  67. #elif (UBOOT_EXEC_AT_SYS_PORT == 1)
  68. #define DEFAULT_UBOOT_ADDR 0x1000000000
  69. #else
  70. #define DEFAULT_UBOOT_ADDR 0x80000000
  71. #endif
  72. #define DEFAULT_UBOOT_OFFSET 0x400
  73. /*kernel image file*/
  74. #define DEFAULT_KERNEL_ADDR 0xa0000000
  75. #define DEFAULT_KERNEL_OFFSET 0x1200
  76. #define FLASH_SECONDBOOT_START_ADDR 0
  77. #define FLASH_SECONDBOOT_SIZE_LIMIT (64*1024)
  78. #define FLASH_DDRINIT_START_ADDR 0x10000
  79. #define FLASH_DDRINIT_SIZE_LIMIT (192*1024)
  80. #define FLASH_UBOOT_START_ADDR 0x40000
  81. #define FLASH_UBOOT_SIZE_LIMIT (896*1024)
  82. #define DEFAULT_UBOOT_LOAD_ADDR DEFAULT_UBOOT_ADDR
  83. #define DEFAULT_SECONDBOOT_LOAD_ADDR 0x180a8000 /*32k*/
  84. #define DEFAULT_DDRINIT_LOAD_ADDR 0x18000000 /*128K*/
  85. #endif