start.S 1.5 KB

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  1. // See LICENSE for license details.
  2. #include "encoding.h"
  3. #include "platform.h"
  4. #include "sys.h"
  5. /* This is defined in sifive/platform.h, but that can't be included from
  6. * assembly. */
  7. .section .init
  8. .globl _start
  9. _start:
  10. la t0, trap_entry
  11. csrw mtvec, t0
  12. csrwi mstatus, 0
  13. csrwi mie, 0
  14. // Allocate 4 KiB stack for each hart
  15. csrr t0, mhartid
  16. slli t0, t0, 12
  17. la sp, _sp
  18. sub sp, sp, t0
  19. li a1, NONSMP_HART;
  20. csrr a0, mhartid;
  21. bne a0, a1, .LbootOtherHart //other hart
  22. // Load data section
  23. la t0, _data_lma
  24. la t1, _data
  25. beq t0, t1, 2f
  26. la t2, _edata
  27. bgeu t1, t2, 2f
  28. 1:
  29. ld t3, 0(t0)
  30. sd t3, 0(t1)
  31. addi t0, t0, 8
  32. addi t1, t1, 8
  33. bltu t1, t2, 1b
  34. 2:
  35. /* Clear bss section */
  36. la t1, _bss_start
  37. la t2, _bss_end
  38. bgeu t1, t2, 4f
  39. 3:
  40. sd x0, 0(t1)
  41. addi t1, t1, 8
  42. blt t1, t2, 3b
  43. 4:
  44. /*only hart 0*/
  45. call BootMain
  46. j .enter_uboot
  47. .LbootOtherHart:
  48. #if 0 //no need to clear
  49. li s1, CLINT_CTRL_ADDR
  50. csrr a0, mhartid
  51. slli s2, a0, 2
  52. add s2, s2, s1
  53. sw zero, 0(s2)
  54. fence
  55. csrw mip, 0
  56. #endif
  57. # core 1 jumps to main_other_hart
  58. # Set MSIE bit to receive IPI
  59. li a2, MIP_MSIP
  60. csrw mie, a2
  61. .LwaitOtherHart:
  62. # Wait for an IPI to signal that its safe to boot
  63. // call second_hart
  64. wfi
  65. # Only start if MIP_MSIP is set
  66. csrr a2, mip
  67. andi a2, a2, MIP_MSIP
  68. beqz a2, .LwaitOtherHart
  69. li s1, CLINT_CTRL_ADDR
  70. csrr a0, mhartid
  71. slli s2, a0, 2
  72. add s2, s2, s1
  73. sw zero, 0(s2)
  74. fence
  75. csrw mip, 0
  76. li a2, NUM_CORES
  77. bltu a0, a2, .enter_uboot
  78. j .LwaitOtherHart
  79. .enter_uboot:
  80. li t0, DEFAULT_UBOOT_ADDR
  81. csrr a0, mhartid
  82. la a1, 0
  83. jr t0