uart.h 7.1 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file uart.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/24/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef _UART_H
  22. #define _UART_H
  23. #define UART_REG_ADDR_INTERVAL 4
  24. #define REG_THR 0x00 /* Transmitter holding reg. */
  25. #define REG_RDR 0x00 /* Receiver data reg. */
  26. #define REG_BRDL 0x00 /* Baud rate divisor (LSB) */
  27. #define REG_BRDH 0x01 /* Baud rate divisor (MSB) */
  28. #define REG_IER 0x01 /* Interrupt enable reg. */
  29. #define REG_IIR 0x02 /* Interrupt ID reg. */
  30. #define REG_FCR 0x02 /* FIFO control reg. */
  31. #define REG_LCR 0x03 /* Line control reg. */
  32. #define REG_MDC 0x04 /* Modem control reg. */
  33. #define REG_LSR 0x05 /* Line status reg. */
  34. #define REG_MSR 0x06 /* Modem status reg. */
  35. #define REG_DLF 0xC0 /* Divisor Latch Fraction */
  36. #define UART_USR 31
  37. #define UART_USR_BUSY (1 << 0) /* UART is busy (1) */
  38. #define UART_USR_Tx_FIFO_NFUL (1 << 1) /* Tx FIFO is not full (1) */
  39. #define UART_USR_Tx_FIFO_NEMP (1 << 2) /* Tx FIFO is empty (1) */
  40. #define UART_USR_Rx_FIFO_NHFL (1 << 3) /* Rx FIFO is not empty (1) */
  41. #define UART_USR_Rx_FIFO_NFUL (1 << 4) /* Rx FIFO is full (1) */
  42. /* equates for interrupt enable register */
  43. #define IER_RXRDY 0x01 /* receiver data ready */
  44. #define IER_TBE 0x02 /* transmit bit enable */
  45. #define IER_LSR 0x04 /* line status interrupts */
  46. #define IER_MSI 0x08 /* modem status interrupts */
  47. /* constants for line control register */
  48. #define LCR_CS5 0x00 /* 5 bits data size */
  49. #define LCR_CS6 0x01 /* 6 bits data size */
  50. #define LCR_CS7 0x02 /* 7 bits data size */
  51. #define LCR_CS8 0x03 /* 8 bits data size */
  52. #define LCR_2_STB 0x04 /* 2 stop bits */
  53. #define LCR_1_STB 0x00 /* 1 stop bit */
  54. #define LCR_PEN 0x08 /* parity enable */
  55. #define LCR_PDIS 0x00 /* parity disable */
  56. #define LCR_EPS 0x10 /* even parity select */
  57. #define LCR_SP 0x20 /* stick parity select */
  58. #define LCR_SBRK 0x40 /* break control bit */
  59. #define LCR_DLAB 0x80 /* divisor latch access enable */
  60. /* constants for line status register */
  61. #define LSR_RXRDY 0x01 /* receiver data available */
  62. #define LSR_OE 0x02 /* overrun error */
  63. #define LSR_PE 0x04 /* parity error */
  64. #define LSR_FE 0x08 /* framing error */
  65. #define LSR_BI 0x10 /* break interrupt */
  66. #define LSR_EOB_MASK 0x1E /* Error or Break mask */
  67. #define LSR_THRE 0x20 /* transmit holding register empty */
  68. #define LSR_TEMT 0x40 /* transmitter empty */
  69. /* equates for FIFO control register */
  70. #define FCR_FIFO 0x01 /* enable XMIT and RCVR FIFO */
  71. #define FCR_RCVRCLR 0x02 /* clear RCVR FIFO */
  72. #define FCR_XMITCLR 0x04 /* clear XMIT FIFO */
  73. /*
  74. * Per PC16550D (Literature Number: SNLS378B):
  75. *
  76. * RXRDY, Mode 0: When in the 16450 Mode (FCR0 = 0) or in
  77. * the FIFO Mode (FCR0 = 1, FCR3 = 0) and there is at least 1
  78. * character in the RCVR FIFO or RCVR holding register, the
  79. * RXRDY pin (29) will be low active. Once it is activated the
  80. * RXRDY pin will go inactive when there are no more charac-
  81. * ters in the FIFO or holding register.
  82. *
  83. * RXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when the
  84. * FCR3 = 1 and the trigger level or the timeout has been
  85. * reached, the RXRDY pin will go low active. Once it is acti-
  86. * vated it will go inactive when there are no more characters
  87. * in the FIFO or holding register.
  88. *
  89. * TXRDY, Mode 0: In the 16450 Mode (FCR0 = 0) or in the
  90. * FIFO Mode (FCR0 = 1, FCR3 = 0) and there are no charac-
  91. * ters in the XMIT FIFO or XMIT holding register, the TXRDY
  92. * pin (24) will be low active. Once it is activated the TXRDY
  93. * pin will go inactive after the first character is loaded into the
  94. * XMIT FIFO or holding register.
  95. *
  96. * TXRDY, Mode 1: In the FIFO Mode (FCR0 = 1) when
  97. * FCR3 = 1 and there are no characters in the XMIT FIFO, the
  98. * TXRDY pin will go low active. This pin will become inactive
  99. * when the XMIT FIFO is completely full.
  100. */
  101. #define FCR_MODE0 0x00 /* set receiver in mode 0 */
  102. #define FCR_MODE1 0x08 /* set receiver in mode 1 */
  103. /* RCVR FIFO interrupt levels: trigger interrupt with this bytes in FIFO */
  104. #define FCR_FIFO_1 0x00 /* 1 byte in RCVR FIFO */
  105. #define FCR_FIFO_4 0x40 /* 4 bytes in RCVR FIFO */
  106. #define FCR_FIFO_8 0x80 /* 8 bytes in RCVR FIFO */
  107. #define FCR_FIFO_14 0xC0 /* 14 bytes in RCVR FIFO */
  108. /*
  109. * UART NS16750 supports 64 bytes FIFO, which can be enabled
  110. * via the FCR register
  111. */
  112. #define FCR_FIFO_64 0x20 /* Enable 64 bytes FIFO */
  113. /* constants for line control register */
  114. #define LCR_CS5 0x00 /* 5 bits data size */
  115. #define LCR_CS6 0x01 /* 6 bits data size */
  116. #define LCR_CS7 0x02 /* 7 bits data size */
  117. #define LCR_CS8 0x03 /* 8 bits data size */
  118. #define LCR_2_STB 0x04 /* 2 stop bits */
  119. #define LCR_1_STB 0x00 /* 1 stop bit */
  120. #define LCR_PEN 0x08 /* parity enable */
  121. #define LCR_PDIS 0x00 /* parity disable */
  122. #define LCR_EPS 0x10 /* even parity select */
  123. #define LCR_SP 0x20 /* stick parity select */
  124. #define LCR_SBRK 0x40 /* break control bit */
  125. #define LCR_DLAB 0x80 /* divisor latch access enable */
  126. /* constants for the modem control register */
  127. #define MCR_DTR 0x01 /* dtr output */
  128. #define MCR_RTS 0x02 /* rts output */
  129. #define MCR_OUT1 0x04 /* output #1 */
  130. #define MCR_OUT2 0x08 /* output #2 */
  131. #define MCR_LOOP 0x10 /* loop back */
  132. #define MCR_AFCE 0x20 /* auto flow control enable */
  133. /* constants for line status register */
  134. #define LSR_RXRDY 0x01 /* receiver data available */
  135. #define LSR_OE 0x02 /* overrun error */
  136. #define LSR_PE 0x04 /* parity error */
  137. #define LSR_FE 0x08 /* framing error */
  138. #define LSR_BI 0x10 /* break interrupt */
  139. #define LSR_EOB_MASK 0x1E /* Error or Break mask */
  140. #define LSR_THRE 0x20 /* transmit holding register empty */
  141. #define LSR_TEMT 0x40 /* transmitter empty */
  142. /* constants for modem status register */
  143. #define MSR_DCTS 0x01 /* cts change */
  144. #define MSR_DDSR 0x02 /* dsr change */
  145. #define MSR_DRI 0x04 /* ring change */
  146. #define MSR_DDCD 0x08 /* data carrier change */
  147. #define MSR_CTS 0x10 /* complement of cts */
  148. #define MSR_DSR 0x20 /* complement of dsr */
  149. #define MSR_RI 0x40 /* complement of ring signal */
  150. #define MSR_DCD 0x80 /* complement of dcd */
  151. extern void uart_init();
  152. extern int _putc(char c);
  153. extern void rlSendString(char *s);
  154. extern int serial_getc();
  155. extern int CtrlBreak( void );
  156. extern int serial_nowait_getc();
  157. extern void print_ubyte_hex(unsigned char bval);
  158. extern void printk(const char* s, ...);
  159. extern int _inbyte(unsigned short timeout);
  160. extern void _outbyte(int c);
  161. #endif // _UART_H