orbit_boot_800.c 26 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file orbit_boot_800.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/20/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include <regconfig.h.sim_PI.h>
  22. #include <regconfig.h.sim_PHY.h>
  23. #include <sys.h>
  24. #include <clkgen_ctrl_macro.h>
  25. #include <comdef.h>
  26. #include <timer.h>
  27. void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
  28. {
  29. u32 tmp = 0;
  30. int count = 0;
  31. int i = 0;
  32. //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
  33. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  34. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
  35. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
  36. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);
  37. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);
  38. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
  39. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
  40. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
  41. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
  42. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
  43. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
  44. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
  45. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
  46. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
  47. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  48. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
  49. // Memory frequency should be changed below 50MHz somewhere before here
  50. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
  51. udelay(300);
  52. //cdns_dll_rst_deassert()
  53. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  54. //printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  55. while((tmp & 0x80000000) != 0x80000000) {
  56. udelay(1);
  57. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  58. }
  59. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
  60. // tINIT0 is controlled by System
  61. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
  62. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  63. udelay(300);
  64. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
  65. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  66. udelay(3000);
  67. // Drive CKE high
  68. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
  69. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  70. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  71. udelay(4);
  72. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
  73. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
  74. // Write down RCLK-related CRs
  75. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
  76. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  77. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  78. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  79. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  80. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  81. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  82. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
  83. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
  84. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);
  85. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
  86. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
  87. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
  88. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  89. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  90. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00110000);
  91. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  92. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);
  93. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00080c00);
  94. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0040007);
  95. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  96. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);
  97. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  98. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  99. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  100. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
  101. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  102. //apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);
  103. //apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
  104. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);
  105. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
  106. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
  107. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  108. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  109. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  110. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  111. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  112. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  113. //while(1)
  114. {
  115. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  116. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  117. //printf("write 05\r\n");
  118. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  119. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  120. //printf("write 00\r\n");
  121. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  122. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  123. //printf("write 31\r\n");
  124. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0000);
  125. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  126. //printf("write 66\r\n");
  127. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160000);
  128. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  129. //printf("write 00****\r\n");
  130. }
  131. /*read MR4 reg*/
  132. //apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  133. //apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  134. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
  135. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  136. // Waits tZQCAL (1 us)
  137. udelay(4);
  138. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
  139. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  140. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
  141. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  142. // Waits tZQCAL (1 us)
  143. udelay(4);
  144. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
  145. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  146. #if 0
  147. //while(1)
  148. {
  149. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  150. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  151. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  152. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  153. }
  154. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  155. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  156. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  157. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  158. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0000);
  159. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  160. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  161. printf("ddr ctrl 0xc = 0x%x\n", tmp);
  162. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  163. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  164. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  165. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  166. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30040000);
  167. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000001);
  168. tmp = apb_read(OMC_APB_BASE_ADDR + 0x8);
  169. printf("ddr ctrl 0x4 = 0x%x\n", tmp);
  170. #endif
  171. #if 0
  172. for(i = 0; i< 363; i++)
  173. {
  174. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 +i) << 2));
  175. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((2048 +i) << 2)), tmp);
  176. }
  177. for(i = 0; i< 1931; i++)
  178. {
  179. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 +i) << 2));
  180. printf("apb_read: addr=%x, rdata=%08x\n", (PHY_APB_BASE_ADDR + ((4096 +i) << 2)), tmp);
  181. }
  182. tmp = apb_read(OMC_APB_BASE_ADDR + 0x0);
  183. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x0), tmp);
  184. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf00);
  185. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf00), tmp);
  186. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf04);
  187. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf04), tmp);
  188. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf10);
  189. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf10), tmp);
  190. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf14);
  191. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf14), tmp);
  192. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf18);
  193. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf18), tmp);
  194. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf30);
  195. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf30), tmp);
  196. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0xf34);
  197. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0xf34), tmp);
  198. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x110);
  199. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x110), tmp);
  200. tmp = apb_read(OMC_SECURE_APB_BASE_ADDR + 0x114);
  201. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_SECURE_APB_BASE_ADDR + 0x114), tmp);
  202. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10c);
  203. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10c), tmp);
  204. tmp = apb_read(OMC_APB_BASE_ADDR + 0x11c);
  205. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x11c), tmp);
  206. tmp = apb_read(OMC_APB_BASE_ADDR + 0x500);
  207. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x500), tmp);
  208. tmp = apb_read(OMC_APB_BASE_ADDR + 0x514);
  209. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x514), tmp);
  210. tmp = apb_read(OMC_APB_BASE_ADDR + 0x6a8);
  211. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x6a8), tmp);
  212. tmp = apb_read(OMC_APB_BASE_ADDR + 0xea8);
  213. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xea8), tmp);
  214. tmp = // Mread frequency should be changed below 50MHz somewhere before here
  215. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  216. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  217. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  218. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  219. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  220. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x504), tmp);
  221. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  222. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  223. tmp = apb_read(OMC_APB_BASE_ADDR + 0x50c);
  224. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x50c), tmp);
  225. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  226. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  227. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  228. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  229. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  230. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  231. tmp = apb_read(OMC_APB_BASE_ADDR + 0x310);
  232. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x310), tmp);
  233. tmp = apb_read(OMC_APB_BASE_ADDR + 0x600);
  234. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x600), tmp);
  235. tmp = apb_read(OMC_APB_BASE_ADDR + 0x604);
  236. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x604), tmp);
  237. for(i = 0x600; i < 0x6ac;)
  238. {
  239. tmp = apb_read(OMC_APB_BASE_ADDR + i);
  240. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + i),tmp);
  241. i +=4;
  242. }
  243. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  244. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  245. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  246. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  247. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  248. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  249. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  250. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  251. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  252. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  253. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  254. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  255. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  256. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  257. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  258. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  259. tmp = apb_read(OMC_APB_BASE_ADDR + 0x4 );
  260. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x4), tmp);
  261. tmp = apb_read(OMC_APB_BASE_ADDR + 0xc );
  262. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0xc), tmp);
  263. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  264. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  265. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  266. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  267. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  268. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  269. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  270. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  271. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  272. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  273. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  274. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  275. tmp = apb_read(OMC_APB_BASE_ADDR + 0x10 );
  276. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x10), tmp);
  277. tmp = apb_read(OMC_APB_BASE_ADDR + 0x14 );
  278. printf("apb_read: addr=%x, rdata=%08x\n", (OMC_APB_BASE_ADDR + 0x14), tmp);
  279. #endif
  280. #if 1
  281. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  282. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  283. while((tmp & 0x00000002) != 0x00000002) {
  284. udelay(1);
  285. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  286. }
  287. //------ training start ------
  288. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  289. while((tmp & 0x00000002) != 0x00000000) {
  290. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  291. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  292. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  293. case 0:
  294. if(ddr_num == 0) //ddrc_clock=12.5M
  295. {
  296. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  297. udelay(100);
  298. }
  299. else
  300. {
  301. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  302. udelay(100);
  303. }
  304. break;
  305. case 1:
  306. if(ddr_num == 0) //ddrc_clock=200M
  307. {
  308. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_;
  309. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  310. udelay(100);
  311. }
  312. else
  313. {
  314. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_;
  315. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  316. udelay(100);
  317. }
  318. break;
  319. case 2:
  320. if(ddr_num == 0) //ddrc_clock=400M
  321. {
  322. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  323. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  324. udelay(100);
  325. }
  326. else
  327. {
  328. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
  329. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  330. udelay(100);
  331. }
  332. break;
  333. default:
  334. break;
  335. }
  336. //printf("tmp = 0x%x\r\n", (u32)tmp);
  337. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  338. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  339. #if 0
  340. if(count == 4)
  341. {
  342. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  343. printf("start phy %d = 0x%x\r\n", i,(u32)tmp);
  344. udelay(100);
  345. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + 1826) << 2));
  346. printf("post phy %d = 0x%x\r\n", i,(u32)tmp);
  347. }
  348. #endif
  349. count++;
  350. //printf("count = 0x%x\r\n", count);
  351. while((tmp & 0x00000001) != 0x00000000) {
  352. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  353. }
  354. #if 0
  355. if(count == 5)
  356. {
  357. for(i = 0; i < 1913; i++)
  358. {
  359. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  360. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  361. }
  362. for(i = 0; i < 362; i++)
  363. {
  364. tmp = apb_read(PHY_APB_BASE_ADDR + ((2048 + i) << 2));
  365. printf("pi phy %d = 0x%x\r\n", i,(u32)tmp);
  366. }
  367. }
  368. #endif
  369. }
  370. udelay(1);
  371. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  372. }
  373. #if 0
  374. //if(count == 5)
  375. {
  376. for(i = 0; i < 1913; i++)
  377. {
  378. tmp = apb_read(PHY_APB_BASE_ADDR + ((4096 + i) << 2));
  379. printf("phy %d = 0x%x\r\n", i,(u32)tmp);
  380. }
  381. }
  382. #endif
  383. //------ training end --------
  384. //cdns_pi_end( 3);
  385. //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);//`DENALI_PI_11_DATA
  386. //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp & ~4'hF | 4'h3);//set PI_CS_MAP=3
  387. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA //read PI_INT_STATUS
  388. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  389. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  390. DEBUG_INFO("PI_83_DATA = 0x%x\r\n", tmp);
  391. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), tmp & 0xF8000000);
  392. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  393. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  394. DEBUG_INFO("PI_46_DATA = 0x%x\r\n", tmp);
  395. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<24) | (0x3 <<24));
  396. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  397. DEBUG_INFO("PI_33_DATA = 0x%x\r\n", tmp);
  398. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<24));
  399. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  400. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  401. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<16));
  402. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  403. DEBUG_INFO("PI_44_DATA = 0x%x\r\n", tmp);
  404. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<24));
  405. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  406. DEBUG_INFO("PI_45_DATA = 0x%x\r\n", tmp);
  407. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), tmp | 0x1);
  408. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  409. DEBUG_INFO("PI_146_DATA = 0x%x\r\n", tmp);
  410. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<24));
  411. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  412. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  413. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<8));
  414. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  415. DEBUG_INFO("PI_147_DATA = 0x%x\r\n", tmp);
  416. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<24));
  417. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  418. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | (0x1 <<8));
  419. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  420. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  421. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<16) | (0x3 <<16));
  422. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  423. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<16));
  424. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  425. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<16));
  426. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  427. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<24));
  428. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  429. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | 0x1);
  430. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  431. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<16));
  432. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  433. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | 0x3);
  434. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  435. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<16));
  436. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  437. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), tmp | (0x3 <<24));
  438. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  439. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), tmp | (0x3 <<24));
  440. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  441. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), tmp | (0x3 <<24));
  442. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  443. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp | (0x1 <<8));
  444. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  445. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  446. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp & ~(0xF <<8) | (0x3 <<8));
  447. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  448. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), tmp & ~(0x1<<8));
  449. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  450. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<16));
  451. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  452. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<24));
  453. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  454. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), tmp | (0x1 <<8));
  455. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  456. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), tmp | (0x3 <<8));
  457. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  458. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), tmp | (0x3 <<8));
  459. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  460. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
  461. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
  462. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030f11);
  463. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x060c0506);
  464. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x3022088f);
  465. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x20190820);
  466. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x21190e08);
  467. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001a0000);
  468. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200c0c08);
  469. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x2131fa06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
  470. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00e61866);
  471. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x507000e0);
  472. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  473. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00082110);
  474. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x1033240a);
  475. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00001310);
  476. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  477. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00480018);
  478. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  479. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x0600040a);//trdcslat=0x8->0x6;trddata_en=0x8->0xa
  480. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000404);//twrcslat=0x2->0x1;twrlat=0x4;twrdata=0x4
  481. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040d);
  482. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002920);
  483. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  484. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  485. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  486. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20290c00);
  487. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  488. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010026);
  489. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  490. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020012);
  491. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  492. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  493. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  494. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
  495. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  496. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  497. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  498. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
  499. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  500. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  501. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  502. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  503. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  504. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
  505. apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
  506. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
  507. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
  508. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
  509. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
  510. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  511. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
  512. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
  513. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
  514. #endif
  515. }
  516. //cdns_per_tr_longcnt_set( 16);
  517. // Initialization done