orbit_boot_training.c 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file orbit_boot_training.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/20/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include <regconfig.h.sim_PI.h>
  22. #include <regconfig.h.sim_PHY.h>
  23. #include <sys.h>
  24. #include <clkgen_ctrl_macro.h>
  25. #include <comdef.h>
  26. #include <timer.h>
  27. void lpddr4_1600_orbit_boot_training(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
  28. {
  29. u32 tmp = 0;
  30. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
  31. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
  32. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
  33. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);//region0_start //0x00800000
  34. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);//region0_end,SOC addr shift right 8bits //0x01ffffff
  35. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
  36. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
  37. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
  38. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
  39. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
  40. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
  41. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
  42. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
  43. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
  44. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  45. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
  46. // Memory frequency should be changed below 50MHz somewhere before here
  47. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
  48. //cdns_dll_rst_deassert()
  49. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  50. while((tmp & 0x80000000) != 0x80000000) {
  51. udelay(1);
  52. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  53. }
  54. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
  55. // tINIT0 is controlled by System
  56. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
  57. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  58. udelay(200);
  59. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
  60. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  61. udelay(2000);
  62. // Drive CKE high
  63. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
  64. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  65. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  66. udelay(2);
  67. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
  68. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  69. // Waits tZQCAL (1 us)
  70. udelay(1);
  71. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
  72. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  73. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
  74. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  75. // Waits tZQCAL (1 us)
  76. udelay(1);
  77. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
  78. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  79. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
  80. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
  81. // Write down RCLK-related CRs
  82. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
  83. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  84. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  85. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  86. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  87. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  88. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  89. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
  90. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
  91. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000fc);
  92. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
  93. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
  94. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);//
  95. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  96. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  97. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x000d0000);
  98. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  99. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x17300803);
  100. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00060c00);
  101. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0030006);
  102. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  103. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);//
  104. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  105. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  106. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  107. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00020008);
  108. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  109. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);
  110. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
  111. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x04130409);
  112. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  113. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  114. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  115. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  116. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  117. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  118. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  119. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  120. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  121. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  122. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  123. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  124. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  125. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  126. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  127. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  128. while((tmp & 0x00000002) != 0x00000002) {
  129. udelay(1);
  130. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  131. }
  132. //------ training start ------
  133. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);//wait for dfi_phymstr_ack=0
  134. while((tmp & 0x00000002) != 0x00000000) {
  135. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  136. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  137. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  138. case 0:
  139. if(ddr_num == 1) //ddrc_clock=12.5M
  140. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_
  141. else
  142. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_
  143. break;
  144. case 1:
  145. if(ddr_num == 1) //ddrc_clock=200M
  146. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_
  147. else
  148. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_
  149. break;
  150. case 2:
  151. if(ddr_num == 1) //ddrc_clock=800M
  152. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_
  153. else
  154. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_
  155. break;
  156. default:
  157. break;
  158. }
  159. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  160. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  161. while((tmp & 0x00000001) != 0x00000000) {
  162. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  163. }
  164. }
  165. udelay(1);
  166. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518); //read dfi_phymstr_ack
  167. }
  168. //------ training end --------
  169. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  170. while((tmp & 0x00000002) != 0x00000000) {
  171. udelay(1);
  172. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  173. }
  174. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +11 <<2));//`DENALI_PI_11_DATA
  175. apb_write(PHY_APB_BASE_ADDR + (2048 +11 <<2), 0x03000803);
  176. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA
  177. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  178. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), 0x00000000);
  179. //cdns_pi_end( 3);
  180. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  181. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), 0x030f0000);
  182. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  183. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), 0x00000000);
  184. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  185. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x01000000);
  186. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  187. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000000);
  188. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  189. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), 0x00000001);
  190. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  191. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), 0x03011808);
  192. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  193. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x01010301);
  194. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  195. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03010301);
  196. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  197. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000100);
  198. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  199. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), 0x03030000);
  200. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  201. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), 0x00000000);
  202. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  203. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x01000000);
  204. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  205. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x00000000);
  206. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  207. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), 0x00000101);
  208. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  209. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), 0x03031808);
  210. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  211. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03010303);
  212. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  213. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), 0x03030303);
  214. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  215. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), 0x03170a0a);
  216. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  217. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), 0x03000000);
  218. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  219. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), 0x03000000);
  220. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  221. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), 0x00000100);
  222. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  223. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), 0x01010300);
  224. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  225. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), 0x34000000);
  226. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  227. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), 0x01000000);
  228. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  229. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), 0x00000000);
  230. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  231. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), 0x00000100);
  232. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  233. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), 0x06000301);
  234. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  235. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), 0x01000301);
  236. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  237. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), 0x13000301);
  238. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  239. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  240. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  241. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
  242. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x04031d22);
  243. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0c18080c);
  244. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x60440d9d);//bit[13:8]:tRTP>=0xC
  245. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x34271140);//tRRD[12:8]>=0x10
  246. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x36231c0e);
  247. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001e0000);
  248. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20171708);
  249. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x36420806);
  250. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01cf2cd6);//tXSR>=0x1CC(287.5ns_8gibx16);tXP+tmrri?
  251. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x00e101c1);//lpddr4:tRFCpb>=0xe0,tRFCab>=0x1c0
  252. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  253. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000d351e);//bit[21:16]:tRTP>=0xC
  254. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x20664713);
  255. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00002520);
  256. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  257. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00900030);
  258. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  259. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x14000416);//trdcslat=0x16->0x14;trddata_en=0x16->0x16
  260. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x08000a04);//twrcslat=0x8(-1);twrlat=0xa(-1);twrdata=0x4
  261. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040a);
  262. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003320);
  263. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  264. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  265. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  266. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20330c00);
  267. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  268. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010056);
  269. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  270. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3002002d);
  271. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  272. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  273. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  274. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
  275. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  276. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
  277. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  278. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  279. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  280. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  281. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  282. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
  283. apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
  284. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
  285. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
  286. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
  287. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
  288. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  289. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
  290. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
  291. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
  292. }
  293. //cdns_per_tr_longcnt_set( 16);
  294. // Initialization done