orbit_boot_1066.c 16 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file orbit_boot_1066.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/20/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include <regconfig.h.sim_PI.h>
  22. #include <regconfig.h.sim_PHY.h>
  23. #include <sys.h>
  24. #include <clkgen_ctrl_macro.h>
  25. #include <comdef.h>
  26. #include <timer.h>
  27. void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
  28. {
  29. u32 tmp = 0;
  30. int count = 0;
  31. int i = 0;
  32. //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
  33. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  34. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
  35. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
  36. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);
  37. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);
  38. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
  39. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
  40. apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
  41. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
  42. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
  43. apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
  44. apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
  45. apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
  46. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
  47. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  48. apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
  49. // Memory frequency should be changed below 50MHz somewhere before here
  50. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
  51. udelay(300);
  52. //cdns_dll_rst_deassert()
  53. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  54. while((tmp & 0x80000000) != 0x80000000) {
  55. udelay(1);
  56. tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
  57. }
  58. apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
  59. // tINIT0 is controlled by System
  60. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
  61. // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
  62. udelay(300);
  63. apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
  64. // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
  65. udelay(3000);
  66. // Drive CKE high
  67. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
  68. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  69. // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
  70. udelay(4);
  71. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
  72. apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
  73. // Write down RCLK-related CRs
  74. apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
  75. apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
  76. apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
  77. apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
  78. apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
  79. apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
  80. apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
  81. apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
  82. apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
  83. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);
  84. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
  85. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
  86. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
  87. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
  88. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
  89. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00110000);
  90. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
  91. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);
  92. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00080c00);
  93. apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0040007);
  94. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  95. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00081306);
  96. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x04070304);
  97. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00000404);
  98. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  99. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
  100. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  101. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);
  102. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
  103. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
  104. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
  105. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  106. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  107. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  108. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
  109. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  110. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
  111. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  112. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020000);
  113. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  114. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  115. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  116. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0000);
  117. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  118. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160000);
  119. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  120. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
  121. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  122. // Waits tZQCAL (1 us)
  123. udelay(4);
  124. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
  125. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  126. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
  127. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  128. // Waits tZQCAL (1 us)
  129. udelay(4);
  130. apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
  131. apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
  132. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  133. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  134. while((tmp & 0x00000002) != 0x00000002) {
  135. udelay(1);
  136. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  137. }
  138. //------ training start ------
  139. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  140. while((tmp & 0x00000002) != 0x00000000) {
  141. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +1 << 2)); //read freq_change_req_type
  142. if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
  143. switch(tmp & 0x0000001f) { //judge freq_change_req_type
  144. case 0:
  145. if(ddr_num == 0) //ddrc_clock=12.5M
  146. {
  147. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  148. udelay(100);
  149. }
  150. else
  151. {
  152. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  153. udelay(100);
  154. }
  155. break;
  156. case 1:
  157. if(ddr_num == 0) //ddrc_clock=200M
  158. {
  159. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  160. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  161. udelay(100);
  162. }
  163. else
  164. {
  165. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
  166. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  167. udelay(100);
  168. }
  169. break;
  170. case 2:
  171. if(ddr_num == 0) //ddrc_clock=400M
  172. {
  173. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_;
  174. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  175. udelay(100);
  176. }
  177. else
  178. {
  179. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_;
  180. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  181. udelay(100);
  182. }
  183. break;
  184. default:
  185. break;
  186. }
  187. apb_write(PHY_APB_BASE_ADDR + (0 +2 << 2), 0x01); //set freq_change_ack
  188. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  189. count++;
  190. //printf("count = 0x%x\r\n", count);
  191. while((tmp & 0x00000001) != 0x00000000) {
  192. tmp = apb_read(PHY_APB_BASE_ADDR + (0 +2 << 2)); //read freq_change_ack
  193. }
  194. }
  195. udelay(1);
  196. tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
  197. }
  198. //------ training end --------
  199. //cdns_pi_end( 3);
  200. //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);//`DENALI_PI_11_DATA
  201. //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp & ~4'hF | 4'h3);//set PI_CS_MAP=3
  202. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +83 <<2));//`DENALI_PI_83_DATA //read PI_INT_STATUS
  203. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +84 <<2));//`DENALI_PI_84_DATA
  204. apb_write(PHY_APB_BASE_ADDR + (2048 +84 <<2), tmp & 0xF8000000);
  205. //cdns_rdlvl_gate_tr_init( 3,0,0,0,0);
  206. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  207. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<24) | (0x3 <<24));
  208. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  209. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<24));
  210. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  211. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<16));
  212. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  213. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp & ~(0x1<<24));
  214. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +45 <<2));//`DENALI_PI_45_DATA
  215. apb_write(PHY_APB_BASE_ADDR + (2048 +45 <<2), tmp | 0x1);
  216. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  217. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<24));
  218. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  219. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<8));
  220. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  221. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<24));
  222. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  223. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | (0x1 <<8));
  224. //cdns_rdlvl_tr_init( 3,0,0,0,0);
  225. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +46 <<2));//`DENALI_PI_46_DATA
  226. apb_write(PHY_APB_BASE_ADDR + (2048 +46 <<2), tmp & ~(0xF <<16) | (0x3 <<16));
  227. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +33 <<2));//`DENALI_PI_33_DATA
  228. apb_write(PHY_APB_BASE_ADDR + (2048 +33 <<2), tmp & ~(0x1<<16));
  229. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  230. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<16));
  231. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  232. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp & ~(0x1<<24));
  233. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +44 <<2));//`DENALI_PI_44_DATA
  234. apb_write(PHY_APB_BASE_ADDR + (2048 +44 <<2), tmp | 0x1);
  235. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +146 <<2));//`DENALI_PI_146_DATA
  236. apb_write(PHY_APB_BASE_ADDR + (2048 +146 <<2), tmp | (0x3 <<16));
  237. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  238. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | 0x3);
  239. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +147 <<2));//`DENALI_PI_147_DATA
  240. apb_write(PHY_APB_BASE_ADDR + (2048 +147 <<2), tmp | (0x3 <<16));
  241. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +148 <<2));//`DENALI_PI_148_DATA
  242. apb_write(PHY_APB_BASE_ADDR + (2048 +148 <<2), tmp | (0x3 <<24));
  243. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +149 <<2));//`DENALI_PI_149_DATA
  244. apb_write(PHY_APB_BASE_ADDR + (2048 +149 <<2), tmp | (0x3 <<24));
  245. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +150 <<2));//`DENALI_PI_150_DATA
  246. apb_write(PHY_APB_BASE_ADDR + (2048 +150 <<2), tmp | (0x3 <<24));
  247. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +43 <<2));//`DENALI_PI_43_DATA
  248. apb_write(PHY_APB_BASE_ADDR + (2048 +43 <<2), tmp | (0x1 <<8));
  249. //cdns_wdqlvl_tr_init( 3,0,0,0,0);
  250. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
  251. apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp & ~(0xF <<8) | (0x3 <<8));
  252. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +68 <<2));//`DENALI_PI_68_DATA
  253. apb_write(PHY_APB_BASE_ADDR + (2048 +68 <<2), tmp & ~(0x1<<8));
  254. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  255. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<16));
  256. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +71 <<2));//`DENALI_PI_71_DATA
  257. apb_write(PHY_APB_BASE_ADDR + (2048 +71 <<2), tmp & ~(0x1<<24));
  258. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +72 <<2));//`DENALI_PI_72_DATA
  259. apb_write(PHY_APB_BASE_ADDR + (2048 +72 <<2), tmp | (0x1 <<8));
  260. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +180 <<2));//`DENALI_PI_180_DATA
  261. apb_write(PHY_APB_BASE_ADDR + (2048 +180 <<2), tmp | (0x3 <<8));
  262. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +183 <<2));//`DENALI_PI_183_DATA
  263. apb_write(PHY_APB_BASE_ADDR + (2048 +183 <<2), tmp | (0x3 <<8));
  264. tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
  265. apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
  266. apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
  267. apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03031417);
  268. apb_write(OMC_APB_BASE_ADDR + 0x624, 0x08100608);
  269. apb_write(OMC_APB_BASE_ADDR + 0x628, 0x402d0894);
  270. apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x271e0b2b);
  271. apb_write(OMC_APB_BASE_ADDR + 0x630, 0x281b140a);
  272. apb_write(OMC_APB_BASE_ADDR + 0x634, 0x001c0000);
  273. apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200f0f08);
  274. apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x28410a06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
  275. apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01331f8b);
  276. apb_write(OMC_APB_BASE_ADDR + 0x644, 0x1096012b);
  277. apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
  278. apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x00082714);
  279. apb_write(OMC_APB_BASE_ADDR + 0x650, 0x16442f0d);
  280. apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00001916);
  281. apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
  282. apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00600020);
  283. apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
  284. apb_write(OMC_APB_BASE_ADDR + 0x680, 0x0c00040f);//trdcslat=0xe->0xc;trddata_en=0xe->0xf
  285. apb_write(OMC_APB_BASE_ADDR + 0x684, 0x03000604);//twrcslat=0x4->0x3;twrlat=0x6;twrdata=0x4
  286. apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040d);
  287. apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002c20);
  288. apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
  289. apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
  290. apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
  291. apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x202c0c00);
  292. apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
  293. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010036);
  294. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  295. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3002001b);
  296. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  297. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
  298. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  299. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0036); //0x06->0x66
  300. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  301. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3016001e); //0x06->0x1e
  302. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  303. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0030); //vref(ca)
  304. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  305. apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300e0020); //vref(dq)
  306. apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
  307. apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
  308. apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
  309. apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
  310. apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
  311. apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
  312. apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
  313. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
  314. apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
  315. apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000013);
  316. apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
  317. apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
  318. apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
  319. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
  320. apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
  321. apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
  322. apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
  323. }
  324. //cdns_per_tr_longcnt_set( 16);
  325. // Initialization done