sys.h 3.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file sys.h
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/22/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #ifndef SYS_H_
  22. #define SYS_H_
  23. /*********************************** sys clock************************/
  24. #define E32_ADDR_REMAP_OFFSET 0
  25. #define U74_SYS_PORT_DDRC_BASE_ADDR 0x1000000000LL
  26. #define OMC_CFG0_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011000000LL)
  27. #define OMC_CFG1_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011010000LL)
  28. #define DDRPHY0_CSR_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011820000LL)
  29. #define DDRPHY1_CSR_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011830000LL)
  30. #define QSPI_CLK 100000000
  31. #define QSPI_REF_CLK 250000000
  32. #define TIMER_CLK_HZ 6250000
  33. #define DEFAULT_SD_BOOT_LOAD_BLOCK 1000
  34. #define DEFAULT_SPI_BOOT_START_ADDR 1
  35. #define DEFAULT_SPI_BOOT_SIZE_ADDR 0x0
  36. #define DEFAULT_SPI_BOOT_LOAD_PAGES 512
  37. // QSPI
  38. #define QSPI_BASE_ADDR 0x11860000
  39. //CADENCE QSPI AHB
  40. #define QSPI_BASE_AHB_ADDR 0x20000000
  41. // TIMER --WDT
  42. #define TIMER_BASE_ADDR 0x12480000
  43. // SDIO0
  44. #define SDIO0_BASE_ADDR 0x10000000
  45. // SDIO1
  46. #define SDIO1_BASE_ADDR 0x10010000
  47. // GPIO
  48. #define GPIO_BASE_ADDR 0x11910000///0xA9060000
  49. #define EZGPIO_FULLMUX_BASE_ADDR 0x11910000
  50. #define RSTGEN_BASE_ADDR 0x11840000
  51. #define CLKGEN_BASE_ADDR 0x11800000
  52. // CLKGEN
  53. #define VIC_CLKGEN_TOP_SV_BASE_ADDR 0x11800000///0xA9090000
  54. // RSTGEN
  55. #define VIC_RSTGEN_BASE_ADDR 0x11840000///0xA90A0000
  56. #define SYSCON_IOPAD_CTRL_BASE_ADDR 0x11858000
  57. // SYSCON
  58. #define SYSCON_SYSMAIN_CTRL_BASE_ADDR 0x11850000
  59. // HS-UART0
  60. #define UART0_HS_BASE_ADDR 0x11870000
  61. // HS-UART1
  62. #define UART1_HS_BASE_ADDR 0x11880000
  63. // UART2
  64. #define UART2_BASE_ADDR 0x12430000
  65. // UART3
  66. #define UART3_BASE_ADDR 0x12440000
  67. /*Reserved information:
  68. *second boot:64K 0x0 - 0xffff
  69. *ddr init:64K 0x10000 - 0x1ffff
  70. *uboot:1M 0x20000 - 0x11ffff
  71. *kernel:25M 0x120000 - 0x1a1ffff
  72. */
  73. /*Reserved information:
  74. *second boot:32K 0x0 - 0x7fff
  75. *ddr init:50K 0x8000 - 0x147ff
  76. *uboot:500K 0x14800 - 0x917ff
  77. *kernel:25M 0x130000 - 0x1a3ffff
  78. */
  79. #define UBOOT_EXEC_AT_NBDLA_2M 0
  80. #define UBOOT_EXEC_AT_SYS_PORT 0
  81. /*DDR bin file */
  82. #define DEFAULT_DDR_ADDR 0x18080000
  83. #define DEFAULT_DDR_OFFSET 0x100
  84. /*uboot bin file*/
  85. #if (UBOOT_EXEC_AT_NBDLA_2M == 1)
  86. #define DEFAULT_UBOOT_ADDR 0x19c00000
  87. #elif (UBOOT_EXEC_AT_SYS_PORT == 1)
  88. #define DEFAULT_UBOOT_ADDR 0x1000000000
  89. #else
  90. #define DEFAULT_UBOOT_ADDR 0x80000000
  91. #endif
  92. #define DEFAULT_UBOOT_OFFSET 0x400
  93. /*kernel image file*/
  94. #define DEFAULT_KERNEL_ADDR 0xa0000000
  95. #define DEFAULT_KERNEL_OFFSET 0x1200
  96. #define FLASH_SECONDBOOT_START_ADDR 0
  97. #define FLASH_SECONDBOOT_SIZE_LIMIT (64*1024)
  98. #define FLASH_DDRINIT_START_ADDR 0x10000
  99. #define FLASH_DDRINIT_SIZE_LIMIT (192*1024)
  100. #define FLASH_UBOOT_START_ADDR 0x40000
  101. #define FLASH_UBOOT_SIZE_LIMIT (10*1024*1024)
  102. #define DEFAULT_UBOOT_LOAD_ADDR DEFAULT_UBOOT_ADDR
  103. #define DEFAULT_SECONDBOOT_LOAD_ADDR 0x180a8000 /*32k*/
  104. #define DEFAULT_DDRINIT_LOAD_ADDR 0x18000000 /*128K*/
  105. #endif