bootmain.c 17 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file bootmain.c
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/29/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 20120 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include "sys.h"
  22. #include "spi_flash.h"
  23. #include "spi.h"
  24. #include "timer.h"
  25. #include "encoding.h"
  26. #include "gpt.h"
  27. #include "clkgen_ctrl_macro.h"
  28. #include "syscon_sysmain_ctrl_macro.h"
  29. #include "rstgen_ctrl_macro.h"
  30. #include "crc32.h"
  31. extern void boot_sdio_init(void);
  32. extern int boot_load_gpt_partition(void* dst, const gpt_guid* partition_type_guid);
  33. extern const gpt_guid gpt_guid_sifive_uboot;
  34. extern const gpt_guid gpt_guid_sifive_kernel;
  35. extern unsigned int receive_count;
  36. typedef void ( *STARTRUNNING )( unsigned int par1 );
  37. /*
  38. To run a procedure from the address:start
  39. start: start address of runing in armmode, not do address align checking
  40. */
  41. void start2run32(unsigned int start)
  42. {
  43. (( STARTRUNNING )(start))(0);
  44. }
  45. #define SPIBOOT_LOAD_ADDR_OFFSET 252
  46. /*read data from flash to the destination address
  47. *
  48. *spi_flash: flash device informations
  49. *des_addr: store the data read from flash
  50. *page_offset:Offset of data stored in flash
  51. *mode:flash work mode
  52. */
  53. static int load_data(struct spi_flash* spi_flash,void *des_addr,unsigned int page_offset,int mode)
  54. {
  55. u8 dataBuf[260];
  56. u32 startPage,endPage;
  57. u32 pageSize;
  58. u32 fileSize;
  59. u8 *addr;
  60. int ret;
  61. int i;
  62. u32 offset;
  63. pageSize = spi_flash->page_size;
  64. addr = (u8 *)des_addr;
  65. offset = page_offset*pageSize;
  66. /*read first page,get the file size*/
  67. ret = spi_flash->read(spi_flash,offset,pageSize,dataBuf,mode);
  68. if(ret != 0)
  69. {
  70. printk("read fail#\r\n");
  71. return -1;
  72. }
  73. /*calculate file size*/
  74. fileSize = (dataBuf[3] << 24) | (dataBuf[2] << 16) | (dataBuf[1] << 8) | (dataBuf[0]) ;
  75. if(fileSize == 0)
  76. return -1;
  77. endPage = ((fileSize + 255) >> 8);//page align
  78. /*copy the first page data*/
  79. sys_memcpy(addr, &dataBuf[4], SPIBOOT_LOAD_ADDR_OFFSET);
  80. //copy data from flash to des_addr, with crc check
  81. #if 1
  82. uint32_t crc_org = 0, crc_ddr = 0;
  83. uint32_t n_bytes_left = fileSize - SPIBOOT_LOAD_ADDR_OFFSET;
  84. uint32_t once = 0;
  85. crc32(dataBuf+4, SPIBOOT_LOAD_ADDR_OFFSET, &crc_org);
  86. crc32(addr, SPIBOOT_LOAD_ADDR_OFFSET, &crc_ddr);
  87. offset += pageSize;
  88. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  89. /*read Remaining pages data*/
  90. while (n_bytes_left) {
  91. once = n_bytes_left > pageSize ? pageSize : n_bytes_left;
  92. ret = spi_flash->read(spi_flash, offset, once, dataBuf, mode);
  93. if(ret != 0)
  94. {
  95. printk("read 0x%x fail##\r\n", offset);
  96. return -1;
  97. }
  98. sys_memcpy(addr, dataBuf, once);
  99. crc32(dataBuf, once, &crc_org);
  100. crc32(addr, once, &crc_ddr);
  101. offset += once;
  102. addr += once;
  103. n_bytes_left -= once;
  104. }
  105. printk("crc flash: %08x, crc ddr: %08x\r\n", crc_org, crc_ddr);
  106. if (crc_org != crc_ddr) {
  107. printk("ERROR: crc check FAILED\r\n");
  108. while (1) {
  109. __asm__ ("wfi");
  110. }
  111. } else {
  112. printk("crc check PASSED\r\n");
  113. }
  114. #else
  115. offset += pageSize;
  116. addr += SPIBOOT_LOAD_ADDR_OFFSET;
  117. for(i=1; i<=endPage; i++)
  118. {
  119. ret = spi_flash->read(spi_flash,offset,pageSize, addr, mode);
  120. if(ret != 0)
  121. {
  122. printk("read fail##\r\n");
  123. return -1;
  124. }
  125. offset += pageSize;
  126. addr +=pageSize;
  127. }
  128. #endif
  129. return 0;
  130. }
  131. int updata_flash(struct spi_flash* spi_flash,u32 flash_addr,u32 flash_size_limit, u32 load_addr,unsigned char mode)
  132. {
  133. int ret = 0;
  134. u32 offset = 0;
  135. int erase_block = 0;
  136. unsigned int page_count = 0;
  137. unsigned int index = 0;
  138. unsigned int blockSize,pageSize;
  139. u8 *data;
  140. printk("send file by xmodem\r\n");
  141. blockSize = spi_flash->block_size;
  142. pageSize = spi_flash->page_size;
  143. ret = xmodemReceive((unsigned char *)load_addr,0);
  144. if(ret <= 0)
  145. return -1;
  146. if ((u32)ret > flash_size_limit) {
  147. printk("error: size %d exceeds the limit %d\r\n", ret, flash_size_limit);
  148. return -1;
  149. }
  150. erase_block = (ret + blockSize - 1) / blockSize;
  151. page_count = (ret + pageSize - 1) / pageSize;
  152. /*erase flash*/
  153. offset = flash_addr;
  154. for(index=0; index<erase_block; index++)
  155. {
  156. ret = spi_flash->erase(spi_flash, offset, blockSize, 64);
  157. if(ret < 0)
  158. {
  159. printk("erases block %d fail\r\n",offset);
  160. return -1;
  161. }
  162. offset +=blockSize;
  163. }
  164. /*write data*/
  165. offset = flash_addr;
  166. data = (u8 *)load_addr;
  167. for(index=0; index<page_count; index++)
  168. {
  169. ret = spi_flash->write(spi_flash, offset,pageSize, data, mode);
  170. printk(".");
  171. if(index%64 == 0)
  172. printk("\r\n");
  173. if(ret < 0)
  174. {
  175. printk("write page %d fail\r\n",offset);
  176. return -1;
  177. }
  178. offset +=pageSize;
  179. data += pageSize;
  180. }
  181. return 0;
  182. }
  183. static int updata_flash_code(struct spi_flash* spi_flash,unsigned int updata_num,unsigned char mode)
  184. {
  185. int ret = 0;
  186. switch (updata_num){
  187. case 0:
  188. ret = updata_flash(spi_flash,FLASH_SECONDBOOT_START_ADDR,FLASH_SECONDBOOT_SIZE_LIMIT,DEFAULT_SECONDBOOT_LOAD_ADDR,mode);
  189. break;
  190. case 1:
  191. ret = updata_flash(spi_flash,FLASH_DDRINIT_START_ADDR,FLASH_DDRINIT_SIZE_LIMIT,DEFAULT_DDRINIT_LOAD_ADDR,mode);
  192. break;
  193. case 2:
  194. ret = updata_flash(spi_flash,FLASH_UBOOT_START_ADDR,FLASH_UBOOT_SIZE_LIMIT,DEFAULT_UBOOT_LOAD_ADDR,mode);
  195. break;
  196. default:
  197. break;
  198. }
  199. return ret;
  200. }
  201. static int prog_2ndboot(struct spi_flash *flash, int mode)
  202. {
  203. updata_flash_code(flash, 0, mode);
  204. return 0;
  205. }
  206. static int prog_ddrinit(struct spi_flash *flash, int mode)
  207. {
  208. updata_flash_code(flash, 1, mode);
  209. return 0;
  210. }
  211. static int prog_uboot(struct spi_flash *flash, int mode)
  212. {
  213. updata_flash_code(flash, 2, mode);
  214. return 0;
  215. }
  216. typedef struct
  217. {
  218. const char *text;
  219. int (*prog_op)(struct spi_flash *, int);
  220. } prog_menu_t;
  221. static int prog_menu(struct spi_flash *flash, int mode, const prog_menu_t *menu, int count)
  222. {
  223. int i, sel;
  224. char buff[32]={0};
  225. char *str = NULL, *str_end = NULL;
  226. const char *ROOT_MENU_KEY = "root@s5t";
  227. while (1) {
  228. printk("\r\n");
  229. for (i = 0; i < count; i++) {
  230. printk("%d:%s\r\n", i, menu[i].text);
  231. }
  232. printk("%d:quit\r\n", count);
  233. printk("select the function: ");
  234. serial_gets(buff);
  235. str = buff;
  236. while (*str == '\n' || *str == ' ') {
  237. //skip white
  238. str++;
  239. }
  240. if (strcmp(str, ROOT_MENU_KEY) == 0) {
  241. //request root menu
  242. return 1;
  243. }
  244. sel = (int)strtol(str, &str_end, 10);
  245. if (str == str_end || sel < 0 || sel > count) {
  246. //invalid sel
  247. continue;
  248. }
  249. if (sel == count) {
  250. //quit
  251. printk("\r\nquit\r\n");
  252. return 0;
  253. }
  254. if (menu[sel].prog_op) {
  255. menu[sel].prog_op(flash, mode);
  256. }
  257. }
  258. return 0;
  259. }
  260. static void prog_flash(void)
  261. {
  262. prog_menu_t user_menu[] = {
  263. { "update uboot", prog_uboot },
  264. };
  265. prog_menu_t root_menu[] = {
  266. { "update second boot", prog_2ndboot },
  267. { "update ddr init boot", prog_ddrinit },
  268. { "update uboot", prog_uboot },
  269. };
  270. struct spi_flash *flash = NULL;
  271. unsigned char mode = 1;// or 4
  272. cadence_qspi_init(0, mode);
  273. flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  274. printk("\r\n***************************************************\r\n");
  275. printk("*************** FLASH PROGRAMMING *****************\r\n");
  276. printk("***************************************************\r\n");
  277. if (prog_menu(flash, mode, &user_menu, sizeof(user_menu)/sizeof(user_menu[0]))) {
  278. prog_menu(flash, mode, &root_menu, ARRAY_SIZE(root_menu));
  279. }
  280. }
  281. void boot_from_chiplink(void)
  282. {
  283. int bootdelay = 3;
  284. int abort = 0;
  285. char str[6];
  286. char *tmp;
  287. int ret=0;
  288. s32 usel;
  289. unsigned long ts;
  290. struct spi_flash* spi_flash;
  291. unsigned char mode = 1;// or 4
  292. while ((bootdelay > 0) && (!abort)) {
  293. --bootdelay;
  294. /* delay 1000 ms */
  295. ts = get_timer(0);
  296. do {
  297. if (serial_tstc()) { /* we got a key press */
  298. abort = 1; /* don't auto boot */
  299. bootdelay = 0; /* no more delay */
  300. serial_getc(); /* consume input */
  301. break;
  302. }
  303. mdelay(100);
  304. } while (!abort && get_timer(ts) < 1000);
  305. printk("\b\b\b%d ", bootdelay);
  306. }
  307. if(1 == abort)
  308. {
  309. prog_flash();
  310. #if 0
  311. cadence_qspi_init(0, mode);
  312. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  313. printk("***************************************************\r\n");
  314. printk("***************VIC DDR INIT BOOT ********************\r\n");
  315. printk("***************************************************\r\n");
  316. again:
  317. tmp = str;
  318. printk("0:updata second boot\r\n");
  319. printk("1:updata ddr init boot\r\n");
  320. printk("2:updata uboot\r\n");
  321. printk("3:quit\r\n");
  322. printk("Select the function to test : ");
  323. serial_gets(str);
  324. if(str[0] == 0)
  325. goto again;
  326. while(*tmp == 4){tmp++;} /*skip EOT*/
  327. usel = atoi(tmp);
  328. if(usel > 3)
  329. {
  330. printk("error select,try again\r\n");
  331. goto again;
  332. }
  333. /*quit*/
  334. if(usel == 3)
  335. return;
  336. printk("usel:%d\n",usel);
  337. ret = updata_flash_code(spi_flash,usel,mode);
  338. if(ret < 0)
  339. printk("updata fail\r\n");
  340. else
  341. printk("updata success\r\n");
  342. goto again;
  343. #endif
  344. }
  345. }
  346. void boot_from_uart(void)
  347. {
  348. sys_cmd_proc();
  349. }
  350. void boot_from_sdio(void)
  351. {
  352. boot_sdio_init();
  353. /*load uboot bin file from sd card*/
  354. boot_load_gpt_partition((void *)DEFAULT_UBOOT_ADDR,&gpt_guid_sifive_uboot);
  355. /*load kernel bin file from sd card*/
  356. // boot_load_gpt_partition((void *)DEFAULT_KERNEL_ADDR,&gpt_guid_sifive_kernel);
  357. }
  358. void boot_from_spi(int mode)
  359. {
  360. struct spi_flash* spi_flash;
  361. int ret;
  362. u32 *addr;
  363. u32 val;
  364. cadence_qspi_init(0, mode);
  365. spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
  366. /*load uboot*/
  367. load_data(spi_flash,DEFAULT_UBOOT_ADDR,DEFAULT_UBOOT_OFFSET,mode);
  368. }
  369. static int init_ddr(void)
  370. {
  371. int fail_flag = 0;
  372. uint32_t tmp;
  373. uint32_t OMC_APB_BASE_ADDR, OMC_SECURE_APB_BASE_ADDR, PHY_APB_BASE_ADDR;
  374. uint64_t mem_addr;
  375. uint32_t wdata;
  376. int i = 0;
  377. u32 count = 0;
  378. uint64_t base_addr = U74_SYS_PORT_DDRC_BASE_ADDR;
  379. ///printf_led("Main start");
  380. //Set PLL to 15750M
  381. //_ASSERT_RESET_rstgen_rstn_ddrphy_apb_ //reset ddrphy,unvalid
  382. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_;
  383. //SCFG_PLL [31:24] [23:16] [15:8] [7:4] [3] [2] [1] [0]
  384. // OD BWADJ CLKFDIV CLKR bypass infb pd rst
  385. #if defined(DDR_2133)
  386. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x292905);//set reset
  387. udelay(10); //wait(500*(1/25M))
  388. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x0292904);//clear reset
  389. udelay(10); //wait(500*(1/25M))
  390. #elif defined(DDR_2800)
  391. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x373705);//set reset
  392. udelay(10); //wait(500*(1/25M))
  393. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x0373704);//clear reset
  394. udelay(10); //wait(500*(1/25M))
  395. #elif defined(DDR_3200)
  396. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x3f3f05);//set reset
  397. udelay(10); //wait(500*(1/25M))
  398. MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x03f3f04);//clear reset
  399. udelay(10); //wait(500*(1/25M))
  400. #endif
  401. _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
  402. //_CLEAR_RESET_rstgen_rstn_ddrphy_apb_ //clear reset of ddrphy,unvalid
  403. //ddrc_clock=400M test
  404. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  405. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
  406. //ddrc_clock=800M
  407. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_;
  408. //_SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_;
  409. //12.5M
  410. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  411. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  412. _ENABLE_CLOCK_clk_ddrc0_;
  413. _ENABLE_CLOCK_clk_ddrc1_;
  414. #if 0
  415. _ENABLE_CLOCK_clk_ddrphy_apb_ ;
  416. _CLEAR_RESET_rstgen_rstn_ddrphy_apb_ ;
  417. _ENABLE_CLOCK_clk_dla_bus_ ;
  418. _ENABLE_CLOCK_clk_dla_axi_ ;
  419. _ENABLE_CLOCK_clk_dlanoc_axi_ ;
  420. _ENABLE_CLOCK_clk_dla_apb_ ;
  421. _ENABLE_CLOCK_clk_dlaslv_axi_ ;
  422. _CLEAR_RESET_rstgen_rstn_dla_axi_ ;
  423. _CLEAR_RESET_rstgen_rstn_dlanoc_axi_ ;
  424. _CLEAR_RESET_rstgen_rstn_dla_apb_ ;
  425. _CLEAR_RESET_rstgen_rstn_dlaslv_axi_ ;
  426. #endif
  427. //---- config ddrphy0/omc0 ----
  428. for(int ddr_num=0; ddr_num<2; ddr_num++) {
  429. if(ddr_num == 0) {
  430. OMC_APB_BASE_ADDR = OMC_CFG0_BASE_ADDR;
  431. OMC_SECURE_APB_BASE_ADDR = OMC_CFG0_BASE_ADDR+0x1000;
  432. PHY_APB_BASE_ADDR = DDRPHY0_CSR_BASE_ADDR;
  433. } else {
  434. OMC_APB_BASE_ADDR = OMC_CFG1_BASE_ADDR;
  435. OMC_SECURE_APB_BASE_ADDR = OMC_CFG1_BASE_ADDR+0x1000;
  436. PHY_APB_BASE_ADDR = DDRPHY1_CSR_BASE_ADDR;
  437. }
  438. //reg_wr_test;
  439. //`ifdef G_OPENEDGE_DDRPHY
  440. // `include "noc/continue_wr/orbit_cfg/orbit_boot.c"
  441. //`else
  442. #if 0
  443. #include "./ddrphy_cfg/regconfig.h.sim_PI.C"
  444. #include "./ddrphy_cfg/regconfig.h.sim_PHY.C"
  445. #else
  446. regconfig_h_sim_pi(OMC_APB_BASE_ADDR, OMC_SECURE_APB_BASE_ADDR, PHY_APB_BASE_ADDR);
  447. regconfig_h_sim_phy(OMC_APB_BASE_ADDR, OMC_SECURE_APB_BASE_ADDR, PHY_APB_BASE_ADDR);
  448. #endif
  449. //#include "./ddrc_cfg/lpddr4_1600_cl28_bl16/orbit_boot_8gx16.v"
  450. regconfig_pi_start(OMC_APB_BASE_ADDR, OMC_SECURE_APB_BASE_ADDR, PHY_APB_BASE_ADDR, ddr_num);
  451. if(ddr_num == 0) //ddrc_clock=12.5M
  452. {
  453. _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
  454. //_SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
  455. }
  456. else
  457. {
  458. _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
  459. }
  460. udelay(300);
  461. apb_write(PHY_APB_BASE_ADDR + (0 +0 << 2), 0x01);//release dll_rst_n
  462. udelay(300);
  463. orbit_boot(OMC_APB_BASE_ADDR, OMC_SECURE_APB_BASE_ADDR, PHY_APB_BASE_ADDR, ddr_num);
  464. //`endif
  465. }
  466. #if 1
  467. //while(1)
  468. {
  469. for(i = 0; i < 0x80000; i++)
  470. {
  471. writel(0xa5a5a5a5, 0x1000000000 + i *4);
  472. tmp = readl(0x1000000000 + i *4);
  473. if(tmp != 0xa5a5a5a5)
  474. {
  475. printk("error addr %d = 0x%x\r\n", i *4, tmp);
  476. fail_flag = -1;
  477. }
  478. writel(0x5a5a5a5a, 0x1000000000 + i *4);
  479. tmp = readl(0x1000000000 + i *4);
  480. if(tmp != 0x5a5a5a5a)
  481. {
  482. printk("error addr %d = 0x%x\r\n", i *4, tmp);
  483. fail_flag = -1;
  484. }
  485. writel(0x00000000, 0x1000000000 + i *4);
  486. tmp = readl(0x1000000000 + i *4);
  487. if(tmp != 0x00000000)
  488. {
  489. printk("error addr %d = 0x%x\r\n", i *4, tmp);
  490. fail_flag = -1;
  491. }
  492. writel(0xffffffff, 0x1000000000 + i *4);
  493. tmp = readl(0x1000000000 + i *4);
  494. if(tmp != 0xffffffff)
  495. {
  496. printk("error addr %d = 0x%x\r\n", i *4, tmp);
  497. fail_flag = -1;
  498. }
  499. if((i% 262144) == 0)
  500. {
  501. count++;
  502. printk("ddr 0x%x, %dM test\r\n",(i * 4), count);
  503. }
  504. }
  505. }
  506. #endif
  507. }
  508. /*only hartid 0 call this function*/
  509. void BootMain(void)
  510. {
  511. int boot_mode = 0;
  512. int ret=0;
  513. // gpio_init();
  514. uart_init(3);
  515. printk("\r\n");
  516. ret = init_ddr();
  517. if(ret == 0)
  518. {
  519. _SET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(1);
  520. #if defined(DDR_2133)
  521. printk("DDR clk 2133M,Version: %s\r\n",VERSION);
  522. #elif defined(DDR_2800)
  523. printk("DDR clk 2800M,Version: %s\r\n",VERSION);
  524. #elif defined(DDR_3200)
  525. printk("DDR clk 3200M,Version: %s\r\n",VERSION);
  526. #endif
  527. }
  528. else
  529. printk("End init lpddr4, test ddr fail\r\n");
  530. #if (UBOOT_EXEC_AT_NBDLA_2M == 1)
  531. printk("init nbdla 2M ram\r\n");
  532. _SET_SYSCON_REG_register16_SCFG_nbdla_clkgating_en(1);
  533. _ENABLE_CLOCK_clk_dla_axi_;
  534. _ENABLE_CLOCK_clk_dlanoc_axi_;
  535. _ENABLE_CLOCK_clk_dla_apb_;
  536. _ENABLE_CLOCK_clk_dlaslv_axi_;
  537. _CLEAR_RESET_rstgen_rstn_dla_axi_;
  538. _CLEAR_RESET_rstgen_rstn_dlanoc_axi_;
  539. _CLEAR_RESET_rstgen_rstn_dla_apb_;
  540. _CLEAR_RESET_rstgen_rstn_dlaslv_axi_;
  541. #endif /* UBOOT_EXEC_AT_NBDLA_2M */
  542. boot_from_chiplink();
  543. boot_mode = get_boot_mode();
  544. switch(boot_mode){
  545. case 0:
  546. boot_from_spi(1);
  547. break;
  548. case 1:
  549. boot_from_spi(4);
  550. break;
  551. case 2:
  552. boot_from_sdio();
  553. break;
  554. case 4:
  555. boot_from_uart();
  556. break;
  557. case 6:
  558. boot_from_chiplink();
  559. break;
  560. default:
  561. break;
  562. }
  563. printk("\r\nbootloader.\r\n");
  564. writel(0x1, 0x2000004);
  565. }