start.S 2.3 KB

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  1. /**
  2. ******************************************************************************
  3. * @file start.S
  4. * @author StarFive Technology
  5. * @version V1.0
  6. * @date 07/29/2020
  7. * @brief
  8. ******************************************************************************
  9. * @copy
  10. *
  11. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  12. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  13. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  14. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  15. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  16. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  17. *
  18. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  19. */
  20. #include "encoding.h"
  21. #include "platform.h"
  22. #include "sys.h"
  23. /* This is defined in sifive/platform.h, but that can't be included from
  24. * assembly. */
  25. .section .init
  26. .globl _start
  27. _start:
  28. la t0, trap_entry
  29. csrw mtvec, t0
  30. csrwi mstatus, 0
  31. csrwi mie, 0
  32. // Allocate 4 KiB stack for each hart
  33. csrr t0, mhartid
  34. slli t0, t0, 12
  35. la sp, _sp
  36. sub sp, sp, t0
  37. li a1, NONSMP_HART;
  38. csrr a0, mhartid;
  39. bne a0, a1, .LbootOtherHart //other hart
  40. // Load data section
  41. la t0, _data_lma
  42. la t1, _data
  43. beq t0, t1, 2f
  44. la t2, _edata
  45. bgeu t1, t2, 2f
  46. 1:
  47. ld t3, 0(t0)
  48. sd t3, 0(t1)
  49. addi t0, t0, 8
  50. addi t1, t1, 8
  51. bltu t1, t2, 1b
  52. 2:
  53. /* Clear bss section */
  54. la t1, _bss_start
  55. la t2, _bss_end
  56. bgeu t1, t2, 4f
  57. 3:
  58. sd x0, 0(t1)
  59. addi t1, t1, 8
  60. blt t1, t2, 3b
  61. 4:
  62. /*only hart 0*/
  63. call BootMain
  64. j .enter_uboot
  65. .LbootOtherHart:
  66. #if 0 //no need to clear
  67. li s1, CLINT_CTRL_ADDR
  68. csrr a0, mhartid
  69. slli s2, a0, 2
  70. add s2, s2, s1
  71. sw zero, 0(s2)
  72. fence
  73. csrw mip, 0
  74. #endif
  75. # core 1 jumps to main_other_hart
  76. # Set MSIE bit to receive IPI
  77. li a2, MIP_MSIP
  78. csrw mie, a2
  79. .LwaitOtherHart:
  80. # Wait for an IPI to signal that its safe to boot
  81. // call second_hart
  82. wfi
  83. # Only start if MIP_MSIP is set
  84. csrr a2, mip
  85. andi a2, a2, MIP_MSIP
  86. beqz a2, .LwaitOtherHart
  87. li s1, CLINT_CTRL_ADDR
  88. csrr a0, mhartid
  89. slli s2, a0, 2
  90. add s2, s2, s1
  91. sw zero, 0(s2)
  92. fence
  93. csrw mip, 0
  94. li a2, NUM_CORES
  95. bltu a0, a2, .enter_uboot
  96. j .LwaitOtherHart
  97. .enter_uboot:
  98. # Synchronize the instruction and data caches.
  99. fence.i
  100. li t0, DEFAULT_UBOOT_ADDR
  101. csrr a0, mhartid
  102. la a1, 0
  103. jr t0