start.S 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-or-later */
  2. /**
  3. ******************************************************************************
  4. * @file start.S
  5. * @author StarFive Technology
  6. * @version V1.0
  7. * @date 07/29/2020
  8. * @brief
  9. ******************************************************************************
  10. * @copy
  11. *
  12. * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
  13. * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
  14. * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY
  15. * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
  16. * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
  17. * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  18. *
  19. * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd.
  20. */
  21. #include "encoding.h"
  22. #include "platform.h"
  23. #include "sys.h"
  24. /* This is defined in sifive/platform.h, but that can't be included from
  25. * assembly. */
  26. .section .init
  27. .globl _start
  28. _start:
  29. la t0, trap_entry
  30. csrw mtvec, t0
  31. csrwi mstatus, 0
  32. csrwi mie, 0
  33. // Allocate 4 KiB stack for each hart
  34. csrr t0, mhartid
  35. slli t0, t0, 12
  36. la sp, _sp
  37. sub sp, sp, t0
  38. li a1, NONSMP_HART;
  39. csrr a0, mhartid;
  40. bne a0, a1, .LbootOtherHart //other hart
  41. // Load data section
  42. la t0, _data_lma
  43. la t1, _data
  44. beq t0, t1, 2f
  45. la t2, _edata
  46. bgeu t1, t2, 2f
  47. 1:
  48. ld t3, 0(t0)
  49. sd t3, 0(t1)
  50. addi t0, t0, 8
  51. addi t1, t1, 8
  52. bltu t1, t2, 1b
  53. 2:
  54. /* Clear bss section */
  55. la t1, _bss_start
  56. la t2, _bss_end
  57. bgeu t1, t2, 4f
  58. 3:
  59. sd x0, 0(t1)
  60. addi t1, t1, 8
  61. blt t1, t2, 3b
  62. 4:
  63. /*only hart 0*/
  64. call BootMain
  65. j .enter_uboot
  66. .LbootOtherHart:
  67. #if 0 //no need to clear
  68. li s1, CLINT_CTRL_ADDR
  69. csrr a0, mhartid
  70. slli s2, a0, 2
  71. add s2, s2, s1
  72. sw zero, 0(s2)
  73. fence
  74. csrw mip, 0
  75. #endif
  76. # core 1 jumps to main_other_hart
  77. # Set MSIE bit to receive IPI
  78. li a2, MIP_MSIP
  79. csrw mie, a2
  80. .LwaitOtherHart:
  81. # Wait for an IPI to signal that its safe to boot
  82. // call second_hart
  83. wfi
  84. # Only start if MIP_MSIP is set
  85. csrr a2, mip
  86. andi a2, a2, MIP_MSIP
  87. beqz a2, .LwaitOtherHart
  88. li s1, CLINT_CTRL_ADDR
  89. csrr a0, mhartid
  90. slli s2, a0, 2
  91. add s2, s2, s1
  92. sw zero, 0(s2)
  93. fence
  94. csrw mip, 0
  95. li a2, NUM_CORES
  96. bltu a0, a2, .enter_uboot
  97. j .LwaitOtherHart
  98. .enter_uboot:
  99. # Synchronize the instruction and data caches.
  100. fence.i
  101. li t0, DEFAULT_UBOOT_ADDR
  102. csrr a0, mhartid
  103. la a1, 0
  104. jr t0