/* SPDX-License-Identifier: GPL-2.0-or-later */ /** ****************************************************************************** * @file regconfig.h.sim_PI.h * @author StarFive Technology * @version V1.0 * @date 07/20/2020 * @brief ****************************************************************************** * @copy * * THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STARFIVE SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * COPYRIGHT 2020 Shanghai StarFive Technology Co., Ltd. */ #define DENALI_PI_00_DATA 0b00000000000000000000101100000000 // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00 #define DENALI_PI_01_DATA 0b00000000000000000000000100000001 // PI_ONBUS_MBIST:RW:24:1:=0x00 PI_NOTCARE_PHYUPD:RW:16:1:=0x00 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x01 #define DENALI_PI_02_DATA 0b00000000011001000000000000000000 // PI_TRAIN_ALL_FREQ_REQ:WR:24:1:=0x00 RESERVED:RW_D:16:8:=0x64 PI_TCMD_GAP:RW:0:16:=0x0000 #define DENALI_PI_03_DATA 0b00000000000000000000000000000001 // PI_DFI_PHYMSTR_STATE_SEL_R:RW:24:1:=0x00 PI_DFI_PHYMSTR_CS_STATE_R:RW:16:1:=0x00 PI_DFI_PHYMSTR_TYPE:RW:8:2:=0x00 PI_DFI_VERSION:RW:0:1:=0x01 #define DENALI_PI_04_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYMSTR_MAX:RD:0:32:=0x00000000 #define DENALI_PI_05_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYMSTR_RESP:RD:0:20:=0x000000 #define DENALI_PI_06_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYUPD_RESP:RD:0:20:=0x000000 #define DENALI_PI_07_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYUPD_MAX:RD:0:32:=0x00000000 #define DENALI_PI_08_DATA 0b00000000000000000000000000000001 // PI_EXIT_AFTER_INIT_CALVL:RW_D:0:1:=0x01 #define DENALI_PI_09_DATA 0b00000000000000000000000000000111 // PI_FREQ_MAP:RW:0:32:=0x00000007 #define DENALI_PI_10_DATA 0b00000000000000010000000000000010 // RESERVED:RW:24:1:=0x00 PI_SW_RST_N:RW_D:16:1:=0x01 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x02 #define DENALI_PI_11_DATA 0b00000011000000000000100000001111 // PI_PREAMBLE_SUPPORT:RW:24:2:=0x03 PI_TMPRR:RW:16:4:=0x00 PI_TMRR:RW:8:4:=0x08 PI_CS_MAP:RW:0:4:=0x0f #define DENALI_PI_12_DATA 0b00000000000000000000000000000001 // RESERVED:RW:8:1:=0x00 PI_MCAREF_FORWARD_ONLY:RW:0:1:=0x01 #define DENALI_PI_13_DATA 0b00000000000000000000000000000101 // PI_ON_DFIBUS:RD:24:1:=0x00 PI_TREF_INTERVAL:RW:0:20:=0x000005 #define DENALI_PI_14_DATA 0b00000000000000000000000000000000 // PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 PI_DATA_RETENTION:RD:0:1:=0x00 #define DENALI_PI_15_DATA 0b00000000000000000000000000000000 // PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00 #define DENALI_PI_16_DATA 0b00000000000000000000000000000000 // PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00 #define DENALI_PI_17_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00 #define DENALI_PI_18_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_0:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00 #define DENALI_PI_19_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_2:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_1:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00 #define DENALI_PI_20_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_3:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_2:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_2:WR:0:1:=0x00 #define DENALI_PI_21_DATA 0b00000000000000000000000000000000 // PI_SWLVL_SM2_START:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_3:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_3:WR:0:1:=0x00 #define DENALI_PI_22_DATA 0b00000000000000000000000000000000 // PI_DFS_PERIOD_EN:RW:24:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:16:1:=0x00 PI_SWLVL_SM2_RD:WR:8:1:=0x00 PI_SWLVL_SM2_WR:WR:0:1:=0x00 #define DENALI_PI_23_DATA 0b00000001000000010000000000000000 // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_DFI40_POLARITY:RW:16:1:=0x01 PI_MPD_PERIOD_EN:RW:8:1:=0x00 PI_SRE_PERIOD_EN:RW:0:1:=0x00 #define DENALI_PI_24_DATA 0b00101000000010100000000000000000 // PI_WLMRD:RW:24:6:=0x28 PI_WLDQSEN:RW:16:6:=0x0a PI_WRLVL_CS:RW:8:2:=0x00 PI_WRLVL_REQ:WR:0:1:=0x00 #define DENALI_PI_25_DATA 0b00000000000000000000000000000000 // PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000 #define DENALI_PI_26_DATA 0b00000000000000000000000000000001 // PI_WRLVL_ROTATE:RW:24:1:=0x00 PI_WRLVL_RESP_MASK:RW:16:4:=0x00 PI_WRLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WRLVL_ON_DPDX:RW:0:1:=0x01 #define DENALI_PI_27_DATA 0b00110010000000000000000000001111 // PI_TDFI_WRLVL_EN:RW:24:8:=0x32 PI_WRLVL_ERROR_STATUS:RD:16:1:=0x00 PI_WRLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_WRLVL_CS_MAP:RW:0:4:=0x0f #define DENALI_PI_28_DATA 0b00000000000000000000000000000000 // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000 #define DENALI_PI_29_DATA 0b00000000000000000000000000000000 // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000 #define DENALI_PI_30_DATA 0b00000000000000010000000100000010 // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_TODTH_RD:RW:16:4:=0x01 PI_TODTH_WR:RW:8:4:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02 #define DENALI_PI_31_DATA 0b00000000000000000000000000000001 // PI_ADDRESS_MIRRORING:RW:8:4:=0x00 PI_ODT_VALUE:RW:0:4:=0x01 #define DENALI_PI_32_DATA 0b00000000000000000000000000000000 // PI_CA_PARITY_ERROR_INJECT:RW:0:25:=0x00000000 #define DENALI_PI_33_DATA 0b00000000000000000000000000000000 // PI_RDLVL_GATE_REQ:WR:24:1:=0x00 PI_RDLVL_REQ:WR:16:1:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW+:0:3:=0x00 #define DENALI_PI_34_DATA 0b00000000000000000000000000000000 // PI_RDLVL_CS:RW:0:2:=0x00 #define DENALI_PI_35_DATA 0b00000000000000000000000010101010 // PI_RDLVL_PAT_0:RW:0:32:=0x000000aa #define DENALI_PI_36_DATA 0b00000000000000000000000001010101 // PI_RDLVL_PAT_1:RW:0:32:=0x00000055 #define DENALI_PI_37_DATA 0b00000000000000000000000010110101 // PI_RDLVL_PAT_2:RW:0:32:=0x000000b5 #define DENALI_PI_38_DATA 0b00000000000000000000000001001010 // PI_RDLVL_PAT_3:RW:0:32:=0x0000004a #define DENALI_PI_39_DATA 0b00000000000000000000000001010110 // PI_RDLVL_PAT_4:RW:0:32:=0x00000056 #define DENALI_PI_40_DATA 0b00000000000000000000000010101001 // PI_RDLVL_PAT_5:RW:0:32:=0x000000a9 #define DENALI_PI_41_DATA 0b00000000000000000000000010101001 // PI_RDLVL_PAT_6:RW:0:32:=0x000000a9 #define DENALI_PI_42_DATA 0b00000000000000000000000010110101 // PI_RDLVL_PAT_7:RW:0:32:=0x000000b5 #define DENALI_PI_43_DATA 0b00000001000000000000000000000000 // PI_RDLVL_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_SEQ_EN:RW:0:4:=0x00 #define DENALI_PI_44_DATA 0b00000001000000000000000000000000 // PI_RDLVL_GATE_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_GATE_PERIODIC:RW:8:1:=0x00 PI_RDLVL_DISABLE_DFS:RW:0:1:=0x00 #define DENALI_PI_45_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 PI_RDLVL_GATE_ON_MPD_EXIT:RW:16:1:=0x00 PI_RDLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_RDLVL_GATE_DISABLE_DFS:RW:0:1:=0x00 #define DENALI_PI_46_DATA 0b00001111000011110000000000000000 // PI_RDLVL_GATE_CS_MAP:RW:24:4:=0x0f PI_RDLVL_CS_MAP:RW:16:4:=0x0f PI_RDLVL_GATE_ROTATE:RW:8:1:=0x00 PI_RDLVL_ROTATE:RW:0:1:=0x00 #define DENALI_PI_47_DATA 0b00000000000000000000000000010100 // PI_TDFI_RDLVL_RR:RW:0:10:=0x0014 #define DENALI_PI_48_DATA 0b00000000000000000000011111010000 // PI_TDFI_RDLVL_RESP:RW:0:32:=0x000007d0 #define DENALI_PI_49_DATA 0b00000000000000000000001100000000 // PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00 #define DENALI_PI_50_DATA 0b00000000000000000000000000000000 // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000 #define DENALI_PI_51_DATA 0b00000000000000000000000000000000 // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:1:=0x00 #define DENALI_PI_52_DATA 0b00000001000000000000000000000000 // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000 #define DENALI_PI_53_DATA 0b00000000000000010000000100000001 // PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01 #define DENALI_PI_54_DATA 0b00000000000000000000000000000000 // PI_CALVL_CS:RW:24:2:=0x00 PI_CALVL_REQ:WR:16:1:=0x00 PI_TDFI_PHY_WRLAT:RD:8:8:=0x00 PI_TDFI_RDDATA_EN:RD:0:8:=0x00 #define DENALI_PI_55_DATA 0b00000000000000110000000000000000 // PI_CALVL_PERIODIC:RW:24:1:=0x00 PI_CALVL_SEQ_EN:RW:16:2:=0x03 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_56_DATA 0b00000000000000000000000100000000 // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_DISABLE_DFS:RW:16:1:=0x00 PI_CALVL_ON_DPDX:RW:8:1:=0x01 PI_CALVL_ON_SREF_EXIT:RW:0:1:=0x00 #define DENALI_PI_57_DATA 0b00000000000000000001011100001111 // PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x0f #define DENALI_PI_58_DATA 0b00000000000000000000000000000000 // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000 #define DENALI_PI_59_DATA 0b00000000000000000000000000000000 // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000 #define DENALI_PI_60_DATA 0b00000000000000000000000000000000 // PI_CALVL_INTERVAL:RW:16:16:=0x0000 PI_CALVL_ERROR_STATUS:RD:8:2:=0x00 PI_CALVL_RESP_MASK:RW:0:1:=0x00 #define DENALI_PI_61_DATA 0b00001010000101000000101000000001 // PI_TCACKEH:RW:24:5:=0x0a PI_TCAMRD:RW:16:6:=0x14 PI_TCACKEL:RW:8:5:=0x0a PI_CALVL_MAX_STROBE_PEND:RW:0:4:=0x01 #define DENALI_PI_62_DATA 0b00000010000001000000000100001010 // PI_CALVL_VREF_NORMAL_STEPSIZE:RW:24:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:16:4:=0x04 PI_CA_TRAIN_VREF_EN:RW:8:1:=0x01 PI_TCAEXT:RW:0:5:=0x0a #define DENALI_PI_63_DATA 0b00000010000010000000010100010000 // PI_CALVL_STROBE_NUM:RW:24:5:=0x02 PI_TCKCKEH:RW:16:4:=0x08 PI_TDFI_INIT_COMPLETE_MIN:RW:8:8:=0x05 PI_TDFI_INIT_START_MIN:RW:0:8:=0x10 #define DENALI_PI_64_DATA 0b00000000000001000000010000000000 // PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:24:1:=0x00 PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:16:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:8:8:=0x04 PI_SW_CA_TRAIN_VREF:RW:0:7:=0x00 #define DENALI_PI_65_DATA 0b00000001000000000000000100000001 // PI_VREFLVL_DISABLE_DFS:RW:24:1:=0x01 PI_VREF_PDA_EN:RW:16:1:=0x00 PI_VREF_CS:RW:8:2:=0x01 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:0:1:=0x01 #define DENALI_PI_66_DATA 0b00000000000000010000000100000000 // PI_WDQLVL_RESP_MASK:RW:24:4:=0x00 PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_MC_DFS_PI_SET_VREF_ENABLE:RW:0:1:=0x00 #define DENALI_PI_67_DATA 0b00000010000001000000111100000000 // PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:24:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:16:5:=0x04 PI_WDQLVL_CS_MAP:RW:8:4:=0x0f PI_WDQLVL_ROTATE:RW:0:1:=0x00 #define DENALI_PI_68_DATA 0b00110100000000000000000000000000 // PI_TDFI_WDQLVL_EN:RW:24:8:=0x34 PI_WDQLVL_CS:RW:16:2:=0x00 PI_WDQLVL_REQ:WR:8:1:=0x00 PI_WDQLVL_PERIODIC:RW:0:1:=0x00 #define DENALI_PI_69_DATA 0b00000000000000000000000000000000 // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000 #define DENALI_PI_70_DATA 0b00000000000000000000000000000000 // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000 #define DENALI_PI_71_DATA 0b00000001000000000000000000000000 // PI_WDQLVL_ON_DPDX:RW:24:1:=0x01 PI_WDQLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000 #define DENALI_PI_72_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_NEED_SAVE_RESTORE:RW:24:2:=0x00 PI_WDQLVL_ERROR_STATUS:RD:16:2:=0x00 PI_WDQLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WDQLVL_ON_MPD_EXIT:RW:0:1:=0x00 #define DENALI_PI_73_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00000000 #define DENALI_PI_74_DATA 0b00000000000000000000000000000000 // PI_NO_MEMORY_DM:RW:16:1:=0x00 PI_WDQLVL_DM_LEVEL_EN:RW:8:1:=0x00 PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00 #define DENALI_PI_75_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_NIBBLE_MODE:RW:24:1:=0x00 PI_SWLVL_SM2_DM_NIBBLE_START:WR:16:1:=0x00 PI_TDFI_WDQLVL_WW:RW:0:10:=0x0000 #define DENALI_PI_76_DATA 0b00000000000000010000000100000000 // PI_DBILVL_RESP_MASK:RW:24:4:=0x00 PI_PARALLEL_WDQLVL_EN:RW:16:1:=0x01 PI_WDQLVL_PDA_VREF_TRAIN:RW:8:1:=0x01 PI_WDQLVL_PDA_EN:RW:0:1:=0x00 #define DENALI_PI_77_DATA 0b00000000000010000000000100000001 // RESERVED:RW_D:24:4:=0x00 PI_TCCD:RW:16:5:=0x08 PI_ROW_DIFF:RW:8:3:=0x01 PI_BANK_DIFF:RW:0:2:=0x01 #define DENALI_PI_78_DATA 0b00000010000000000000001000000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 #define DENALI_PI_79_DATA 0b00000001000000000000000100000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00 #define DENALI_PI_80_DATA 0b00000001000000000000000000000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00 #define DENALI_PI_81_DATA 0b00000010000000000000001000000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 #define DENALI_PI_82_DATA 0b00000000000000000000001000000000 // RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00 #define DENALI_PI_83_DATA 0b00000000000000000000000000000000 // PI_INT_STATUS:RD:0:28:=0x00000000 #define DENALI_PI_84_DATA 0b00000000000000000000000000000000 // PI_INT_ACK:WR:0:27:=0x00000000 #define DENALI_PI_85_DATA 0b00000000000000000000000000000000 // PI_INT_MASK:RW:0:28:=0x00000000 #define DENALI_PI_86_DATA 0b00001110000000000000000000000100 // PI_PARITY_IN_MUX:RW_D:24:5:=0x0e PI_CMD_SWAP_EN:RW_D:16:1:=0x00 PI_LONG_COUNT_MASK:RW:8:5:=0x00 PI_BSTLEN:RW_D:0:5:=0x04 #define DENALI_PI_87_DATA 0b00001100000011010001000000001111 // PI_CAS_N_MUX:RW_D:24:5:=0x0c PI_RAS_N_MUX:RW_D:16:5:=0x0d PI_A14_MUX:RW_D:8:5:=0x10 PI_A15_MUX:RW_D:0:5:=0x0f #define DENALI_PI_88_DATA 0b00001010000010010000100000001011 // PI_BANK_MUX_2:RW_D:24:5:=0x0a PI_BANK_MUX_1:RW_D:16:5:=0x09 PI_BANK_MUX_0:RW_D:8:5:=0x08 PI_WE_N_MUX:RW_D:0:5:=0x0b #define DENALI_PI_89_DATA 0b00000010000000010000000000000000 // PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00 #define DENALI_PI_90_DATA 0b00000000000010000000000100000011 // PI_UPDATE_ERROR_STATUS:RD:24:2:=0x00 PI_TDFI_CTRLUPD_MIN:RW:16:8:=0x08 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03 #define DENALI_PI_91_DATA 0b00000000000000000000001000000000 // PI_SELF_REFRESH_EN:RW:24:1:=0x00 PI_BG_ROTATE_EN:RW:16:1:=0x00 PI_COL_DIFF:RW:8:4:=0x02 PI_TDFI_PARIN_LAT:RW:0:3:=0x00 #define DENALI_PI_92_DATA 0b00000000000000000000000000000000 // PI_NO_MRW_BT_INIT:RW:24:1:=0x00 PI_SREF_ENTRY_REQ:WR:16:1:=0x00 PI_SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PI_PWRUP_SREFRESH_EXIT:RW+:0:1:=0x00 #define DENALI_PI_93_DATA 0b00001111000000000000000000000000 // PI_PWRUP_SREFRESH_EXIT_CS:RW:24:4:=0x0f PI_NO_AUTO_MRR_INIT:RW:16:1:=0x00 PI_NO_PHY_IND_TRAIN_INIT:RW:8:1:=0x00 PI_NO_MRW_INIT:RW:0:1:=0x00 #define DENALI_PI_94_DATA 0b00000000000000000000000000000100 // PI_TRST_PWRON:RW:0:32:=0x00000004 #define DENALI_PI_95_DATA 0b00000000000000000000000000001010 // PI_CKE_INACTIVE:RW:0:32:=0x0000000a #define DENALI_PI_96_DATA 0b00000000000000000000000000000000 // PI_DLL_RST_DELAY:RW:16:16:=0x0000 PI_DRAM_INIT_EN:RW:8:1:=0x00 PI_DLL_RST:RW:0:1:=0x00 #define DENALI_PI_97_DATA 0b00000000000000000000000000000000 // PI_DLL_RST_ADJ_DLY:RW:0:8:=0x00 #define DENALI_PI_98_DATA 0b00000000000000000000000000000000 // PI_WRITE_MODEREG:RW+:0:26:=0x00000000 #define DENALI_PI_99_DATA 0b00000000000000000000000000000000 // RESERVED:RW:8:1:=0x00 PI_MRW_STATUS:RD:0:8:=0x00 #define DENALI_PI_100_DATA 0b00000000000000000000000000000000 // PI_READ_MODEREG:RW+:0:17:=0x000000 #define DENALI_PI_101_DATA 0b00000000000000000000000000000000 // PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000 #define DENALI_PI_102_DATA 0b00000000000000000000000000000000 // RESERVED:WR:24:4:=0x00 RESERVED:RW:16:4:=0x00 PI_NO_ZQ_INIT:RW:8:1:=0x00 PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00 #define DENALI_PI_103_DATA 0b00000000000000110000000100000000 // PI_MONITOR_SRC_SEL_0:RW:24:4:=0x00 RESERVED:RW:16:3:=0x03 RESERVED:RW:8:1:=0x01 PI_ZQ_REQ_PENDING:RD:0:1:=0x00 #define DENALI_PI_104_DATA 0b00000001000000010000000000000001 // PI_MONITOR_CAP_SEL_1:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_1:RW:16:4:=0x01 PI_MONITOR_0:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_0:RW:0:1:=0x01 #define DENALI_PI_105_DATA 0b00000000000000010000001000000000 // PI_MONITOR_2:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_2:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_2:RW:8:4:=0x02 PI_MONITOR_1:RD:0:8:=0x00 #define DENALI_PI_106_DATA 0b00000100000000000000000100000011 // PI_MONITOR_SRC_SEL_4:RW:24:4:=0x04 PI_MONITOR_3:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_3:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_3:RW:0:4:=0x03 #define DENALI_PI_107_DATA 0b00000001000001010000000000000001 // PI_MONITOR_CAP_SEL_5:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_5:RW:16:4:=0x05 PI_MONITOR_4:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_4:RW:0:1:=0x01 #define DENALI_PI_108_DATA 0b00000000000000010000011000000000 // PI_MONITOR_6:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_6:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_6:RW:8:4:=0x06 PI_MONITOR_5:RD:0:8:=0x00 #define DENALI_PI_109_DATA 0b00000000000000000000000100000111 // PI_MONITOR_7:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_7:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_7:RW:0:4:=0x07 #define DENALI_PI_110_DATA 0b00000000000000000000000000000000 // PI_MONITOR_STROBE:WR:0:8:=0x00 #define DENALI_PI_111_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 PI_FREQ_RETENTION_NUM:RW+:16:5:=0x00 PI_FREQ_NUMBER_STATUS:RD:8:5:=0x00 PI_DLL_LOCK:RD:0:1:=0x00 #define DENALI_PI_112_DATA 0b00000000000000010000000000000001 // RESERVED:RW:24:1:=0x00 PI_POWER_REDUC_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PI_PHYMSTR_TYPE:RW:0:2:=0x01 #define DENALI_PI_113_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_114_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_115_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_116_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_117_DATA 0b00000000000000010000000000000000 // PI_WRLVL_MAX_STROBE_PEND:RW:16:8:=0x01 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00 #define DENALI_PI_118_DATA 0b00000000000000000000000000000100 // PI_TREFBW_THR:RW:0:9:=0x0004 #define DENALI_PI_119_DATA 0b00000000000000000000000000000000 // PI_FREQ_CHANGE_REG_COPY:RW:0:5:=0x00 #define DENALI_PI_120_DATA 0b00000000000000010000000000000000 // PI_CATR:RW:24:4:=0x00 PI_PARALLEL_CALVL_EN:RW:16:1:=0x01 RESERVED:RW:8:5:=0x00 PI_FREQ_SEL_FROM_REGIF:RW:0:1:=0x00 #define DENALI_PI_121_DATA 0b00000000000000000000000000000000 // PI_NOTCARE_MC_INIT_START:RW:24:1:=0x00 PI_DISCONNECT_MC:RW:16:1:=0x00 PI_MASK_INIT_COMPLETE:RW:8:1:=0x00 PI_NO_CATR_READ:RW:0:1:=0x00 #define DENALI_PI_122_DATA 0b00000000001111000000000000000011 // PI_TVREF_F1:RW:16:16:=0x003c PI_TVREF_F0:RW:0:16:=0x0003 #define DENALI_PI_123_DATA 0b00001000000000010000000011001000 // PI_TSDO_F1:RW:24:8:=0x08 PI_TSDO_F0:RW:16:8:=0x01 PI_TVREF_F2:RW:0:16:=0x00c8 #define DENALI_PI_124_DATA 0b00000000000000000000000000011011 // PI_TSDO_F2:RW:0:8:=0x1b #define DENALI_PI_125_DATA 0b00000000000000000000000000101100 // PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x2c #define DENALI_PI_126_DATA 0b00000000000000000000000000110011 // PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:0:8:=0x33 #define DENALI_PI_127_DATA 0b00000000000000100000000001001001 // PI_ZQINIT_F0:RW_D:8:12:=0x0200 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:0:8:=0x49 #define DENALI_PI_128_DATA 0b00000010000000000000001000000000 // PI_ZQINIT_F2:RW_D:16:12:=0x0200 PI_ZQINIT_F1:RW_D:0:12:=0x0200 #define DENALI_PI_129_DATA 0b00000000000000000000000000000100 // PI_TPARITY_ERROR_CMD_INHIBIT_F0:RW:24:8:=0x00 PI_CA_PARITY_LAT_F0:RW:16:4:=0x00 PI_ADDITIVE_LAT_F0:RW:8:6:=0x00 PI_WRLAT_F0:RW:0:7:=0x04 #define DENALI_PI_130_DATA 0b00000000000000000000011000001100 // PI_CA_PARITY_LAT_F1:RW:24:4:=0x00 PI_ADDITIVE_LAT_F1:RW:16:6:=0x00 PI_WRLAT_F1:RW:8:7:=0x06 PI_CASLAT_LIN_F0:RW:0:7:=0x0c #define DENALI_PI_131_DATA 0b00000000000011000001010000000000 // PI_ADDITIVE_LAT_F2:RW:24:6:=0x00 PI_WRLAT_F2:RW:16:7:=0x0c PI_CASLAT_LIN_F1:RW:8:7:=0x14 PI_TPARITY_ERROR_CMD_INHIBIT_F1:RW:0:8:=0x00 #define DENALI_PI_132_DATA 0b00000000001100000000000000000000 // PI_CASLAT_LIN_F2:RW:16:7:=0x30 PI_TPARITY_ERROR_CMD_INHIBIT_F2:RW:8:8:=0x00 PI_CA_PARITY_LAT_F2:RW:0:4:=0x00 #define DENALI_PI_133_DATA 0b00000000000000000000000000000110 // PI_TRFC_F0:RW:0:10:=0x0006 #define DENALI_PI_134_DATA 0b00000000000000000000000001000110 // PI_TREF_F0:RW:0:20:=0x000046 #define DENALI_PI_135_DATA 0b00000000000000000000000001110000 // PI_TRFC_F1:RW:0:10:=0x0070 #define DENALI_PI_136_DATA 0b00000000000000000000011000010000 // PI_TREF_F1:RW:0:20:=0x000610 #define DENALI_PI_137_DATA 0b00000000000000000000000101110110 // PI_TRFC_F2:RW:0:10:=0x0176 #define DENALI_PI_138_DATA 0b00000100000000000001010001001000 // PI_TDFI_CTRL_DELAY_F0:RW_D:24:4:=0x04 PI_TREF_F2:RW:0:20:=0x001448 #define DENALI_PI_139_DATA 0b00000001000000010000010000000100 // PI_WRLVL_EN_F1:RW:24:2:=0x01 PI_WRLVL_EN_F0:RW:16:2:=0x01 PI_TDFI_CTRL_DELAY_F2:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x04 #define DENALI_PI_140_DATA 0b00000000000000000010000100000001 // PI_TDFI_WRLVL_WW_F0:RW:8:10:=0x0021 PI_WRLVL_EN_F2:RW:0:2:=0x01 #define DENALI_PI_141_DATA 0b00000000001000010000000000100001 // PI_TDFI_WRLVL_WW_F2:RW:16:10:=0x0021 PI_TDFI_WRLVL_WW_F1:RW:0:10:=0x0021 #define DENALI_PI_142_DATA 0b00000001000000000000000100000000 // PI_ODT_EN_F1:RW:24:1:=0x01 PI_TODTL_2CMD_F1:RW:16:8:=0x00 PI_ODT_EN_F0:RW:8:1:=0x01 PI_TODTL_2CMD_F0:RW:0:8:=0x00 #define DENALI_PI_143_DATA 0b00000000000000000000000100000000 // PI_TODTON_MIN_F0:RW:24:4:=0x00 PI_ODTLON_F0:RW:16:4:=0x00 PI_ODT_EN_F2:RW:8:1:=0x01 PI_TODTL_2CMD_F2:RW:0:8:=0x00 #define DENALI_PI_144_DATA 0b00000000000000000000000000000000 // PI_TODTON_MIN_F2:RW:24:4:=0x00 PI_ODTLON_F2:RW:16:4:=0x00 PI_TODTON_MIN_F1:RW:8:4:=0x00 PI_ODTLON_F1:RW:0:4:=0x00 #define DENALI_PI_145_DATA 0b00000101000001110000010000000011 // PI_RD_TO_ODTH_F0:RW:24:6:=0x05 PI_WR_TO_ODTH_F2:RW:16:6:=0x07 PI_WR_TO_ODTH_F1:RW:8:6:=0x04 PI_WR_TO_ODTH_F0:RW:0:6:=0x03 #define DENALI_PI_146_DATA 0b00000001000000010001010000001000 // PI_RDLVL_GATE_EN_F0:RW:24:2:=0x01 PI_RDLVL_EN_F0:RW:16:2:=0x01 PI_RD_TO_ODTH_F2:RW:8:6:=0x14 PI_RD_TO_ODTH_F1:RW:0:6:=0x08 #define DENALI_PI_147_DATA 0b00000001000000010000000100000001 // PI_RDLVL_GATE_EN_F2:RW:24:2:=0x01 PI_RDLVL_EN_F2:RW:16:2:=0x01 PI_RDLVL_GATE_EN_F1:RW:8:2:=0x01 PI_RDLVL_EN_F1:RW:0:2:=0x01 #define DENALI_PI_148_DATA 0b00000000000100110000101000001010 // PI_RDLVL_PAT0_EN_F0:RW:24:2:=0x00 PI_TWR_MPR_F2:RW:16:8:=0x13 PI_TWR_MPR_F1:RW:8:8:=0x0a PI_TWR_MPR_F0:RW:0:8:=0x0a #define DENALI_PI_149_DATA 0b00000000000000000000000000000000 // PI_RDLVL_PAT0_EN_F1:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F0:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F0:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F0:RW:0:2:=0x00 #define DENALI_PI_150_DATA 0b00000000000000000000000000000000 // PI_RDLVL_PAT0_EN_F2:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F1:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F1:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F1:RW:0:2:=0x00 #define DENALI_PI_151_DATA 0b00000100000000000000000000000000 // PI_RDLAT_ADJ_F0:RW:24:8:=0x04 PI_RDLVL_MULTI_EN_F2:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F2:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F2:RW:0:2:=0x00 #define DENALI_PI_152_DATA 0b00000100000000100001010000001000 // PI_WRLAT_ADJ_F1:RW:24:8:=0x04 PI_WRLAT_ADJ_F0:RW:16:8:=0x02 PI_RDLAT_ADJ_F2:RW:8:8:=0x14 PI_RDLAT_ADJ_F1:RW:0:8:=0x08 #define DENALI_PI_153_DATA 0b00000100000000100000001000001000 // PI_TDFI_PHY_WRDATA_F2:RW:24:3:=0x04 PI_TDFI_PHY_WRDATA_F1:RW:16:3:=0x02 PI_TDFI_PHY_WRDATA_F0:RW:8:3:=0x02 PI_WRLAT_ADJ_F2:RW:0:8:=0x08 #define DENALI_PI_154_DATA 0b00000000000011000000000000110100 // PI_TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x000c PI_TDFI_CALVL_CC_F0:RW:0:10:=0x0034 #define DENALI_PI_155_DATA 0b00000000000100000000000000111000 // PI_TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x0010 PI_TDFI_CALVL_CC_F1:RW:0:10:=0x0038 #define DENALI_PI_156_DATA 0b00000000000110010000000001000001 // PI_TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x0019 PI_TDFI_CALVL_CC_F2:RW:0:10:=0x0041 #define DENALI_PI_157_DATA 0b00000000000000010000000000000001 // PI_CALVL_AREF_LP3_EN_F1:RW:24:1:=0x00 PI_CALVL_EN_F1:RW:16:2:=0x01 PI_CALVL_AREF_LP3_EN_F0:RW:8:1:=0x00 PI_CALVL_EN_F0:RW:0:2:=0x01 #define DENALI_PI_158_DATA 0b00000000000000010000000000000001 // PI_TMRZ_F0:RW:16:5:=0x01 PI_CALVL_AREF_LP3_EN_F2:RW:8:1:=0x00 PI_CALVL_EN_F2:RW:0:2:=0x01 #define DENALI_PI_159_DATA 0b00000000000000010000000000000101 // PI_TMRZ_F1:RW:16:5:=0x01 PI_TCAENT_F0:RW:0:14:=0x0005 #define DENALI_PI_160_DATA 0b00000000000000100000000001100100 // PI_TMRZ_F2:RW:16:5:=0x02 PI_TCAENT_F1:RW:0:14:=0x0064 #define DENALI_PI_161_DATA 0b00000001000000000000000101001110 // PI_TDFI_CASEL_F0:RW:24:5:=0x01 PI_TDFI_CACSCA_F0:RW:16:5:=0x00 PI_TCAENT_F2:RW:0:14:=0x014e #define DENALI_PI_162_DATA 0b00000000000001100000000000000110 // PI_TVREF_LONG_F0:RW:16:10:=0x0006 PI_TVREF_SHORT_F0:RW:0:10:=0x0006 #define DENALI_PI_163_DATA 0b00000000011001010000000100000000 // PI_TVREF_SHORT_F1:RW:16:10:=0x0065 PI_TDFI_CASEL_F1:RW:8:5:=0x01 PI_TDFI_CACSCA_F1:RW:0:5:=0x00 #define DENALI_PI_164_DATA 0b00000001000000000000000001100101 // PI_TDFI_CASEL_F2:RW:24:5:=0x01 PI_TDFI_CACSCA_F2:RW:16:5:=0x00 PI_TVREF_LONG_F1:RW:0:10:=0x0065 #define DENALI_PI_165_DATA 0b00000001010011110000000101001111 // PI_TVREF_LONG_F2:RW:16:10:=0x014f PI_TVREF_SHORT_F2:RW:0:10:=0x014f #define DENALI_PI_166_DATA 0b00011110000110100001111000011010 // PI_CALVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_CALVL_VREF_INITIAL_STOP_POINT_F0:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F0:RW:0:7:=0x1a #define DENALI_PI_167_DATA 0b00000001000000010001111000011010 // PI_CALVL_VREF_DELTA_F1:RW:24:4:=0x01 PI_CALVL_VREF_DELTA_F0:RW:16:4:=0x01 PI_CALVL_VREF_INITIAL_STOP_POINT_F2:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F2:RW:0:7:=0x1a #define DENALI_PI_168_DATA 0b00001010000001110000011000000001 // PI_TMRWCKEL_F0:RW:24:8:=0x0a PI_TXP_F0:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_CALVL_VREF_DELTA_F2:RW:0:4:=0x01 #define DENALI_PI_169_DATA 0b00001010000001110000011000001101 // PI_TMRWCKEL_F1:RW:24:8:=0x0a PI_TXP_F1:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F1:RW:8:4:=0x06 PI_TCKELCK_F0:RW:0:5:=0x0d #define DENALI_PI_170_DATA 0b00010100000011010000100000001101 // PI_TMRWCKEL_F2:RW:24:8:=0x14 PI_TXP_F2:RW:16:5:=0x0d PI_TDFI_CALVL_STROBE_F2:RW:8:4:=0x08 PI_TCKELCK_F1:RW:0:5:=0x0d #define DENALI_PI_171_DATA 0b00000000000000001100000000010000 // PI_TDFI_INIT_START_F0:RW:8:10:=0x00c0 PI_TCKELCK_F2:RW:0:5:=0x10 #define DENALI_PI_172_DATA 0b00000000110000000001000000000000 // PI_TDFI_INIT_START_F1:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000 #define DENALI_PI_173_DATA 0b00000000110000000001000000000000 // PI_TDFI_INIT_START_F2:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000 #define DENALI_PI_174_DATA 0b00000000000000100001000000000000 // PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000 #define DENALI_PI_175_DATA 0b00000000000100100000000000000101 // PI_TCKEHDQS_F1:RW:16:6:=0x12 PI_TFC_F0:RW:0:10:=0x0005 #define DENALI_PI_176_DATA 0b00000000000111000000000001100100 // PI_TCKEHDQS_F2:RW:16:6:=0x1c PI_TFC_F1:RW:0:10:=0x0064 #define DENALI_PI_177_DATA 0b00000000000000000000000101001110 // PI_VREF_EN_F1:RW:24:2:=0x00 PI_VREF_EN_F0:RW:16:2:=0x00 PI_TFC_F2:RW:0:10:=0x014e #define DENALI_PI_178_DATA 0b00000000000000000001000100000000 // PI_TDFI_WDQLVL_WR_F0:RW:8:10:=0x0011 PI_VREF_EN_F2:RW:0:2:=0x00 #define DENALI_PI_179_DATA 0b00011110000110100000000001010110 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F0:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F0:RW:0:10:=0x0056 #define DENALI_PI_180_DATA 0b00000110000000000000000100000001 // PI_WDQLVL_CL_F0:RW:24:5:=0x06 PI_NTP_TRAIN_EN_F0:RW:16:2:=0x00 PI_WDQLVL_EN_F0:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F0:RW:0:4:=0x01 #define DENALI_PI_181_DATA 0b00000000000100110000001000000100 // PI_TDFI_WDQLVL_WR_F1:RW:16:10:=0x0013 PI_WDQLVL_WRLAT_ADJ_F0:RW:8:8:=0x02 PI_WDQLVL_RDLAT_ADJ_F0:RW:0:8:=0x04 #define DENALI_PI_182_DATA 0b00011110000110100000000001011000 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F1:RW:0:10:=0x0058 #define DENALI_PI_183_DATA 0b00000001000000000000000100000001 // PI_WDQLVL_CL_F1:RW:24:5:=0x01 PI_NTP_TRAIN_EN_F1:RW:16:2:=0x00 PI_WDQLVL_EN_F1:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F1:RW:0:4:=0x01 #define DENALI_PI_184_DATA 0b00000000001010000000010000001000 // PI_TDFI_WDQLVL_WR_F2:RW:16:10:=0x0028 PI_WDQLVL_WRLAT_ADJ_F1:RW:8:8:=0x04 PI_WDQLVL_RDLAT_ADJ_F1:RW:0:8:=0x08 #define DENALI_PI_185_DATA 0b00011110000110100000000001100000 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F2:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F2:RW:0:10:=0x0060 #define DENALI_PI_186_DATA 0b00001011000000000000000100000001 // PI_WDQLVL_CL_F2:RW:24:5:=0x0b PI_NTP_TRAIN_EN_F2:RW:16:2:=0x00 PI_WDQLVL_EN_F2:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F2:RW:0:4:=0x01 #define DENALI_PI_187_DATA 0b00000000000000000000100000010100 // PI_RD_DBI_LEVEL_EN_F1:RW:24:2:=0x00 PI_RD_DBI_LEVEL_EN_F0:RW:16:2:=0x00 PI_WDQLVL_WRLAT_ADJ_F2:RW:8:8:=0x08 PI_WDQLVL_RDLAT_ADJ_F2:RW:0:8:=0x14 #define DENALI_PI_188_DATA 0b00000100000001000000100000000000 // PI_TRCD_F0:RW:24:8:=0x04 PI_TRP_F0:RW:16:8:=0x04 PI_TRTP_F0:RW:8:8:=0x08 PI_RD_DBI_LEVEL_EN_F2:RW:0:2:=0x00 #define DENALI_PI_189_DATA 0b00000000000001000000000100000000 // PI_TWR_F0:RW:16:8:=0x04 PI_TWTR_F0:RW:8:6:=0x01 PI_TCCD_L_F0:RW:0:5:=0x00 #define DENALI_PI_190_DATA 0b00000011000000000000001001110111 // PI_TRAS_MIN_F0:RW:24:8:=0x03 PI_TRAS_MAX_F0:RW:0:20:=0x000277 #define DENALI_PI_191_DATA 0b00001010000000110010000000000001 // PI_TMRD_F0:RW:24:8:=0x0a PI_TSR_F0:RW:16:8:=0x03 PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01 #define DENALI_PI_192_DATA 0b00000000000000000000101000001010 // PI_TMRD_PAR_F0:RW:24:8:=0x00 PI_TMOD_PAR_F0:RW:16:8:=0x00 PI_TMOD_F0:RW:8:8:=0x0a PI_TMRW_F0:RW:0:8:=0x0a #define DENALI_PI_193_DATA 0b00000000000010000000100100001000 // PI_TCCD_L_F1:RW:24:5:=0x00 PI_TRCD_F1:RW:16:8:=0x08 PI_TRP_F1:RW:8:8:=0x09 PI_TRTP_F1:RW:0:8:=0x08 #define DENALI_PI_194_DATA 0b00000000000000000000100100000001 // PI_TWR_F1:RW:8:8:=0x09 PI_TWTR_F1:RW:0:6:=0x01 #define DENALI_PI_195_DATA 0b00010001000000000011000101011100 // PI_TRAS_MIN_F1:RW:24:8:=0x11 PI_TRAS_MAX_F1:RW:0:20:=0x00315c #define DENALI_PI_196_DATA 0b00001010000001100010000000000010 // PI_TMRD_F1:RW:24:8:=0x0a PI_TSR_F1:RW:16:8:=0x06 PI_TCCDMW_F1:RW:8:6:=0x20 PI_TDQSCK_MAX_F1:RW:0:4:=0x02 #define DENALI_PI_197_DATA 0b00000000000000000000101000001010 // PI_TMRD_PAR_F1:RW:24:8:=0x00 PI_TMOD_PAR_F1:RW:16:8:=0x00 PI_TMOD_F1:RW:8:8:=0x0a PI_TMRW_F1:RW:0:8:=0x0a #define DENALI_PI_198_DATA 0b00000000000110000001110000001010 // PI_TCCD_L_F2:RW:24:5:=0x00 PI_TRCD_F2:RW:16:8:=0x18 PI_TRP_F2:RW:8:8:=0x1c PI_TRTP_F2:RW:0:8:=0x0a #define DENALI_PI_199_DATA 0b00000000000000000001100100010000 // PI_TWR_F2:RW:8:8:=0x19 PI_TWTR_F2:RW:0:6:=0x10 #define DENALI_PI_200_DATA 0b00111000000000001010010010001000 // PI_TRAS_MIN_F2:RW:24:8:=0x38 PI_TRAS_MAX_F2:RW:0:20:=0x00a488 #define DENALI_PI_201_DATA 0b00010011000101000010000000000101 // PI_TMRD_F2:RW:24:8:=0x13 PI_TSR_F2:RW:16:8:=0x14 PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x05 #define DENALI_PI_202_DATA 0b00000000000000000001001100001110 // PI_TMRD_PAR_F2:RW:24:8:=0x00 PI_TMOD_PAR_F2:RW:16:8:=0x00 PI_TMOD_F2:RW:8:8:=0x13 PI_TMRW_F2:RW:0:8:=0x0e #define DENALI_PI_203_DATA 0b00000000000000000000000010001100 // PI_TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x00008c #define DENALI_PI_204_DATA 0b00000000000000000000010101111000 // PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578 #define DENALI_PI_205_DATA 0b00000000000000000000110000100000 // PI_TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x000c20 #define DENALI_PI_206_DATA 0b00000000000000000111100101000000 // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00007940 #define DENALI_PI_207_DATA 0b00000000000000000010100010010000 // PI_TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x002890 #define DENALI_PI_208_DATA 0b00000000000000011001010110100000 // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x000195a0 #define DENALI_PI_209_DATA 0b00000000011100110000000000000110 // PI_TXSR_F1:RW:16:16:=0x0073 PI_TXSR_F0:RW:0:16:=0x0006 #define DENALI_PI_210_DATA 0b00000011000000110000000110000000 // PI_TEXCKE_F1:RW:24:6:=0x03 PI_TEXCKE_F0:RW:16:6:=0x03 PI_TXSR_F2:RW:0:16:=0x0180 #define DENALI_PI_211_DATA 0b00000000000000000000000000000011 // PI_TDLL_F0:RW:8:16:=0x0000 PI_TEXCKE_F2:RW:0:6:=0x03 #define DENALI_PI_212_DATA 0b00000000000000000000000000000000 // PI_TDLL_F2:RW:16:16:=0x0000 PI_TDLL_F1:RW:0:16:=0x0000 #define DENALI_PI_213_DATA 0b00000000000000000000000000000100 // PI_TINIT_F0:RW:0:24:=0x000004 #define DENALI_PI_214_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F0:RW:0:24:=0x000001 #define DENALI_PI_215_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F0:RW:0:24:=0x000005 #define DENALI_PI_216_DATA 0b00000000000000000000000000000010 // PI_TINIT5_F0:RW:0:24:=0x000002 #define DENALI_PI_217_DATA 0b00000000000000000000000000000110 // PI_TXSNR_F0:RW:0:16:=0x0006 #define DENALI_PI_218_DATA 0b00000000000000000000000001010000 // PI_TINIT_F1:RW:0:24:=0x000050 #define DENALI_PI_219_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F1:RW:0:24:=0x000001 #define DENALI_PI_220_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F1:RW:0:24:=0x000005 #define DENALI_PI_221_DATA 0b00000000000000000000000000101000 // PI_TINIT5_F1:RW:0:24:=0x000028 #define DENALI_PI_222_DATA 0b00000000000000000000000001110011 // PI_TXSNR_F1:RW:0:16:=0x0073 #define DENALI_PI_223_DATA 0b00000000000000000000000100001011 // PI_TINIT_F2:RW:0:24:=0x00010b #define DENALI_PI_224_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F2:RW:0:24:=0x000001 #define DENALI_PI_225_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F2:RW:0:24:=0x000005 #define DENALI_PI_226_DATA 0b00000000000000000000000010000110 // PI_TINIT5_F2:RW:0:24:=0x000086 #define DENALI_PI_227_DATA 0b00000001000000000000000110000000 // RESERVED:RW:16:12:=0x0100 PI_TXSNR_F2:RW:0:16:=0x0180 #define DENALI_PI_228_DATA 0b00000000000101000000000001000000 // PI_TZQCAL_F0:RW:16:12:=0x0014 RESERVED:RW:0:12:=0x0040 #define DENALI_PI_229_DATA 0b00000000000000010000000000000001 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F0:RW:0:7:=0x01 #define DENALI_PI_230_DATA 0b00000001100100000000000001000000 // PI_TZQCAL_F1:RW:16:12:=0x0190 RESERVED:RW:0:12:=0x0040 #define DENALI_PI_231_DATA 0b00000000000000010000000000001100 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F1:RW:0:7:=0x0c #define DENALI_PI_232_DATA 0b00000101001101100000000001000000 // PI_TZQCAL_F2:RW:16:12:=0x0536 RESERVED:RW:0:12:=0x0040 #define DENALI_PI_233_DATA 0b00000000000000000000001100101000 // RESERVED:RW:8:12:=0x0003 PI_TZQLAT_F2:RW:0:7:=0x28 #define DENALI_PI_234_DATA 0b00000000010000110000000000010100 // RESERVED:RW:16:12:=0x0043 RESERVED:RW:0:12:=0x0014 #define DENALI_PI_235_DATA 0b00000001000000010000000100000001 // PI_MEMDATA_RATIO_3:RW:24:3:=0x01 PI_MEMDATA_RATIO_2:RW:16:3:=0x01 PI_MEMDATA_RATIO_1:RW:8:3:=0x01 PI_MEMDATA_RATIO_0:RW:0:3:=0x01 #define DENALI_PI_236_DATA 0b00000010000000100000000100000001 // PI_ODT_WR_MAP_CS1:RW:24:4:=0x02 PI_ODT_RD_MAP_CS1:RW:16:4:=0x02 PI_ODT_WR_MAP_CS0:RW:8:4:=0x01 PI_ODT_RD_MAP_CS0:RW:0:4:=0x01 #define DENALI_PI_237_DATA 0b00001000000010000000010000000100 // PI_ODT_WR_MAP_CS3:RW:24:4:=0x08 PI_ODT_RD_MAP_CS3:RW:16:4:=0x08 PI_ODT_WR_MAP_CS2:RW:8:4:=0x04 PI_ODT_RD_MAP_CS2:RW:0:4:=0x04 #define DENALI_PI_238_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV0_3:RW:24:7:=0x67 PI_VREF_VAL_DEV0_2:RW:16:7:=0x67 PI_VREF_VAL_DEV0_1:RW:8:7:=0x67 PI_VREF_VAL_DEV0_0:RW:0:7:=0x67 #define DENALI_PI_239_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV1_3:RW:24:7:=0x67 PI_VREF_VAL_DEV1_2:RW:16:7:=0x67 PI_VREF_VAL_DEV1_1:RW:8:7:=0x67 PI_VREF_VAL_DEV1_0:RW:0:7:=0x67 #define DENALI_PI_240_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV2_3:RW:24:7:=0x67 PI_VREF_VAL_DEV2_2:RW:16:7:=0x67 PI_VREF_VAL_DEV2_1:RW:8:7:=0x67 PI_VREF_VAL_DEV2_0:RW:0:7:=0x67 #define DENALI_PI_241_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV3_3:RW:24:7:=0x67 PI_VREF_VAL_DEV3_2:RW:16:7:=0x67 PI_VREF_VAL_DEV3_1:RW:8:7:=0x67 PI_VREF_VAL_DEV3_0:RW:0:7:=0x67 #define DENALI_PI_242_DATA 0b00000000000000000000000000000000 // PI_SLICE_PER_DEV_3:RW:24:2:=0x00 PI_SLICE_PER_DEV_2:RW:16:2:=0x00 PI_SLICE_PER_DEV_1:RW:8:2:=0x00 PI_SLICE_PER_DEV_0:RW:0:2:=0x00 #define DENALI_PI_243_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_0_3:RD:24:6:=0x00 PI_MR6_VREF_0_2:RD:16:6:=0x00 PI_MR6_VREF_0_1:RD:8:6:=0x00 PI_MR6_VREF_0_0:RD:0:6:=0x00 #define DENALI_PI_244_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_1_3:RD:24:6:=0x00 PI_MR6_VREF_1_2:RD:16:6:=0x00 PI_MR6_VREF_1_1:RD:8:6:=0x00 PI_MR6_VREF_1_0:RD:0:6:=0x00 #define DENALI_PI_245_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_2_3:RD:24:6:=0x00 PI_MR6_VREF_2_2:RD:16:6:=0x00 PI_MR6_VREF_2_1:RD:8:6:=0x00 PI_MR6_VREF_2_0:RD:0:6:=0x00 #define DENALI_PI_246_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_3_3:RD:24:6:=0x00 PI_MR6_VREF_3_2:RD:16:6:=0x00 PI_MR6_VREF_3_1:RD:8:6:=0x00 PI_MR6_VREF_3_0:RD:0:6:=0x00 #define DENALI_PI_247_DATA 0b00000000000000000101010100000000 // PI_MR17_DATA_0:RW:24:8:=0x00 PI_MR16_DATA_0:RW:16:8:=0x00 PI_MR15_DATA_0:RW:8:8:=0x55 PI_MR13_DATA_0:RW+:0:8:=0x00 #define DENALI_PI_248_DATA 0b00000000000000000101101000000000 // PI_MR32_DATA_0:RW:8:17:=0x00005a PI_MR20_DATA_0:RW:0:8:=0x00 #define DENALI_PI_249_DATA 0b00000000010101010000000000111100 // PI_MR16_DATA_1:RW:24:8:=0x00 PI_MR15_DATA_1:RW:16:8:=0x55 PI_MR13_DATA_1:RW+:8:8:=0x00 PI_MR40_DATA_0:RW:0:8:=0x3c #define DENALI_PI_250_DATA 0b00000000000000000000000000000000 // PI_MR20_DATA_1:RW:8:8:=0x00 PI_MR17_DATA_1:RW:0:8:=0x00 #define DENALI_PI_251_DATA 0b00111100000000000000000001011010 // PI_MR40_DATA_1:RW:24:8:=0x3c PI_MR32_DATA_1:RW:0:17:=0x00005a #define DENALI_PI_252_DATA 0b00000000000000000101010100000000 // PI_MR17_DATA_2:RW:24:8:=0x00 PI_MR16_DATA_2:RW:16:8:=0x00 PI_MR15_DATA_2:RW:8:8:=0x55 PI_MR13_DATA_2:RW+:0:8:=0x00 #define DENALI_PI_253_DATA 0b00000000000000000101101000000000 // PI_MR32_DATA_2:RW:8:17:=0x00005a PI_MR20_DATA_2:RW:0:8:=0x00 #define DENALI_PI_254_DATA 0b00000000010101010000000000111100 // PI_MR16_DATA_3:RW:24:8:=0x00 PI_MR15_DATA_3:RW:16:8:=0x55 PI_MR13_DATA_3:RW+:8:8:=0x00 PI_MR40_DATA_2:RW:0:8:=0x3c #define DENALI_PI_255_DATA 0b00000000000000000000000000000000 // PI_MR20_DATA_3:RW:8:8:=0x00 PI_MR17_DATA_3:RW:0:8:=0x00 #define DENALI_PI_256_DATA 0b00111100000000000000000001011010 // PI_MR40_DATA_3:RW:24:8:=0x3c PI_MR32_DATA_3:RW:0:17:=0x00005a #define DENALI_PI_257_DATA 0b00011000000101110001011000010101 // PI_CKE_MUX_3:RW_D:24:5:=0x18 PI_CKE_MUX_2:RW_D:16:5:=0x17 PI_CKE_MUX_1:RW_D:8:5:=0x16 PI_CKE_MUX_0:RW_D:0:5:=0x15 #define DENALI_PI_258_DATA 0b00010100000100110001001000010001 // PI_CS_MUX_3:RW_D:24:5:=0x14 PI_CS_MUX_2:RW_D:16:5:=0x13 PI_CS_MUX_1:RW_D:8:5:=0x12 PI_CS_MUX_0:RW_D:0:5:=0x11 #define DENALI_PI_259_DATA 0b00000111000001100000010100000100 // PI_ODT_MUX_3:RW_D:24:5:=0x07 PI_ODT_MUX_2:RW_D:16:5:=0x06 PI_ODT_MUX_1:RW_D:8:5:=0x05 PI_ODT_MUX_0:RW_D:0:5:=0x04 #define DENALI_PI_260_DATA 0b00000011000000100000000100000000 // PI_RESET_N_MUX_3:RW_D:24:5:=0x03 PI_RESET_N_MUX_2:RW_D:16:5:=0x02 PI_RESET_N_MUX_1:RW_D:8:5:=0x01 PI_RESET_N_MUX_0:RW_D:0:5:=0x00 #define DENALI_PI_261_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_0:RW:0:17:=0x000000 #define DENALI_PI_262_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_1:RW:0:17:=0x000000 #define DENALI_PI_263_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_2:RW:0:17:=0x000000 #define DENALI_PI_264_DATA 0b00000001000000000000000000000000 // PI_ZQ_CAL_START_MAP_0:RW_D:24:4:=0x01 PI_MRSINGLE_DATA_3:RW:0:17:=0x000000 #define DENALI_PI_265_DATA 0b00000100000000100000001000000001 // PI_ZQ_CAL_START_MAP_2:RW_D:24:4:=0x04 PI_ZQ_CAL_LATCH_MAP_1:RW_D:16:4:=0x02 PI_ZQ_CAL_START_MAP_1:RW_D:8:4:=0x02 PI_ZQ_CAL_LATCH_MAP_0:RW_D:0:4:=0x01 #define DENALI_PI_266_DATA 0b00000000000010000000100000000100 // PI_ZQ_CAL_LATCH_MAP_3:RW_D:16:4:=0x08 PI_ZQ_CAL_START_MAP_3:RW_D:8:4:=0x08 PI_ZQ_CAL_LATCH_MAP_2:RW_D:0:4:=0x04 #define DENALI_PI_267_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_0:RW:0:17:=0x000000 #define DENALI_PI_268_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_0:RW+:0:17:=0x000004 #define DENALI_PI_269_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_0:RW+:0:17:=0x000000 #define DENALI_PI_270_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_0:RW+:0:17:=0x000031 #define DENALI_PI_271_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_0:RW:0:17:=0x000031 #define DENALI_PI_272_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_0:RW:0:17:=0x000000 #define DENALI_PI_273_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_0:RW+:24:8:=0x00 PI_MR6_DATA_F0_0:RW+:0:17:=0x000000 #define DENALI_PI_274_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_0:RW+:16:8:=0x00 PI_MR14_DATA_F0_0:RW+:8:8:=0x4d PI_MR12_DATA_F0_0:RW+:0:8:=0x4d #define DENALI_PI_275_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_0:RW:0:17:=0x000000 #define DENALI_PI_276_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_0:RW+:0:17:=0x000014 #define DENALI_PI_277_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_0:RW+:0:17:=0x000009 #define DENALI_PI_278_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_0:RW+:0:17:=0x000031 #define DENALI_PI_279_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_0:RW:0:17:=0x000031 #define DENALI_PI_280_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_0:RW:0:17:=0x000000 #define DENALI_PI_281_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_0:RW+:24:8:=0x00 PI_MR6_DATA_F1_0:RW+:0:17:=0x000000 #define DENALI_PI_282_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_0:RW+:16:8:=0x00 PI_MR14_DATA_F1_0:RW+:8:8:=0x4d PI_MR12_DATA_F1_0:RW+:0:8:=0x4d #define DENALI_PI_283_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_0:RW:0:17:=0x000000 #define DENALI_PI_284_DATA 0b00000000000000000000000001000100 // PI_MR1_DATA_F2_0:RW+:0:17:=0x000044 #define DENALI_PI_285_DATA 0b00000000000000000000000000100100 // PI_MR2_DATA_F2_0:RW+:0:17:=0x000024 #define DENALI_PI_286_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_0:RW+:0:17:=0x000031 #define DENALI_PI_287_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_0:RW:0:17:=0x000031 #define DENALI_PI_288_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_0:RW:0:17:=0x000000 #define DENALI_PI_289_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_0:RW+:24:8:=0x00 PI_MR6_DATA_F2_0:RW+:0:17:=0x000000 #define DENALI_PI_290_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_0:RW+:16:8:=0x00 PI_MR14_DATA_F2_0:RW+:8:8:=0x4d PI_MR12_DATA_F2_0:RW+:0:8:=0x4d #define DENALI_PI_291_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_1:RW:0:17:=0x000000 #define DENALI_PI_292_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_1:RW+:0:17:=0x000004 #define DENALI_PI_293_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_1:RW+:0:17:=0x000000 #define DENALI_PI_294_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_1:RW+:0:17:=0x000031 #define DENALI_PI_295_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_1:RW:0:17:=0x000031 #define DENALI_PI_296_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_1:RW:0:17:=0x000000 #define DENALI_PI_297_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR6_DATA_F0_1:RW+:0:17:=0x000000 #define DENALI_PI_298_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_1:RW+:16:8:=0x00 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d #define DENALI_PI_299_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_1:RW:0:17:=0x000000 #define DENALI_PI_300_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_1:RW+:0:17:=0x000014 #define DENALI_PI_301_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_1:RW+:0:17:=0x000009 #define DENALI_PI_302_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_1:RW+:0:17:=0x000031 #define DENALI_PI_303_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_1:RW:0:17:=0x000031 #define DENALI_PI_304_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_1:RW:0:17:=0x000000 #define DENALI_PI_305_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_1:RW+:24:8:=0x00 PI_MR6_DATA_F1_1:RW+:0:17:=0x000000 #define DENALI_PI_306_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_1:RW+:16:8:=0x00 PI_MR14_DATA_F1_1:RW+:8:8:=0x4d PI_MR12_DATA_F1_1:RW+:0:8:=0x4d #define DENALI_PI_307_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_1:RW:0:17:=0x000000 #define DENALI_PI_308_DATA 0b00000000000000000000000001000100 // PI_MR1_DATA_F2_1:RW+:0:17:=0x000044 #define DENALI_PI_309_DATA 0b00000000000000000000000000100100 // PI_MR2_DATA_F2_1:RW+:0:17:=0x000024 #define DENALI_PI_310_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_1:RW+:0:17:=0x000031 #define DENALI_PI_311_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_1:RW:0:17:=0x000031 #define DENALI_PI_312_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_1:RW:0:17:=0x000000 #define DENALI_PI_313_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR6_DATA_F2_1:RW+:0:17:=0x000000 #define DENALI_PI_314_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d #define DENALI_PI_315_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_2:RW:0:17:=0x000000 #define DENALI_PI_316_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_2:RW+:0:17:=0x000004 #define DENALI_PI_317_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_2:RW+:0:17:=0x000000 #define DENALI_PI_318_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_2:RW+:0:17:=0x000031 #define DENALI_PI_319_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_2:RW:0:17:=0x000031 #define DENALI_PI_320_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_2:RW:0:17:=0x000000 #define DENALI_PI_321_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_2:RW+:24:8:=0x00 PI_MR6_DATA_F0_2:RW+:0:17:=0x000000 #define DENALI_PI_322_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_2:RW+:16:8:=0x00 PI_MR14_DATA_F0_2:RW+:8:8:=0x4d PI_MR12_DATA_F0_2:RW+:0:8:=0x4d #define DENALI_PI_323_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_2:RW:0:17:=0x000000 #define DENALI_PI_324_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_2:RW+:0:17:=0x000014 #define DENALI_PI_325_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_2:RW+:0:17:=0x000009 #define DENALI_PI_326_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_2:RW+:0:17:=0x000031 #define DENALI_PI_327_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_2:RW:0:17:=0x000031 #define DENALI_PI_328_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_2:RW:0:17:=0x000000 #define DENALI_PI_329_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_2:RW+:24:8:=0x00 PI_MR6_DATA_F1_2:RW+:0:17:=0x000000 #define DENALI_PI_330_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_2:RW+:16:8:=0x00 PI_MR14_DATA_F1_2:RW+:8:8:=0x4d PI_MR12_DATA_F1_2:RW+:0:8:=0x4d #define DENALI_PI_331_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_2:RW:0:17:=0x000000 #define DENALI_PI_332_DATA 0b00000000000000000000000001000100 // PI_MR1_DATA_F2_2:RW+:0:17:=0x000044 #define DENALI_PI_333_DATA 0b00000000000000000000000000100100 // PI_MR2_DATA_F2_2:RW+:0:17:=0x000024 #define DENALI_PI_334_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_2:RW+:0:17:=0x000031 #define DENALI_PI_335_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_2:RW:0:17:=0x000031 #define DENALI_PI_336_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_2:RW:0:17:=0x000000 #define DENALI_PI_337_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_2:RW+:24:8:=0x00 PI_MR6_DATA_F2_2:RW+:0:17:=0x000000 #define DENALI_PI_338_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_2:RW+:16:8:=0x00 PI_MR14_DATA_F2_2:RW+:8:8:=0x4d PI_MR12_DATA_F2_2:RW+:0:8:=0x4d #define DENALI_PI_339_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_3:RW:0:17:=0x000000 #define DENALI_PI_340_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_3:RW+:0:17:=0x000004 #define DENALI_PI_341_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_3:RW+:0:17:=0x000000 #define DENALI_PI_342_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_3:RW+:0:17:=0x000031 #define DENALI_PI_343_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_3:RW:0:17:=0x000031 #define DENALI_PI_344_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_3:RW:0:17:=0x000000 #define DENALI_PI_345_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_3:RW+:24:8:=0x00 PI_MR6_DATA_F0_3:RW+:0:17:=0x000000 #define DENALI_PI_346_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_3:RW+:16:8:=0x00 PI_MR14_DATA_F0_3:RW+:8:8:=0x4d PI_MR12_DATA_F0_3:RW+:0:8:=0x4d #define DENALI_PI_347_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_3:RW:0:17:=0x000000 #define DENALI_PI_348_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_3:RW+:0:17:=0x000014 #define DENALI_PI_349_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_3:RW+:0:17:=0x000009 #define DENALI_PI_350_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_3:RW+:0:17:=0x000031 #define DENALI_PI_351_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_3:RW:0:17:=0x000031 #define DENALI_PI_352_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_3:RW:0:17:=0x000000 #define DENALI_PI_353_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR6_DATA_F1_3:RW+:0:17:=0x000000 #define DENALI_PI_354_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_3:RW+:16:8:=0x00 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d #define DENALI_PI_355_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_3:RW:0:17:=0x000000 #define DENALI_PI_356_DATA 0b00000000000000000000000001000100 // PI_MR1_DATA_F2_3:RW+:0:17:=0x000044 #define DENALI_PI_357_DATA 0b00000000000000000000000000100100 // PI_MR2_DATA_F2_3:RW+:0:17:=0x000024 #define DENALI_PI_358_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_3:RW+:0:17:=0x000031 #define DENALI_PI_359_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_3:RW:0:17:=0x000031 #define DENALI_PI_360_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_3:RW:0:17:=0x000000 #define DENALI_PI_361_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_3:RW+:24:8:=0x00 PI_MR6_DATA_F2_3:RW+:0:17:=0x000000 #define DENALI_PI_362_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_3:RW+:16:8:=0x00 PI_MR14_DATA_F2_3:RW+:8:8:=0x4d PI_MR12_DATA_F2_3:RW+:0:8:=0x4d //* ******************************************************** //* The below are used only for simulation phy purposes. //* Please ignore if using integrated Cadence PHY. //* SimulationValues {{{ //* ******************************************************** #define SIM_PHY_VALS_DEFINED 1 // Global define for simulation #define SMALL_TREF_ENABLE 0x0 // CTL #define MR8_VAL 0x10 // CTL #define MR0_VAL 0x0 // CTL #define MR0_RL3_SUPPORT 0x0 // CTL #define ODT_RD_TIMING 0x0 // CTL #define TAC_MIN 0x0 // CTL #define TAC_MAX 0x0 // CTL #define LPDDR1_PD_CLK_GATE_DISABLE 0x0 // CTL #define LPDDR1_ATTACHED 0x0 // CTL //* ******************************************************** //* SimulationValues }}} //* ********************************************************