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@@ -443,7 +443,19 @@ void cadence_qspi_apb_config_baudrate_div(void * reg_base,
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cadence_qspi_apb_controller_disable(reg_base);
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reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
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reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
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+
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+ /*
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+ * The baud_div field in the config reg is 4 bits, and the ref clock is
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+ * divided by 2 * (baud_div + 1). Round up the divider to ensure the
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+ * SPI clock rate is less than or equal to the requested clock rate.
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+ */
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+ div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
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+ /* ensure the baud rate doesn't exceed the max value */
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+ if (div > CQSPI_REG_CONFIG_BAUD_MASK)
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+ div = CQSPI_REG_CONFIG_BAUD_MASK;
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+
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+#if 0
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div = ref_clk_hz / sclk_hz;
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if (div > 32)
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@@ -460,9 +472,10 @@ void cadence_qspi_apb_config_baudrate_div(void * reg_base,
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else
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div = (div / 2) - 1;
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}
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+#endif
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- //uart_printf("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
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- //ref_clk_hz, sclk_hz, div);
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+// printk("%s: ref_clk %dHz sclk %dHz Div 0x%x actual:%dHz\n", __func__,
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+// ref_clk_hz, sclk_hz, div,ref_clk_hz / (2 * (div + 1)));
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div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
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reg |= div;
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