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update qspi clk and del repeat init

yanhong.wang 3 years ago
parent
commit
db6e0650b9
5 changed files with 22 additions and 9 deletions
  1. 2 3
      boot/bootmain.c
  2. 1 1
      common/sys.h
  3. 2 1
      spi/cadence_qspi.c
  4. 15 2
      spi/cadence_qspi_apb.c
  5. 2 2
      uart/uart.c

+ 2 - 3
boot/bootmain.c

@@ -216,7 +216,7 @@ void boot_from_chiplink(void)
 	if(1 == abort)
 	{
 		cadence_qspi_init(0, mode);
-		spi_flash = spi_flash_probe(0, 0, 50000000, 0, (u32)SPI_DATAMODE_8);
+		spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
 		
 		printk("***************************************************\r\n");
 		printk("***************VIC	DDR INIT BOOT ********************\r\n");
@@ -282,8 +282,7 @@ void boot_from_spi(int mode)
 	u32 val;
 
     cadence_qspi_init(0, mode);
-	spi_flash = spi_flash_probe(0, 0, 50000000, 0, (u32)SPI_DATAMODE_8);
-
+	spi_flash = spi_flash_probe(0, 0, 31250000, 0, (u32)SPI_DATAMODE_8);
 	/*load uboot*/
 	load_data(spi_flash,DEFAULT_UBOOT_ADDR,DEFAULT_UBOOT_OFFSET,mode);
 }

+ 1 - 1
common/sys.h

@@ -12,7 +12,7 @@
 #define DDRPHY1_CSR_BASE_ADDR (E32_ADDR_REMAP_OFFSET+0x0011830000LL)
 
 
-#define QSPI_CLK            10000000
+#define QSPI_CLK            100000000
 #define QSPI_REF_CLK        250000000
 #define TIMER_CLK_HZ		6250000
 

+ 2 - 1
spi/cadence_qspi.c

@@ -305,7 +305,7 @@ void cadence_qspi_init(unsigned int bus, u32 mode)
 {
 	struct spi_operation *func;
     struct cadence_spi_platdata *plat = &cadence_plat;
-
+#if 0 //repeat init
 	/******************* reset ****************/
 	_ENABLE_CLOCK_clk_qspi_refclk_;
     _ENABLE_CLOCK_clk_qspi_apb_;
@@ -316,6 +316,7 @@ void cadence_qspi_init(unsigned int bus, u32 mode)
     _CLEAR_RESET_rstgen_rstn_qspi_ahb_;
     _CLEAR_RESET_rstgen_rstn_qspi_core_;
     _CLEAR_RESET_rstgen_rstn_qspi_apb_;
+#endif
 	plat->bit_mode = mode;
 	
 	func = &cadence_spi4x_func;

+ 15 - 2
spi/cadence_qspi_apb.c

@@ -443,7 +443,19 @@ void cadence_qspi_apb_config_baudrate_div(void * reg_base,
 	cadence_qspi_apb_controller_disable(reg_base);
 	reg = readl((u32)reg_base + CQSPI_REG_CONFIG);
 	reg &= ~(CQSPI_REG_CONFIG_BAUD_MASK << CQSPI_REG_CONFIG_BAUD_LSB);
+	
+	/*
+	 * The baud_div field in the config reg is 4 bits, and the ref clock is
+	 * divided by 2 * (baud_div + 1). Round up the divider to ensure the
+	 * SPI clock rate is less than or equal to the requested clock rate.
+	 */
+	div = DIV_ROUND_UP(ref_clk_hz, sclk_hz * 2) - 1;
 
+	/* ensure the baud rate doesn't exceed the max value */
+	if (div > CQSPI_REG_CONFIG_BAUD_MASK)
+		div = CQSPI_REG_CONFIG_BAUD_MASK;
+
+#if 0
 	div = ref_clk_hz / sclk_hz;
 
 	if (div > 32)
@@ -460,9 +472,10 @@ void cadence_qspi_apb_config_baudrate_div(void * reg_base,
 		else
 			div = (div / 2) - 1;
 	}
+#endif 
 
-	//uart_printf("%s: ref_clk %dHz sclk %dHz Div 0x%x\n", __func__,
-	      //ref_clk_hz, sclk_hz, div);
+//	printk("%s: ref_clk %dHz sclk %dHz Div 0x%x actual:%dHz\n", __func__,
+//	      ref_clk_hz, sclk_hz, div,ref_clk_hz / (2 * (div + 1)));
 
 	div = (div & CQSPI_REG_CONFIG_BAUD_MASK) << CQSPI_REG_CONFIG_BAUD_LSB;
 	reg |= div;

+ 2 - 2
uart/uart.c

@@ -79,7 +79,7 @@ void uart_init(int id)
 {
 	unsigned int divisor;
 	unsigned char lcr_cache;
-
+#if 0 //repeat init
 	switch(id)
 	{
 		case 0:
@@ -111,7 +111,7 @@ void uart_init(int id)
 		default:
 			return;
 	}
-
+#endif
  	uart_id = id;
 	
 	divisor = (UART_CLK / UART_BUADRATE_32MCLK_115200) >> 4;