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update ddr frequency to 2800/3200

yanhong.wang 3 years ago
parent
commit
d63c45eb56

+ 21 - 2
boot/bootmain.c

@@ -307,10 +307,23 @@ static int init_ddr(void)
   _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_osc_sys_;
   //SCFG_PLL [31:24] [23:16] [15:8]   [7:4] [3]    [2]   [1] [0]
   //          OD      BWADJ  CLKFDIV  CLKR  bypass infb  pd  rst
+#if defined(DDR_2133)
   MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x292905);//set reset
   udelay(10); //wait(500*(1/25M))
   MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x0292904);//clear reset
   udelay(10); //wait(500*(1/25M))
+#elif defined(DDR_2800)
+  MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x373705);//set reset
+  udelay(10); //wait(500*(1/25M))
+  MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x0373704);//clear reset
+  udelay(10); //wait(500*(1/25M))
+#elif defined(DDR_3200)
+  MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x3f3f05);//set reset
+  udelay(10); //wait(500*(1/25M))
+  MA_OUTW(syscon_sysmain_ctrl_SCFG_pll1_REG_ADDR,0x03f3f04);//clear reset
+  udelay(10); //wait(500*(1/25M))
+#endif
+
   _SWITCH_CLOCK_clk_dla_root_SOURCE_clk_pll1_out_;
   //_CLEAR_RESET_rstgen_rstn_ddrphy_apb_ //clear reset of ddrphy,unvalid
 
@@ -445,14 +458,20 @@ void BootMain(void)
 	int boot_mode = 0;
 	int ret=0;
 
-	gpio_init();
+//	gpio_init();
 	uart_init(3);
 
 	ret = init_ddr();
 	if(ret == 0)
 	{
 		_SET_SYSCON_REG_register68_SCFG_disable_u74_memaxi_remap(1);
-		printk("DDR clk 2133M,Version: %s\r\n",VERSION);
+#if defined(DDR_2133)
+		  printk("DDR clk 2133M,Version: %s\r\n",VERSION);
+#elif defined(DDR_2800)
+		  printk("DDR clk 2800M,Version: %s\r\n",VERSION);
+#elif defined(DDR_3200)
+		  printk("DDR clk 3200M,Version: %s\r\n",VERSION);
+#endif
 	}
 	else
 		printk("End init lpddr4, test ddr fail\r\n");

+ 22 - 16
build/Makefile

@@ -7,19 +7,18 @@ LD=${CROSSCOMPILE}ld
 OBJCOPY=${CROSSCOMPILE}objcopy
 OBJDUMP=${CROSSCOMPILE}objdump
 
+#DDR_SPEED 1:1600. 2:2133 3:2800 4 :3200
+DDR_SPEED = 3200
+
 SUFFIX=$(shell date +%y%m%d)
 GIT_VERSION=$(shell git show -s --pretty=format:%h)
 VERSION=$(SUFFIX)-$(GIT_VERSION)
 
-TARGET 	= ddrinit-$(SUFFIX)
+TARGET 	= ddrinit-$(DDR_SPEED)-$(SUFFIX)
 
 LINKER_SCRIPT := ddrinit.lds
 MAP_FILE := ddrinit.map
 
-#DDR_SPEED 1:1600. 2:2133 3:2666 4 :3200
-DDR_SPEED = DDR2133
-
-
 INCLUDE_DIR = -I. -I../boot\
 			-I../common\
 			-I../gpio\
@@ -30,13 +29,13 @@ INCLUDE_DIR = -I. -I../boot\
 			-I../sdio\
 			-I../gpt
 
-ifeq ($(strip $(DDR_SPEED)),DDR1600)
+ifeq ($(strip $(DDR_SPEED)),1600)
 INCLUDE_DIR +=-I../ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_800_cl14_bl16
-else ifeq ($(strip $(DDR_SPEED)),DDR2133)
+else ifeq ($(strip $(DDR_SPEED)),2133)
 INCLUDE_DIR +=-I../ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1066_cl20_bl16
-else ifeq ($(strip $(DDR_SPEED)),DDR2666)
-INCLUDE_DIR +=-I../ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1333_cl24_bl16
-else ifeq ($(strip $(DDR_SPEED)),DDR2666)
+else ifeq ($(strip $(DDR_SPEED)),2800)
+INCLUDE_DIR +=-I../ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16
+else ifeq ($(strip $(DDR_SPEED)),3200)
 INCLUDE_DIR +=-I../ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16
 else
 $(error DDR_SPEED $(DDR_SPEED) illegal!)
@@ -79,17 +78,24 @@ OBJECTLIST=../boot/start.o \
 		../sdio/sdio.o \
 		../gpt/gpt.o \
 		../ddrphy_cfg/regconfig.h.sim_PHY.o \
-		../ddrphy_cfg/regconfig.h.sim_PI.o \
-		../ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start.o 
+		../ddrphy_cfg/regconfig.h.sim_PI.o 
 
-ifeq ($(strip $(DDR_SPEED)),DDR1600)
+ifeq ($(strip $(DDR_SPEED)),1600)
 OBJECTLIST +=../ddrc_cfg/lpddr4_800_cl14_bl16/orbit_boot_800.o
-else ifeq ($(strip $(DDR_SPEED)),DDR2133)
+OBJECTLIST +=../ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start.o
+CFLAGS +=-DDDR_1600
+else ifeq ($(strip $(DDR_SPEED)),2133)
 OBJECTLIST +=../ddrc_cfg/lpddr4_1066_cl20_bl16/orbit_boot_1066.o
-else ifeq ($(strip $(DDR_SPEED)),DDR2666)
+OBJECTLIST +=../ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start.o
+CFLAGS +=-DDDR_2133
+else ifeq ($(strip $(DDR_SPEED)),2800)
 OBJECTLIST +=../ddrc_cfg/lpddr4_1333_cl24_bl16/orbit_boot_1333.o
-else ifeq ($(strip $(DDR_SPEED)),DDR2666)
+OBJECTLIST +=../ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start_2800.o
+CFLAGS +=-DDDR_2800
+else ifeq ($(strip $(DDR_SPEED)),3200)
 OBJECTLIST +=../ddrc_cfg/lpddr4_1600_cl28_bl16/orbit_boot_1600.o
+OBJECTLIST +=../ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start_3200.o
+CFLAGS +=-DDDR_3200
 else
 $(error DDR_SPEED $(DDR_SPEED) illegal!)
 endif

+ 107 - 97
ddrc_cfg/lpddr4_1333_cl24_bl16/orbit_boot_1333.c

@@ -1,8 +1,4 @@
-// void inline orbit_writel(volatile void __iomem *addr, uint32_t data);
-// void inline orbit_readl_poll(volatile void __iomem *addr, uint32_t expected, uint32_t strobe);
-// void orbit_nsleep(int ns); // Sleep ns nano-seconds
-// void udelay(int us); // Sleep us micro-seconds
-//cdns_phy_initialize(1);
+
 #include <regconfig.h.sim_PI.h>
 #include <regconfig.h.sim_PHY.h>
 #include <sys.h>
@@ -12,66 +8,70 @@
 void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
 {
     u32 tmp = 0;
-    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);
+	int count = 0;
+    int i = 0;
+    //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);//ignore_phy_rresp=1(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
+    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);//enable address region 0; 2ranks; bit15?
     apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);
-    apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);
-    apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);
-    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
-    apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);//region0_start //0x00800000
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf14, 0x027fffff);//region0_end,SOC addr shift right 8bits //0x01ffffff
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf18, 0x00000001);//2-channel interleaving
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf30, 0x0f000031);//chip0:rank_size=128MB*(f+1)(2GB?);bg=0;row_width=16;col_width=10
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf34, 0x0f000031);//chip1
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x110, 0xc0000001);//region0 attribute: allow secure write/read;enable security check for this region
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x114, 0xffffffff);//region0: [31:16]:nsaid_wr_en(allow non-secure write); [15:0]:nsaid_rd_en(allow non-secure read)
+    apb_write(OMC_APB_BASE_ADDR + 0x10c, 0x00000505);//Temperature monitor reads to determine the maximum re-fresh interval
+    apb_write(OMC_APB_BASE_ADDR + 0x11c, 0x00000000);//nop(byte lane no inversion,temperature monitor used)
+    apb_write(OMC_APB_BASE_ADDR + 0x500, 0x00000201);//enable retimer for read data; freq_ratio
+    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000100);//phymstr_ack_disable=1
+    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);//Keep OMC idle for additional idle_num_upd cycles (ACLK) after dfi_phyupd_ack assertion
+    apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);//Keep OMC idle for additional idle_num_upd cycles (ACLK) after dfi_phyupd_ack assertion
     // Memory frequency should be changed below 50MHz somewhere before here
-    apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);//assert dfi_init_start
+    udelay(300);
     //cdns_dll_rst_deassert()
 
-    tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
+    tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);//wait for dfi_init_complete
     while((tmp & 0x80000000) != 0x80000000) {
       udelay(1);
       tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);
     }
 
-    apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x504, 0x00000000);//de-assert dfi_init_start; de-assert dfi_ctrlupd_req on exit from self-refresh mode
     // tINIT0 is controlled by System
-    apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);//Drive DRAM_RST_N low
     // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
-    udelay(200);
-    apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);
+    udelay(300);
+    apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);//Drive DRAM_RST_N high
     // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
-    udelay(2000);
+    udelay(3000);
     // Drive CKE high
-    apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);
-    apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
+    apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);//dram_command_cs: rank0/1; dram_command: power-down exit
+    apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);//dram_command_start
     // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
-    udelay(2);
-    apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);
-    apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);
+    udelay(4);
+    apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);//dfs_dfi_frequency=2
+    apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);//dfs_dfi_init_start_toggle; assert dfi_init_start when dfi_frequency change
     // Write down RCLK-related CRs
-    apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);
+    apb_write(OMC_APB_BASE_ADDR + 0x600, 0x002e0176);//Per-bank(31:16)/all-bank(15:0) refresh interval in OSC clock cycles for each of eight MR4 values.
     apb_write(OMC_APB_BASE_ADDR + 0x604, 0x002e0176);
     apb_write(OMC_APB_BASE_ADDR + 0x608, 0x001700bb);
     apb_write(OMC_APB_BASE_ADDR + 0x60c, 0x000b005d);
     apb_write(OMC_APB_BASE_ADDR + 0x610, 0x0005002e);
     apb_write(OMC_APB_BASE_ADDR + 0x614, 0x00020017);
     apb_write(OMC_APB_BASE_ADDR + 0x618, 0x00020017);
-    apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);
-    apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);
-    apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);
-    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);
-    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);
+    apb_write(OMC_APB_BASE_ADDR + 0x61c, 0x00020017);//Per-bank(31:16)/all-bank(15:0) refresh interval in OSC clock cycles for each of eight MR4 values.
+    apb_write(OMC_APB_BASE_ADDR + 0x678, 0x00000019);//t_zqcal(lpddr4) >= 1us(0x640) 
+    apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000f8);//abr_en[7:0]
+    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x03030404);//error: tCKCKEH(tCKSRX)>=3,tCMDCKE>=3,tRPpb(tRP)>=29,tRPab(tRP)>=34
+    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x04030505);//error: tCKE>=12,tSR(tCKESR)>=24,tCKELCK>=8,tXP>=12
     apb_write(OMC_APB_BASE_ADDR + 0x628, 0x07030884);
     apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x13150401);
     apb_write(OMC_APB_BASE_ADDR + 0x630, 0x17150604);
     apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00110000);
     apb_write(OMC_APB_BASE_ADDR + 0x638, 0x200a0a08);
-    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);
+    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x1730f803);//t_add_wr_p
     apb_write(OMC_APB_BASE_ADDR + 0x640, 0x00080c00);
     apb_write(OMC_APB_BASE_ADDR + 0x644, 0xa0040007);
     apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
@@ -81,13 +81,13 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
     apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
     apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);
-    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
+    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);//DFI_timing
+    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
     apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
     apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
     apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
     apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);//dfi_tlvl_max=0, dfi_tctrlupd_interval=0
     apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20240c00);
     apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010006);
@@ -96,25 +96,25 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066); //0x66->0x66
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160016); //0x06->0x16
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     // Waits tZQCAL (1 us)
-    udelay(1);
+    udelay(4);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     // Waits tZQCAL (1 us)
-    udelay(1);
+    udelay(4);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
-    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);//phymstr_ack_disable=0
 
-    tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
+    tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);//wait for dfi_phymstr_ack=1
     while((tmp & 0x00000002) != 0x00000002) {
       udelay(1);
       tmp = apb_read(OMC_APB_BASE_ADDR + 0x518);
@@ -128,33 +128,39 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
       if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
         switch(tmp & 0x0000001f) { //judge freq_change_req_type
           case 0: 
-            if(ddr_num == 1) //ddrc_clock=12.5M
+            if(ddr_num == 0) //ddrc_clock=12.5M
             {
                 _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
+                udelay(100);
             }
             else
             {
                 _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
+                udelay(100);
             }
             break;
           case 1:
-            if(ddr_num == 1) //ddrc_clock=200M
+            if(ddr_num == 0) //ddrc_clock=1600/8=200M
             {
                 _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_;
+                udelay(100);
             }
             else
             {
                 _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_;
+                udelay(100);
             }
             break;
           case 2:
-            if(ddr_num == 1) //ddrc_clock=400M
+            if(ddr_num == 0) //ddrc_clock=1600/2=800M
             {
-                _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
+                _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_;
+                udelay(100);
             }
             else
             {
-                _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
+                _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_;
+                udelay(100);
             }
             break;
           default:
@@ -244,59 +250,63 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +186 <<2));//`DENALI_PI_186_DATA
     apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
 
-    apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);
-    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x0403181c);
-    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0a14070a);
-    apb_write(OMC_APB_BASE_ADDR + 0x628, 0x50380a98);
-    apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x2d230e36);
-    apb_write(OMC_APB_BASE_ADDR + 0x630, 0x2f1f180c);
-    apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00200000);
-    apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20131308);
-    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x2f420a06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
-    apb_write(OMC_APB_BASE_ADDR + 0x640, 0x018025b1);
-    apb_write(OMC_APB_BASE_ADDR + 0x644, 0x00bb0176);
-    apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000a2d18);
-    apb_write(OMC_APB_BASE_ADDR + 0x650, 0x1b553b10);
-    apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00001f1b);
-    apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
-    apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00780028);
-    apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x10000413);//trdcslat=0x12->0x10;trddata_en=0x12->0x13
-    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x05000804);//twrcslat=0x6->0x5;twrlat=0x8;twrdata=0x4
-    apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040e);
-    apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003020);
-    apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
-    apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20300c00);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010046);
+    apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);//abr_en[7:5]
+    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x04041d22);//tCKCKEH(tCKSRX)[31:24]>=3,tCMDCKE[18:16]>=3,tRPpb(tRP)[13:8]>=0x1D,tRPab(tRP)>=0x22
+    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0c18080c);//tCKE[28:24]>=0xc,tSR(tCKESR)[21:16]>=0x18,tCKELCK[12:8]>=8,tXP[4:0]>=0xc
+    apb_write(OMC_APB_BASE_ADDR + 0x628, 0x60440c9d);//tRC[31:24]>=(0x60||0x63)/tCK,tRAS[22:16]>=0x44,tRTP[13:8]>=0xc,adv_al[7]=1,tRCD[5:0]>=0x1d
+    apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x34271140);//t_wra[30:24]>=,t_wtra[21:16]>=,tRRD[12:8]>=0x10,tfaw[6:0]>=0x40
+    apb_write(OMC_APB_BASE_ADDR + 0x630, 0x36231c0e);//t_rtrrd[30:24]>=,t_wrwtr[21:16]>=,RL[13:8]>=,WL[5:0]>=
+    apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00230000);//t_rtw[21:16]>=
+    apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20171708);//t_ccdmw[29:24]>=,t_mrw[21:16]>=,t_mrd[13:8]>=,t_mrr[3:0]>=8
+    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x36420a06);//t_rtrrd[30:24]>=,n_add_wr_p[23:20]>=,t_add_wr_p[19:16]>=,twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
+    apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01cf2cd6);//t_ccd_gap[30:28]>=?,t_xsr[25:16]>=0x1CC(287.5ns_8gibx16),t_xp_mrri[14:8]>=31, t_refdpr[7:0]>=?
+    apb_write(OMC_APB_BASE_ADDR + 0x644, 0x01320262);//t_wtrcr[31:28]>=?, t_rfcpb[25:16]>=0xe0(0x130),t_rfcab[9:0]>=0x1c0(0x260)
+    apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);//t_pbr2pbr[7:0]=0x00
+    apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000d351e);//n_rtp[21:16]>=0xC, n_wr_a[14:8]>=0x35, n_wr[5:0]>=0x1e
+    apb_write(OMC_APB_BASE_ADDR + 0x650, 0x20664713);//t_rcd_derate[29:24]>=0x20,t_rc_derate[23:16]>=0x66(per-bank-precharge),t_ras_derate[14:8]>=0x47,t_rrd_derate[4:0]>=0x13
+    apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00002520);//t_rpab_derate[13:8]>=0x,t_rppb_derate[5:0]>=0x
+    apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);//delay_wrexit_cyc_th[11:0]=?
+    apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00900030);//t_zqcs[23:16]=0(lpddr4), t_zqlatch[9:0]>=0x20
+    apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);//pwdn_entry_th[31:16], sr_entry_th[15:0]
+    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x14000416);//trdcslat=0x16->0x14;trddata_en=0x16->0x16
+    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x07000a04);//twrcslat=0x8->0x7;twrlat=0xa;twrdata=0x4
+    apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0515040e);//dfi_tctrl_delay[31:24]=4+1||5+1;dfi_twrdata_delay[23:16]=0x5(phy_ctrl);dfi_tdram_clk_disable[15:8]=2+1||3+1(phy);dfi_tdram_clk_enable[7:0]=2+1||3+1;
+    apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003320);//dfi_trdlvl_en[31:24];dfi_trdlvl_rr[15:8];dfi_twrlvl_en[7:0]
+    apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);//dfi_twrlvl_ww[23:16];
+    apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);//dfi_tctrlupd_max[25:16]>=0x124??;dfi_tctrlupd_min[9:0]==0x74;
+    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);//dfi_tlvl_max[31:16]=0; dfi_tctrlupd_interval[9:0]=0???;
+    apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20330c00);//dfi_twdqlvl_en[31:24];dfi_twdqlvl_rw[23:16];dfi_twdqlvl_ww[15:8];
+    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);//idle_num_upd[31:16];dfi_tphymstr_rfsh[13:8];dfi_twdqlvl_resp[7:0];
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010056);//nWR=30,BL=on the fly
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30020024);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3002002d);//WL/RL for 1333M~1600M
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);//PDDS=RZQ/6,PU-CAl=VDDQ/3(default)
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066); //0x06->0x66
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160016);//soc_ODT=RZQ/6, 0x06->0x1e->0x16
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0015); //vref(ca)
+    apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300e0017); //vref(dq)
+    apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
+    apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);//generation/urgent<->oldest request
     apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
     apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
     apb_write(OMC_APB_BASE_ADDR + 0x428, 0x80000020);
-    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
+    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);//ignore_phy_rresp=0(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
     apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);
-    apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);
-    apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);
-    apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);
-    apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);
-    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);
-    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);
-    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);
-    apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);//enable scrambler/axi/apb logic clock gating
+    apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);//enable various clock gating
+    apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000013);//drive ODT pin for rank0/rank1; ODT pins is always driven by fixed_odt_cs
+    apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);//disable dynamic DRAM power down/self-refresh;wait until enough auto-refresh is issued.
+    apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);//Enable auto-refresh;Opportunistic selection of target bank refresh to reduce bank confliction
+    apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);//Issue {num_phyupd_abr} number of all-bank-refresh commands before ac-knowledging phyupd_req.
+    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);//phymstr_ack_disable=0
+    apb_write(OMC_SECURE_APB_BASE_ADDR + 0x700, 0x00000003);//CR_UPDATE_CTRL
+    apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000600);//Wait dfi_phymstr_* handshake after (POWER Gating mode/DFS completed) exited
+    apb_write(OMC_APB_BASE_ADDR + 0x20, 0x00000001);//DRAM_INIT_DONE
 }
 //cdns_per_tr_longcnt_set( 16);
 // Initialization done

+ 56 - 42
ddrc_cfg/lpddr4_1600_cl28_bl16/orbit_boot_1600.c

@@ -8,7 +8,10 @@
 void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
 {
     u32 tmp = 0;
-    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);//ignore_phy_rresp=1(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
+	int count = 0;
+    int i = 0;
+    //apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000401);//ignore_phy_rresp=1(Ignore dfi_rddata_valid from PHY,Only used in booting period);dram type=LPDDR4
+    apb_write(OMC_APB_BASE_ADDR + 0x0, 0x00000001);
     apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf00, 0x40001030);//enable address region 0; 2ranks; bit15?
     apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf04, 0x00000001);
     apb_write(OMC_SECURE_APB_BASE_ADDR + 0xf10, 0x00800000);//region0_start //0x00800000
@@ -26,6 +29,7 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0xea8, 0x00040000);//Keep OMC idle for additional idle_num_upd cycles (ACLK) after dfi_phyupd_ack assertion
     // Memory frequency should be changed below 50MHz somewhere before here
     apb_write(OMC_APB_BASE_ADDR + 0x504, 0x40000000);//assert dfi_init_start
+    udelay(300);
     //cdns_dll_rst_deassert()
 
     tmp = apb_read(OMC_APB_BASE_ADDR + 0x504);//wait for dfi_init_complete
@@ -38,15 +42,15 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     // tINIT0 is controlled by System
     apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000000);//Drive DRAM_RST_N low
     // Waits tINIT1 (200 us): Minimum RESET_n LOW time after completion of voltage ramp
-    udelay(200);
+    udelay(300);
     apb_write(OMC_APB_BASE_ADDR + 0x50c, 0x00000001);//Drive DRAM_RST_N high
     // Waits tINIT3 (2 ms): Minimum CKE low time after RESET_n high
-    udelay(2000);
+    udelay(3000);
     // Drive CKE high
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x0000003c);//dram_command_cs: rank0/1; dram_command: power-down exit
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);//dram_command_start
     // Waits tINIT5 (2 us): Minimum idle time before first MRW/MRR command
-    udelay(2);
+    udelay(4);
     apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020000);//dfs_dfi_frequency=2
     apb_write(OMC_APB_BASE_ADDR + 0x310, 0x00020001);//dfs_dfi_init_start_toggle; assert dfi_init_start when dfi_frequency change
     // Write down RCLK-related CRs
@@ -77,8 +81,8 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
     apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00030008);
     apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
-    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000400);//DFI_timing
-    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x02000202);
+    apb_write(OMC_APB_BASE_ADDR + 0x680, 0x00000603);//DFI_timing
+    apb_write(OMC_APB_BASE_ADDR + 0x684, 0x01000202);
     apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0413040d);
     apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20002420);
     apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
@@ -92,20 +96,20 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066); //0x66->0x66
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160016); //0x06->0x16
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000010);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     // Waits tZQCAL (1 us)
-    udelay(1);
+    udelay(4);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000011);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000020);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     // Waits tZQCAL (1 us)
-    udelay(1);
+    udelay(4);
     apb_write(OMC_APB_BASE_ADDR + 0x10, 0x00000021);
     apb_write(OMC_APB_BASE_ADDR + 0x14, 0x00000001);
     apb_write(OMC_APB_BASE_ADDR + 0x514, 0x00000000);//phymstr_ack_disable=0
@@ -124,33 +128,39 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
       if((tmp & 0x00000020) == 0x00000020) { //judge freq_change_req
         switch(tmp & 0x0000001f) { //judge freq_change_req_type
           case 0: 
-            if(ddr_num == 1) //ddrc_clock=12.5M
+            if(ddr_num == 0) //ddrc_clock=12.5M
             {
                 _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrosc_div2_;
+                udelay(100);
             }
             else
             {
                 _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrosc_div2_;
+                udelay(100);
             }
             break;
           case 1:
-            if(ddr_num == 1) //ddrc_clock=200M
+            if(ddr_num == 0) //ddrc_clock=1600/8=200M
             {
                 _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div8_;
+                udelay(100);
             }
             else
             {
                 _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div8_;
+                udelay(100);
             }
             break;
           case 2:
-            if(ddr_num == 1) //ddrc_clock=400M
+            if(ddr_num == 0) //ddrc_clock=1600/2=800M
             {
-                _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div4_;
+                _SWITCH_CLOCK_clk_ddrc0_SOURCE_clk_ddrpll_div2_;
+                udelay(100);
             }
             else
             {
-                _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div4_;
+                _SWITCH_CLOCK_clk_ddrc1_SOURCE_clk_ddrpll_div2_;
+                udelay(100);
             }
             break;
           default:
@@ -241,42 +251,46 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(PHY_APB_BASE_ADDR + (2048 +186 <<2), tmp | (0x3 <<8));
 
     apb_write(OMC_APB_BASE_ADDR + 0x100, 0x000000e0);//abr_en[7:5]
-    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x04031d22);//tCKCKEH(tCKSRX)>=3,tCMDCKE>=3,tRPpb(tRP)>=29,tRPab(tRP)>=34
-    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0c18080c);//tCKE>=12,tSR(tCKESR)>=24,tCKELCK>=8,tXP>=12
-    apb_write(OMC_APB_BASE_ADDR + 0x628, 0x60440c9d);//tRC>=(60||63)/tCK,tRAS>=44,tRTP>=12,adv_al=1,tRCD>=0x1d
-    apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x34271140);//tRRD[12:8]>=0x10
-    apb_write(OMC_APB_BASE_ADDR + 0x630, 0x36231c0e);
-    apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00230000);
-    apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20171708);
-    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x36420a06);//twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
-    apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01cf2cd6);//tXSR>=0x1CC(287.5ns_8gibx16);tXP+tmrri?
-    apb_write(OMC_APB_BASE_ADDR + 0x644, 0x00e101c1);//lpddr4:tRFCpb>=0xe0,tRFCab>=0x1c0
-    apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);//tXSDLL,tXSfast>=0x110(170ns_8gib)
-    apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000d351e);//bit[21:16]:tRTP>=0xC
-    apb_write(OMC_APB_BASE_ADDR + 0x650, 0x20664713);
-    apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00002520);
-    apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);
-    apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00900030);
-    apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);
+    apb_write(OMC_APB_BASE_ADDR + 0x620, 0x04041d22);//tCKCKEH(tCKSRX)[31:24]>=3,tCMDCKE[18:16]>=3,tRPpb(tRP)[13:8]>=0x1D,tRPab(tRP)>=0x22
+    apb_write(OMC_APB_BASE_ADDR + 0x624, 0x0c18080c);//tCKE[28:24]>=0xc,tSR(tCKESR)[21:16]>=0x18,tCKELCK[12:8]>=8,tXP[4:0]>=0xc
+    apb_write(OMC_APB_BASE_ADDR + 0x628, 0x60440c9d);//tRC[31:24]>=(0x60||0x63)/tCK,tRAS[22:16]>=0x44,tRTP[13:8]>=0xc,adv_al[7]=1,tRCD[5:0]>=0x1d
+    apb_write(OMC_APB_BASE_ADDR + 0x62c, 0x34271140);//t_wra[30:24]>=,t_wtra[21:16]>=,tRRD[12:8]>=0x10,tfaw[6:0]>=0x40
+    apb_write(OMC_APB_BASE_ADDR + 0x630, 0x36231c0e);//t_rtrrd[30:24]>=,t_wrwtr[21:16]>=,RL[13:8]>=,WL[5:0]>=
+    apb_write(OMC_APB_BASE_ADDR + 0x634, 0x00230000);//t_rtw[21:16]>=
+    apb_write(OMC_APB_BASE_ADDR + 0x638, 0x20171708);//t_ccdmw[29:24]>=,t_mrw[21:16]>=,t_mrd[13:8]>=,t_mrr[3:0]>=8
+    apb_write(OMC_APB_BASE_ADDR + 0x63c, 0x36420a06);//t_rtrrd[30:24]>=,n_add_wr_p[23:20]>=,t_add_wr_p[19:16]>=,twrcsgap[11:8]>=a(2*5), trdcsgap[3:0]>=6(2*3)
+    apb_write(OMC_APB_BASE_ADDR + 0x640, 0x01cf2cd6);//t_ccd_gap[30:28]>=?,t_xsr[25:16]>=0x1CC(287.5ns_8gibx16),t_xp_mrri[14:8]>=31, t_refdpr[7:0]>=?
+    apb_write(OMC_APB_BASE_ADDR + 0x644, 0x01320262);//t_wtrcr[31:28]>=?, t_rfcpb[25:16]>=0xe0(0x130),t_rfcab[9:0]>=0x1c0(0x260)
+    apb_write(OMC_APB_BASE_ADDR + 0x648, 0x00000000);//t_pbr2pbr[7:0]=0x00
+    apb_write(OMC_APB_BASE_ADDR + 0x64c, 0x000d351e);//n_rtp[21:16]>=0xC, n_wr_a[14:8]>=0x35, n_wr[5:0]>=0x1e
+    apb_write(OMC_APB_BASE_ADDR + 0x650, 0x20664713);//t_rcd_derate[29:24]>=0x20,t_rc_derate[23:16]>=0x66(per-bank-precharge),t_ras_derate[14:8]>=0x47,t_rrd_derate[4:0]>=0x13
+    apb_write(OMC_APB_BASE_ADDR + 0x654, 0x00002520);//t_rpab_derate[13:8]>=0x,t_rppb_derate[5:0]>=0x
+    apb_write(OMC_APB_BASE_ADDR + 0x658, 0x00000060);//delay_wrexit_cyc_th[11:0]=?
+    apb_write(OMC_APB_BASE_ADDR + 0x65c, 0x00900030);//t_zqcs[23:16]=0(lpddr4), t_zqlatch[9:0]>=0x20
+    apb_write(OMC_APB_BASE_ADDR + 0x660, 0x00000000);//pwdn_entry_th[31:16], sr_entry_th[15:0]
     apb_write(OMC_APB_BASE_ADDR + 0x680, 0x14000416);//trdcslat=0x16->0x14;trddata_en=0x16->0x16
     apb_write(OMC_APB_BASE_ADDR + 0x684, 0x07000a04);//twrcslat=0x8->0x7;twrlat=0xa;twrdata=0x4
-    apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0415040e);
-    apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003320);
-    apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);
-    apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);//dfi_tlvl_max=0, dfi_tctrlupd_interval=0
-    apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20330c00);
-    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);
+    apb_write(OMC_APB_BASE_ADDR + 0x688, 0x0515040e);//dfi_tctrl_delay[31:24]=4+1||5+1;dfi_twrdata_delay[23:16]=0x5(phy_ctrl);dfi_tdram_clk_disable[15:8]=2+1||3+1(phy);dfi_tdram_clk_enable[7:0]=2+1||3+1;
+    apb_write(OMC_APB_BASE_ADDR + 0x68c, 0x20003320);//dfi_trdlvl_en[31:24];dfi_trdlvl_rr[15:8];dfi_twrlvl_en[7:0]
+    apb_write(OMC_APB_BASE_ADDR + 0x690, 0x00140000);//dfi_twrlvl_ww[23:16];
+    apb_write(OMC_APB_BASE_ADDR + 0x69c, 0x01240074);//dfi_tctrlupd_max[25:16]>=0x124??;dfi_tctrlupd_min[9:0]==0x74;
+    apb_write(OMC_APB_BASE_ADDR + 0x6a0, 0x00000000);//dfi_tlvl_max[31:16]=0; dfi_tctrlupd_interval[9:0]=0???;
+    apb_write(OMC_APB_BASE_ADDR + 0x6a4, 0x20330c00);//dfi_twdqlvl_en[31:24];dfi_twdqlvl_rw[23:16];dfi_twdqlvl_ww[15:8];
+    apb_write(OMC_APB_BASE_ADDR + 0x6a8, 0x00040000);//idle_num_upd[31:16];dfi_tphymstr_rfsh[13:8];dfi_twdqlvl_resp[7:0];
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30010056);//nWR=30,BL=on the fly
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x3002002d);//WL/RL for 1333M~1600M
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30030031);//PDDS=RZQ/6,PU-CAl=VDDQ/3(default)
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066);
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300b0066); //0x06->0x66
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
-    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160006);//soc_ODT=RZQ/6
+    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x30160016);//soc_ODT=RZQ/6, 0x06->0x1e->0x16
     apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
+//    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300c0015); //vref(ca)
+//    apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
+//    apb_write(OMC_APB_BASE_ADDR + 0x4, 0x300e0018); //vref(dq)
+//    apb_write(OMC_APB_BASE_ADDR + 0xc, 0x00000002);
     apb_write(OMC_APB_BASE_ADDR + 0x410, 0x00101010);//generation/urgent<->oldest request
     apb_write(OMC_APB_BASE_ADDR + 0x420, 0x0c181006);
     apb_write(OMC_APB_BASE_ADDR + 0x424, 0x20200820);
@@ -285,7 +299,7 @@ void orbit_boot(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, u
     apb_write(OMC_APB_BASE_ADDR + 0x108, 0x00003000);
     apb_write(OMC_SECURE_APB_BASE_ADDR + 0x704, 0x00000007);//enable scrambler/axi/apb logic clock gating
     apb_write(OMC_APB_BASE_ADDR + 0x330, 0x09313fff);//enable various clock gating
-    apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000033);//drive ODT pin for rank0/rank1; ODT pins is always driven by fixed_odt_cs
+    apb_write(OMC_APB_BASE_ADDR + 0x508, 0x00000013);//drive ODT pin for rank0/rank1; ODT pins is always driven by fixed_odt_cs
     apb_write(OMC_APB_BASE_ADDR + 0x324, 0x00002000);//disable dynamic DRAM power down/self-refresh;wait until enough auto-refresh is issued.
     apb_write(OMC_APB_BASE_ADDR + 0x104, 0x90000000);//Enable auto-refresh;Opportunistic selection of target bank refresh to reduce bank confliction
     apb_write(OMC_APB_BASE_ADDR + 0x510, 0x00000100);//Issue {num_phyupd_abr} number of all-bank-refresh commands before ac-knowledging phyupd_req.

+ 736 - 0
ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start_2800.c

@@ -0,0 +1,736 @@
+#include <regconfig.h.sim_PI.h>
+#include <regconfig.h.sim_PHY.h>
+#include <sys.h>
+#include <clkgen_ctrl_macro.h>
+#include <comdef.h>
+#include <ddr_define.h>
+void regconfig_pi_start(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
+{
+    u32 tmp = 0;
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +89 <<2));//`DENALI_PHY_89_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +89 <<2), tmp&0xffffff00|0x00000051); //0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +78 <<2));//`DENALI_PHY_78_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +78 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +345 <<2));//`DENALI_PHY_345_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +345 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +334 <<2));//`DENALI_PHY_334_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +334 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +601 <<2));//`DENALI_PHY_601_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +601 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +590 <<2));//`DENALI_PHY_590_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +590 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +857 <<2));//`DENALI_PHY_857_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +857 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +846 <<2));//`DENALI_PHY_846_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +846 <<2), tmp&0xfffffcff);
+
+    //turn off multicast
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffffeff);
+
+    //set to freq copy 0
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffcffff);
+
+    //data slice registers
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +125 <<2));//`DENALI_PHY_125_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +125 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +102 <<2));//`DENALI_PHY_102_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +102 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +105 <<2));//`DENALI_PHY_105_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +105 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +92 <<2));//`DENALI_PHY_92_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +92 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +94 <<2));//`DENALI_PHY_94_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +94 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +89 <<2));//`DENALI_PHY_89_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +89 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +381 <<2));//`DENALI_PHY_381_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +381 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +358 <<2));//`DENALI_PHY_358_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +358 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +361 <<2));//`DENALI_PHY_361_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +361 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +348 <<2));//`DENALI_PHY_348_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +348 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +350 <<2));//`DENALI_PHY_350_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +350 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +345 <<2));//`DENALI_PHY_345_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +345 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +637 <<2));//`DENALI_PHY_637_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +637 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +614 <<2));//`DENALI_PHY_614_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +614 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +617 <<2));//`DENALI_PHY_617_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +617 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +604 <<2));//`DENALI_PHY_604_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +604 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +606 <<2));//`DENALI_PHY_606_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +606 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +601 <<2));//`DENALI_PHY_601_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +601 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +893 <<2));//`DENALI_PHY_893_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +893 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +870 <<2));//`DENALI_PHY_870_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +870 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +873 <<2));//`DENALI_PHY_873_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +873 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +860 <<2));//`DENALI_PHY_860_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +860 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +862 <<2));//`DENALI_PHY_862_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +862 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +857 <<2));//`DENALI_PHY_857_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +857 <<2), tmp&0xffffff00|0x00000051);
+
+    //phy level registers
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1895 <<2));//`DENALI_PHY_1895_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1895 <<2), tmp&0xffffe000|0x00001342);
+
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1895 <<2), tmp);//`DENALI_PHY_1895_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1895 <<2), tmp&32'hfffe_ffff|32'h0001_0000); //for memory clock<=400M
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1835 <<2));//`DENALI_PHY_1835_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1835 <<2), tmp&0xfffff0ff|0x00000200);
+
+    //turn on multicast
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffffeff|0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfffffeff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +66 <<2));//`DENALI_PI_66_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +66 <<2), tmp&0xfffffeff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xffffff80|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xffff80ff|0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +179 <<2));//`DENALI_PI_179_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +179 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +179 <<2));//`DENALI_PI_179_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +179 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +182 <<2));//`DENALI_PI_182_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +182 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +182 <<2));//`DENALI_PI_182_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +182 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +167 <<2));//`DENALI_PI_167_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +167 <<2), tmp&0xffffff80|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +167 <<2));//`DENALI_PI_167_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +167 <<2), tmp&0xffff80ff|0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +185 <<2));//`DENALI_PI_185_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +185 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +185 <<2));//`DENALI_PI_185_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +185 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +10 <<2));//`DENALI_PI_10_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +10 <<2), tmp&0xffffffe0|0x00000002);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +0 <<2));//`DENALI_PI_00_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +0 <<2), tmp&0xfffffffe|0x00000001);
+
+    //Reduce time for IO pad calibration TODO
+    //tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1860 <<2));//`DENALI_PHY_1860_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (4096 +1860 <<2), tmp&0x80ffffff|0x01000000);
+
+
+    //PI_CS_MAP: 0xf->0x3
+    //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);
+    //if(tmp != 32'h0300080f) $stop; //`DENALI_PI_11_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), 32'h03000803);
+
+    //set CS0 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +247 <<2));//`DENALI_PI_247_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +247 <<2), tmp | 0x00000008);
+
+    //set CS1 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +249 <<2));//`DENALI_PI_249_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +249 <<2), tmp | 0x00000800);
+
+    //set CS2 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +252 <<2));//`DENALI_PI_252_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +252 <<2), tmp | 0x00000008);
+
+    //set CS3 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +254 <<2));//`DENALI_PI_254_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +254 <<2), tmp | 0x00000800);
+
+	//PI_MR11_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +281 <<2)); //DENALI_PI_281_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +281 <<2), tmp|0x66000000); //DENALI_PI_281_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +305 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +305 <<2), tmp|0x66000000); //DENALI_PI_305_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +329 <<2)); //DENALI_PI_337_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +329 <<2), tmp|0x66000000); //DENALI_PI_329_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +353 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +353 <<2), tmp|0x66000000); //DENALI_PI_353_DATA
+
+	//PI_MR11_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +289 <<2)); //DENALI_PI_289_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +289 <<2), tmp|0x66000000); //DENALI_PI_289_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +313 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +313 <<2), tmp|0x66000000); //DENALI_PI_313_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +337 <<2)); //DENALI_PI_337_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +337 <<2), tmp|0x66000000); //DENALI_PI_337_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +361 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +361 <<2), tmp|0x66000000); //DENALI_PI_361_DATA
+
+	//PI_MR22_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp|0x00160000); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp|0x00160000); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp|0x00160000); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp|0x00160000); //DENALI_PI_354_DATA
+
+	//PI_MR22_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp|0x00160000); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp|0x00160000); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp|0x00160000); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp|0x00160000); //DENALI_PI_362_DATA
+#if 1
+	//PI_MR12_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp&0xffffff00|0x15); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp&0xffffff00|0x15); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp&0xffffff00|0x15); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp&0xffffff00|0x15); //DENALI_PI_354_DATA
+
+	//PI_MR12_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp&0xffffff00|0x15); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp&0xffffff00|0x15); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp&0xffffff00|0x15); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp&0xffffff00|0x15); //DENALI_PI_362_DATA
+
+	//PI_MR14_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_354_DATA
+
+	//PI_MR14_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_362_DATA
+#endif
+		
+/*
+    //set PHY_LP4_WDQS_OE_EXTEND_x
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +65 <<2));//`DENALI_PHY_65_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +65 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +321 <<2));//`DENALI_PHY_321_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +321 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +577 <<2));//`DENALI_PHY_577_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +577 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +833 <<2));//`DENALI_PHY_833_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +833 <<2), tmp | 0x00000100);
+*/
+    //PHY_RPTR_UPDATE_x: bit[11:8]+=3
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp+0x0300);
+
+#ifdef G_SPEED_3200
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h18
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00180000);
+#elif defined G_SPEED_2666
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h14
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00140000);
+#elif defined G_SPEED_2133
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h12
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00120000);
+    //`elsif G_SPEED_1600
+#endif
+
+    //PHY_WDQLVL_CLK_JITTER_TOLERANCE_X: 8'h20 -> 8'h40 
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +33 <<2));//`DENALI_PHY_33_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +33 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +289 <<2));//`DENALI_PHY_289_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +289 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +545 <<2));//`DENALI_PHY_545_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +545 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +801 <<2));//`DENALI_PHY_801_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +801 <<2), tmp&0xffffff00|0x0040);
+
+    //PHY_ADR_CALVL_NUM_PATTERNS_X: 2'h0 -> 2'h01 TODO
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1039 <<2), tmp);//`DENALI_PHY_1039_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1039 <<2), tmp|32'h01);
+    //
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1295 <<2), tmp);//`DENALI_PHY_1295_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1295 <<2), tmp|32'h01);
+    //
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1551 <<2), tmp);//`DENALI_PHY_1551_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1551 <<2), tmp|32'h01);
+
+
+    //PHY_ADR_CALVL_RANK_CTRL_x: 2'b11 -> 2'b10
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1038 <<2));//`DENALI_PHY_1038_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1038 <<2), tmp&0xfcffffff|0x02000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1294 <<2));//`DENALI_PHY_1294_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1294 <<2), tmp&0xfcffffff|0x02000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1550 <<2));//`DENALI_PHY_1550_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1550 <<2), tmp&0xfcffffff|0x02000000);
+
+#if 1//0807
+//PHY_PAD_DSLICE_IO_CFG_x:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +83 <<2)); //DENALI_PHY_83_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +83 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_83_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +339 <<2)); //DENALI_PHY_339_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +339 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_339_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +595 <<2)); //DENALI_PHY_595_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +595 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_595_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +851 <<2)); //DENALI_PHY_851_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +851 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_851_DATA
+
+//PHY_PAD_ADR_IO_CFG_x:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1062 <<2)); //DENALI_PHY_1062_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1062 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1062_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1318 <<2)); //DENALI_PHY_1318_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1318 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1318_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1574 <<2)); //DENALI_PHY_1574_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1574 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1574_DATA
+
+//PHY_PAD_CAL_IO_CFG_0:0->7->0x15547 VREFSEL_CAL/CAL2[5:0]=0x15
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1892 <<2)); //DENALI_PHY_1892_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1892 <<2), tmp&0xfffc0000|0x15547); //DENALI_PHY_1892_DATA
+
+//PHY_ADRCTL_PVT_MAP_0:0x35->0x14
+//tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1864 <<2)); //DENALI_PHY_1864_DATA
+//apb_write(PHY_APB_BASE_ADDR + (4096 +1864 <<2), tmp&0xffffff00|0x14); //DENALI_PHY_1864_DATA
+
+//PHY_PAD_ACS_IO_CFG:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1893 <<2)); //DENALI_PHY_1893_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1893 <<2), tmp&0xfffc0000|0x7); //DENALI_PHY_1893_DATA
+
+//PHY_CAL_MODE_0 TODO: 0x78->0x7a, periodic_enable
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1852 <<2)); //DENALI_PHY_1852_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1852 <<2), tmp&0xffffe000|0x07a); //DENALI_PHY_1852_DATA
+
+//PHY_CAL_INTERVAL_COUNT_0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1853 <<2), tmp&0x8000); //DENALI_PHY_1853_DATA
+
+//PHY_PLL_WAIT
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1822 <<2)); //DENALI_PHY_1822_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1822 <<2), tmp|0xFF); //DENALI_PHY_1822_DATA
+
+//PHY_PAD_VREF_CTRL_AC:10'h0100->10'h3d5
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1896 <<2)); //DENALI_PHY_1896_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1896 <<2), tmp&0xfffffc00|0x03d5); //DENALI_PHY_1896_DATA
+
+//PHY_PAD_VREF_CTRL_DQ_x:10'h11f->10'h3d5
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +91 <<2)); //DENALI_PHY_91_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +91 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_91_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +347 <<2)); //DENALI_PHY_347_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +347 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_347_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +603 <<2)); //DENALI_PHY_603_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +603 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_603_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +859 <<2)); //DENALI_PHY_859_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +859 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_859_DATA
+
+//PHY_PAD_FDBK_DRIVE:bit[7:0]:{ENSLICEP_DRV,ENSLICEN_DRV}
+apb_write(PHY_APB_BASE_ADDR + (4096 +1912 <<2), 0xcc3bfc7); //DENALI_PHY_1912_DATA //RX_CTLE[25:24], SPEED[23:22]=3, tx_pulldwn[21:20]=2'b00, MODE[17:15]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_FDBK_DRIVE2:bit[7:0]:{ENSLICEP_ODT,ENSLICEN_ODT}
+apb_write(PHY_APB_BASE_ADDR + (4096 +1913 <<2), 0xff8f); //DENALI_PHY_1913_DATA      //BOOSTP[15:12]=F, BOOSTN[11:18]=F
+//PHY_PAD_DATA_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1914 <<2), 0x33f07ff); //DENALI_PHY_1914_DATA   //tx_pulldwn[21:20]=2'b11, SPEED[10:9]=3, MODE[8:6]=7, SLEWP[5:3]=7, SLEWN[2:0]=7
+//PHY_PAD_DQS_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1915 <<2), 0xc3c37ff); //DENALI_PHY_1915_DATA   //tx_pulldwn[13:12]=2'b11, SPEED[10:9]=3, MODE[8:6]=7, SLEWP[5:3]=7, SLEWN[2:0]=7
+//PHY_PAD_ADDR_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1916 <<2), 0x1fffff10); //DENALI_PHY_1916_DATA //BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7, tx_pulldwn[6:5]=2'b00
+//PHY_PAD_ADDR_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1917 <<2), 0x230070); //DENALI_PHY_1917_DATA    //RX_CTLE[6:5]=2'b11
+//PHY_PAD_CLK_DRIVE  //ENSLICEP_DRV/ODT[7:4], ENSLICEN_DRV/ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1918 <<2), 0x3ff7ffff); //DENALI_PHY_1918_DATA //BOOSTP[29:26]=F, BOOSTN[25:22]=F, tx_pulldwn[21:20]=2'b11, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CLK_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1919 <<2), 0xe10); //DENALI_PHY_1919_DATA
+//PHY_PAD_ERR_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1920 <<2), 0x1fffffff); //DENALI_PHY_1920_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_ERR_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1921 <<2), 0x188411); //DENALI_PHY_1921_DATA    //RX_CTLE[18:17]
+//PHY_PAD_CKE_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1922 <<2), 0x1fffffff); //DENALI_PHY_1922_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CKE_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1923 <<2), 0x180400); //DENALI_PHY_1923_DATA    //RX_CTLE[18:17]
+//PHY_PAD_RST_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1924 <<2), 0x1fffffff); //DENALI_PHY_1924_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_RST_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1925 <<2), 0x180400); //DENALI_PHY_1925_DATA    //RX_CTLE[18:17]
+//PHY_PAD_CS_DRIVE   //ENSLICEP_DRV/ODT[7:4], ENSLICEN_DRV/ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1926 <<2), 0x1fffffcf); //DENALI_PHY_1926_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CS_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1927 <<2), 0x188400); //DENALI_PHY_1927_DATA    //RX_CTLE[18:17]
+//PHY_PAD_ODT_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1928 <<2), 0x1fffffff); //DENALI_PHY_1928_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_CAL_CLK_SELECT_0[26:24],PHY_PAD_ODT_DRIVE2[21:0]:1->4
+apb_write(PHY_APB_BASE_ADDR + (4096 +1929 <<2), 0x4188411); //DENALI_PHY_1929_DATA  //PHY_CAL_CLK_SELECT_0[26:24], RX_CTLE[18:17]
+
+//PHY_PAD_FDBK_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1837 <<2), 0x24410); //DENALI_PHY_1837_DATA //TSEL[17]=1
+//PHY_PAD_ADDR_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1840 <<2), 0x24410); //DENALI_PHY_1840_DATA //TSEL[17]=1
+//PHY_PAD_ERR_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1842 <<2), 0x2ffff); //DENALI_PHY_1842_DATA //TSEL[17]=1
+
+//PHY_DQ_TSEL_SELECT_X bit[15:8]={ENSLICEP_DRV,ENSLICEN_DRV}:tsel_wr_select  bit[7:0]={ENSLICEP_ODT,ENSLICEN_ODT}:tsel_rd_select
+if(ddr_num == 0) //ddr0
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +76 <<2)); //DENALI_PHY_76_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +76 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_76_DATA //dqs0/dm0/dq0:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +332 <<2)); //DENALI_PHY_332_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +332 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_332_DATA //dqs1/dm1/dq8:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +588 <<2)); //DENALI_PHY_588_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +588 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_588_DATA //dqs2/dm2/dq16:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +844 <<2)); //DENALI_PHY_844_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +844 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_844_DATA //dqs3/dm3/dq24:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+}
+else //ddr1
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +76 <<2)); //DENALI_PHY_76_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +76 <<2), tmp&0xff0000f8|0x00ff4f07); //DENALI_PHY_76_DATA //dqs0/dm0/dq0:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +332 <<2)); //DENALI_PHY_332_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +332 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_332_DATA //dqs1/dm1/dq8:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +588 <<2)); //DENALI_PHY_588_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +588 <<2), tmp&0xff0000f8|0x00ff4f07); //DENALI_PHY_588_DATA //dqs2/dm2/dq16:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +844 <<2)); //DENALI_PHY_844_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +844 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_844_DATA //dqs3/dm3/dq24:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+}
+
+//PHY_DQS_TSEL_SELECT_X  bit[15:8]={ENSLICEP_DRV,ENSLICEN_DRV}:tsel_wr_select  bit[7:0]={ENSLICEP_ODT,ENSLICEN_ODT}:tsel_rd_select
+if(ddr_num == 0) //ddr0
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +77 <<2)); //DENALI_PHY_77_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +77 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_77_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +333 <<2)); //DENALI_PHY_333_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +333 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_333_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +589 <<2)); //DENALI_PHY_589_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +589 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_589_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +845 <<2)); //DENALI_PHY_845_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +845 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_845_DATA
+}
+else //ddr1
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +77 <<2)); //DENALI_PHY_77_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +77 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_77_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +333 <<2)); //DENALI_PHY_333_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +333 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_333_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +589 <<2)); //DENALI_PHY_589_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +589 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_589_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +845 <<2)); //DENALI_PHY_845_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +845 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_845_DATA
+}
+
+//PHY_ADR_TSEL_SELECT_X:bit[7:0]:{ENSLICEP_ODT/DRV,PENSLICEN_ODT/DRV}
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1062 <<2)); //DENALI_PHY_1062_DATA for addr5-0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1062 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1062_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1318 <<2)); //DENALI_PHY_1318_DATA for addr11-6
+apb_write(PHY_APB_BASE_ADDR + (4096 +1318 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1318_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1574 <<2)); //DENALI_PHY_1574_DATA for addr15-12
+apb_write(PHY_APB_BASE_ADDR + (4096 +1574 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1574_DATA
+
+//PHY_ADR_TSEL_ENABLE_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1028 <<2)); //DENALI_PHY_1028_DATA for addr5-0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1028 <<2), tmp|0x1000000); //DENALI_PHY_1028_DATA //addr5-0:TSEL[24]=1
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1284 <<2)); //DENALI_PHY_1284_DATA for addr11-6
+apb_write(PHY_APB_BASE_ADDR + (4096 +1284 <<2), tmp|0x1000000); //DENALI_PHY_1284_DATA //addr11-6:TSEL[24]=1
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1540 <<2)); //DENALI_PHY_1540_DATA for addr15-12
+apb_write(PHY_APB_BASE_ADDR + (4096 +1540 <<2), tmp|0x1000000); //DENALI_PHY_1540_DATA //addr15-12:TSEL[24]=1
+
+//PHY_TST_CLK_PAD_CTRL_x   tst_clk_pad/tst_refclk_pad
+apb_write(PHY_APB_BASE_ADDR + (4096 +1848 <<2), 0x3cf07f8); //DENALI_PHY_1848_DATA  //tx_pulldwn[31:30]=2'b00, ENSLICEP_DRV[10:7], ENSLICEN_DRV[6:3], IE[2], TSEL[1], OE[0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1849 <<2), 0x3f); //DENALI_PHY_1849_DATA       //SLEWP[5:3]=7, SLEWN[2:0]=7
+apb_write(PHY_APB_BASE_ADDR + (4096 +1850 <<2), 0x1fffff); //DENALI_PHY_1850_DATA   //SPEED[20:19]=3, MODE[18:16]=7, BOOSTN[15:12]=F, BOOSTP[11:8]=F, ENSLICEP_ODT[7:4], ENSLICEN_ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1851 <<2), 0x190000); //DENALI_PHY_1851_DATA   //RX_CTLE[18:17]=3
+
+//PHY_DSLICE_PAD_BOOSTPN_SETTING_x
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +130 <<2)); //DENALI_PI_130_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +130 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_130_DATA //dqs0_BOOSTP[31:28]=F, dqs0_BOOSTN[27:24]=F, dq0/dm0_BOOSTP[23:20]=F, dq0/dm0_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +386 <<2)); //DENALI_PI_386_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +386 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_386_DATA //dqs1_BOOSTP[31:28]=F, dqs1_BOOSTN[27:24]=F, dq8/dm1_BOOSTP[23:20]=F, dq8/dm1_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +642 <<2)); //DENALI_PI_642_DATA
+apb_write(PHY_APB_BASE_ADDR + (2048 +642 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_642_DATA //dqs2_BOOSTP[31:28]=F, dqs2_BOOSTN[27:24]=F, dq16/dm2_BOOSTP[23:20]=F, dq16/dm2_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +898 <<2)); //DENALI_PI_898_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +898 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_898_DATA //dqs3_BOOSTP[31:28]=F, dqs3_BOOSTN[27:24]=F, dq24/dm3_BOOSTP[23:20]=F, dq24/dm3_BOOSTN[19:16]=F
+
+//PHY_DSLICE_PAD_RX_CTLE_SETTING_x
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +131 <<2)); //DENALI_PI_131_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +131 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_131_DATA //dqs0_RX_CTLE[3:2]=3, dq0/dm0_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +387 <<2)); //DENALI_PI_387_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +387 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_387_DATA //dqs1_RX_CTLE[3:2]=3, dq8/dm1_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +643 <<2)); //DENALI_PI_643_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +643 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_643_DATA //dqs2_RX_CTLE[3:2]=3, dq16/dm2_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +899 <<2)); //DENALI_PI_899_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +899 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_899_DATA //dqs3_RX_CTLE[3:2]=3, dq24/dm3_RX_CTLE[1:0]=3
+
+
+#if 1
+//PHY_WRLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +29 <<2)); //DENALI_PHY_29_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +29 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_29_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +285 <<2)); //DENALI_PHY_285_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +285 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_285_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +541 <<2)); //DENALI_PHY_541_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +541 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_541_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +797 <<2)); //DENALI_PHY_797_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +797 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_797_DATA
+
+//PHY_GTLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +30 <<2)); //DENALI_PHY_30_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +30 <<2), (tmp |0x00080000)); //DENALI_PHY_30_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +286 <<2)); //DENALI_PHY_286_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +286 <<2), (tmp |0x00080000)); //DENALI_PHY_286_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +542 <<2)); //DENALI_PHY_542_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +542 <<2), (tmp |0x00080000)); //DENALI_PHY_542_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +798 <<2)); //DENALI_PHY_798_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +798 <<2), (tmp |0x00080000)); //DENALI_PHY_797_DATA
+
+
+//PHY_RDLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +31 <<2)); //DENALI_PHY_31_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +31 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_31_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +287 <<2)); //DENALI_PHY_287_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +287 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_287_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +543 <<2)); //DENALI_PHY_543_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +543 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_543_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +799 <<2)); //DENALI_PHY_799_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +799 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_799_DATA
+
+//PHY_ADRLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1071 <<2)); //DENALI_PHY_1071_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1071 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1071_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1327 <<2)); //DENALI_PHY_1327_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1327 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1327_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1583 <<2)); //DENALI_PHY_1583_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1583 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1583_DATA
+
+//PHY_CSLVL_COARSECAPTURE_CNT
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1808 <<2)); //DENALI_PHY_1808_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1808 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1808_DATA
+
+//PHY_CSLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1896 <<2)); //DENALI_PHY_1896_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1896 <<2), ((tmp & 0xFFFFFFF0)|0X00080000)); //DENALI_PHY_1896DATA
+#endif
+
+	
+#endif
+
+}
+
+//PHY_WRLVL_DELAY_EARLY_THRESHOLD_X: 10'h1A0 -> 10'h00 TODO:need deleted
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd123 <<2), tmp);//`DENALI_PHY_123_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd123 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd379 <<2), tmp);//`DENALI_PHY_379_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd379 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd635 <<2), tmp);//`DENALI_PHY_635_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd635 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd891 <<2), tmp);//`DENALI_PHY_891_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd891 <<2), tmp&32'hfc00_ffff);
+
+//release dll_rst_n
+//apb_write(PHY_APB_BASE_ADDR + (16'd0000 +16'd00 << 2), 32'h01);

+ 736 - 0
ddrphy_cfg/lpddr4_1600_cl28_bl16/regconfig_pi_start_3200.c

@@ -0,0 +1,736 @@
+#include <regconfig.h.sim_PI.h>
+#include <regconfig.h.sim_PHY.h>
+#include <sys.h>
+#include <clkgen_ctrl_macro.h>
+#include <comdef.h>
+#include <ddr_define.h>
+void regconfig_pi_start(uint32_t OMC_APB_BASE_ADDR, uint32_t OMC_SECURE_APB_BASE_ADDR, uint32_t PHY_APB_BASE_ADDR, u32 ddr_num)
+{
+    u32 tmp = 0;
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +89 <<2));//`DENALI_PHY_89_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +89 <<2), tmp&0xffffff00|0x00000051); //0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +78 <<2));//`DENALI_PHY_78_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +78 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +345 <<2));//`DENALI_PHY_345_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +345 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +334 <<2));//`DENALI_PHY_334_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +334 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +601 <<2));//`DENALI_PHY_601_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +601 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +590 <<2));//`DENALI_PHY_590_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +590 <<2), tmp&0xfffffcff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +857 <<2));//`DENALI_PHY_857_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +857 <<2), tmp&0xffffff00|0x00000051);//0x51->0x61
+
+    //disable RDLVL VREF
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +846 <<2));//`DENALI_PHY_846_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +846 <<2), tmp&0xfffffcff);
+
+    //turn off multicast
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffffeff);
+
+    //set to freq copy 0
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffcffff);
+
+    //data slice registers
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +125 <<2));//`DENALI_PHY_125_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +125 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +102 <<2));//`DENALI_PHY_102_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +102 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +105 <<2));//`DENALI_PHY_105_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +105 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +92 <<2));//`DENALI_PHY_92_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +92 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +94 <<2));//`DENALI_PHY_94_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +94 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +89 <<2));//`DENALI_PHY_89_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +89 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +381 <<2));//`DENALI_PHY_381_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +381 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +358 <<2));//`DENALI_PHY_358_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +358 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +361 <<2));//`DENALI_PHY_361_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +361 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +348 <<2));//`DENALI_PHY_348_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +348 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +350 <<2));//`DENALI_PHY_350_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +350 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +345 <<2));//`DENALI_PHY_345_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +345 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +637 <<2));//`DENALI_PHY_637_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +637 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +614 <<2));//`DENALI_PHY_614_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +614 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +617 <<2));//`DENALI_PHY_617_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +617 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +604 <<2));//`DENALI_PHY_604_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +604 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +606 <<2));//`DENALI_PHY_606_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +606 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +601 <<2));//`DENALI_PHY_601_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +601 <<2), tmp&0xffffff00|0x00000051);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +893 <<2));//`DENALI_PHY_893_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +893 <<2), tmp&0xfff0ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +870 <<2));//`DENALI_PHY_870_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +870 <<2), tmp&0xfffffffc|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +873 <<2));//`DENALI_PHY_873_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +873 <<2), tmp&0xffffffe0|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +860 <<2));//`DENALI_PHY_860_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +860 <<2), tmp&0xfffffffe|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +862 <<2));//`DENALI_PHY_862_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +862 <<2), tmp&0xffffe0ff|0x00000200);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xfffff0ff|0x00000400);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +857 <<2));//`DENALI_PHY_857_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +857 <<2), tmp&0xffffff00|0x00000051);
+
+    //phy level registers
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1895 <<2));//`DENALI_PHY_1895_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1895 <<2), tmp&0xffffe000|0x00001342);
+
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1895 <<2), tmp);//`DENALI_PHY_1895_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1895 <<2), tmp&32'hfffe_ffff|32'h0001_0000); //for memory clock<=400M
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1835 <<2));//`DENALI_PHY_1835_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1835 <<2), tmp&0xfffff0ff|0x00000200);
+
+    //turn on multicast
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1793 <<2));//`DENALI_PHY_1793_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1793 <<2), tmp&0xfffffeff|0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfffffeff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +66 <<2));//`DENALI_PI_66_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +66 <<2), tmp&0xfffffeff);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xffffff80|0x00000001);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[19:16]=0x1
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xffff80ff|0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +179 <<2));//`DENALI_PI_179_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +179 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[20:16]=0x01
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +179 <<2));//`DENALI_PI_179_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +179 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[19:16]=0x1
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +166 <<2));//`DENALI_PI_166_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +166 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +182 <<2));//`DENALI_PI_182_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +182 <<2), tmp&0xff80ffff|0x00010000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[20:16]=0x01
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +182 <<2));//`DENALI_PI_182_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +182 <<2), tmp&0x80ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +167 <<2));//`DENALI_PI_167_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +167 <<2), tmp&0xffffff80|0x00000015);//PI_CALVL_VREF_INITIAL_START_POINT_F2[6:0]:0x01->0x15
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xfff0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[19:16]=0x1
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +62 <<2));//`DENALI_PI_62_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +62 <<2), tmp&0xf0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +167 <<2));//`DENALI_PI_167_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +167 <<2), tmp&0xffff80ff|0x00001500);//PI_CALVL_VREF_INITIAL_STOP_POINT_F2[14:8]:0x01->0x15
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +185 <<2));//`DENALI_PI_185_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +185 <<2), tmp&0xff80ffff|0x001a0000);//PI_WDQLVL_VREF_INITIAL_START_POINT_F2[22:16]:0x01->0x1a
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xffe0ffff|0x00010000);//PI_CALVL_VREF_INITIAL_STEPSIZE[20:16]=0x01
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +67 <<2));//`DENALI_PI_67_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +67 <<2), tmp&0xe0ffffff|0x01000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +185 <<2));//`DENALI_PI_185_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +185 <<2), tmp&0x80ffffff|0x1a000000);//PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2[30:24]:0x01->0x1a
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +10 <<2));//`DENALI_PI_10_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +10 <<2), tmp&0xffffffe0|0x00000002);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +0 <<2));//`DENALI_PI_00_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +0 <<2), tmp&0xfffffffe|0x00000001);
+
+    //Reduce time for IO pad calibration TODO
+    //tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1860 <<2));//`DENALI_PHY_1860_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (4096 +1860 <<2), tmp&0x80ffffff|0x01000000);
+
+
+    //PI_CS_MAP: 0xf->0x3
+    //apb_read(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), tmp);
+    //if(tmp != 32'h0300080f) $stop; //`DENALI_PI_11_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd2048 +16'd11 <<2), 32'h03000803);
+
+    //set CS0 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +247 <<2));//`DENALI_PI_247_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +247 <<2), tmp | 0x00000008);
+
+    //set CS1 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +249 <<2));//`DENALI_PI_249_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +249 <<2), tmp | 0x00000800);
+
+    //set CS2 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +252 <<2));//`DENALI_PI_252_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +252 <<2), tmp | 0x00000008);
+
+    //set CS3 MR13.VRCG=1
+    tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +254 <<2));//`DENALI_PI_254_DATA
+    apb_write(PHY_APB_BASE_ADDR + (2048 +254 <<2), tmp | 0x00000800);
+
+	//PI_MR11_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +281 <<2)); //DENALI_PI_281_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +281 <<2), tmp|0x66000000); //DENALI_PI_281_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +305 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +305 <<2), tmp|0x66000000); //DENALI_PI_305_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +329 <<2)); //DENALI_PI_337_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +329 <<2), tmp|0x66000000); //DENALI_PI_329_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +353 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +353 <<2), tmp|0x66000000); //DENALI_PI_353_DATA
+
+	//PI_MR11_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +289 <<2)); //DENALI_PI_289_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +289 <<2), tmp|0x66000000); //DENALI_PI_289_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +313 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +313 <<2), tmp|0x66000000); //DENALI_PI_313_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +337 <<2)); //DENALI_PI_337_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +337 <<2), tmp|0x66000000); //DENALI_PI_337_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +361 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +361 <<2), tmp|0x66000000); //DENALI_PI_361_DATA
+
+	//PI_MR22_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp|0x00160000); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp|0x00160000); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp|0x00160000); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp|0x00160000); //DENALI_PI_354_DATA
+
+	//PI_MR22_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp|0x00160000); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp|0x00160000); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp|0x00160000); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp|0x00160000); //DENALI_PI_362_DATA
+#if 1
+	//PI_MR12_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp&0xffffff00|0x15); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp&0xffffff00|0x15); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp&0xffffff00|0x15); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp&0xffffff00|0x15); //DENALI_PI_354_DATA
+
+	//PI_MR12_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp&0xffffff00|0x15); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp&0xffffff00|0x15); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp&0xffffff00|0x15); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp&0xffffff00|0x15); //DENALI_PI_362_DATA
+
+	//PI_MR14_DATA_F1_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +282 <<2)); //DENALI_PI_282_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +282 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_282_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +306 <<2)); //DENALI_PI_313_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +306 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_306_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +330 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +330 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_330_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +354 <<2)); //DENALI_PI_361_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +354 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_354_DATA
+
+	//PI_MR14_DATA_F2_X
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +290 <<2)); //DENALI_PI_290_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +290 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_290_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +314 <<2)); //DENALI_PI_314_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +314 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_314_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +338 <<2)); //DENALI_PI_330_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +338 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_338_DATA
+	tmp = apb_read(PHY_APB_BASE_ADDR + (2048 +362 <<2)); //DENALI_PI_362_DATA
+	apb_write(PHY_APB_BASE_ADDR + (2048 +362 <<2), tmp&0xffff00ff|0x1700); //DENALI_PI_362_DATA
+#endif
+		
+/*
+    //set PHY_LP4_WDQS_OE_EXTEND_x
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +65 <<2));//`DENALI_PHY_65_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +65 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +321 <<2));//`DENALI_PHY_321_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +321 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +577 <<2));//`DENALI_PHY_577_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +577 <<2), tmp | 0x00000100);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +833 <<2));//`DENALI_PHY_833_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +833 <<2), tmp | 0x00000100);
+*/
+    //PHY_RPTR_UPDATE_x: bit[11:8]+=3
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp+0x0300);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp+0x0300);
+
+#ifdef G_SPEED_3200
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h18
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00180000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00180000);
+#elif defined G_SPEED_2666
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h14
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00140000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00140000);
+#elif defined G_SPEED_2133
+    //PHY_WRLVL_DLY_STEP_X: 8'hC -> 8'h12
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +96 <<2));//`DENALI_PHY_96_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +96 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +352 <<2));//`DENALI_PHY_352_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +352 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +608 <<2));//`DENALI_PHY_608_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +608 <<2), tmp&0xff00ffff|0x00120000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +864 <<2));//`DENALI_PHY_864_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +864 <<2), tmp&0xff00ffff|0x00120000);
+    //`elsif G_SPEED_1600
+#endif
+
+    //PHY_WDQLVL_CLK_JITTER_TOLERANCE_X: 8'h20 -> 8'h40 
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +33 <<2));//`DENALI_PHY_33_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +33 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +289 <<2));//`DENALI_PHY_289_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +289 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +545 <<2));//`DENALI_PHY_545_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +545 <<2), tmp&0xffffff00|0x0040);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +801 <<2));//`DENALI_PHY_801_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +801 <<2), tmp&0xffffff00|0x0040);
+
+    //PHY_ADR_CALVL_NUM_PATTERNS_X: 2'h0 -> 2'h01 TODO
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1039 <<2), tmp);//`DENALI_PHY_1039_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1039 <<2), tmp|32'h01);
+    //
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1295 <<2), tmp);//`DENALI_PHY_1295_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1295 <<2), tmp|32'h01);
+    //
+    //apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd1551 <<2), tmp);//`DENALI_PHY_1551_DATA
+    //apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd1551 <<2), tmp|32'h01);
+
+
+    //PHY_ADR_CALVL_RANK_CTRL_x: 2'b11 -> 2'b10
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1038 <<2));//`DENALI_PHY_1038_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1038 <<2), tmp&0xfcffffff|0x02000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1294 <<2));//`DENALI_PHY_1294_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1294 <<2), tmp&0xfcffffff|0x02000000);
+
+    tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1550 <<2));//`DENALI_PHY_1550_DATA
+    apb_write(PHY_APB_BASE_ADDR + (4096 +1550 <<2), tmp&0xfcffffff|0x02000000);
+
+#if 1//0807
+//PHY_PAD_DSLICE_IO_CFG_x:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +83 <<2)); //DENALI_PHY_83_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +83 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_83_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +339 <<2)); //DENALI_PHY_339_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +339 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_339_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +595 <<2)); //DENALI_PHY_595_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +595 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_595_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +851 <<2)); //DENALI_PHY_851_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +851 <<2), tmp&0xffc0ffff|0x70000); //DENALI_PHY_851_DATA
+
+//PHY_PAD_ADR_IO_CFG_x:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1062 <<2)); //DENALI_PHY_1062_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1062 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1062_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1318 <<2)); //DENALI_PHY_1318_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1318 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1318_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1574 <<2)); //DENALI_PHY_1574_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1574 <<2), tmp&0xf800ffff|0x70000); //DENALI_PHY_1574_DATA
+
+//PHY_PAD_CAL_IO_CFG_0:0->7->0x15547 VREFSEL_CAL/CAL2[5:0]=0x15
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1892 <<2)); //DENALI_PHY_1892_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1892 <<2), tmp&0xfffc0000|0x15547); //DENALI_PHY_1892_DATA
+
+//PHY_ADRCTL_PVT_MAP_0:0x35->0x14
+//tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1864 <<2)); //DENALI_PHY_1864_DATA
+//apb_write(PHY_APB_BASE_ADDR + (4096 +1864 <<2), tmp&0xffffff00|0x14); //DENALI_PHY_1864_DATA
+
+//PHY_PAD_ACS_IO_CFG:0->7
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1893 <<2)); //DENALI_PHY_1893_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1893 <<2), tmp&0xfffc0000|0x7); //DENALI_PHY_1893_DATA
+
+//PHY_CAL_MODE_0 TODO: 0x78->0x7a, periodic_enable
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1852 <<2)); //DENALI_PHY_1852_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1852 <<2), tmp&0xffffe000|0x07a); //DENALI_PHY_1852_DATA
+
+//PHY_CAL_INTERVAL_COUNT_0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1853 <<2), tmp&0x8000); //DENALI_PHY_1853_DATA
+
+//PHY_PLL_WAIT
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1822 <<2)); //DENALI_PHY_1822_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1822 <<2), tmp|0xFF); //DENALI_PHY_1822_DATA
+
+//PHY_PAD_VREF_CTRL_AC:10'h0100->10'h3d5
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1896 <<2)); //DENALI_PHY_1896_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1896 <<2), tmp&0xfffffc00|0x03d5); //DENALI_PHY_1896_DATA
+
+//PHY_PAD_VREF_CTRL_DQ_x:10'h11f->10'h3d5
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +91 <<2)); //DENALI_PHY_91_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +91 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_91_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +347 <<2)); //DENALI_PHY_347_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +347 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_347_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +603 <<2)); //DENALI_PHY_603_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +603 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_603_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +859 <<2)); //DENALI_PHY_859_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +859 <<2), tmp&0xfc00ffff|0x03d50000); //DENALI_PHY_859_DATA
+
+//PHY_PAD_FDBK_DRIVE:bit[7:0]:{ENSLICEP_DRV,ENSLICEN_DRV}
+apb_write(PHY_APB_BASE_ADDR + (4096 +1912 <<2), 0xcc3bfc7); //DENALI_PHY_1912_DATA //RX_CTLE[25:24], SPEED[23:22]=3, tx_pulldwn[21:20]=2'b00, MODE[17:15]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_FDBK_DRIVE2:bit[7:0]:{ENSLICEP_ODT,ENSLICEN_ODT}
+apb_write(PHY_APB_BASE_ADDR + (4096 +1913 <<2), 0xff8f); //DENALI_PHY_1913_DATA      //BOOSTP[15:12]=F, BOOSTN[11:18]=F
+//PHY_PAD_DATA_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1914 <<2), 0x33f07ff); //DENALI_PHY_1914_DATA   //tx_pulldwn[21:20]=2'b11, SPEED[10:9]=3, MODE[8:6]=7, SLEWP[5:3]=7, SLEWN[2:0]=7
+//PHY_PAD_DQS_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1915 <<2), 0xc3c37ff); //DENALI_PHY_1915_DATA   //tx_pulldwn[13:12]=2'b11, SPEED[10:9]=3, MODE[8:6]=7, SLEWP[5:3]=7, SLEWN[2:0]=7
+//PHY_PAD_ADDR_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1916 <<2), 0x1fffff10); //DENALI_PHY_1916_DATA //BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7, tx_pulldwn[6:5]=2'b00
+//PHY_PAD_ADDR_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1917 <<2), 0x230070); //DENALI_PHY_1917_DATA    //RX_CTLE[6:5]=2'b11
+//PHY_PAD_CLK_DRIVE  //ENSLICEP_DRV/ODT[7:4], ENSLICEN_DRV/ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1918 <<2), 0x3ff7ffff); //DENALI_PHY_1918_DATA //BOOSTP[29:26]=F, BOOSTN[25:22]=F, tx_pulldwn[21:20]=2'b11, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CLK_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1919 <<2), 0xe10); //DENALI_PHY_1919_DATA
+//PHY_PAD_ERR_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1920 <<2), 0x1fffffff); //DENALI_PHY_1920_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_ERR_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1921 <<2), 0x188411); //DENALI_PHY_1921_DATA    //RX_CTLE[18:17]
+//PHY_PAD_CKE_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1922 <<2), 0x1fffffff); //DENALI_PHY_1922_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CKE_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1923 <<2), 0x180400); //DENALI_PHY_1923_DATA    //RX_CTLE[18:17]
+//PHY_PAD_RST_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1924 <<2), 0x1fffffff); //DENALI_PHY_1924_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_RST_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1925 <<2), 0x180400); //DENALI_PHY_1925_DATA    //RX_CTLE[18:17]
+//PHY_PAD_CS_DRIVE   //ENSLICEP_DRV/ODT[7:4], ENSLICEN_DRV/ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1926 <<2), 0x1fffffcf); //DENALI_PHY_1926_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_PAD_CS_DRIVE2
+apb_write(PHY_APB_BASE_ADDR + (4096 +1927 <<2), 0x188400); //DENALI_PHY_1927_DATA    //RX_CTLE[18:17]
+//PHY_PAD_ODT_DRIVE
+apb_write(PHY_APB_BASE_ADDR + (4096 +1928 <<2), 0x1fffffff); //DENALI_PHY_1928_DATA //tx_pulldwn[28:27]=2'b11, BOOSTP[26:23]=F, BOOSTN[22:19]=F, SPEED[18:17]=3, MODE[16:14]=7, SLEWP[13:11]=7, SLEWN[10:8]=7
+//PHY_CAL_CLK_SELECT_0[26:24],PHY_PAD_ODT_DRIVE2[21:0]:1->4
+apb_write(PHY_APB_BASE_ADDR + (4096 +1929 <<2), 0x4188411); //DENALI_PHY_1929_DATA  //PHY_CAL_CLK_SELECT_0[26:24], RX_CTLE[18:17]
+
+//PHY_PAD_FDBK_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1837 <<2), 0x24410); //DENALI_PHY_1837_DATA //TSEL[17]=1
+//PHY_PAD_ADDR_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1840 <<2), 0x24410); //DENALI_PHY_1840_DATA //TSEL[17]=1
+//PHY_PAD_ERR_TERM
+apb_write(PHY_APB_BASE_ADDR + (4096 +1842 <<2), 0x2ffff); //DENALI_PHY_1842_DATA //TSEL[17]=1
+
+//PHY_DQ_TSEL_SELECT_X bit[15:8]={ENSLICEP_DRV,ENSLICEN_DRV}:tsel_wr_select  bit[7:0]={ENSLICEP_ODT,ENSLICEN_ODT}:tsel_rd_select
+if(ddr_num == 0) //ddr0
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +76 <<2)); //DENALI_PHY_76_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +76 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_76_DATA //dqs0/dm0/dq0:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +332 <<2)); //DENALI_PHY_332_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +332 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_332_DATA //dqs1/dm1/dq8:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +588 <<2)); //DENALI_PHY_588_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +588 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_588_DATA //dqs2/dm2/dq16:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +844 <<2)); //DENALI_PHY_844_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +844 <<2), tmp&0xff0000f8|0x00ff8f07); //DENALI_PHY_844_DATA //dqs3/dm3/dq24:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+}
+else //ddr1
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +76 <<2)); //DENALI_PHY_76_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +76 <<2), tmp&0xff0000f8|0x00ff4f07); //DENALI_PHY_76_DATA //dqs0/dm0/dq0:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +332 <<2)); //DENALI_PHY_332_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +332 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_332_DATA //dqs1/dm1/dq8:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +588 <<2)); //DENALI_PHY_588_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +588 <<2), tmp&0xff0000f8|0x00ff4f07); //DENALI_PHY_588_DATA //dqs2/dm2/dq16:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +844 <<2)); //DENALI_PHY_844_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +844 <<2), tmp&0xff0000f8|0x00ff7c07); //DENALI_PHY_844_DATA //dqs3/dm3/dq24:tsel_idle_enp[2]=1, tsel_rd_en[1]=1, tsel_wr_en[0]=1
+}
+
+//PHY_DQS_TSEL_SELECT_X  bit[15:8]={ENSLICEP_DRV,ENSLICEN_DRV}:tsel_wr_select  bit[7:0]={ENSLICEP_ODT,ENSLICEN_ODT}:tsel_rd_select
+if(ddr_num == 0) //ddr0
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +77 <<2)); //DENALI_PHY_77_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +77 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_77_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +333 <<2)); //DENALI_PHY_333_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +333 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_333_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +589 <<2)); //DENALI_PHY_589_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +589 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_589_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +845 <<2)); //DENALI_PHY_845_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +845 <<2), tmp&0xffff0000|0xff7c); //DENALI_PHY_845_DATA
+}
+else //ddr1
+{
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +77 <<2)); //DENALI_PHY_77_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +77 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_77_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +333 <<2)); //DENALI_PHY_333_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +333 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_333_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +589 <<2)); //DENALI_PHY_589_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +589 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_589_DATA
+
+  tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +845 <<2)); //DENALI_PHY_845_DATA
+  apb_write(PHY_APB_BASE_ADDR + (4096 +845 <<2), tmp&0xffff0000|0xff8f); //DENALI_PHY_845_DATA
+}
+
+//PHY_ADR_TSEL_SELECT_X:bit[7:0]:{ENSLICEP_ODT/DRV,PENSLICEN_ODT/DRV}
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1062 <<2)); //DENALI_PHY_1062_DATA for addr5-0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1062 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1062_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1318 <<2)); //DENALI_PHY_1318_DATA for addr11-6
+apb_write(PHY_APB_BASE_ADDR + (4096 +1318 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1318_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1574 <<2)); //DENALI_PHY_1574_DATA for addr15-12
+apb_write(PHY_APB_BASE_ADDR + (4096 +1574 <<2), tmp&0xffffff00|0xff); //DENALI_PHY_1574_DATA
+
+//PHY_ADR_TSEL_ENABLE_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1028 <<2)); //DENALI_PHY_1028_DATA for addr5-0
+apb_write(PHY_APB_BASE_ADDR + (4096 +1028 <<2), tmp|0x1000000); //DENALI_PHY_1028_DATA //addr5-0:TSEL[24]=1
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1284 <<2)); //DENALI_PHY_1284_DATA for addr11-6
+apb_write(PHY_APB_BASE_ADDR + (4096 +1284 <<2), tmp|0x1000000); //DENALI_PHY_1284_DATA //addr11-6:TSEL[24]=1
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1540 <<2)); //DENALI_PHY_1540_DATA for addr15-12
+apb_write(PHY_APB_BASE_ADDR + (4096 +1540 <<2), tmp|0x1000000); //DENALI_PHY_1540_DATA //addr15-12:TSEL[24]=1
+
+//PHY_TST_CLK_PAD_CTRL_x   tst_clk_pad/tst_refclk_pad
+apb_write(PHY_APB_BASE_ADDR + (4096 +1848 <<2), 0x3cf07f8); //DENALI_PHY_1848_DATA  //tx_pulldwn[31:30]=2'b00, ENSLICEP_DRV[10:7], ENSLICEN_DRV[6:3], IE[2], TSEL[1], OE[0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1849 <<2), 0x3f); //DENALI_PHY_1849_DATA       //SLEWP[5:3]=7, SLEWN[2:0]=7
+apb_write(PHY_APB_BASE_ADDR + (4096 +1850 <<2), 0x1fffff); //DENALI_PHY_1850_DATA   //SPEED[20:19]=3, MODE[18:16]=7, BOOSTN[15:12]=F, BOOSTP[11:8]=F, ENSLICEP_ODT[7:4], ENSLICEN_ODT[3:0]
+apb_write(PHY_APB_BASE_ADDR + (4096 +1851 <<2), 0x190000); //DENALI_PHY_1851_DATA   //RX_CTLE[18:17]=3
+
+//PHY_DSLICE_PAD_BOOSTPN_SETTING_x
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +130 <<2)); //DENALI_PI_130_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +130 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_130_DATA //dqs0_BOOSTP[31:28]=F, dqs0_BOOSTN[27:24]=F, dq0/dm0_BOOSTP[23:20]=F, dq0/dm0_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +386 <<2)); //DENALI_PI_386_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +386 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_386_DATA //dqs1_BOOSTP[31:28]=F, dqs1_BOOSTN[27:24]=F, dq8/dm1_BOOSTP[23:20]=F, dq8/dm1_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +642 <<2)); //DENALI_PI_642_DATA
+apb_write(PHY_APB_BASE_ADDR + (2048 +642 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_642_DATA //dqs2_BOOSTP[31:28]=F, dqs2_BOOSTN[27:24]=F, dq16/dm2_BOOSTP[23:20]=F, dq16/dm2_BOOSTN[19:16]=F
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +898 <<2)); //DENALI_PI_898_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +898 <<2), tmp&0x0000ffff|0xffff0000); //DENALI_PI_898_DATA //dqs3_BOOSTP[31:28]=F, dqs3_BOOSTN[27:24]=F, dq24/dm3_BOOSTP[23:20]=F, dq24/dm3_BOOSTN[19:16]=F
+
+//PHY_DSLICE_PAD_RX_CTLE_SETTING_x
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +131 <<2)); //DENALI_PI_131_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +131 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_131_DATA //dqs0_RX_CTLE[3:2]=3, dq0/dm0_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +387 <<2)); //DENALI_PI_387_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +387 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_387_DATA //dqs1_RX_CTLE[3:2]=3, dq8/dm1_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +643 <<2)); //DENALI_PI_643_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +643 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_643_DATA //dqs2_RX_CTLE[3:2]=3, dq16/dm2_RX_CTLE[1:0]=3
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +899 <<2)); //DENALI_PI_899_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +899 <<2), tmp&0xfffffff0|0xf); //DENALI_PI_899_DATA //dqs3_RX_CTLE[3:2]=3, dq24/dm3_RX_CTLE[1:0]=3
+
+
+#if 1
+//PHY_WRLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +29 <<2)); //DENALI_PHY_29_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +29 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_29_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +285 <<2)); //DENALI_PHY_285_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +285 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_285_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +541 <<2)); //DENALI_PHY_541_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +541 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_541_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +797 <<2)); //DENALI_PHY_797_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +797 <<2), ((tmp & 0xc0ffffff)|0x10000000)); //DENALI_PHY_797_DATA
+
+//PHY_GTLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +30 <<2)); //DENALI_PHY_30_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +30 <<2), (tmp |0x00080000)); //DENALI_PHY_30_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +286 <<2)); //DENALI_PHY_286_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +286 <<2), (tmp |0x00080000)); //DENALI_PHY_286_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +542 <<2)); //DENALI_PHY_542_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +542 <<2), (tmp |0x00080000)); //DENALI_PHY_542_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +798 <<2)); //DENALI_PHY_798_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +798 <<2), (tmp |0x00080000)); //DENALI_PHY_797_DATA
+
+
+//PHY_RDLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +31 <<2)); //DENALI_PHY_31_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +31 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_31_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +287 <<2)); //DENALI_PHY_287_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +287 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_287_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +543 <<2)); //DENALI_PHY_543_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +543 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_543_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +799 <<2)); //DENALI_PHY_799_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +799 <<2), ((tmp & 0xFFFFFFC0)|0X00000010)); //DENALI_PHY_799_DATA
+
+//PHY_ADRLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1071 <<2)); //DENALI_PHY_1071_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1071 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1071_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1327 <<2)); //DENALI_PHY_1327_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1327 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1327_DATA
+
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1583 <<2)); //DENALI_PHY_1583_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1583 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1583_DATA
+
+//PHY_CSLVL_COARSECAPTURE_CNT
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1808 <<2)); //DENALI_PHY_1808_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1808 <<2), ((tmp & 0xFFFFFFF0)|0X00000008)); //DENALI_PHY_1808_DATA
+
+//PHY_CSLVL_CAPTURE_CNT_X
+tmp = apb_read(PHY_APB_BASE_ADDR + (4096 +1896 <<2)); //DENALI_PHY_1896_DATA
+apb_write(PHY_APB_BASE_ADDR + (4096 +1896 <<2), ((tmp & 0xFFFFFFF0)|0X00080000)); //DENALI_PHY_1896DATA
+#endif
+
+	
+#endif
+
+}
+
+//PHY_WRLVL_DELAY_EARLY_THRESHOLD_X: 10'h1A0 -> 10'h00 TODO:need deleted
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd123 <<2), tmp);//`DENALI_PHY_123_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd123 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd379 <<2), tmp);//`DENALI_PHY_379_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd379 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd635 <<2), tmp);//`DENALI_PHY_635_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd635 <<2), tmp&32'hfc00_ffff);
+//
+//apb_read(PHY_APB_BASE_ADDR + (16'd4096 +16'd891 <<2), tmp);//`DENALI_PHY_891_DATA
+//apb_write(PHY_APB_BASE_ADDR + (16'd4096 +16'd891 <<2), tmp&32'hfc00_ffff);
+
+//release dll_rst_n
+//apb_write(PHY_APB_BASE_ADDR + (16'd0000 +16'd00 << 2), 32'h01);

+ 0 - 2
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16/reg_config.v

@@ -1,2 +0,0 @@
-`define SIM_CLK  0.63 * `TSCALE
-`define SIM_CASLAT 28

+ 10 - 10
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16/regconfig.h.sim_PHY.h

@@ -51,16 +51,16 @@
 // ********************************************************************
 
 
-#define               DENALI_PHY_00_DATA 0b00000000000000000000010011110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0
-#define               DENALI_PHY_01_DATA 0b00000000000000000000000000000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000
-#define               DENALI_PHY_02_DATA 0b00000001000000110000001000000000 // PHY_LP2_DQS_GATE_CLS_0:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200
-#define               DENALI_PHY_03_DATA 0b00000000000000000000000000000000 // PHY_SW_WRDQ2_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_0:RW:0:1:=0x00
-#define               DENALI_PHY_04_DATA 0b00000000000000000000000000000000 // PHY_SW_WRDQ6_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_0:RW:0:6:=0x00
-#define               DENALI_PHY_05_DATA 0b00000011000000000000000000000000 // PHY_PER_RANK_CS_MAP_0:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_0:RW:0:6:=0x00
-#define               DENALI_PHY_06_DATA 0b00000001000000000000000000000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:0:1:=0x01
-#define               DENALI_PHY_07_DATA 0b00000011000000000000010000000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:0:5:=0x00
-#define               DENALI_PHY_08_DATA 0b00000001000000000000000000000001 // PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:0:5:=0x01
-#define               DENALI_PHY_09_DATA 0b00000000000000000000000000000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000
+#define               DENALI_PHY_0_DATA 0b00000000000000000000010011110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0
+#define               DENALI_PHY_1_DATA 0b00000000000000000000000000000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000
+#define               DENALI_PHY_2_DATA 0b00000001000000110000001000000000 // PHY_LP2_DQS_GATE_CLS_0:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200
+#define               DENALI_PHY_3_DATA 0b00000000000000000000000000000000 // PHY_SW_WRDQ2_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_0:RW:0:1:=0x00
+#define               DENALI_PHY_4_DATA 0b00000000000000000000000000000000 // PHY_SW_WRDQ6_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_0:RW:0:6:=0x00
+#define               DENALI_PHY_5_DATA 0b00000011000000000000000000000000 // PHY_PER_RANK_CS_MAP_0:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_0:RW:0:6:=0x00
+#define               DENALI_PHY_6_DATA 0b00000001000000000000000000000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:0:1:=0x01
+#define               DENALI_PHY_7_DATA 0b00000011000000000000010000000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:0:5:=0x00
+#define               DENALI_PHY_8_DATA 0b00000001000000000000000000000001 // PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:0:5:=0x01
+#define               DENALI_PHY_9_DATA 0b00000000000000000000000000000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000
 #define               DENALI_PHY_10_DATA 0b00000000000000000000000000000000 // PHY_AUTO_TIMING_MARGIN_OBS_0:RD:0:28:=0x00000000
 #define               DENALI_PHY_11_DATA 0b00000001000000000000000000000001 // PHY_PRBS_PATTERN_START_0:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_0:RW:8:9:=0x0000 PHY_PDA_MODE_EN_0:RW:0:1:=0x01
 #define               DENALI_PHY_12_DATA 0b00000000000000000000000000000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_0:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_0:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_0:RW:0:9:=0x0000

+ 0 - 2002
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16/regconfig.h.sim_PHY.v

@@ -1,2002 +0,0 @@
-
-/* ****************************************************************
- *        CADENCE                    Copyright (c) 2001-2018      *
- *                                   Cadence Design Systems, Inc. *
- *                                   All rights reserved.         *
- ******************************************************************
- *  The values calculated from this script are meant to be        *
- *  representative programmings.   The values may not reflect the *
- *  actual required programming for production use.   Please      *
- *  closely review all programmed values for technical accuracy   *
- *  before use in production parts.                               *
- ******************************************************************
- *                                                                 
- *   Module:         regconfig.h
- *   Documentation:  Register programming header file
- *
- ******************************************************************
- ******************************************************************
- * WARNING:  This file was automatically generated.  Manual
- * editing may result in undetermined behavior.
- ******************************************************************
- ******************************************************************/
-// REL: sifive.shanghai.n1-VIC_DDR__20180206
-
-
-`timescale 10ps/10ps
-
-// ********************************************************************
-// Option: IP    : IP Mode                       = PHY
-// Option: BL    : Burst Length                  = 16
-// Option: CL    : CAS Latency                   = 28
-// Option: MHZ   : Simulation MHz                = 1600
-// Option: AP    : Auto Precharge Mode     (0/1) = 0
-// Option: DLLBP : DLL Bypass Mode         (0/1) = 0
-// Option: HALF  : Half-Memory Support     (0/1) = 0
-// Option: RDIMM : Registered Dimm Support (0/1) = 0
-// Option: AL    : Additive Latency              = 0
-// Option: PREAM : Preamble Support    (0/1/2/3) = 0
-// Option: BOF   : Burst On the Fly        (0/1) = 0
-// Option: WLS   : Write Latency Set       (0/1) = 0
-// Option: TCK   : Simulation period in ns       = 
-// Option: WRDBIEN : Write DBI Enable       (0/1) = 0
-// Option: RDDBIEN : Read DBI Enable       (0/1) = 0
-// Option: RDPSTMBLE : RD Postamble En      (0/1) = 0
-// Option: WRPSTMBLE : WR Postamble En      (0/1) = 0
-// Option: CRC : CRC En      (0/1) = 0
-// Option: SOMA  : Memory-SOMA file(s)           = /proj/iprel/sifive.shanghai.n1-VIC_DDR/sifive.shanghai.n1-VIC_DDR__20180201/mcip/mem/sifive.shanghai.n1-VIC_DDR/memory/jedec_lpddr4_16gb_3200/memory.xml.sim
-// Option: PL    : CA Parity Latency              = -1
-// ********************************************************************
-// Memory: jedec_lpddr4_16gb_3200
-// ********************************************************************
-
-
-`define               DENALI_PHY_00_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0
-`define               DENALI_PHY_01_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000
-`define               DENALI_PHY_02_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_0:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200
-`define               DENALI_PHY_03_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_0:RW:0:1:=0x00
-`define               DENALI_PHY_04_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_0:RW:0:6:=0x00
-`define               DENALI_PHY_05_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_0:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_0:RW:0:6:=0x00
-`define               DENALI_PHY_06_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:0:1:=0x01
-`define               DENALI_PHY_07_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:0:5:=0x00
-`define               DENALI_PHY_08_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:0:5:=0x01
-`define               DENALI_PHY_09_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000
-`define               DENALI_PHY_10_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_0:RD:0:28:=0x00000000
-`define               DENALI_PHY_11_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_0:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_0:RW:8:9:=0x0000 PHY_PDA_MODE_EN_0:RW:0:1:=0x01
-`define               DENALI_PHY_12_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_0:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_0:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_0:RW:0:9:=0x0000
-`define               DENALI_PHY_13_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_0:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_0:RW:0:5:=0x04
-`define               DENALI_PHY_14_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_0:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_0:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_0:RW:0:4:=0x08
-`define               DENALI_PHY_15_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_0:RW:16:9:=0x0066 PHY_MEM_CLASS_0:RW:8:3:=0x06 PHY_LPDDR_0:RW:0:1:=0x01
-`define               DENALI_PHY_16_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_0:RW:0:2:=0x03
-`define               DENALI_PHY_17_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_18_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_0:RW:8:2:=0x00 PHY_DFI40_POLARITY_0:RW:0:1:=0x01
-`define               DENALI_PHY_19_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_0:RW:0:32:=0x0000AAAA
-`define               DENALI_PHY_20_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_0:RW:0:32:=0x00005555
-`define               DENALI_PHY_21_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_0:RW:0:32:=0x0000B5B5
-`define               DENALI_PHY_22_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_0:RW:0:32:=0x00004A4A
-`define               DENALI_PHY_23_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_0:RW:0:32:=0x00005656
-`define               DENALI_PHY_24_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_0:RW:0:32:=0x0000A9A9
-`define               DENALI_PHY_25_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_0:RW:0:32:=0x0000A9A9
-`define               DENALI_PHY_26_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_0:RW:0:32:=0x0000B5B5
-`define               DENALI_PHY_27_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_0:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_0:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00
-`define               DENALI_PHY_28_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_0:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_0:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_0:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_0:RW:0:4:=0x00
-`define               DENALI_PHY_29_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_0:RW:24:6:=0x08 PHY_WRLVL_ALGO_0:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_0:RW:0:1:=0x00
-`define               DENALI_PHY_30_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_0:RW:16:6:=0x00 PHY_DQ_MASK_0:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_0:RW:0:4:=0x08
-`define               DENALI_PHY_31_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_0:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_0:RW:0:6:=0x08
-`define               DENALI_PHY_32_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_0:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_0:RW:0:8:=0x00
-`define               DENALI_PHY_33_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_0:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_0:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_0:RW:0:8:=0x20
-`define               DENALI_PHY_34_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_0:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_0:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0:RW:0:11:=0x0020
-`define               DENALI_PHY_35_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_0:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_0:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_0:RW:0:8:=0x20
-`define               DENALI_PHY_36_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_0:RW:0:9:=0x0100
-`define               DENALI_PHY_37_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_0:RW:0:32:=0x55555555
-`define               DENALI_PHY_38_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_0:RW:0:32:=0xAAAAAAAA
-`define               DENALI_PHY_39_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_0:RW:0:32:=0x55555555
-`define               DENALI_PHY_40_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_0:RW:0:32:=0xAAAAAAAA
-`define               DENALI_PHY_41_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_0:RW:16:1:=0x00 PHY_USER_PATT4_0:RW:0:16:=0x5555
-`define               DENALI_PHY_42_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_0:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_0:RW:0:10:=0x0100
-`define               DENALI_PHY_43_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_0:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_0:RW:0:10:=0x0180
-`define               DENALI_PHY_44_DATA 32'b00000000_00000000_00000000_00000001 // PHY_FIFO_PTR_OBS_0:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_0:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_0:RW:0:1:=0x01
-`define               DENALI_PHY_45_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_46_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_0:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000
-`define               DENALI_PHY_47_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_0:RD:0:7:=0x00
-`define               DENALI_PHY_48_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_49_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_0:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_0:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00
-`define               DENALI_PHY_50_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_51_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_0:RD:0:17:=0x000000
-`define               DENALI_PHY_52_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_53_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_0:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_0:RD:0:16:=0x0000
-`define               DENALI_PHY_54_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_0:RD:0:14:=0x0000
-`define               DENALI_PHY_55_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_0:RD:0:18:=0x000000
-`define               DENALI_PHY_56_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_57_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0:RD:0:2:=0x00
-`define               DENALI_PHY_58_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_59_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_0:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_60_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_61_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_0:RW:0:31:=0x00000000
-`define               DENALI_PHY_62_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_0:RW:0:6:=0x00
-`define               DENALI_PHY_63_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_64_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_65_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_0:RW:24:1:=0x00 SC_PHY_RX_CAL_START_0:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_0:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_0:RW:0:8:=0x04
-`define               DENALI_PHY_66_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_0:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_0:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_0:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_0:RW:0:8:=0x20
-`define               DENALI_PHY_67_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_0:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_0:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_0:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_0:RW+:0:6:=0x00
-`define               DENALI_PHY_68_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_0:RW+:24:6:=0x00 PHY_RX_CAL_DQS_0:RW+:16:6:=0x00 PHY_RX_CAL_DM_0:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_0:RW+:0:6:=0x00
-`define               DENALI_PHY_69_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_0:RD:16:9:=0x0000 PHY_RX_CAL_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_70_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_0:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_0:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_0:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_0:RW:0:1:=0x00
-`define               DENALI_PHY_71_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_0:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_0:RW:0:12:=0x0000
-`define               DENALI_PHY_72_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_0:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define               DENALI_PHY_73_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10
-`define               DENALI_PHY_74_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_0:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_0:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_0:RW+:0:1:=0x00
-`define               DENALI_PHY_75_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_0:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_0:RW_D:0:1:=0x00
-`define               DENALI_PHY_76_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_0:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_0:RW+:0:3:=0x01
-`define               DENALI_PHY_77_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_0:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_0:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_0:RW+:0:16:=0x880c
-`define               DENALI_PHY_78_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_0:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_0:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_0:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_0:RW+:0:6:=0x25
-`define               DENALI_PHY_79_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_0:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_0:RW+:0:11:=0x0200
-`define               DENALI_PHY_80_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_0:RW+:24:5:=0x00 PHY_PAD_TX_DCD_0:RW+:16:5:=0x00 PHY_FAST_LVL_EN_0:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_0:RW+:0:8:=0x01
-`define               DENALI_PHY_81_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_0:RW+:0:5:=0x00
-`define               DENALI_PHY_82_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_0:RW+:0:5:=0x00
-`define               DENALI_PHY_83_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_0:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_0:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_0:RW+:0:5:=0x00
-`define               DENALI_PHY_84_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_85_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_86_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_87_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_88_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_0:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_89_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x52
-`define               DENALI_PHY_90_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_0:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_0:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_0:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_0:RW+:0:4:=0x00
-`define               DENALI_PHY_91_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_0:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_0:RW+:0:16:=0x0004
-`define               DENALI_PHY_92_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_0:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_0:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:0:1:=0x01
-`define               DENALI_PHY_93_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_0:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_0:RW+:16:1:=0x00 PHY_DBI_MODE_0:RW+:8:2:=0x00 PHY_IE_MODE_0:RW+:0:2:=0x00
-`define               DENALI_PHY_94_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_0:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_0:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_0:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0:RW+:0:5:=0x03
-`define               DENALI_PHY_95_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_0:RW+:0:11:=0x0010
-`define               DENALI_PHY_96_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_0:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_0:RW+:16:8:=0x0c PHY_RPTR_UPDATE_0:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e
-`define               DENALI_PHY_97_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_0:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_0:RW+:0:6:=0x2b
-`define               DENALI_PHY_98_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_0:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_0:RW+:0:10:=0x0140
-`define               DENALI_PHY_99_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_0:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_0:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_0:RW+:0:8:=0x20
-`define              DENALI_PHY_100_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_0:RW+:0:1:=0x00
-`define              DENALI_PHY_101_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_0:RW+:0:10:=0x0299
-`define              DENALI_PHY_102_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_0:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_0:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_0:RW+:0:2:=0x00
-`define              DENALI_PHY_103_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_0:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_104_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_0:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_0:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_0:RW+:0:1:=0x01
-`define              DENALI_PHY_105_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_0:RW+:0:5:=0x04
-`define              DENALI_PHY_106_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_0:RW+:0:32:=0x76543210
-`define              DENALI_PHY_107_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_0:RW+:0:4:=0x08
-`define              DENALI_PHY_108_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_109_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_110_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_111_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_112_DATA 32'b00000000_00000000_00000010_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_113_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_0:RW+:0:2:=0x00
-`define              DENALI_PHY_114_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_115_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_116_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_117_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_118_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_119_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_120_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_121_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_122_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_123_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_0:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_0:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:0:4:=0x04
-`define              DENALI_PHY_124_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_0:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_125_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_0:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_126_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_0:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_0:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_0:RW+:0:11:=0x0200
-`define              DENALI_PHY_127_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_128_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_129_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_130_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_0:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_131_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_0:RW+:0:4:=0x00
-`define              DENALI_PHY_132_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_133_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_134_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_135_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_136_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_137_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_138_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_139_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_140_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_141_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_142_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_143_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_144_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_145_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_146_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_147_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_148_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_149_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_150_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_151_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_152_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_153_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_154_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_155_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_156_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_157_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_158_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_159_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_160_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_161_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_162_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_163_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_164_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_165_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_166_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_167_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_168_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_169_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_170_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_171_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_172_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_173_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_174_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_175_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_176_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_177_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_178_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_179_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_180_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_181_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_182_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_183_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_184_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_185_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_186_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_187_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_188_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_189_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_190_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_191_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_192_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_193_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_194_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_195_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_196_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_197_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_198_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_199_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_200_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_201_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_202_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_203_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_204_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_205_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_206_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_207_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_208_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_209_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_210_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_211_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_212_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_213_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_214_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_215_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_216_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_217_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_218_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_219_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_220_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_221_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_222_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_223_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_224_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_225_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_226_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_227_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_228_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_229_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_230_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_231_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_232_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_233_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_234_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_235_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_236_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_237_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_238_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_239_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_240_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_241_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_242_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_243_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_244_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_245_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_246_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_247_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_248_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_249_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_250_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_251_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_252_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_253_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_254_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_255_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_256_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_1:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x04f0
-`define              DENALI_PHY_257_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_1:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1:RW:0:10:=0x0000
-`define              DENALI_PHY_258_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_1:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_1:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x0200
-`define              DENALI_PHY_259_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_1:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_1:RW:0:1:=0x00
-`define              DENALI_PHY_260_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_1:RW:0:6:=0x00
-`define              DENALI_PHY_261_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_1:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_1:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_1:RW:0:6:=0x00
-`define              DENALI_PHY_262_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_1:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_1:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_1:RW_D:0:1:=0x01
-`define              DENALI_PHY_263_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_1:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1:RW:0:5:=0x00
-`define              DENALI_PHY_264_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_1:RW:24:1:=0x01 PHY_LPBK_CONTROL_1:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1:RW:0:5:=0x01
-`define              DENALI_PHY_265_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_1:RW:0:32:=0x00000000
-`define              DENALI_PHY_266_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_1:RD:0:28:=0x00000000
-`define              DENALI_PHY_267_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_1:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_1:RW:8:9:=0x0000 PHY_PDA_MODE_EN_1:RW:0:1:=0x01
-`define              DENALI_PHY_268_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_1:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_1:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_1:RW:0:9:=0x0000
-`define              DENALI_PHY_269_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_1:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_1:RW:0:5:=0x04
-`define              DENALI_PHY_270_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_1:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_1:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_1:RW:0:4:=0x08
-`define              DENALI_PHY_271_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_1:RW:16:9:=0x0066 PHY_MEM_CLASS_1:RW:8:3:=0x06 PHY_LPDDR_1:RW:0:1:=0x01
-`define              DENALI_PHY_272_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_1:RW:0:2:=0x03
-`define              DENALI_PHY_273_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_274_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_1:RW:8:2:=0x00 PHY_DFI40_POLARITY_1:RW:0:1:=0x01
-`define              DENALI_PHY_275_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_1:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_276_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_1:RW:0:32:=0x00005555
-`define              DENALI_PHY_277_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_1:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_278_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_1:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_279_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_1:RW:0:32:=0x00005656
-`define              DENALI_PHY_280_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_1:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_281_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_1:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_282_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_1:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_283_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_1:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_1:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00
-`define              DENALI_PHY_284_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_1:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_1:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_1:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_1:RW:0:4:=0x00
-`define              DENALI_PHY_285_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_1:RW:24:6:=0x08 PHY_WRLVL_ALGO_1:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_1:RW:0:1:=0x00
-`define              DENALI_PHY_286_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_1:RW:16:6:=0x00 PHY_DQ_MASK_1:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_1:RW:0:4:=0x08
-`define              DENALI_PHY_287_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_1:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_1:RW:0:6:=0x08
-`define              DENALI_PHY_288_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_1:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_1:RW:0:8:=0x00
-`define              DENALI_PHY_289_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_1:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_1:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_1:RW:0:8:=0x20
-`define              DENALI_PHY_290_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_1:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_1:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1:RW:0:11:=0x0020
-`define              DENALI_PHY_291_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_1:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_1:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_1:RW:0:8:=0x20
-`define              DENALI_PHY_292_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_1:RW:0:9:=0x0100
-`define              DENALI_PHY_293_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_1:RW:0:32:=0x55555555
-`define              DENALI_PHY_294_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_1:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_295_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_1:RW:0:32:=0x55555555
-`define              DENALI_PHY_296_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_1:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_297_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_1:RW:16:1:=0x00 PHY_USER_PATT4_1:RW:0:16:=0x5555
-`define              DENALI_PHY_298_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_1:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_1:RW:0:10:=0x0100
-`define              DENALI_PHY_299_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_1:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_1:RW:0:10:=0x0180
-`define              DENALI_PHY_300_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_1:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_1:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_1:RW:0:1:=0x00
-`define              DENALI_PHY_301_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_302_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_1:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000
-`define              DENALI_PHY_303_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_1:RD:0:7:=0x00
-`define              DENALI_PHY_304_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_305_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_1:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_1:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00
-`define              DENALI_PHY_306_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_307_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_1:RD:0:17:=0x000000
-`define              DENALI_PHY_308_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_309_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_1:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_1:RD:0:16:=0x0000
-`define              DENALI_PHY_310_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_1:RD:0:14:=0x0000
-`define              DENALI_PHY_311_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_1:RD:0:18:=0x000000
-`define              DENALI_PHY_312_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_313_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1:RD:0:2:=0x00
-`define              DENALI_PHY_314_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_315_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_1:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_316_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_317_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_1:RW:0:31:=0x00000000
-`define              DENALI_PHY_318_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_1:RW:0:6:=0x00
-`define              DENALI_PHY_319_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_320_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_321_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_1:RW:24:1:=0x00 SC_PHY_RX_CAL_START_1:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_1:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_1:RW:0:8:=0x04
-`define              DENALI_PHY_322_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_1:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_1:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_1:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_1:RW:0:8:=0x20
-`define              DENALI_PHY_323_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_1:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_1:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_1:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_1:RW+:0:6:=0x00
-`define              DENALI_PHY_324_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_1:RW+:24:6:=0x00 PHY_RX_CAL_DQS_1:RW+:16:6:=0x00 PHY_RX_CAL_DM_1:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_1:RW+:0:6:=0x00
-`define              DENALI_PHY_325_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_1:RD:16:9:=0x0000 PHY_RX_CAL_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_326_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_1:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_1:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_1:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_1:RW:0:1:=0x00
-`define              DENALI_PHY_327_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_1:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_1:RW:0:12:=0x0000
-`define              DENALI_PHY_328_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_1:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_1:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_1:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_1:RW:0:8:=0x08
-`define              DENALI_PHY_329_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_1:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_1:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_1:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_1:RW:0:8:=0x10
-`define              DENALI_PHY_330_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_1:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_1:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_1:RW+:0:1:=0x00
-`define              DENALI_PHY_331_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_1:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_1:RW_D:0:1:=0x00
-`define              DENALI_PHY_332_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_1:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_1:RW+:0:3:=0x01
-`define              DENALI_PHY_333_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_1:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_1:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_1:RW+:0:16:=0x880c
-`define              DENALI_PHY_334_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_1:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_1:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_1:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_1:RW+:0:6:=0x25
-`define              DENALI_PHY_335_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_1:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_1:RW+:0:11:=0x0200
-`define              DENALI_PHY_336_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_1:RW+:24:5:=0x00 PHY_PAD_TX_DCD_1:RW+:16:5:=0x00 PHY_FAST_LVL_EN_1:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_1:RW+:0:8:=0x01
-`define              DENALI_PHY_337_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_1:RW+:0:5:=0x00
-`define              DENALI_PHY_338_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_1:RW+:0:5:=0x00
-`define              DENALI_PHY_339_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_1:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_1:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_1:RW+:0:5:=0x00
-`define              DENALI_PHY_340_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_341_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_342_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_343_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_344_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_1:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_345_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x52
-`define              DENALI_PHY_346_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_1:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_1:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_1:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_1:RW+:0:4:=0x00
-`define              DENALI_PHY_347_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_1:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_1:RW+:0:16:=0x0004
-`define              DENALI_PHY_348_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_1:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_1:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:0:1:=0x01
-`define              DENALI_PHY_349_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_1:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_1:RW+:16:1:=0x00 PHY_DBI_MODE_1:RW+:8:2:=0x00 PHY_IE_MODE_1:RW+:0:2:=0x00
-`define              DENALI_PHY_350_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_1:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_1:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_1:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1:RW+:0:5:=0x03
-`define              DENALI_PHY_351_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_1:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_1:RW+:0:11:=0x0010
-`define              DENALI_PHY_352_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_1:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_1:RW+:16:8:=0x0c PHY_RPTR_UPDATE_1:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_1:RW+:0:8:=0x3e
-`define              DENALI_PHY_353_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_1:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_1:RW+:0:6:=0x2b
-`define              DENALI_PHY_354_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_1:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_1:RW+:0:10:=0x0140
-`define              DENALI_PHY_355_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_1:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_1:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_1:RW+:0:8:=0x20
-`define              DENALI_PHY_356_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_1:RW+:0:1:=0x00
-`define              DENALI_PHY_357_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_1:RW+:0:10:=0x0299
-`define              DENALI_PHY_358_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_1:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_1:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_1:RW+:0:2:=0x00
-`define              DENALI_PHY_359_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_1:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_360_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_1:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_1:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_1:RW+:0:1:=0x01
-`define              DENALI_PHY_361_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_1:RW+:0:5:=0x04
-`define              DENALI_PHY_362_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_1:RW+:0:32:=0x76543210
-`define              DENALI_PHY_363_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_1:RW+:0:4:=0x08
-`define              DENALI_PHY_364_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_365_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_366_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_367_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_368_DATA 32'b00000000_00000000_00000010_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_369_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_1:RW+:0:2:=0x00
-`define              DENALI_PHY_370_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_371_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_372_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_373_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_374_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_375_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_376_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_377_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_378_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_379_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_1:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_1:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:0:4:=0x04
-`define              DENALI_PHY_380_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_1:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_381_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_1:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_382_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_1:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_1:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_1:RW+:0:11:=0x0200
-`define              DENALI_PHY_383_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_384_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_385_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_386_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_1:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_387_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_1:RW+:0:4:=0x00
-`define              DENALI_PHY_388_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_389_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_390_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_391_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_392_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_393_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_394_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_395_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_396_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_397_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_398_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_399_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_400_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_401_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_402_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_403_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_404_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_405_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_406_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_407_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_408_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_409_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_410_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_411_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_412_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_413_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_414_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_415_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_416_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_417_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_418_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_419_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_420_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_421_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_422_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_423_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_424_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_425_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_426_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_427_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_428_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_429_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_430_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_431_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_432_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_433_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_434_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_435_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_436_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_437_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_438_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_439_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_440_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_441_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_442_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_443_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_444_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_445_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_446_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_447_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_448_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_449_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_450_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_451_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_452_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_453_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_454_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_455_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_456_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_457_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_458_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_459_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_460_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_461_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_462_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_463_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_464_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_465_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_466_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_467_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_468_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_469_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_470_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_471_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_472_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_473_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_474_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_475_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_476_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_477_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_478_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_479_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_480_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_481_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_482_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_483_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_484_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_485_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_486_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_487_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_488_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_489_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_490_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_491_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_492_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_493_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_494_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_495_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_496_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_497_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_498_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_499_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_500_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_501_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_502_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_503_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_504_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_505_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_506_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_507_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_508_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_509_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_510_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_511_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_512_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_2:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x04f0
-`define              DENALI_PHY_513_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_2:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2:RW:0:10:=0x0000
-`define              DENALI_PHY_514_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_2:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_2:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x0200
-`define              DENALI_PHY_515_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_2:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_2:RW:0:1:=0x00
-`define              DENALI_PHY_516_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_2:RW:0:6:=0x00
-`define              DENALI_PHY_517_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_2:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_2:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_2:RW:0:6:=0x00
-`define              DENALI_PHY_518_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_2:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_2:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_2:RW_D:0:1:=0x01
-`define              DENALI_PHY_519_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_2:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2:RW:0:5:=0x00
-`define              DENALI_PHY_520_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_2:RW:24:1:=0x01 PHY_LPBK_CONTROL_2:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2:RW:0:5:=0x01
-`define              DENALI_PHY_521_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_2:RW:0:32:=0x00000000
-`define              DENALI_PHY_522_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_2:RD:0:28:=0x00000000
-`define              DENALI_PHY_523_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_2:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_2:RW:8:9:=0x0000 PHY_PDA_MODE_EN_2:RW:0:1:=0x01
-`define              DENALI_PHY_524_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_2:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_2:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_2:RW:0:9:=0x0000
-`define              DENALI_PHY_525_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_2:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_2:RW:0:5:=0x04
-`define              DENALI_PHY_526_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_2:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_2:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_2:RW:0:4:=0x08
-`define              DENALI_PHY_527_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_2:RW:16:9:=0x0066 PHY_MEM_CLASS_2:RW:8:3:=0x06 PHY_LPDDR_2:RW:0:1:=0x01
-`define              DENALI_PHY_528_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_2:RW:0:2:=0x03
-`define              DENALI_PHY_529_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_530_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_2:RW:8:2:=0x00 PHY_DFI40_POLARITY_2:RW:0:1:=0x01
-`define              DENALI_PHY_531_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_2:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_532_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_2:RW:0:32:=0x00005555
-`define              DENALI_PHY_533_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_2:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_534_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_2:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_535_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_2:RW:0:32:=0x00005656
-`define              DENALI_PHY_536_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_2:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_537_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_2:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_538_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_2:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_539_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_2:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_2:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00
-`define              DENALI_PHY_540_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_2:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_2:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_2:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_2:RW:0:4:=0x00
-`define              DENALI_PHY_541_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_2:RW:24:6:=0x08 PHY_WRLVL_ALGO_2:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_2:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_2:RW:0:1:=0x00
-`define              DENALI_PHY_542_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_2:RW:16:6:=0x00 PHY_DQ_MASK_2:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_2:RW:0:4:=0x08
-`define              DENALI_PHY_543_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_2:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_2:RW:0:6:=0x08
-`define              DENALI_PHY_544_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_2:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_2:RW:0:8:=0x00
-`define              DENALI_PHY_545_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_2:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_2:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_2:RW:0:8:=0x20
-`define              DENALI_PHY_546_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_2:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_2:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2:RW:0:11:=0x0020
-`define              DENALI_PHY_547_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_2:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_2:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_2:RW:0:8:=0x20
-`define              DENALI_PHY_548_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_2:RW:0:9:=0x0100
-`define              DENALI_PHY_549_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_2:RW:0:32:=0x55555555
-`define              DENALI_PHY_550_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_2:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_551_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_2:RW:0:32:=0x55555555
-`define              DENALI_PHY_552_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_2:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_553_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_2:RW:16:1:=0x00 PHY_USER_PATT4_2:RW:0:16:=0x5555
-`define              DENALI_PHY_554_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_2:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_2:RW:0:10:=0x0100
-`define              DENALI_PHY_555_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_2:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_2:RW:0:10:=0x0180
-`define              DENALI_PHY_556_DATA 32'b00000000_00000000_00000000_00000001 // PHY_FIFO_PTR_OBS_2:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_2:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_2:RW:0:1:=0x01
-`define              DENALI_PHY_557_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_558_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_2:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000
-`define              DENALI_PHY_559_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_2:RD:0:7:=0x00
-`define              DENALI_PHY_560_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_561_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_2:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_2:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00
-`define              DENALI_PHY_562_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_563_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_2:RD:0:17:=0x000000
-`define              DENALI_PHY_564_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_565_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_2:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_2:RD:0:16:=0x0000
-`define              DENALI_PHY_566_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_2:RD:0:14:=0x0000
-`define              DENALI_PHY_567_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_2:RD:0:18:=0x000000
-`define              DENALI_PHY_568_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_569_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2:RD:0:2:=0x00
-`define              DENALI_PHY_570_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_571_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_2:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_572_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_573_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_2:RW:0:31:=0x00000000
-`define              DENALI_PHY_574_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_2:RW:0:6:=0x00
-`define              DENALI_PHY_575_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_576_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_577_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_2:RW:24:1:=0x00 SC_PHY_RX_CAL_START_2:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_2:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_2:RW:0:8:=0x04
-`define              DENALI_PHY_578_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_2:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_2:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_2:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_2:RW:0:8:=0x20
-`define              DENALI_PHY_579_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_2:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_2:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_2:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_2:RW+:0:6:=0x00
-`define              DENALI_PHY_580_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_2:RW+:24:6:=0x00 PHY_RX_CAL_DQS_2:RW+:16:6:=0x00 PHY_RX_CAL_DM_2:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_2:RW+:0:6:=0x00
-`define              DENALI_PHY_581_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_2:RD:16:9:=0x0000 PHY_RX_CAL_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_582_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_2:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_2:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_2:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_2:RW:0:1:=0x00
-`define              DENALI_PHY_583_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_2:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_2:RW:0:12:=0x0000
-`define              DENALI_PHY_584_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_2:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_2:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_2:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_2:RW:0:8:=0x08
-`define              DENALI_PHY_585_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_2:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_2:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_2:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_2:RW:0:8:=0x10
-`define              DENALI_PHY_586_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_2:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_2:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_2:RW+:0:1:=0x00
-`define              DENALI_PHY_587_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_2:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_2:RW_D:0:1:=0x00
-`define              DENALI_PHY_588_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_2:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_2:RW+:0:3:=0x01
-`define              DENALI_PHY_589_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_2:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_2:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_2:RW+:0:16:=0x880c
-`define              DENALI_PHY_590_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_2:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_2:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_2:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_2:RW+:0:6:=0x25
-`define              DENALI_PHY_591_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_2:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_2:RW+:0:11:=0x0200
-`define              DENALI_PHY_592_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_2:RW+:24:5:=0x00 PHY_PAD_TX_DCD_2:RW+:16:5:=0x00 PHY_FAST_LVL_EN_2:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_2:RW+:0:8:=0x01
-`define              DENALI_PHY_593_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_2:RW+:0:5:=0x00
-`define              DENALI_PHY_594_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_2:RW+:0:5:=0x00
-`define              DENALI_PHY_595_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_2:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_2:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_2:RW+:0:5:=0x00
-`define              DENALI_PHY_596_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_597_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_598_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_599_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_600_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_2:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_601_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x52
-`define              DENALI_PHY_602_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_2:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_2:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_2:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_2:RW+:0:4:=0x00
-`define              DENALI_PHY_603_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_2:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_2:RW+:0:16:=0x0004
-`define              DENALI_PHY_604_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_2:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_2:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:0:1:=0x01
-`define              DENALI_PHY_605_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_2:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_2:RW+:16:1:=0x00 PHY_DBI_MODE_2:RW+:8:2:=0x00 PHY_IE_MODE_2:RW+:0:2:=0x00
-`define              DENALI_PHY_606_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_2:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_2:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_2:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2:RW+:0:5:=0x03
-`define              DENALI_PHY_607_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_2:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_2:RW+:0:11:=0x0010
-`define              DENALI_PHY_608_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_2:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_2:RW+:16:8:=0x0c PHY_RPTR_UPDATE_2:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_2:RW+:0:8:=0x3e
-`define              DENALI_PHY_609_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_2:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_2:RW+:0:6:=0x2b
-`define              DENALI_PHY_610_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_2:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_2:RW+:0:10:=0x0140
-`define              DENALI_PHY_611_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_2:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_2:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_2:RW+:0:8:=0x20
-`define              DENALI_PHY_612_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_2:RW+:0:1:=0x00
-`define              DENALI_PHY_613_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_2:RW+:0:10:=0x0299
-`define              DENALI_PHY_614_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_2:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_2:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_2:RW+:0:2:=0x00
-`define              DENALI_PHY_615_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_2:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_616_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_2:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_2:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_2:RW+:0:1:=0x01
-`define              DENALI_PHY_617_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_2:RW+:0:5:=0x04
-`define              DENALI_PHY_618_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_2:RW+:0:32:=0x76543210
-`define              DENALI_PHY_619_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_2:RW+:0:4:=0x08
-`define              DENALI_PHY_620_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_621_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_622_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_623_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_624_DATA 32'b00000000_00000000_00000010_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_625_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_2:RW+:0:2:=0x00
-`define              DENALI_PHY_626_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_627_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_628_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_629_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_630_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_631_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_632_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_633_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_634_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_635_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_2:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_2:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:0:4:=0x04
-`define              DENALI_PHY_636_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_2:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_637_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_2:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_638_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_2:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_2:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_2:RW+:0:11:=0x0200
-`define              DENALI_PHY_639_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_640_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_641_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_642_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_2:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_643_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_2:RW+:0:4:=0x00
-`define              DENALI_PHY_644_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_645_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_646_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_647_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_648_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_649_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_650_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_651_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_652_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_653_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_654_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_655_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_656_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_657_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_658_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_659_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_660_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_661_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_662_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_663_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_664_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_665_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_666_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_667_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_668_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_669_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_670_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_671_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_672_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_673_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_674_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_675_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_676_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_677_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_678_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_679_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_680_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_681_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_682_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_683_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_684_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_685_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_686_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_687_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_688_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_689_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_690_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_691_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_692_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_693_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_694_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_695_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_696_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_697_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_698_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_699_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_700_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_701_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_702_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_703_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_704_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_705_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_706_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_707_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_708_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_709_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_710_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_711_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_712_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_713_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_714_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_715_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_716_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_717_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_718_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_719_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_720_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_721_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_722_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_723_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_724_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_725_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_726_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_727_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_728_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_729_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_730_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_731_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_732_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_733_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_734_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_735_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_736_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_737_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_738_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_739_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_740_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_741_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_742_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_743_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_744_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_745_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_746_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_747_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_748_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_749_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_750_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_751_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_752_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_753_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_754_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_755_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_756_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_757_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_758_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_759_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_760_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_761_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_762_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_763_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_764_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_765_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_766_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_767_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_768_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_3:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_3:RW:0:11:=0x04f0
-`define              DENALI_PHY_769_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_3:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3:RW:0:10:=0x0000
-`define              DENALI_PHY_770_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_3:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_3:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x0200
-`define              DENALI_PHY_771_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_3:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_3:RW:0:1:=0x00
-`define              DENALI_PHY_772_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_3:RW:0:6:=0x00
-`define              DENALI_PHY_773_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_3:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_3:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_3:RW:0:6:=0x00
-`define              DENALI_PHY_774_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_3:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_3:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_3:RW_D:0:1:=0x01
-`define              DENALI_PHY_775_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_3:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3:RW:0:5:=0x00
-`define              DENALI_PHY_776_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_3:RW:24:1:=0x01 PHY_LPBK_CONTROL_3:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3:RW:0:5:=0x01
-`define              DENALI_PHY_777_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_3:RW:0:32:=0x00000000
-`define              DENALI_PHY_778_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_3:RD:0:28:=0x00000000
-`define              DENALI_PHY_779_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_3:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_3:RW:8:9:=0x0000 PHY_PDA_MODE_EN_3:RW:0:1:=0x01
-`define              DENALI_PHY_780_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_3:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_3:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_3:RW:0:9:=0x0000
-`define              DENALI_PHY_781_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_3:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_3:RW:0:5:=0x04
-`define              DENALI_PHY_782_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_3:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_3:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_3:RW:0:4:=0x08
-`define              DENALI_PHY_783_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_3:RW:16:9:=0x0066 PHY_MEM_CLASS_3:RW:8:3:=0x06 PHY_LPDDR_3:RW:0:1:=0x01
-`define              DENALI_PHY_784_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_3:RW:0:2:=0x03
-`define              DENALI_PHY_785_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_786_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_3:RW:8:2:=0x00 PHY_DFI40_POLARITY_3:RW:0:1:=0x01
-`define              DENALI_PHY_787_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_3:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_788_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_3:RW:0:32:=0x00005555
-`define              DENALI_PHY_789_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_3:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_790_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_3:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_791_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_3:RW:0:32:=0x00005656
-`define              DENALI_PHY_792_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_3:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_793_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_3:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_794_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_3:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_795_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_3:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_3:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_3:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_3:RW:0:3:=0x00
-`define              DENALI_PHY_796_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_3:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_3:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_3:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_3:RW:0:4:=0x00
-`define              DENALI_PHY_797_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_3:RW:24:6:=0x08 PHY_WRLVL_ALGO_3:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_3:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_3:RW:0:1:=0x00
-`define              DENALI_PHY_798_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_3:RW:16:6:=0x00 PHY_DQ_MASK_3:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_3:RW:0:4:=0x08
-`define              DENALI_PHY_799_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_3:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_3:RW:0:6:=0x08
-`define              DENALI_PHY_800_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_3:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_3:RW:0:8:=0x00
-`define              DENALI_PHY_801_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_3:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_3:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_3:RW:0:8:=0x20
-`define              DENALI_PHY_802_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_3:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_3:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3:RW:0:11:=0x0020
-`define              DENALI_PHY_803_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_3:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_3:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_3:RW:0:8:=0x20
-`define              DENALI_PHY_804_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_3:RW:0:9:=0x0100
-`define              DENALI_PHY_805_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_3:RW:0:32:=0x55555555
-`define              DENALI_PHY_806_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_3:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_807_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_3:RW:0:32:=0x55555555
-`define              DENALI_PHY_808_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_3:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_809_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_3:RW:16:1:=0x00 PHY_USER_PATT4_3:RW:0:16:=0x5555
-`define              DENALI_PHY_810_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_3:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_3:RW:0:10:=0x0100
-`define              DENALI_PHY_811_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_3:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_3:RW:0:10:=0x0180
-`define              DENALI_PHY_812_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_3:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_3:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_3:RW:0:1:=0x00
-`define              DENALI_PHY_813_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_814_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_3:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_3:RD:0:16:=0x0000
-`define              DENALI_PHY_815_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_3:RD:0:7:=0x00
-`define              DENALI_PHY_816_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_817_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_3:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_3:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00
-`define              DENALI_PHY_818_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_819_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_3:RD:0:17:=0x000000
-`define              DENALI_PHY_820_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_821_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_3:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_3:RD:0:16:=0x0000
-`define              DENALI_PHY_822_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_3:RD:0:14:=0x0000
-`define              DENALI_PHY_823_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_3:RD:0:18:=0x000000
-`define              DENALI_PHY_824_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_825_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3:RD:0:2:=0x00
-`define              DENALI_PHY_826_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_827_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_3:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_828_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_829_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_3:RW:0:31:=0x00000000
-`define              DENALI_PHY_830_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_3:RW:0:6:=0x00
-`define              DENALI_PHY_831_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_832_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_833_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_3:RW:24:1:=0x00 SC_PHY_RX_CAL_START_3:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_3:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_3:RW:0:8:=0x04
-`define              DENALI_PHY_834_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_3:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_3:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_3:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_3:RW:0:8:=0x20
-`define              DENALI_PHY_835_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_3:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_3:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_3:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_3:RW+:0:6:=0x00
-`define              DENALI_PHY_836_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_3:RW+:24:6:=0x00 PHY_RX_CAL_DQS_3:RW+:16:6:=0x00 PHY_RX_CAL_DM_3:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_3:RW+:0:6:=0x00
-`define              DENALI_PHY_837_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_3:RD:16:9:=0x0000 PHY_RX_CAL_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_838_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_3:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_3:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_3:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_3:RW:0:1:=0x00
-`define              DENALI_PHY_839_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_3:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_3:RW:0:12:=0x0000
-`define              DENALI_PHY_840_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_3:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_3:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_3:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_3:RW:0:8:=0x08
-`define              DENALI_PHY_841_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_3:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_3:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_3:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_3:RW:0:8:=0x10
-`define              DENALI_PHY_842_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_3:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_3:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_3:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_3:RW+:0:1:=0x00
-`define              DENALI_PHY_843_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_3:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_3:RW_D:0:1:=0x00
-`define              DENALI_PHY_844_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_3:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_3:RW+:0:3:=0x01
-`define              DENALI_PHY_845_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_3:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_3:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_3:RW+:0:16:=0x880c
-`define              DENALI_PHY_846_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_3:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_3:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_3:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_3:RW+:0:6:=0x25
-`define              DENALI_PHY_847_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_3:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_3:RW+:0:11:=0x0200
-`define              DENALI_PHY_848_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_3:RW+:24:5:=0x00 PHY_PAD_TX_DCD_3:RW+:16:5:=0x00 PHY_FAST_LVL_EN_3:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_3:RW+:0:8:=0x01
-`define              DENALI_PHY_849_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_3:RW+:0:5:=0x00
-`define              DENALI_PHY_850_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_3:RW+:0:5:=0x00
-`define              DENALI_PHY_851_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_3:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_3:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_3:RW+:0:5:=0x00
-`define              DENALI_PHY_852_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_853_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_854_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_855_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_856_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_3:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_857_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x52
-`define              DENALI_PHY_858_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_3:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_3:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_3:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_3:RW+:0:4:=0x00
-`define              DENALI_PHY_859_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_3:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_3:RW+:0:16:=0x0004
-`define              DENALI_PHY_860_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_3:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_3:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:0:1:=0x01
-`define              DENALI_PHY_861_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_3:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_3:RW+:16:1:=0x00 PHY_DBI_MODE_3:RW+:8:2:=0x00 PHY_IE_MODE_3:RW+:0:2:=0x00
-`define              DENALI_PHY_862_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_3:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_3:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_3:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3:RW+:0:5:=0x03
-`define              DENALI_PHY_863_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_3:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_3:RW+:0:11:=0x0010
-`define              DENALI_PHY_864_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_3:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_3:RW+:16:8:=0x0c PHY_RPTR_UPDATE_3:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_3:RW+:0:8:=0x3e
-`define              DENALI_PHY_865_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_3:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_3:RW+:0:6:=0x2b
-`define              DENALI_PHY_866_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_3:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_3:RW+:0:10:=0x0140
-`define              DENALI_PHY_867_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_3:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_3:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_3:RW+:0:8:=0x20
-`define              DENALI_PHY_868_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_3:RW+:0:1:=0x00
-`define              DENALI_PHY_869_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_3:RW+:0:10:=0x0299
-`define              DENALI_PHY_870_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_3:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_3:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_3:RW+:0:2:=0x00
-`define              DENALI_PHY_871_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_3:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_872_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_3:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_3:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_3:RW+:0:1:=0x01
-`define              DENALI_PHY_873_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_3:RW+:0:5:=0x04
-`define              DENALI_PHY_874_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_3:RW+:0:32:=0x76543210
-`define              DENALI_PHY_875_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_3:RW+:0:4:=0x08
-`define              DENALI_PHY_876_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_877_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_878_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_879_DATA 32'b00000010_10000000_00000010_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_880_DATA 32'b00000000_00000000_00000010_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_881_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_3:RW+:0:2:=0x00
-`define              DENALI_PHY_882_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_883_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_884_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_885_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_886_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_887_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_888_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_889_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_890_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_891_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_3:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_3:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:0:4:=0x04
-`define              DENALI_PHY_892_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_3:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_893_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_3:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_894_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_3:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_3:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_3:RW+:0:11:=0x0200
-`define              DENALI_PHY_895_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_896_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_897_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_898_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_3:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_899_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_3:RW+:0:4:=0x00
-`define              DENALI_PHY_900_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_901_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_902_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_903_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_904_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_905_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_906_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_907_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_908_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_909_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_910_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_911_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_912_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_913_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_914_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_915_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_916_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_917_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_918_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_919_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_920_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_921_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_922_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_923_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_924_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_925_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_926_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_927_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_928_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_929_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_930_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_931_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_932_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_933_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_934_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_935_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_936_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_937_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_938_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_939_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_940_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_941_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_942_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_943_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_944_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_945_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_946_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_947_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_948_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_949_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_950_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_951_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_952_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_953_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_954_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_955_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_956_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_957_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_958_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_959_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_960_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_961_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_962_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_963_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_964_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_965_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_966_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_967_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_968_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_969_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_970_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_971_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_972_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_973_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_974_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_975_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_976_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_977_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_978_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_979_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_980_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_981_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_982_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_983_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_984_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_985_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_986_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_987_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_988_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_989_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_990_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_991_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_992_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_993_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_994_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_995_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_996_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_997_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_998_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_999_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1000_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1001_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1002_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1003_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1004_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1005_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1006_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1007_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1008_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1009_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1010_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1011_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1012_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1013_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1014_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1015_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1016_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1017_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1018_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1019_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1020_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1021_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1022_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1023_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1024_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_0:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_0:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x0000
-`define             DENALI_PHY_1025_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1026_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000
-`define             DENALI_PHY_1027_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_0:RD:0:11:=0x0000
-`define             DENALI_PHY_1028_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_0:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_0:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00
-`define             DENALI_PHY_1029_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_0:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_0:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_0:RW:0:7:=0x00
-`define             DENALI_PHY_1030_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_0:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_ADR_TYPE_0:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00
-`define             DENALI_PHY_1031_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_0:RW:0:27:=0x00000000
-`define             DENALI_PHY_1032_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_0:RW:0:6:=0x00
-`define             DENALI_PHY_1033_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1034_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1035_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0000
-`define             DENALI_PHY_1036_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0080
-`define             DENALI_PHY_1037_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_0:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1038_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_0:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_0:RW:0:24:=0x000000
-`define             DENALI_PHY_1039_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_0:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_0:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:0:2:=0x00
-`define             DENALI_PHY_1040_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_0:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_0:WR:0:1:=0x00
-`define             DENALI_PHY_1041_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1042_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1043_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1044_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1045_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1046_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_0:RW:0:20:=0x00002a
-`define             DENALI_PHY_1047_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_0:RW:0:20:=0x000015
-`define             DENALI_PHY_1048_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_0:RW:0:20:=0x000015
-`define             DENALI_PHY_1049_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_0:RW:0:20:=0x00002a
-`define             DENALI_PHY_1050_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_0:RW:0:20:=0x000033
-`define             DENALI_PHY_1051_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_0:RW:0:20:=0x00000c
-`define             DENALI_PHY_1052_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_0:RW:0:20:=0x00000c
-`define             DENALI_PHY_1053_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_0:RW:0:20:=0x000033
-`define             DENALI_PHY_1054_DATA 32'b00001010_01000001_10001000_00100000 // PHY_ADR_ADDR_SEL_0:RW:0:30:=0x0a418820
-`define             DENALI_PHY_1055_DATA 32'b00000000_00111111_00000000_00000000 // PHY_ADR_SEG_MASK_0:RW:24:6:=0x00 PHY_ADR_BIT_MASK_0:RW:16:6:=0x3f PHY_ADR_LP4_BOOT_SLV_DELAY_0:RW:0:10:=0x0000
-`define             DENALI_PHY_1056_DATA 32'b00000000_00000000_00000001_00111111 // PHY_ADR_SW_TXIO_CTRL_0:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_0:RW:8:6:=0x01 PHY_ADR_CALVL_TRAIN_MASK_0:RW:0:6:=0x3f
-`define             DENALI_PHY_1057_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_0:RW+:0:2:=0x00
-`define             DENALI_PHY_1058_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_0:RW+:0:8:=0x20
-`define             DENALI_PHY_1059_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_0:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define             DENALI_PHY_1060_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10
-`define             DENALI_PHY_1061_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_0:RW+:0:1:=0x00
-`define             DENALI_PHY_1062_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_0:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_0:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55
-`define             DENALI_PHY_1063_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_0:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00
-`define             DENALI_PHY_1064_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1065_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1066_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1067_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1068_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1069_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_0:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_0:RW+:0:11:=0x0010
-`define             DENALI_PHY_1070_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_0:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e
-`define             DENALI_PHY_1071_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_0:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_0:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_0:RW+:0:4:=0x02
-`define             DENALI_PHY_1072_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_0:RW+:0:8:=0x80
-`define             DENALI_PHY_1073_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1074_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1075_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1076_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1077_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1078_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1079_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1080_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1081_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1082_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1083_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1084_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1085_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1086_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1087_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1088_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1089_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1090_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1091_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1092_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1093_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1094_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1095_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1096_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1097_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1098_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1099_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1100_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1101_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1102_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1103_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1104_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1105_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1106_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1107_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1108_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1109_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1110_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1111_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1112_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1113_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1114_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1115_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1116_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1117_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1118_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1119_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1120_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1121_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1122_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1123_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1124_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1125_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1126_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1127_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1128_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1129_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1130_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1131_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1132_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1133_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1134_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1135_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1136_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1137_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1138_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1139_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1140_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1141_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1142_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1143_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1144_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1145_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1146_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1147_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1148_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1149_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1150_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1151_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1152_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1153_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1154_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1155_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1156_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1157_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1158_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1159_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1160_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1161_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1162_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1163_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1164_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1165_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1166_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1167_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1168_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1169_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1170_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1171_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1172_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1173_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1174_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1175_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1176_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1177_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1178_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1179_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1180_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1181_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1182_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1183_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1184_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1185_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1186_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1187_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1188_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1189_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1190_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1191_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1192_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1193_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1194_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1195_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1196_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1197_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1198_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1199_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1200_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1201_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1202_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1203_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1204_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1205_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1206_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1207_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1208_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1209_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1210_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1211_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1212_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1213_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1214_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1215_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1216_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1217_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1218_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1219_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1220_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1221_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1222_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1223_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1224_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1225_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1226_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1227_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1228_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1229_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1230_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1231_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1232_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1233_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1234_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1235_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1236_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1237_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1238_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1239_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1240_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1241_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1242_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1243_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1244_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1245_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1246_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1247_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1248_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1249_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1250_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1251_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1252_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1253_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1254_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1255_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1256_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1257_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1258_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1259_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1260_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1261_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1262_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1263_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1264_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1265_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1266_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1267_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1268_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1269_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1270_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1271_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1272_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1273_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1274_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1275_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1276_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1277_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1278_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1279_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1280_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_1:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_1:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x0000
-`define             DENALI_PHY_1281_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1282_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000
-`define             DENALI_PHY_1283_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_1:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_1:RD:0:11:=0x0000
-`define             DENALI_PHY_1284_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_1:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_1:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00
-`define             DENALI_PHY_1285_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_1:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_1:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_1:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_1:RW:0:7:=0x00
-`define             DENALI_PHY_1286_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_1:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_1:RD:16:3:=0x00 PHY_ADR_TYPE_1:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:0:1:=0x00
-`define             DENALI_PHY_1287_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_1:RW:0:27:=0x00000000
-`define             DENALI_PHY_1288_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_1:RW:0:6:=0x00
-`define             DENALI_PHY_1289_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1290_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1291_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_1:RW:16:11:=0x0040 PHY_ADR_CALVL_START_1:RW:0:11:=0x0000
-`define             DENALI_PHY_1292_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_1:RW:0:11:=0x0080
-`define             DENALI_PHY_1293_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_1:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1294_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_1:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_1:RW:0:24:=0x000000
-`define             DENALI_PHY_1295_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_1:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_1:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_1:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_1:RW:0:2:=0x00
-`define             DENALI_PHY_1296_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_1:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_1:WR:0:1:=0x00
-`define             DENALI_PHY_1297_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1298_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1299_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1300_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1301_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1302_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_1:RW:0:20:=0x00002a
-`define             DENALI_PHY_1303_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_1:RW:0:20:=0x000015
-`define             DENALI_PHY_1304_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_1:RW:0:20:=0x000015
-`define             DENALI_PHY_1305_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_1:RW:0:20:=0x00002a
-`define             DENALI_PHY_1306_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_1:RW:0:20:=0x000033
-`define             DENALI_PHY_1307_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_1:RW:0:20:=0x00000c
-`define             DENALI_PHY_1308_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_1:RW:0:20:=0x00000c
-`define             DENALI_PHY_1309_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_1:RW:0:20:=0x000033
-`define             DENALI_PHY_1310_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDR_SEL_1:RW:0:30:=0x00000000
-`define             DENALI_PHY_1311_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SEG_MASK_1:RW:24:6:=0x00 PHY_ADR_BIT_MASK_1:RW:16:6:=0x00 PHY_ADR_LP4_BOOT_SLV_DELAY_1:RW:0:10:=0x0000
-`define             DENALI_PHY_1312_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SW_TXIO_CTRL_1:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_1:RW:8:6:=0x00 PHY_ADR_CALVL_TRAIN_MASK_1:RW:0:6:=0x00
-`define             DENALI_PHY_1313_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_1:RW+:0:2:=0x00
-`define             DENALI_PHY_1314_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_1:RW+:0:8:=0x20
-`define             DENALI_PHY_1315_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_1:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_1:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_1:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_1:RW:0:8:=0x08
-`define             DENALI_PHY_1316_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_1:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_1:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_1:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_1:RW:0:8:=0x10
-`define             DENALI_PHY_1317_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_1:RW+:0:1:=0x00
-`define             DENALI_PHY_1318_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_1:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_1:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_1:RW+:0:8:=0x55
-`define             DENALI_PHY_1319_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_1:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_1:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_1:RW+:0:5:=0x00
-`define             DENALI_PHY_1320_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1321_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1322_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1323_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1324_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_1:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1325_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_1:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_1:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_1:RW+:0:11:=0x0010
-`define             DENALI_PHY_1326_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_1:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_1:RW+:0:8:=0x3e
-`define             DENALI_PHY_1327_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_1:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_1:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_1:RW+:0:4:=0x02
-`define             DENALI_PHY_1328_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_1:RW+:0:8:=0x80
-`define             DENALI_PHY_1329_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1330_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1331_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1332_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1333_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1334_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1335_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1336_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1337_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1338_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1339_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1340_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1341_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1342_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1343_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1344_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1345_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1346_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1347_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1348_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1349_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1350_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1351_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1352_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1353_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1354_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1355_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1356_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1357_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1358_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1359_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1360_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1361_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1362_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1363_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1364_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1365_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1366_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1367_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1368_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1369_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1370_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1371_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1372_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1373_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1374_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1375_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1376_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1377_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1378_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1379_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1380_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1381_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1382_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1383_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1384_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1385_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1386_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1387_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1388_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1389_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1390_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1391_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1392_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1393_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1394_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1395_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1396_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1397_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1398_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1399_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1400_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1401_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1402_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1403_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1404_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1405_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1406_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1407_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1408_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1409_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1410_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1411_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1412_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1413_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1414_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1415_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1416_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1417_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1418_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1419_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1420_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1421_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1422_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1423_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1424_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1425_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1426_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1427_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1428_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1429_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1430_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1431_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1432_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1433_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1434_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1435_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1436_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1437_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1438_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1439_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1440_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1441_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1442_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1443_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1444_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1445_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1446_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1447_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1448_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1449_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1450_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1451_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1452_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1453_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1454_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1455_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1456_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1457_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1458_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1459_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1460_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1461_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1462_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1463_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1464_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1465_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1466_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1467_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1468_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1469_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1470_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1471_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1472_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1473_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1474_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1475_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1476_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1477_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1478_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1479_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1480_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1481_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1482_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1483_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1484_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1485_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1486_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1487_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1488_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1489_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1490_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1491_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1492_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1493_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1494_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1495_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1496_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1497_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1498_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1499_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1500_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1501_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1502_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1503_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1504_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1505_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1506_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1507_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1508_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1509_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1510_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1511_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1512_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1513_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1514_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1515_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1516_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1517_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1518_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1519_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1520_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1521_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1522_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1523_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1524_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1525_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1526_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1527_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1528_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1529_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1530_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1531_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1532_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1533_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1534_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1535_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1536_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_2:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_2:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x0000
-`define             DENALI_PHY_1537_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1538_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000
-`define             DENALI_PHY_1539_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_2:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_2:RD:0:11:=0x0000
-`define             DENALI_PHY_1540_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_2:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_2:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00
-`define             DENALI_PHY_1541_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_2:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_2:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_2:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_2:RW:0:7:=0x00
-`define             DENALI_PHY_1542_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_2:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_2:RD:16:3:=0x00 PHY_ADR_TYPE_2:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:0:1:=0x00
-`define             DENALI_PHY_1543_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_2:RW:0:27:=0x00000000
-`define             DENALI_PHY_1544_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_2:RW:0:6:=0x00
-`define             DENALI_PHY_1545_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1546_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1547_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_2:RW:16:11:=0x0040 PHY_ADR_CALVL_START_2:RW:0:11:=0x0000
-`define             DENALI_PHY_1548_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_2:RW:0:11:=0x0080
-`define             DENALI_PHY_1549_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_2:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1550_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_2:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_2:RW:0:24:=0x000000
-`define             DENALI_PHY_1551_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_2:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_2:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_2:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_2:RW:0:2:=0x00
-`define             DENALI_PHY_1552_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_2:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_2:WR:0:1:=0x00
-`define             DENALI_PHY_1553_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1554_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1555_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1556_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1557_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1558_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_2:RW:0:20:=0x00002a
-`define             DENALI_PHY_1559_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_2:RW:0:20:=0x000015
-`define             DENALI_PHY_1560_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_2:RW:0:20:=0x000015
-`define             DENALI_PHY_1561_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_2:RW:0:20:=0x00002a
-`define             DENALI_PHY_1562_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_2:RW:0:20:=0x000033
-`define             DENALI_PHY_1563_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_2:RW:0:20:=0x00000c
-`define             DENALI_PHY_1564_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_2:RW:0:20:=0x00000c
-`define             DENALI_PHY_1565_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_2:RW:0:20:=0x000033
-`define             DENALI_PHY_1566_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDR_SEL_2:RW:0:30:=0x00000000
-`define             DENALI_PHY_1567_DATA 32'b00010000_00000000_00000000_00000000 // PHY_ADR_SEG_MASK_2:RW:24:6:=0x10 PHY_ADR_BIT_MASK_2:RW:16:6:=0x00 PHY_ADR_LP4_BOOT_SLV_DELAY_2:RW:0:10:=0x0000
-`define             DENALI_PHY_1568_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SW_TXIO_CTRL_2:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_2:RW:8:6:=0x00 PHY_ADR_CALVL_TRAIN_MASK_2:RW:0:6:=0x00
-`define             DENALI_PHY_1569_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_2:RW+:0:2:=0x00
-`define             DENALI_PHY_1570_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_2:RW+:0:8:=0x20
-`define             DENALI_PHY_1571_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_2:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_2:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_2:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_2:RW:0:8:=0x08
-`define             DENALI_PHY_1572_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_2:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_2:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_2:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_2:RW:0:8:=0x10
-`define             DENALI_PHY_1573_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_2:RW+:0:1:=0x00
-`define             DENALI_PHY_1574_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_2:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_2:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_2:RW+:0:8:=0x55
-`define             DENALI_PHY_1575_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_2:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_2:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_2:RW+:0:5:=0x00
-`define             DENALI_PHY_1576_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1577_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1578_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1579_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1580_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_2:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1581_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_2:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_2:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_2:RW+:0:11:=0x0010
-`define             DENALI_PHY_1582_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_2:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_2:RW+:0:8:=0x3e
-`define             DENALI_PHY_1583_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_2:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_2:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_2:RW+:0:4:=0x02
-`define             DENALI_PHY_1584_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_2:RW+:0:8:=0x80
-`define             DENALI_PHY_1585_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1586_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1587_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1588_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1589_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1590_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1591_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1592_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1593_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1594_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1595_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1596_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1597_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1598_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1599_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1600_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1601_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1602_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1603_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1604_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1605_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1606_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1607_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1608_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1609_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1610_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1611_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1612_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1613_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1614_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1615_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1616_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1617_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1618_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1619_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1620_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1621_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1622_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1623_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1624_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1625_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1626_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1627_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1628_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1629_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1630_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1631_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1632_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1633_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1634_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1635_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1636_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1637_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1638_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1639_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1640_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1641_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1642_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1643_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1644_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1645_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1646_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1647_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1648_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1649_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1650_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1651_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1652_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1653_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1654_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1655_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1656_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1657_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1658_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1659_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1660_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1661_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1662_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1663_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1664_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1665_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1666_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1667_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1668_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1669_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1670_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1671_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1672_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1673_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1674_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1675_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1676_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1677_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1678_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1679_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1680_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1681_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1682_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1683_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1684_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1685_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1686_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1687_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1688_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1689_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1690_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1691_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1692_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1693_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1694_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1695_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1696_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1697_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1698_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1699_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1700_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1701_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1702_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1703_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1704_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1705_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1706_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1707_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1708_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1709_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1710_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1711_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1712_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1713_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1714_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1715_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1716_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1717_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1718_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1719_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1720_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1721_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1722_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1723_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1724_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1725_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1726_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1727_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1728_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1729_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1730_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1731_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1732_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1733_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1734_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1735_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1736_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1737_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1738_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1739_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1740_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1741_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1742_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1743_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1744_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1745_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1746_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1747_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1748_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1749_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1750_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1751_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1752_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1753_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1754_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1755_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1756_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1757_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1758_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1759_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1760_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1761_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1762_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1763_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1764_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1765_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1766_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1767_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1768_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1769_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1770_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1771_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1772_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1773_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1774_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1775_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1776_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1777_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1778_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1779_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1780_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1781_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1782_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1783_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1784_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1785_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1786_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1787_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1788_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1789_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1790_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1791_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1792_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FREQ_SEL:RW:0:2:=0x00
-`define             DENALI_PHY_1793_DATA 32'b00000000_00000000_00000001_00000000 // PHY_SW_GRP0_SHIFT_0:RW+:24:5:=0x00 PHY_FREQ_SEL_INDEX:RW+:16:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW+:8:1:=0x01 PHY_FREQ_SEL_FROM_REGIF:RW_D:0:1:=0x00
-`define             DENALI_PHY_1794_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_0:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_0:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_0:RW+:0:5:=0x00
-`define             DENALI_PHY_1795_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_2:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_1:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_1:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_1:RW+:0:5:=0x00
-`define             DENALI_PHY_1796_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_3:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_2:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_2:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_2:RW+:0:5:=0x00
-`define             DENALI_PHY_1797_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_4:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_3:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_3:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_3:RW+:0:5:=0x00
-`define             DENALI_PHY_1798_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_5:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_4:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_4:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_4:RW+:0:5:=0x00
-`define             DENALI_PHY_1799_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP3_SHIFT_5:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_5:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_5:RW+:0:5:=0x00
-`define             DENALI_PHY_1800_DATA 32'b00000000_00000101_00000000_00000000 // PHY_GRP_BYPASS_OVERRIDE:RW:24:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:16:5:=0x05 PHY_GRP_BYPASS_SLAVE_DELAY:RW:0:11:=0x0000
-`define             DENALI_PHY_1801_DATA 32'b00000100_00000000_00000000_00000000 // PHY_CSLVL_START:RW:16:11:=0x0400 SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE:RW_D:8:1:=0x00 SC_PHY_MANUAL_UPDATE:WR:0:1:=0x00
-`define             DENALI_PHY_1802_DATA 32'b00000000_00000000_00000000_01010101 // SC_PHY_CSLVL_DEBUG_CONT:WR:24:1:=0x00 PHY_CSLVL_DEBUG_MODE:RW:16:1:=0x00 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055
-`define             DENALI_PHY_1803_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_CSLVL_ERROR_CLR:WR:0:1:=0x00
-`define             DENALI_PHY_1804_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CSLVL_OBS0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1805_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CSLVL_OBS1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1806_DATA 32'b00000000_00001111_00000000_00000001 // PHY_CSLVL_CS_MAP:RW:16:4:=0x0f PHY_LP4_BOOT_DISABLE:RW:8:1:=0x00 PHY_CSLVL_ENABLE:RW:0:1:=0x01
-`define             DENALI_PHY_1807_DATA 32'b00000000_00101000_00000000_01000000 // PHY_CSLVL_COARSE_CHK:RW:16:11:=0x0028 PHY_CSLVL_QTR:RW:0:11:=0x0040
-`define             DENALI_PHY_1808_DATA 32'b00000000_00000000_01010000_00000010 // PHY_ADRCTL_SNAP_OBS_REGS:WR:24:1:=0x00 PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE:RW:16:3:=0x00 PHY_CALVL_CS_MAP:RW:8:8:=0x50 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:0:4:=0x02
-`define             DENALI_PHY_1809_DATA 32'b00000000_00000001_00000001_00000001 // PHY_LPDDR3_CS:RW_D:24:1:=0x00 PHY_LP4_ACTIVE:RW:16:1:=0x01 PHY_ADRCTL_LPDDR:RW:8:1:=0x01 PHY_DFI_PHYUPD_TYPE:RW:0:2:=0x01
-`define             DENALI_PHY_1810_DATA 32'b00000000_00000000_10000000_00001000 // PHY_CLK_DC_FREQ_CHG_ADJ:RW:24:1:=0x00 PHY_CLK_DC_WEIGHT:RW:16:2:=0x00 PHY_CLK_DC_CAL_TIMEOUT:RW:8:8:=0x80 PHY_CLK_DC_CAL_SAMPLE_WAIT:RW:0:8:=0x08
-`define             DENALI_PHY_1811_DATA 32'b00000000_00001000_00010000_00100000 // PHY_CLK_DC_ADJUST_DIRECT:RW:24:1:=0x00 PHY_CLK_DC_ADJUST_THRSHLD:RW:16:8:=0x08 PHY_CLK_DC_ADJUST_SAMPLE_CNT:RW:8:8:=0x10 PHY_CLK_DC_ADJUST_START:RW:0:6:=0x20
-`define             DENALI_PHY_1812_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CONTINUOUS_CLK_CAL_UPDATE:RW:24:1:=0x00 SC_PHY_UPDATE_CLK_CAL_VALUES:WR:16:1:=0x00 PHY_CLK_DC_CAL_START:RW+:8:1:=0x00 PHY_CLK_DC_CAL_POLARITY:RW:0:1:=0x00
-`define             DENALI_PHY_1813_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_TXIO_CTRL_3:RW:24:4:=0x00 PHY_SW_TXIO_CTRL_2:RW:16:4:=0x00 PHY_SW_TXIO_CTRL_1:RW:8:4:=0x00 PHY_SW_TXIO_CTRL_0:RW:0:4:=0x00
-`define             DENALI_PHY_1814_DATA 32'b00000001_00000000_00000000_00000000 // PHY_CA_SW_TXPWR_CTRL:RW:24:1:=0x01 PHY_MEMCLK_SW_TXIO_CTRL:RW:16:1:=0x00 PHY_SW_TXIO_CTRL_5:RW:8:4:=0x00 PHY_SW_TXIO_CTRL_4:RW:0:4:=0x00
-`define             DENALI_PHY_1815_DATA 32'b00000000_00000000_00000000_00000001 // PHY_MEMCLK_SW_TXPWR_CTRL:RW:0:1:=0x01
-`define             DENALI_PHY_1816_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_0:RW:0:32:=0x00000000
-`define             DENALI_PHY_1817_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_1:RW:0:32:=0x00000000
-`define             DENALI_PHY_1818_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_2:RW:0:32:=0x00000000
-`define             DENALI_PHY_1819_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_3:RW:0:32:=0x00000000
-`define             DENALI_PHY_1820_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LP4_BOOT_PLL_BYPASS:RW:0:1:=0x00
-`define             DENALI_PHY_1821_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CLK_SWITCH_OBS:RD:0:32:=0x00000000
-`define             DENALI_PHY_1822_DATA 32'b00000000_00000000_00000000_01100100 // PHY_PLL_WAIT:RW:0:8:=0x64
-`define             DENALI_PHY_1823_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_PLL_BYPASS:RW+:0:1:=0x00
-`define             DENALI_PHY_1824_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SET_DFI_INPUT_3:RW:24:4:=0x00 PHY_SET_DFI_INPUT_2:RW:16:4:=0x00 PHY_SET_DFI_INPUT_1:RW:8:4:=0x00 PHY_SET_DFI_INPUT_0:RW:0:4:=0x00
-`define             DENALI_PHY_1825_DATA 32'b00000001_00000001_00000000_00000000 // PHY_CS_ACS_ALLOCATION_bit1_0:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_bit0_0:RW:16:4:=0x01 PHY_SET_DFI_INPUT_5:RW:8:4:=0x00 PHY_SET_DFI_INPUT_4:RW:0:4:=0x00
-`define             DENALI_PHY_1826_DATA 32'b00000010_00000010_00000001_00000001 // PHY_CS_ACS_ALLOCATION_bit1_1:RW:24:4:=0x02 PHY_CS_ACS_ALLOCATION_bit0_1:RW:16:4:=0x02 PHY_CS_ACS_ALLOCATION_bit3_0:RW:8:4:=0x01 PHY_CS_ACS_ALLOCATION_bit2_0:RW:0:4:=0x01
-`define             DENALI_PHY_1827_DATA 32'b00000100_00000100_00000010_00000010 // PHY_CS_ACS_ALLOCATION_bit1_2:RW:24:4:=0x04 PHY_CS_ACS_ALLOCATION_bit0_2:RW:16:4:=0x04 PHY_CS_ACS_ALLOCATION_bit3_1:RW:8:4:=0x02 PHY_CS_ACS_ALLOCATION_bit2_1:RW:0:4:=0x02
-`define             DENALI_PHY_1828_DATA 32'b00001000_00001000_00000100_00000100 // PHY_CS_ACS_ALLOCATION_bit1_3:RW:24:4:=0x08 PHY_CS_ACS_ALLOCATION_bit0_3:RW:16:4:=0x08 PHY_CS_ACS_ALLOCATION_bit3_2:RW:8:4:=0x04 PHY_CS_ACS_ALLOCATION_bit2_2:RW:0:4:=0x04
-`define             DENALI_PHY_1829_DATA 32'b00001111_00001111_00001000_00001000 // PHY_CS_ACS_ALLOCATION_bit1_4:RW:24:4:=0x0f PHY_CS_ACS_ALLOCATION_bit0_4:RW:16:4:=0x0f PHY_CS_ACS_ALLOCATION_bit3_3:RW:8:4:=0x08 PHY_CS_ACS_ALLOCATION_bit2_3:RW:0:4:=0x08
-`define             DENALI_PHY_1830_DATA 32'b00001111_00001111_00001111_00001111 // PHY_CS_ACS_ALLOCATION_bit1_5:RW:24:4:=0x0f PHY_CS_ACS_ALLOCATION_bit0_5:RW:16:4:=0x0f PHY_CS_ACS_ALLOCATION_bit3_4:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_bit2_4:RW:0:4:=0x0f
-`define             DENALI_PHY_1831_DATA 32'b00100000_00100000_00001111_00001111 // PHY_CLK_DC_ADJUST_1:RW+:24:8:=0x20 PHY_CLK_DC_ADJUST_0:RW+:16:8:=0x20 PHY_CS_ACS_ALLOCATION_bit3_5:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_bit2_5:RW:0:4:=0x0f
-`define             DENALI_PHY_1832_DATA 32'b00011011_01000010_10000000_00000000 // PHY_LP4_BOOT_PLL_CTRL:RW:16:13:=0x1b42 PHY_CLK_DC_DM_THRSHLD:RW+:8:8:=0x80 PHY_CLK_DC_INIT_DISABLE:RW+:0:1:=0x00
-`define             DENALI_PHY_1833_DATA 32'b00000000_00000000_00000000_00000100 // PHY_PLL_OBS_0:RD:16:16:=0x0000 PHY_PLL_CTRL_OVERRIDE:RW:0:16:=0x0004
-`define             DENALI_PHY_1834_DATA 32'b00000001_00000001_00000000_00000000 // PHY_PLL_REFOUT_SEL:RW:24:1:=0x01 PHY_PLL_TESTOUT_SEL:RW:16:1:=0x01 PHY_PLL_OBS_1:RD:0:16:=0x0000
-`define             DENALI_PHY_1835_DATA 32'b00000001_00000111_00000101_00000001 // PHY_LS_IDLE_EN:RW:24:1:=0x01 PHY_LP_WAKEUP:RW:16:8:=0x07 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:0:1:=0x01
-`define             DENALI_PHY_1836_DATA 32'b00000000_00000000_00000000_01010100 // PHY_TDFI_PHY_WRDELAY:RW:16:1:=0x00 PHY_LP_CTRLUPD_CNTR_CFG:RW:0:10:=0x0054
-`define             DENALI_PHY_1837_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1838_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_DATA_TERM:RW+:0:17:=0x004410
-`define             DENALI_PHY_1839_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_DQS_TERM:RW+:0:17:=0x004410
-`define             DENALI_PHY_1840_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1841_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CLK_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1842_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_ERR_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1843_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CKE_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1844_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_RST_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1845_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CS_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1846_DATA 32'b00000000_00000000_01000100_00010000 // PHY_ADRCTL_RX_CAL:RW:24:7:=0x00 PHY_PAD_ODT_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1847_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADRCTL_LP3_RX_CAL:RW:0:13:=0x0000
-`define             DENALI_PHY_1848_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL:RW:0:32:=0x00000000
-`define             DENALI_PHY_1849_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL2:RW:0:23:=0x000000
-`define             DENALI_PHY_1850_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL3:RW:0:21:=0x000000
-`define             DENALI_PHY_1851_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL4:RW:0:21:=0x000000
-`define             DENALI_PHY_1852_DATA 32'b00000000_00000000_00000000_01100100 // PHY_CAL_START_0:WR:24:1:=0x00 PHY_CAL_CLEAR_0:WR:16:1:=0x00 PHY_CAL_MODE_0:RW:0:13:=0x0064
-`define             DENALI_PHY_1853_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_INTERVAL_COUNT_0:RW:0:32:=0x00000000
-`define             DENALI_PHY_1854_DATA 32'b00000000_00000000_00000001_00001000 // PHY_LP4_BOOT_CAL_CLK_SELECT_0:RW:8:3:=0x01 PHY_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define             DENALI_PHY_1855_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1856_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT2_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1857_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT4_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1858_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT5_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1859_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT6_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1860_DATA 32'b00000011_00000000_00000000_00000000 // PHY_CAL_CPTR_CNT_0:RW:24:7:=0x03 PHY_CAL_RESULT7_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1861_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_DBG_CFG_0:RW:24:1:=0x00 PHY_CAL_RCV_FINE_ADJ_0:RW:16:8:=0x00 PHY_CAL_PD_FINE_ADJ_0:RW:8:8:=0x00 PHY_CAL_PU_FINE_ADJ_0:RW:0:8:=0x00
-`define             DENALI_PHY_1862_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_PAD_DBG_CONT_0:WR:0:1:=0x00
-`define             DENALI_PHY_1863_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT3_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1864_DATA 32'b00000100_00010000_00100000_00110101 // PHY_CAL_SLOPE_ADJ_0:RW_D:8:20:=0x041020 PHY_ADRCTL_PVT_MAP_0:RW:0:7:=0x35
-`define             DENALI_PHY_1865_DATA 32'b00000000_00000100_00010000_00100000 // PHY_CAL_SLOPE_ADJ_PASS2_0:RW_D:0:20:=0x041020
-`define             DENALI_PHY_1866_DATA 32'b00000001_11001001_10001100_10011000 // PHY_CAL_TWO_PASS_CFG_0:RW_D:0:25:=0x01c98c98
-`define             DENALI_PHY_1867_DATA 32'b00111111_01000000_00000000_00000000 // PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_SW_CAL_CFG_0:RW:0:23:=0x400000
-`define             DENALI_PHY_1868_DATA 32'b00111111_00111111_00011111_00111111 // PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0:RW_D:16:6:=0x3f PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0:RW_D:8:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0:RW_D:0:6:=0x3f
-`define             DENALI_PHY_1869_DATA 32'b00011111_00111111_00111111_00011111 // PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0:RW:24:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0:RW:16:6:=0x3f PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0:RW_D:0:5:=0x1f
-`define             DENALI_PHY_1870_DATA 32'b00000000_00011111_00111111_00111111 // PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0:RW:16:5:=0x1f PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0:RW:0:6:=0x3f
-`define             DENALI_PHY_1871_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_ERR_CLEAR:WR:24:1:=0x00 PHY_ADRCTL_MANUAL_UPDATE:WR:16:1:=0x00 PHY_PAD_ATB_CTRL:RW:0:16:=0x0000
-`define             DENALI_PHY_1872_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_CONTROL:RW:16:9:=0x0000 PHY_AC_LPBK_ENABLE:RW:8:6:=0x00 PHY_AC_LPBK_OBS_SELECT:RW:0:3:=0x00
-`define             DENALI_PHY_1873_DATA 32'b00000000_00000000_00000000_00000001 // PHY_AC_PRBS_PATTERN_MASK:RW:8:4:=0x00 PHY_AC_PRBS_PATTERN_START:RW_D:0:7:=0x01
-`define             DENALI_PHY_1874_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_RESULT_OBS:RD:0:32:=0x00000000
-`define             DENALI_PHY_1875_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_CLK_LPBK_CONTROL:RW:16:6:=0x00 PHY_AC_CLK_LPBK_ENABLE:RW:8:2:=0x00 PHY_AC_CLK_LPBK_OBS_SELECT:RW:0:1:=0x00
-`define             DENALI_PHY_1876_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TOP_PWR_RDC_DISABLE:RW_D:24:1:=0x00 PHY_AC_PWR_RDC_DISABLE:RW:16:1:=0x00 PHY_AC_CLK_LPBK_RESULT_OBS:RD:0:16:=0x0000
-`define             DENALI_PHY_1877_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_SLV_DLY_CTRL_GATE_DISABLE:RW_D:0:1:=0x00
-`define             DENALI_PHY_1878_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DATA_BYTE_ORDER_SEL:RW:0:32:=0x76543210
-`define             DENALI_PHY_1879_DATA 32'b00000110_00000001_00000001_10011000 // PHY_ADR_DISABLE:RW:24:3:=0x06 PHY_CALVL_DEVICE_MAP:RW:16:5:=0x01 PHY_LPDDR4_CONNECT:RW:8:1:=0x01 PHY_DATA_BYTE_ORDER_SEL_HIGH:RW:0:8:=0x98
-`define             DENALI_PHY_1880_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADRCTL_MSTR_DLY_ENC_SEL:RW:0:2:=0x00
-`define             DENALI_PHY_1881_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_AC_ENABLE:RW:0:32:=0x00000000
-`define             DENALI_PHY_1882_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_AC_MODE:RW:0:26:=0x00000000
-`define             DENALI_PHY_1883_DATA 32'b00000000_00000100_00000111_00000000 // PHY_DDL_TRACK_UPD_THRESHOLD_AC:RW:16:8:=0x04 PHY_INIT_UPDATE_CONFIG:RW:8:3:=0x07 PHY_DDL_AC_MASK:RW:0:6:=0x00
-`define             DENALI_PHY_1884_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ERR_STATUS:RW+:24:3:=0x00 PHY_ERR_MASK_EN:RW:16:3:=0x00 PHY_CA_PARITY_ERR_PULSE_MIN:RW:0:16:=0x0000
-`define             DENALI_PHY_1885_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS0_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1886_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS1_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1887_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS2_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1888_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS3_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1889_DATA 32'b00000000_00000000_00000000_00000010 // PHY_DS_INIT_COMPLETE_OBS:RD:24:4:=0x00 PHY_AC_INIT_COMPLETE_OBS:RD:8:14:=0x0000 PHY_DLL_RST_EN:RW_D:0:2:=0x02
-`define             DENALI_PHY_1890_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GRP_SLV_DLY_ENC_OBS_SELECT:RW:24:6:=0x00 PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE:RW_D:16:1:=0x00 PHY_ERR_IE:RW:8:1:=0x00 PHY_UPDATE_MASK:RW:0:1:=0x00
-`define             DENALI_PHY_1891_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GRP_SHIFT_OBS:RD:24:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS:RD:8:11:=0x0000 PHY_GRP_SHIFT_OBS_SELECT:RW:0:5:=0x00
-`define             DENALI_PHY_1892_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_CAL_IO_CFG_0:RW+:0:18:=0x000000
-`define             DENALI_PHY_1893_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_ACS_IO_CFG:RW+:0:19:=0x000000
-`define             DENALI_PHY_1894_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PLL_BYPASS:RW+:0:1:=0x00
-`define             DENALI_PHY_1895_DATA 32'b00000000_00000000_00010001_01000010 // PHY_LOW_FREQ_SEL:RW+:16:1:=0x00 PHY_PLL_CTRL:RW+:0:13:=0x1142
-`define             DENALI_PHY_1896_DATA 32'b00000011_00000010_00000001_00000000 // PHY_CSLVL_DLY_STEP:RW+:24:4:=0x03 PHY_CSLVL_CAPTURE_CNT:RW+:16:4:=0x02 PHY_PAD_VREF_CTRL_AC:RW:0:10:=0x0100
-`define             DENALI_PHY_1897_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1898_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1899_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1900_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1901_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1902_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1903_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_3:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_3:RW+:0:11:=0x0300
-`define             DENALI_PHY_1904_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_3:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_3:RW+:0:11:=0x0300
-`define             DENALI_PHY_1905_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_4:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_4:RW+:0:11:=0x0300
-`define             DENALI_PHY_1906_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_4:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_4:RW+:0:11:=0x0300
-`define             DENALI_PHY_1907_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP0_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1908_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1909_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP2_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1910_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1911_DATA 32'b00000000_00000000_00000000_00000010 // PHY_CLK_DC_CAL_CLK_SEL:RW+:0:3:=0x02
-`define             DENALI_PHY_1912_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_FDBK_DRIVE:RW+:0:28:=0x00004011
-`define             DENALI_PHY_1913_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_FDBK_DRIVE2:RW+:0:16:=0x4011
-`define             DENALI_PHY_1914_DATA 32'b00000000_00000000_00000000_01000000 // PHY_PAD_DATA_DRIVE:RW+:0:30:=0x00000040
-`define             DENALI_PHY_1915_DATA 32'b00000000_00000000_00000000_01000000 // PHY_PAD_DQS_DRIVE:RW+:0:28:=0x00000040
-`define             DENALI_PHY_1916_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ADDR_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1917_DATA 32'b00000000_00011111_11111111_00000000 // PHY_PAD_ADDR_DRIVE2:RW+:0:22:=0x1fff00
-`define             DENALI_PHY_1918_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CLK_DRIVE:RW+:0:31:=0x00004011
-`define             DENALI_PHY_1919_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CLK_DRIVE2:RW+:0:17:=0x004011
-`define             DENALI_PHY_1920_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ERR_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1921_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ERR_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1922_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CKE_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1923_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CKE_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1924_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_RST_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1925_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_RST_DRIVE2:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1926_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CS_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1927_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CS_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1928_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ODT_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1929_DATA 32'b00000001_00000000_01000000_00010001 // PHY_CAL_CLK_SELECT_0:RW+:24:3:=0x01 PHY_PAD_ODT_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1930_DATA 32'b00000000_00100000_00000100_00000000 // PHY_CAL_SETTLING_PRD_0:RW+:16:7:=0x20 PHY_CAL_VREF_SWITCH_TIMER_0:RW+:0:16:=0x0400
-//* ********************************************************
-//* The below are used only for simulation phy purposes.
-//* Please ignore if using integrated Cadence PHY.
-//* SimulationValues {{{
-//* ********************************************************
-`define SIM_PHY_VALS_DEFINED 1 // Global define for simulation
-`define                        SMALL_TREF_ENABLE 8'h0 // CTL
-`define                                  MR8_VAL 8'h10 // CTL
-`define                                  MR0_VAL 8'h0 // CTL
-`define                          MR0_RL3_SUPPORT 2'h0 // CTL
-`define                            ODT_RD_TIMING 6'h0 // CTL
-`define                                  TAC_MIN 6'h0 // CTL
-`define                                  TAC_MAX 6'h0 // CTL
-`define               LPDDR1_PD_CLK_GATE_DISABLE 1'h0 // CTL
-`define                          LPDDR1_ATTACHED 1'h0 // CTL
-//* ********************************************************
-//* SimulationValues }}}
-//* ********************************************************

+ 0 - 2030
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16/regconfig.h.sim_PHY_micron.v

@@ -1,2030 +0,0 @@
-
-/* ****************************************************************
- *        CADENCE                    Copyright (c) 2001-2018      *
- *                                   Cadence Design Systems, Inc. *
- *                                   All rights reserved.         *
- ******************************************************************
- *  The values calculated from this script are meant to be        *
- *  representative programmings.   The values may not reflect the *
- *  actual required programming for production use.   Please      *
- *  closely review all programmed values for technical accuracy   *
- *  before use in production parts.                               *
- ******************************************************************
- *                                                                 
- *   Module:         regconfig.h
- *   Documentation:  Register programming header file
- *
- ******************************************************************
- ******************************************************************
- * WARNING:  This file was automatically generated.  Manual
- * editing may result in undetermined behavior.
- ******************************************************************
- ******************************************************************/
-// REL: sifive.shanghai.n1-VIC_DDR__20180206
-
-
-`timescale 10ps/10ps
-
-// ********************************************************************
-// Option: IP    : IP Mode                       = PHY
-// Option: BL    : Burst Length                  = 16
-// Option: CL    : CAS Latency                   = 28
-// Option: MHZ   : Simulation MHz                = 1600
-// Option: AP    : Auto Precharge Mode     (0/1) = 0
-// Option: DLLBP : DLL Bypass Mode         (0/1) = 0
-// Option: HALF  : Half-Memory Support     (0/1) = 0
-// Option: RDIMM : Registered Dimm Support (0/1) = 0
-// Option: AL    : Additive Latency              = 0
-// Option: PREAM : Preamble Support    (0/1/2/3) = 0
-// Option: BOF   : Burst On the Fly        (0/1) = 0
-// Option: WLS   : Write Latency Set       (0/1) = 0
-// Option: TCK   : Simulation period in ns       = 
-// Option: WRDBIEN : Write DBI Enable       (0/1) = 0
-// Option: RDDBIEN : Read DBI Enable       (0/1) = 0
-// Option: RDPSTMBLE : RD Postamble En      (0/1) = 0
-// Option: WRPSTMBLE : WR Postamble En      (0/1) = 0
-// Option: CRC : CRC En      (0/1) = 0
-// Option: SOMA  : Memory-SOMA file(s)           = /proj/iprel/sifive.shanghai.n1-VIC_DDR/sifive.shanghai.n1-VIC_DDR__20180201/mcip/mem/sifive.shanghai.n1-VIC_DDR/memory/jedec_lpddr4_16gb_3200/memory.xml.sim
-// Option: PL    : CA Parity Latency              = -1
-// ********************************************************************
-// Memory: jedec_lpddr4_16gb_3200
-// ********************************************************************
-
-
-`define               DENALI_PHY_00_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_0:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x04f0
-`define               DENALI_PHY_01_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_0:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0:RW:0:10:=0x0000
-`define               DENALI_PHY_02_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_0:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_0:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0:RW:0:10:=0x0200
-`define               DENALI_PHY_03_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_0:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_0:RW:0:1:=0x00
-`define               DENALI_PHY_04_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_0:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_0:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_0:RW:0:6:=0x00
-`define               DENALI_PHY_05_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_0:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_0:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_0:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_0:RW:0:6:=0x00
-`define               DENALI_PHY_06_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_0:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_0:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_0:RW_D:0:1:=0x01
-`define               DENALI_PHY_07_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_0:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0:RW:0:5:=0x00
-`define               DENALI_PHY_08_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_0:RW:24:1:=0x01 PHY_LPBK_CONTROL_0:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0:RW:0:5:=0x01
-`define               DENALI_PHY_09_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_0:RW:0:32:=0x00000000
-`define               DENALI_PHY_10_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_0:RD:0:28:=0x00000000
-`define               DENALI_PHY_11_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_0:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_0:RW:8:9:=0x0000 PHY_PDA_MODE_EN_0:RW:0:1:=0x01
-`define               DENALI_PHY_12_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_0:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_0:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_0:RW:0:9:=0x0000
-`define               DENALI_PHY_13_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_0:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_0:RW:0:5:=0x04
-`define               DENALI_PHY_14_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_0:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_0:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_0:RW:0:4:=0x08
-`define               DENALI_PHY_15_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_0:RW:16:9:=0x0066 PHY_MEM_CLASS_0:RW:8:3:=0x06 PHY_LPDDR_0:RW:0:1:=0x01
-`define               DENALI_PHY_16_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_0:RW:0:2:=0x03
-`define               DENALI_PHY_17_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_18_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_0:RW:8:2:=0x00 PHY_DFI40_POLARITY_0:RW:0:1:=0x01
-`define               DENALI_PHY_19_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_0:RW:0:32:=0x0000AAAA
-`define               DENALI_PHY_20_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_0:RW:0:32:=0x00005555
-`define               DENALI_PHY_21_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_0:RW:0:32:=0x0000B5B5
-`define               DENALI_PHY_22_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_0:RW:0:32:=0x00004A4A
-`define               DENALI_PHY_23_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_0:RW:0:32:=0x00005656
-`define               DENALI_PHY_24_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_0:RW:0:32:=0x0000A9A9
-`define               DENALI_PHY_25_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_0:RW:0:32:=0x0000A9A9
-`define               DENALI_PHY_26_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_0:RW:0:32:=0x0000B5B5
-`define               DENALI_PHY_27_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_0:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_0:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00
-`define               DENALI_PHY_28_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_0:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_0:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_0:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_0:RW:0:4:=0x00
-`define               DENALI_PHY_29_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_0:RW:24:6:=0x08 PHY_WRLVL_ALGO_0:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_0:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_0:RW:0:1:=0x00
-`define               DENALI_PHY_30_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_0:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_0:RW:16:6:=0x00 PHY_DQ_MASK_0:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_0:RW:0:4:=0x08
-`define               DENALI_PHY_31_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_0:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_0:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_0:RW:0:6:=0x08
-`define               DENALI_PHY_32_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_0:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_0:RW:0:8:=0x00
-`define               DENALI_PHY_33_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_0:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_0:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_0:RW:0:8:=0x20
-`define               DENALI_PHY_34_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_0:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_0:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0:RW:0:11:=0x0020
-`define               DENALI_PHY_35_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_0:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_0:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_0:RW:0:8:=0x20
-`define               DENALI_PHY_36_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_0:RW:0:9:=0x0100
-`define               DENALI_PHY_37_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_0:RW:0:32:=0x55555555
-`define               DENALI_PHY_38_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_0:RW:0:32:=0xAAAAAAAA
-`define               DENALI_PHY_39_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_0:RW:0:32:=0x55555555
-`define               DENALI_PHY_40_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_0:RW:0:32:=0xAAAAAAAA
-`define               DENALI_PHY_41_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_0:RW:16:1:=0x00 PHY_USER_PATT4_0:RW:0:16:=0x5555
-`define               DENALI_PHY_42_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_0:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_0:RW:0:10:=0x0100
-`define               DENALI_PHY_43_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_0:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_0:RW:0:10:=0x0180
-`define               DENALI_PHY_44_DATA 32'b00000000_00000000_00000000_00000001 // PHY_FIFO_PTR_OBS_0:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_0:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_0:RW:0:1:=0x01
-`define               DENALI_PHY_45_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_46_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_0:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000
-`define               DENALI_PHY_47_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_0:RD:0:7:=0x00
-`define               DENALI_PHY_48_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_49_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_0:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_0:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_0:RD:0:8:=0x00
-`define               DENALI_PHY_50_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_51_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_0:RD:0:17:=0x000000
-`define               DENALI_PHY_52_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_53_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_0:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_0:RD:0:16:=0x0000
-`define               DENALI_PHY_54_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_0:RD:0:14:=0x0000
-`define               DENALI_PHY_55_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_0:RD:0:18:=0x000000
-`define               DENALI_PHY_56_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0:RD:0:10:=0x0000
-`define               DENALI_PHY_57_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0:RD:0:2:=0x00
-`define               DENALI_PHY_58_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_59_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_0:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_60_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_61_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_0:RW:0:31:=0x00000000
-`define               DENALI_PHY_62_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_0:RW:0:6:=0x00
-`define               DENALI_PHY_63_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_0:RD:0:32:=0x00000000
-`define               DENALI_PHY_64_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000
-//`define               DENALI_PHY_65_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_0:RW:24:1:=0x00 SC_PHY_RX_CAL_START_0:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_0:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_0:RW:0:8:=0x04
-`define               DENALI_PHY_65_DATA 32'b00000000_00000000_00000001_00000100 // PHY_RX_CAL_OVERRIDE_0:RW:24:1:=0x00 SC_PHY_RX_CAL_START_0:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_0:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_0:RW:0:8:=0x04
-`define               DENALI_PHY_66_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_0:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_0:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_0:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_0:RW:0:8:=0x20
-`define               DENALI_PHY_67_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_0:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_0:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_0:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_0:RW+:0:6:=0x00
-`define               DENALI_PHY_68_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_0:RW+:24:6:=0x00 PHY_RX_CAL_DQS_0:RW+:16:6:=0x00 PHY_RX_CAL_DM_0:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_0:RW+:0:6:=0x00
-`define               DENALI_PHY_69_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_0:RD:16:9:=0x0000 PHY_RX_CAL_OBS_0:RD:0:11:=0x0000
-`define               DENALI_PHY_70_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_0:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_0:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_0:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_0:RW:0:1:=0x00
-`define               DENALI_PHY_71_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_0:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_0:RW:0:12:=0x0000
-`define               DENALI_PHY_72_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_0:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define               DENALI_PHY_73_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10
-`define               DENALI_PHY_74_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_0:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_0:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_0:RW+:0:1:=0x00
-`define               DENALI_PHY_75_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_0:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_0:RW_D:0:1:=0x00
-`define               DENALI_PHY_76_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_0:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_0:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_0:RW+:0:3:=0x01
-`define               DENALI_PHY_77_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_0:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_0:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_0:RW+:0:16:=0x880c
-`define               DENALI_PHY_78_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_0:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_0:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_0:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_0:RW+:0:6:=0x25
-`define               DENALI_PHY_79_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_0:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_0:RW+:0:11:=0x0200
-`define               DENALI_PHY_80_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_0:RW+:24:5:=0x00 PHY_PAD_TX_DCD_0:RW+:16:5:=0x00 PHY_FAST_LVL_EN_0:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_0:RW+:0:8:=0x01
-`define               DENALI_PHY_81_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_0:RW+:0:5:=0x00
-`define               DENALI_PHY_82_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_0:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_0:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_0:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_0:RW+:0:5:=0x00
-`define               DENALI_PHY_83_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_0:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_0:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_0:RW+:0:5:=0x00
-`define               DENALI_PHY_84_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_85_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_86_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_87_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_88_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_0:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_0:RW+:0:10:=0x0000
-`define               DENALI_PHY_89_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x52
-//`define               DENALI_PHY_89_DATA 32'b11111111_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x52
-//`define               DENALI_PHY_89_DATA 32'b00000000_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_0:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_0:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_0:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_0:RW+:0:8:=0x52
-`define               DENALI_PHY_90_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_0:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_0:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_0:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_0:RW+:0:4:=0x00
-`define               DENALI_PHY_91_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_0:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_0:RW+:0:16:=0x0004
-`define               DENALI_PHY_92_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_0:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_0:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_0:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:0:1:=0x01
-//`define               DENALI_PHY_92_DATA 32'b00000010_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_0:RW+:24:2:=0x02 PHY_DQS_IE_TIMING_0:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_0:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_0:RW+:0:1:=0x01
-`define               DENALI_PHY_93_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_0:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_0:RW+:16:1:=0x00 PHY_DBI_MODE_0:RW+:8:2:=0x00 PHY_IE_MODE_0:RW+:0:2:=0x00
-`define               DENALI_PHY_94_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_0:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_0:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_0:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0:RW+:0:5:=0x03
-//`define               DENALI_PHY_94_DATA 32'b00000000_00000000_00000011_00000011 // PHY_SW_MASTER_MODE_0:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_0:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_0:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0:RW+:0:5:=0x03
-`define               DENALI_PHY_95_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_0:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_0:RW+:0:11:=0x0010
-`define               DENALI_PHY_96_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_0:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_0:RW+:16:8:=0x0c PHY_RPTR_UPDATE_0:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e
-//`define               DENALI_PHY_96_DATA 32'b00000001_00001100_00001001_00111110 // PHY_WRLVL_DLY_FINE_STEP_0:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_0:RW+:16:8:=0x0c PHY_RPTR_UPDATE_0:RW+:8:4:=0x09 PHY_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e
-`define               DENALI_PHY_97_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_0:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_0:RW+:0:6:=0x2b
-`define               DENALI_PHY_98_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_0:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_0:RW+:0:10:=0x0140
-`define               DENALI_PHY_99_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_0:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_0:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_0:RW+:0:8:=0x20
-`define              DENALI_PHY_100_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_0:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_0:RW+:0:1:=0x00
-`define              DENALI_PHY_101_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_0:RW+:0:10:=0x0299
-`define              DENALI_PHY_102_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_0:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_0:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_0:RW+:0:2:=0x00
-`define              DENALI_PHY_103_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_0:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_104_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_0:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_0:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_0:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_0:RW+:0:1:=0x01
-//`define              DENALI_PHY_105_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_0:RW+:0:5:=0x04
-`define              DENALI_PHY_105_DATA 32'b00000000_00000000_00000000_00000110 // PHY_RDDATA_EN_DLY_0:RW+:0:5:=0x06/0x07 is ok when tDQSCK=3.5
-`define              DENALI_PHY_106_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_0:RW+:0:32:=0x76543210
-`define              DENALI_PHY_107_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_0:RW+:0:4:=0x08
-`define              DENALI_PHY_108_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_109_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_110_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_111_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_0:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_112_DATA 32'b00000000_00000000_00000100_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_0:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_0:RW+:0:11:=0x0280
-`define              DENALI_PHY_113_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_0:RW+:0:2:=0x00
-`define              DENALI_PHY_114_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_115_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_116_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_117_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_118_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_119_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_120_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_121_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_0:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_122_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_0:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_0:RW+:0:10:=0x00a0
-`define              DENALI_PHY_123_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_0:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_0:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_0:RW+:0:4:=0x04
-`define              DENALI_PHY_124_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_0:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_125_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_0:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_126_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_0:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_0:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_0:RW+:0:11:=0x0200
-`define              DENALI_PHY_127_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0:RW+:0:10:=0x0000
-`define              DENALI_PHY_128_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_129_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_130_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_0:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_0:RW+:0:8:=0x20
-`define              DENALI_PHY_131_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_0:RW+:0:4:=0x00
-`define              DENALI_PHY_132_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_133_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_134_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_135_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_136_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_137_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_138_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_139_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_140_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_141_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_142_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_143_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_144_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_145_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_146_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_147_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_148_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_149_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_150_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_151_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_152_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_153_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_154_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_155_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_156_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_157_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_158_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_159_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_160_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_161_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_162_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_163_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_164_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_165_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_166_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_167_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_168_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_169_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_170_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_171_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_172_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_173_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_174_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_175_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_176_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_177_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_178_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_179_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_180_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_181_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_182_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_183_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_184_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_185_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_186_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_187_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_188_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_189_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_190_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_191_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_192_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_193_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_194_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_195_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_196_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_197_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_198_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_199_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_200_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_201_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_202_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_203_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_204_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_205_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_206_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_207_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_208_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_209_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_210_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_211_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_212_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_213_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_214_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_215_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_216_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_217_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_218_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_219_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_220_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_221_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_222_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_223_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_224_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_225_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_226_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_227_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_228_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_229_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_230_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_231_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_232_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_233_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_234_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_235_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_236_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_237_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_238_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_239_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_240_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_241_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_242_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_243_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_244_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_245_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_246_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_247_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_248_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_249_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_250_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_251_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_252_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_253_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_254_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_255_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_256_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_1:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x04f0
-`define              DENALI_PHY_257_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_1:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1:RW:0:10:=0x0000
-`define              DENALI_PHY_258_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_1:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_1:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1:RW:0:10:=0x0200
-`define              DENALI_PHY_259_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_1:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_1:RW:0:1:=0x00
-`define              DENALI_PHY_260_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_1:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_1:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_1:RW:0:6:=0x00
-`define              DENALI_PHY_261_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_1:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_1:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_1:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_1:RW:0:6:=0x00
-`define              DENALI_PHY_262_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_1:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_1:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_1:RW_D:0:1:=0x01
-`define              DENALI_PHY_263_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_1:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1:RW:0:5:=0x00
-`define              DENALI_PHY_264_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_1:RW:24:1:=0x01 PHY_LPBK_CONTROL_1:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1:RW:0:5:=0x01
-`define              DENALI_PHY_265_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_1:RW:0:32:=0x00000000
-`define              DENALI_PHY_266_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_1:RD:0:28:=0x00000000
-`define              DENALI_PHY_267_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_1:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_1:RW:8:9:=0x0000 PHY_PDA_MODE_EN_1:RW:0:1:=0x01
-`define              DENALI_PHY_268_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_1:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_1:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_1:RW:0:9:=0x0000
-`define              DENALI_PHY_269_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_1:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_1:RW:0:5:=0x04
-`define              DENALI_PHY_270_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_1:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_1:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_1:RW:0:4:=0x08
-`define              DENALI_PHY_271_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_1:RW:16:9:=0x0066 PHY_MEM_CLASS_1:RW:8:3:=0x06 PHY_LPDDR_1:RW:0:1:=0x01
-`define              DENALI_PHY_272_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_1:RW:0:2:=0x03
-`define              DENALI_PHY_273_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_274_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_1:RW:8:2:=0x00 PHY_DFI40_POLARITY_1:RW:0:1:=0x01
-`define              DENALI_PHY_275_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_1:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_276_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_1:RW:0:32:=0x00005555
-`define              DENALI_PHY_277_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_1:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_278_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_1:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_279_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_1:RW:0:32:=0x00005656
-`define              DENALI_PHY_280_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_1:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_281_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_1:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_282_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_1:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_283_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_1:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_1:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00
-`define              DENALI_PHY_284_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_1:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_1:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_1:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_1:RW:0:4:=0x00
-`define              DENALI_PHY_285_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_1:RW:24:6:=0x08 PHY_WRLVL_ALGO_1:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_1:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_1:RW:0:1:=0x00
-`define              DENALI_PHY_286_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_1:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_1:RW:16:6:=0x00 PHY_DQ_MASK_1:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_1:RW:0:4:=0x08
-`define              DENALI_PHY_287_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_1:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_1:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_1:RW:0:6:=0x08
-`define              DENALI_PHY_288_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_1:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_1:RW:0:8:=0x00
-`define              DENALI_PHY_289_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_1:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_1:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_1:RW:0:8:=0x20
-`define              DENALI_PHY_290_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_1:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_1:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1:RW:0:11:=0x0020
-`define              DENALI_PHY_291_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_1:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_1:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_1:RW:0:8:=0x20
-`define              DENALI_PHY_292_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_1:RW:0:9:=0x0100
-`define              DENALI_PHY_293_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_1:RW:0:32:=0x55555555
-`define              DENALI_PHY_294_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_1:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_295_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_1:RW:0:32:=0x55555555
-`define              DENALI_PHY_296_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_1:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_297_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_1:RW:16:1:=0x00 PHY_USER_PATT4_1:RW:0:16:=0x5555
-`define              DENALI_PHY_298_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_1:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_1:RW:0:10:=0x0100
-`define              DENALI_PHY_299_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_1:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_1:RW:0:10:=0x0180
-`define              DENALI_PHY_300_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_1:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_1:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_1:RW:0:1:=0x00
-`define              DENALI_PHY_301_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_302_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_1:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000
-`define              DENALI_PHY_303_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_1:RD:0:7:=0x00
-`define              DENALI_PHY_304_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_305_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_1:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_1:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_1:RD:0:8:=0x00
-`define              DENALI_PHY_306_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_307_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_1:RD:0:17:=0x000000
-`define              DENALI_PHY_308_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_309_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_1:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_1:RD:0:16:=0x0000
-`define              DENALI_PHY_310_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_1:RD:0:14:=0x0000
-`define              DENALI_PHY_311_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_1:RD:0:18:=0x000000
-`define              DENALI_PHY_312_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1:RD:0:10:=0x0000
-`define              DENALI_PHY_313_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1:RD:0:2:=0x00
-`define              DENALI_PHY_314_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_315_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_1:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_316_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_317_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_1:RW:0:31:=0x00000000
-`define              DENALI_PHY_318_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_1:RW:0:6:=0x00
-`define              DENALI_PHY_319_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_1:RD:0:32:=0x00000000
-`define              DENALI_PHY_320_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000
-//`define              DENALI_PHY_321_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_1:RW:24:1:=0x00 SC_PHY_RX_CAL_START_1:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_1:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_1:RW:0:8:=0x04
-`define              DENALI_PHY_321_DATA 32'b00000000_00000000_00000001_00000100 // PHY_RX_CAL_OVERRIDE_1:RW:24:1:=0x00 SC_PHY_RX_CAL_START_1:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_1:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_1:RW:0:8:=0x04
-`define              DENALI_PHY_322_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_1:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_1:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_1:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_1:RW:0:8:=0x20
-`define              DENALI_PHY_323_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_1:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_1:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_1:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_1:RW+:0:6:=0x00
-`define              DENALI_PHY_324_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_1:RW+:24:6:=0x00 PHY_RX_CAL_DQS_1:RW+:16:6:=0x00 PHY_RX_CAL_DM_1:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_1:RW+:0:6:=0x00
-`define              DENALI_PHY_325_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_1:RD:16:9:=0x0000 PHY_RX_CAL_OBS_1:RD:0:11:=0x0000
-`define              DENALI_PHY_326_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_1:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_1:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_1:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_1:RW:0:1:=0x00
-`define              DENALI_PHY_327_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_1:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_1:RW:0:12:=0x0000
-`define              DENALI_PHY_328_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_1:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_1:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_1:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_1:RW:0:8:=0x08
-`define              DENALI_PHY_329_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_1:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_1:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_1:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_1:RW:0:8:=0x10
-`define              DENALI_PHY_330_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_1:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_1:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_1:RW+:0:1:=0x00
-`define              DENALI_PHY_331_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_1:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_1:RW_D:0:1:=0x00
-`define              DENALI_PHY_332_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_1:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_1:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_1:RW+:0:3:=0x01
-`define              DENALI_PHY_333_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_1:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_1:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_1:RW+:0:16:=0x880c
-`define              DENALI_PHY_334_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_1:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_1:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_1:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_1:RW+:0:6:=0x25
-`define              DENALI_PHY_335_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_1:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_1:RW+:0:11:=0x0200
-`define              DENALI_PHY_336_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_1:RW+:24:5:=0x00 PHY_PAD_TX_DCD_1:RW+:16:5:=0x00 PHY_FAST_LVL_EN_1:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_1:RW+:0:8:=0x01
-`define              DENALI_PHY_337_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_1:RW+:0:5:=0x00
-`define              DENALI_PHY_338_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_1:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_1:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_1:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_1:RW+:0:5:=0x00
-`define              DENALI_PHY_339_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_1:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_1:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_1:RW+:0:5:=0x00
-`define              DENALI_PHY_340_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_341_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_342_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_343_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_344_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_1:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_345_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x52
-//`define              DENALI_PHY_345_DATA 32'b11111111_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x52
-//`define              DENALI_PHY_345_DATA 32'b00000000_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_1:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_1:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_1:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_1:RW+:0:8:=0x52
-`define              DENALI_PHY_346_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_1:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_1:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_1:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_1:RW+:0:4:=0x00
-`define              DENALI_PHY_347_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_1:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_1:RW+:0:16:=0x0004
-`define              DENALI_PHY_348_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_1:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_1:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_1:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:0:1:=0x01
-//`define              DENALI_PHY_348_DATA 32'b00000010_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_1:RW+:24:2:=0x02 PHY_DQS_IE_TIMING_1:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_1:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_1:RW+:0:1:=0x01
-`define              DENALI_PHY_349_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_1:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_1:RW+:16:1:=0x00 PHY_DBI_MODE_1:RW+:8:2:=0x00 PHY_IE_MODE_1:RW+:0:2:=0x00
-`define              DENALI_PHY_350_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_1:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_1:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_1:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1:RW+:0:5:=0x03
-//`define              DENALI_PHY_350_DATA 32'b00000000_00000000_00000011_00000011 // PHY_SW_MASTER_MODE_1:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_1:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_1:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1:RW+:0:5:=0x03
-`define              DENALI_PHY_351_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_1:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_1:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_1:RW+:0:11:=0x0010
-`define              DENALI_PHY_352_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_1:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_1:RW+:16:8:=0x0c PHY_RPTR_UPDATE_1:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_1:RW+:0:8:=0x3e
-//`define              DENALI_PHY_352_DATA 32'b00000001_00001100_00001001_00111110 // PHY_WRLVL_DLY_FINE_STEP_1:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_1:RW+:16:8:=0x0c PHY_RPTR_UPDATE_1:RW+:8:4:=0x09 PHY_MASTER_DELAY_HALF_MEASURE_1:RW+:0:8:=0x3e
-`define              DENALI_PHY_353_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_1:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_1:RW+:0:6:=0x2b
-`define              DENALI_PHY_354_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_1:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_1:RW+:0:10:=0x0140
-`define              DENALI_PHY_355_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_1:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_1:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_1:RW+:0:8:=0x20
-`define              DENALI_PHY_356_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_1:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_1:RW+:0:1:=0x00
-`define              DENALI_PHY_357_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_1:RW+:0:10:=0x0299
-`define              DENALI_PHY_358_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_1:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_1:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_1:RW+:0:2:=0x00
-`define              DENALI_PHY_359_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_1:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_360_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_1:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_1:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_1:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_1:RW+:0:1:=0x01
-//`define              DENALI_PHY_361_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_1:RW+:0:5:=0x04
-`define              DENALI_PHY_361_DATA 32'b00000000_00000000_00000000_00000110 // PHY_RDDATA_EN_DLY_1:RW+:0:5:=0x06/0x07 is ok when tDQSCK=3.5
-`define              DENALI_PHY_362_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_1:RW+:0:32:=0x76543210
-`define              DENALI_PHY_363_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_1:RW+:0:4:=0x08
-`define              DENALI_PHY_364_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_365_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_366_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_367_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_1:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_368_DATA 32'b00000000_00000000_00000100_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_1:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_1:RW+:0:11:=0x0280
-`define              DENALI_PHY_369_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_1:RW+:0:2:=0x00
-`define              DENALI_PHY_370_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_371_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_372_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_373_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_374_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_375_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_376_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_377_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_1:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_378_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_1:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_1:RW+:0:10:=0x00a0
-`define              DENALI_PHY_379_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_1:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_1:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_1:RW+:0:4:=0x04
-`define              DENALI_PHY_380_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_1:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_381_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_1:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_382_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_1:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_1:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_1:RW+:0:11:=0x0200
-`define              DENALI_PHY_383_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1:RW+:0:10:=0x0000
-`define              DENALI_PHY_384_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_385_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_386_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_1:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_1:RW+:0:8:=0x20
-`define              DENALI_PHY_387_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_1:RW+:0:4:=0x00
-`define              DENALI_PHY_388_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_389_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_390_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_391_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_392_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_393_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_394_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_395_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_396_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_397_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_398_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_399_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_400_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_401_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_402_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_403_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_404_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_405_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_406_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_407_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_408_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_409_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_410_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_411_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_412_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_413_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_414_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_415_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_416_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_417_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_418_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_419_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_420_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_421_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_422_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_423_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_424_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_425_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_426_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_427_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_428_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_429_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_430_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_431_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_432_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_433_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_434_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_435_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_436_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_437_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_438_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_439_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_440_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_441_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_442_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_443_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_444_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_445_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_446_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_447_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_448_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_449_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_450_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_451_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_452_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_453_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_454_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_455_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_456_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_457_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_458_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_459_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_460_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_461_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_462_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_463_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_464_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_465_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_466_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_467_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_468_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_469_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_470_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_471_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_472_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_473_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_474_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_475_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_476_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_477_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_478_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_479_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_480_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_481_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_482_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_483_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_484_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_485_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_486_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_487_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_488_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_489_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_490_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_491_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_492_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_493_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_494_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_495_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_496_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_497_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_498_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_499_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_500_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_501_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_502_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_503_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_504_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_505_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_506_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_507_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_508_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_509_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_510_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_511_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_512_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_2:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x04f0
-`define              DENALI_PHY_513_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_2:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_2:RW:0:10:=0x0000
-`define              DENALI_PHY_514_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_2:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_2:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_2:RW:0:10:=0x0200
-`define              DENALI_PHY_515_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_2:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_2:RW:0:1:=0x00
-`define              DENALI_PHY_516_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_2:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_2:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_2:RW:0:6:=0x00
-`define              DENALI_PHY_517_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_2:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_2:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_2:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_2:RW:0:6:=0x00
-`define              DENALI_PHY_518_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_2:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_2:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_2:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_2:RW_D:0:1:=0x01
-`define              DENALI_PHY_519_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_2:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_2:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_2:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_2:RW:0:5:=0x00
-`define              DENALI_PHY_520_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_2:RW:24:1:=0x01 PHY_LPBK_CONTROL_2:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_2:RW:0:5:=0x01
-`define              DENALI_PHY_521_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_2:RW:0:32:=0x00000000
-`define              DENALI_PHY_522_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_2:RD:0:28:=0x00000000
-`define              DENALI_PHY_523_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_2:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_2:RW:8:9:=0x0000 PHY_PDA_MODE_EN_2:RW:0:1:=0x01
-`define              DENALI_PHY_524_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_2:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_2:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_2:RW:0:9:=0x0000
-`define              DENALI_PHY_525_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_2:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_2:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_2:RW:0:5:=0x04
-`define              DENALI_PHY_526_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_2:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_2:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_2:RW:0:4:=0x08
-`define              DENALI_PHY_527_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_2:RW:16:9:=0x0066 PHY_MEM_CLASS_2:RW:8:3:=0x06 PHY_LPDDR_2:RW:0:1:=0x01
-`define              DENALI_PHY_528_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_2:RW:0:2:=0x03
-`define              DENALI_PHY_529_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_530_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_2:RW:8:2:=0x00 PHY_DFI40_POLARITY_2:RW:0:1:=0x01
-`define              DENALI_PHY_531_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_2:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_532_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_2:RW:0:32:=0x00005555
-`define              DENALI_PHY_533_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_2:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_534_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_2:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_535_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_2:RW:0:32:=0x00005656
-`define              DENALI_PHY_536_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_2:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_537_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_2:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_538_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_2:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_539_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_2:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_2:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00
-`define              DENALI_PHY_540_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_2:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_2:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_2:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_2:RW:0:4:=0x00
-`define              DENALI_PHY_541_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_2:RW:24:6:=0x08 PHY_WRLVL_ALGO_2:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_2:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_2:RW:0:1:=0x00
-`define              DENALI_PHY_542_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_2:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_2:RW:16:6:=0x00 PHY_DQ_MASK_2:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_2:RW:0:4:=0x08
-`define              DENALI_PHY_543_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_2:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_2:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_2:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_2:RW:0:6:=0x08
-`define              DENALI_PHY_544_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_2:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_2:RW:0:8:=0x00
-`define              DENALI_PHY_545_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_2:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_2:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_2:RW:0:8:=0x20
-`define              DENALI_PHY_546_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_2:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_2:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_2:RW:0:11:=0x0020
-`define              DENALI_PHY_547_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_2:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_2:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_2:RW:0:8:=0x20
-`define              DENALI_PHY_548_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_2:RW:0:9:=0x0100
-`define              DENALI_PHY_549_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_2:RW:0:32:=0x55555555
-`define              DENALI_PHY_550_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_2:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_551_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_2:RW:0:32:=0x55555555
-`define              DENALI_PHY_552_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_2:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_553_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_2:RW:16:1:=0x00 PHY_USER_PATT4_2:RW:0:16:=0x5555
-`define              DENALI_PHY_554_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_2:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_2:RW:0:10:=0x0100
-`define              DENALI_PHY_555_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_2:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_2:RW:0:10:=0x0180
-`define              DENALI_PHY_556_DATA 32'b00000000_00000000_00000000_00000001 // PHY_FIFO_PTR_OBS_2:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_2:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_2:RW:0:1:=0x01
-`define              DENALI_PHY_557_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_558_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_2:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000
-`define              DENALI_PHY_559_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_2:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_2:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_2:RD:0:7:=0x00
-`define              DENALI_PHY_560_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_2:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_561_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_2:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_2:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_2:RD:0:8:=0x00
-`define              DENALI_PHY_562_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_563_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_2:RD:0:17:=0x000000
-`define              DENALI_PHY_564_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_2:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_565_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_2:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_2:RD:0:16:=0x0000
-`define              DENALI_PHY_566_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_2:RD:0:14:=0x0000
-`define              DENALI_PHY_567_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_2:RD:0:18:=0x000000
-`define              DENALI_PHY_568_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_2:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_2:RD:0:10:=0x0000
-`define              DENALI_PHY_569_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_2:RD:0:2:=0x00
-`define              DENALI_PHY_570_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_571_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_2:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_572_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_573_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_2:RW:0:31:=0x00000000
-`define              DENALI_PHY_574_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_2:RW:0:6:=0x00
-`define              DENALI_PHY_575_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_2:RD:0:32:=0x00000000
-`define              DENALI_PHY_576_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000
-//`define              DENALI_PHY_577_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_2:RW:24:1:=0x00 SC_PHY_RX_CAL_START_2:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_2:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_2:RW:0:8:=0x04
-`define              DENALI_PHY_577_DATA 32'b00000000_00000000_00000001_00000100 // PHY_RX_CAL_OVERRIDE_2:RW:24:1:=0x00 SC_PHY_RX_CAL_START_2:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_2:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_2:RW:0:8:=0x04
-`define              DENALI_PHY_578_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_2:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_2:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_2:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_2:RW:0:8:=0x20
-`define              DENALI_PHY_579_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_2:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_2:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_2:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_2:RW+:0:6:=0x00
-`define              DENALI_PHY_580_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_2:RW+:24:6:=0x00 PHY_RX_CAL_DQS_2:RW+:16:6:=0x00 PHY_RX_CAL_DM_2:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_2:RW+:0:6:=0x00
-`define              DENALI_PHY_581_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_2:RD:16:9:=0x0000 PHY_RX_CAL_OBS_2:RD:0:11:=0x0000
-`define              DENALI_PHY_582_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_2:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_2:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_2:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_2:RW:0:1:=0x00
-`define              DENALI_PHY_583_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_2:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_2:RW:0:12:=0x0000
-`define              DENALI_PHY_584_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_2:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_2:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_2:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_2:RW:0:8:=0x08
-`define              DENALI_PHY_585_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_2:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_2:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_2:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_2:RW:0:8:=0x10
-`define              DENALI_PHY_586_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_2:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_2:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_2:RW+:0:1:=0x00
-`define              DENALI_PHY_587_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_2:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_2:RW_D:0:1:=0x00
-`define              DENALI_PHY_588_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_2:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_2:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_2:RW+:0:3:=0x01
-`define              DENALI_PHY_589_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_2:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_2:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_2:RW+:0:16:=0x880c
-`define              DENALI_PHY_590_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_2:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_2:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_2:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_2:RW+:0:6:=0x25
-`define              DENALI_PHY_591_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_2:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_2:RW+:0:11:=0x0200
-`define              DENALI_PHY_592_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_2:RW+:24:5:=0x00 PHY_PAD_TX_DCD_2:RW+:16:5:=0x00 PHY_FAST_LVL_EN_2:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_2:RW+:0:8:=0x01
-`define              DENALI_PHY_593_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_2:RW+:0:5:=0x00
-`define              DENALI_PHY_594_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_2:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_2:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_2:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_2:RW+:0:5:=0x00
-`define              DENALI_PHY_595_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_2:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_2:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_2:RW+:0:5:=0x00
-`define              DENALI_PHY_596_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_597_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_598_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_599_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_600_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_2:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_601_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x52
-//`define              DENALI_PHY_601_DATA 32'b11111111_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x52
-//`define              DENALI_PHY_601_DATA 32'b00000000_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_2:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_2:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_2:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_2:RW+:0:8:=0x52
-`define              DENALI_PHY_602_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_2:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_2:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_2:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_2:RW+:0:4:=0x00
-`define              DENALI_PHY_603_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_2:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_2:RW+:0:16:=0x0004
-`define              DENALI_PHY_604_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_2:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_2:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_2:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:0:1:=0x01
-//`define              DENALI_PHY_604_DATA 32'b00000010_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_2:RW+:24:2:=0x02 PHY_DQS_IE_TIMING_2:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_2:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_2:RW+:0:1:=0x01
-`define              DENALI_PHY_605_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_2:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_2:RW+:16:1:=0x00 PHY_DBI_MODE_2:RW+:8:2:=0x00 PHY_IE_MODE_2:RW+:0:2:=0x00
-`define              DENALI_PHY_606_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_2:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_2:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_2:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2:RW+:0:5:=0x03
-//`define              DENALI_PHY_606_DATA 32'b00000000_00000000_00000011_00000011 // PHY_SW_MASTER_MODE_2:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_2:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_2:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_2:RW+:0:5:=0x03
-`define              DENALI_PHY_607_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_2:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_2:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_2:RW+:0:11:=0x0010
-`define              DENALI_PHY_608_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_2:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_2:RW+:16:8:=0x0c PHY_RPTR_UPDATE_2:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_2:RW+:0:8:=0x3e
-//`define              DENALI_PHY_608_DATA 32'b00000001_00001100_00001001_00111110 // PHY_WRLVL_DLY_FINE_STEP_2:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_2:RW+:16:8:=0x0c PHY_RPTR_UPDATE_2:RW+:8:4:=0x09 PHY_MASTER_DELAY_HALF_MEASURE_2:RW+:0:8:=0x3e
-`define              DENALI_PHY_609_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_2:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_2:RW+:0:6:=0x2b
-`define              DENALI_PHY_610_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_2:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_2:RW+:0:10:=0x0140
-`define              DENALI_PHY_611_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_2:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_2:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_2:RW+:0:8:=0x20
-`define              DENALI_PHY_612_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_2:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_2:RW+:0:1:=0x00
-`define              DENALI_PHY_613_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_2:RW+:0:10:=0x0299
-`define              DENALI_PHY_614_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_2:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_2:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_2:RW+:0:2:=0x00
-`define              DENALI_PHY_615_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_2:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_616_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_2:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_2:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_2:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_2:RW+:0:1:=0x01
-//`define              DENALI_PHY_617_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_2:RW+:0:5:=0x04
-`define              DENALI_PHY_617_DATA 32'b00000000_00000000_00000000_00000110 // PHY_RDDATA_EN_DLY_2:RW+:0:5:=0x06/0x07 is ok when tDQSCK=3.5
-`define              DENALI_PHY_618_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_2:RW+:0:32:=0x76543210
-`define              DENALI_PHY_619_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_2:RW+:0:4:=0x08
-`define              DENALI_PHY_620_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_621_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_622_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_623_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_2:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_624_DATA 32'b00000000_00000000_00000100_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_2:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_2:RW+:0:11:=0x0280
-`define              DENALI_PHY_625_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_2:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_2:RW+:0:2:=0x00
-`define              DENALI_PHY_626_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_627_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_628_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_629_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_630_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_631_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_632_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_633_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_2:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_634_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_2:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_2:RW+:0:10:=0x00a0
-`define              DENALI_PHY_635_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_2:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_2:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_2:RW+:0:4:=0x04
-`define              DENALI_PHY_636_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_2:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_637_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_2:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_638_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_2:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_2:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_2:RW+:0:11:=0x0200
-`define              DENALI_PHY_639_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_2:RW+:0:10:=0x0000
-`define              DENALI_PHY_640_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_641_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_642_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_2:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_2:RW+:0:8:=0x20
-`define              DENALI_PHY_643_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_2:RW+:0:4:=0x00
-`define              DENALI_PHY_644_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_645_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_646_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_647_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_648_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_649_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_650_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_651_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_652_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_653_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_654_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_655_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_656_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_657_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_658_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_659_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_660_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_661_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_662_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_663_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_664_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_665_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_666_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_667_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_668_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_669_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_670_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_671_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_672_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_673_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_674_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_675_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_676_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_677_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_678_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_679_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_680_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_681_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_682_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_683_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_684_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_685_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_686_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_687_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_688_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_689_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_690_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_691_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_692_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_693_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_694_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_695_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_696_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_697_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_698_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_699_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_700_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_701_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_702_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_703_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_704_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_705_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_706_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_707_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_708_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_709_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_710_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_711_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_712_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_713_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_714_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_715_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_716_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_717_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_718_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_719_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_720_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_721_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_722_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_723_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_724_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_725_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_726_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_727_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_728_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_729_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_730_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_731_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_732_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_733_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_734_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_735_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_736_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_737_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_738_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_739_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_740_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_741_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_742_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_743_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_744_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_745_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_746_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_747_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_748_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_749_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_750_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_751_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_752_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_753_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_754_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_755_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_756_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_757_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_758_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_759_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_760_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_761_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_762_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_763_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_764_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_765_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_766_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_767_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_768_DATA 32'b00000000_00000000_00000100_11110000 // PHY_IO_PAD_DELAY_TIMING_BYPASS_3:RW:16:4:=0x00 PHY_CLK_WR_BYPASS_SLAVE_DELAY_3:RW:0:11:=0x04f0
-`define              DENALI_PHY_769_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRITE_PATH_LAT_ADD_BYPASS_3:RW:16:3:=0x00 PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_3:RW:0:10:=0x0000
-`define              DENALI_PHY_770_DATA 32'b00000001_00000011_00000010_00000000 // PHY_LP2_DQS_GATE_CLS_3:RW:24:4:=0x01 PHY_BYPASS_TWO_CYC_PREAMBLE_3:RW:16:2:=0x03 PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_3:RW:0:10:=0x0200
-`define              DENALI_PHY_771_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ2_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ1_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ0_SHIFT_3:RW:8:6:=0x00 PHY_CLK_BYPASS_OVERRIDE_3:RW:0:1:=0x00
-`define              DENALI_PHY_772_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_WRDQ6_SHIFT_3:RW:24:6:=0x00 PHY_SW_WRDQ5_SHIFT_3:RW:16:6:=0x00 PHY_SW_WRDQ4_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ3_SHIFT_3:RW:0:6:=0x00
-`define              DENALI_PHY_773_DATA 32'b00000011_00000000_00000000_00000000 // PHY_PER_RANK_CS_MAP_3:RW+:24:2:=0x03 PHY_SW_WRDQS_SHIFT_3:RW:16:4:=0x00 PHY_SW_WRDM_SHIFT_3:RW:8:6:=0x00 PHY_SW_WRDQ7_SHIFT_3:RW:0:6:=0x00
-`define              DENALI_PHY_774_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LP4_BOOT_RDDATA_EN_DLY_3:RW:24:5:=0x01 PHY_LP4_BOOT_RDDATA_EN_IE_DLY_3:RW:16:2:=0x00 PHY_PER_CS_TRAINING_INDEX_3:RW+:8:1:=0x00 PHY_PER_CS_TRAINING_MULTICAST_EN_3:RW_D:0:1:=0x01
-`define              DENALI_PHY_775_DATA 32'b00000011_00000000_00000100_00000000 // PHY_LP4_BOOT_WRPATH_GATE_DISABLE_3:RW:24:2:=0x03 PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_3:RW:16:4:=0x00 PHY_LP4_BOOT_RPTR_UPDATE_3:RW:8:4:=0x04 PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_3:RW:0:5:=0x00
-`define              DENALI_PHY_776_DATA 32'b00000001_00000000_00000000_00000001 // PHY_LPBK_DFX_TIMEOUT_EN_3:RW:24:1:=0x01 PHY_LPBK_CONTROL_3:RW:8:9:=0x0000 PHY_LP4_BOOT_RDDATA_EN_OE_DLY_3:RW:0:5:=0x01
-`define              DENALI_PHY_777_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_CONTROL_3:RW:0:32:=0x00000000
-`define              DENALI_PHY_778_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AUTO_TIMING_MARGIN_OBS_3:RD:0:28:=0x00000000
-`define              DENALI_PHY_779_DATA 32'b00000001_00000000_00000000_00000001 // PHY_PRBS_PATTERN_START_3:RW_D:24:7:=0x01 PHY_DDR4_DQ_IDLE_3:RW:8:9:=0x0000 PHY_PDA_MODE_EN_3:RW:0:1:=0x01
-`define              DENALI_PHY_780_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_MULTI_PATT_RST_DISABLE_3:RW:24:1:=0x00 PHY_RDLVL_MULTI_PATT_ENABLE_3:RW:16:1:=0x00 PHY_PRBS_PATTERN_MASK_3:RW:0:9:=0x0000
-`define              DENALI_PHY_781_DATA 32'b00000000_11000000_00000000_00000100 // PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_3:RW:16:10:=0x00c0 PHY_VREF_TRAIN_OBS_3:RD:8:6:=0x00 PHY_VREF_INITIAL_STEPSIZE_3:RW:0:5:=0x04
-`define              DENALI_PHY_782_DATA 32'b00000000_11001100_00000000_00001000 // PHY_GATE_SMPL1_SLAVE_DELAY_3:RW:16:9:=0x00cc SC_PHY_SNAP_OBS_REGS_3:WR:8:1:=0x00 PHY_GATE_ERROR_DELAY_SELECT_3:RW:0:4:=0x08
-`define              DENALI_PHY_783_DATA 32'b00000000_01100110_00000110_00000001 // PHY_GATE_SMPL2_SLAVE_DELAY_3:RW:16:9:=0x0066 PHY_MEM_CLASS_3:RW:8:3:=0x06 PHY_LPDDR_3:RW:0:1:=0x01
-`define              DENALI_PHY_784_DATA 32'b00000000_00000000_00000000_00000011 // ON_FLY_GATE_ADJUST_EN_3:RW:0:2:=0x03
-`define              DENALI_PHY_785_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_TRACKING_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_786_DATA 32'b00000000_00000000_00000000_00000001 // PHY_LP4_PST_AMBLE_3:RW:8:2:=0x00 PHY_DFI40_POLARITY_3:RW:0:1:=0x01
-`define              DENALI_PHY_787_DATA 32'b00000000_00000000_10101010_10101010 // PHY_RDLVL_PATT8_3:RW:0:32:=0x0000AAAA
-`define              DENALI_PHY_788_DATA 32'b00000000_00000000_01010101_01010101 // PHY_RDLVL_PATT9_3:RW:0:32:=0x00005555
-`define              DENALI_PHY_789_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT10_3:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_790_DATA 32'b00000000_00000000_01001010_01001010 // PHY_RDLVL_PATT11_3:RW:0:32:=0x00004A4A
-`define              DENALI_PHY_791_DATA 32'b00000000_00000000_01010110_01010110 // PHY_RDLVL_PATT12_3:RW:0:32:=0x00005656
-`define              DENALI_PHY_792_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT13_3:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_793_DATA 32'b00000000_00000000_10101001_10101001 // PHY_RDLVL_PATT14_3:RW:0:32:=0x0000A9A9
-`define              DENALI_PHY_794_DATA 32'b00000000_00000000_10110101_10110101 // PHY_RDLVL_PATT15_3:RW:0:32:=0x0000B5B5
-`define              DENALI_PHY_795_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ_ENC_OBS_SELECT_3:RW:24:3:=0x00 PHY_MASTER_DLY_LOCK_OBS_SELECT_3:RW:16:4:=0x00 PHY_SW_FIFO_PTR_RST_DISABLE_3:RW:8:1:=0x00 PHY_SLAVE_LOOP_CNT_UPDATE_3:RW:0:3:=0x00
-`define              DENALI_PHY_796_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_SELECT_3:RW:24:4:=0x00 PHY_WR_SHIFT_OBS_SELECT_3:RW:16:4:=0x00 PHY_WR_ENC_OBS_SELECT_3:RW:8:4:=0x00 PHY_RDDQS_DQ_ENC_OBS_SELECT_3:RW:0:4:=0x00
-`define              DENALI_PHY_797_DATA 32'b00001000_00000000_00000000_00000000 // PHY_WRLVL_CAPTURE_CNT_3:RW:24:6:=0x08 PHY_WRLVL_ALGO_3:RW:16:2:=0x00 SC_PHY_LVL_DEBUG_CONT_3:WR:8:1:=0x00 PHY_LVL_DEBUG_MODE_3:RW:0:1:=0x00
-`define              DENALI_PHY_798_DATA 32'b00000100_00000000_00000000_00001000 // PHY_GTLVL_UPDT_WAIT_CNT_3:RW:24:4:=0x04 PHY_GTLVL_CAPTURE_CNT_3:RW:16:6:=0x00 PHY_DQ_MASK_3:RW:8:8:=0x00 PHY_WRLVL_UPDT_WAIT_CNT_3:RW:0:4:=0x08
-`define              DENALI_PHY_799_DATA 32'b00000000_00000000_00000100_00001000 // PHY_RDLVL_RDDQS_DQ_OBS_SELECT_3:RW:24:5:=0x00 PHY_RDLVL_OP_MODE_3:RW:16:2:=0x00 PHY_RDLVL_UPDT_WAIT_CNT_3:RW:8:4:=0x04 PHY_RDLVL_CAPTURE_CNT_3:RW:0:6:=0x08
-`define              DENALI_PHY_800_DATA 32'b00000000_11100100_11100100_00000000 // PHY_RDLVL_DATA_SWIZZLE_3:RW:8:18:=0x00e4e4 PHY_RDLVL_DATA_MASK_3:RW:0:8:=0x00
-`define              DENALI_PHY_801_DATA 32'b00000000_00000111_00010000_00100000 // PHY_WDQLVL_PATT_3:RW:16:3:=0x07 PHY_WDQLVL_BURST_CNT_3:RW:8:6:=0x10 PHY_WDQLVL_CLK_JITTER_TOLERANCE_3:RW:0:8:=0x20
-`define              DENALI_PHY_802_DATA 32'b00000000_00001100_00000000_00100000 // PHY_WDQLVL_DQDM_OBS_SELECT_3:RW:24:4:=0x00 PHY_WDQLVL_UPDT_WAIT_CNT_3:RW:16:4:=0x0c PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_3:RW:0:11:=0x0020
-`define              DENALI_PHY_803_DATA 32'b00000000_00000000_00000110_00100000 // SC_PHY_WDQLVL_CLR_PREV_RESULTS_3:WR:16:1:=0x00 PHY_WDQLVL_DM_DLY_STEP_3:RW:8:4:=0x06 PHY_WDQLVL_DQ_SLV_DELTA_3:RW:0:8:=0x20
-`define              DENALI_PHY_804_DATA 32'b00000000_00000000_00000001_00000000 // PHY_WDQLVL_DATADM_MASK_3:RW:0:9:=0x0100
-`define              DENALI_PHY_805_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT0_3:RW:0:32:=0x55555555
-`define              DENALI_PHY_806_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT1_3:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_807_DATA 32'b01010101_01010101_01010101_01010101 // PHY_USER_PATT2_3:RW:0:32:=0x55555555
-`define              DENALI_PHY_808_DATA 32'b10101010_10101010_10101010_10101010 // PHY_USER_PATT3_3:RW:0:32:=0xAAAAAAAA
-`define              DENALI_PHY_809_DATA 32'b00000000_00000000_01010101_01010101 // PHY_NTP_MULT_TRAIN_3:RW:16:1:=0x00 PHY_USER_PATT4_3:RW:0:16:=0x5555
-`define              DENALI_PHY_810_DATA 32'b00000001_00000000_00000001_00000000 // PHY_NTP_PERIOD_THRESHOLD_3:RW:16:10:=0x0100 PHY_NTP_EARLY_THRESHOLD_3:RW:0:10:=0x0100
-`define              DENALI_PHY_811_DATA 32'b00000000_10000000_00000001_10000000 // PHY_NTP_PERIOD_THRESHOLD_MAX_3:RW:16:10:=0x0080 PHY_NTP_PERIOD_THRESHOLD_MIN_3:RW:0:10:=0x0180
-`define              DENALI_PHY_812_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FIFO_PTR_OBS_3:RD:16:8:=0x00 SC_PHY_MANUAL_CLEAR_3:WR:8:6:=0x00 PHY_CALVL_VREF_DRIVING_SLICE_3:RW:0:1:=0x00
-`define              DENALI_PHY_813_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LPBK_RESULT_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_814_DATA 32'b00000000_00000000_00000000_00000000 // PHY_MASTER_DLY_LOCK_OBS_3:RD:16:11:=0x0000 PHY_LPBK_ERROR_COUNT_OBS_3:RD:0:16:=0x0000
-`define              DENALI_PHY_815_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_3:RD:16:8:=0x00 PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_3:RD:8:7:=0x00 PHY_RDDQ_SLV_DLY_ENC_OBS_3:RD:0:7:=0x00
-`define              DENALI_PHY_816_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_3:RD:24:8:=0x00 PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_3:RD:16:7:=0x00 PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_817_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD0_DELAY_OBS_3:RD:16:10:=0x0000 PHY_WR_SHIFT_OBS_3:RD:8:3:=0x00 PHY_WR_ADDER_SLV_DLY_ENC_OBS_3:RD:0:8:=0x00
-`define              DENALI_PHY_818_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_HARD1_DELAY_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_819_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_STATUS_OBS_3:RD:0:17:=0x000000
-`define              DENALI_PHY_820_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_3:RD:16:10:=0x0000 PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_821_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD0_DELAY_OBS_3:RD:16:14:=0x0000 PHY_WRLVL_ERROR_OBS_3:RD:0:16:=0x0000
-`define              DENALI_PHY_822_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_HARD1_DELAY_OBS_3:RD:0:14:=0x0000
-`define              DENALI_PHY_823_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GTLVL_STATUS_OBS_3:RD:0:18:=0x000000
-`define              DENALI_PHY_824_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_3:RD:16:10:=0x0000 PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_3:RD:0:10:=0x0000
-`define              DENALI_PHY_825_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_3:RD:0:2:=0x00
-`define              DENALI_PHY_826_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_STATUS_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_827_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_DQDM_TE_DLY_OBS_3:RD:16:11:=0x0000 PHY_WDQLVL_DQDM_LE_DLY_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_828_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WDQLVL_STATUS_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_829_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MODE_3:RW:0:31:=0x00000000
-`define              DENALI_PHY_830_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_MASK_3:RW:0:6:=0x00
-`define              DENALI_PHY_831_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_OBS_3:RD:0:32:=0x00000000
-`define              DENALI_PHY_832_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_TEST_MSTR_DLY_OBS_3:RD:0:32:=0x00000000
-//`define              DENALI_PHY_833_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RX_CAL_OVERRIDE_3:RW:24:1:=0x00 SC_PHY_RX_CAL_START_3:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_3:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_3:RW:0:8:=0x04
-`define              DENALI_PHY_833_DATA 32'b00000000_00000000_00000001_00000100 // PHY_RX_CAL_OVERRIDE_3:RW:24:1:=0x00 SC_PHY_RX_CAL_START_3:WR:16:1:=0x00 PHY_LP4_WDQS_OE_EXTEND_3:RW:8:1:=0x00 PHY_DDL_TRACK_UPD_THRESHOLD_3:RW:0:8:=0x04
-`define              DENALI_PHY_834_DATA 32'b00000000_00000000_00000000_00100000 // PHY_RX_CAL_DQ2_3:RW+:24:6:=0x00 PHY_RX_CAL_DQ1_3:RW+:16:6:=0x00 PHY_RX_CAL_DQ0_3:RW+:8:6:=0x00 PHY_RX_CAL_SAMPLE_WAIT_3:RW:0:8:=0x20
-`define              DENALI_PHY_835_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_DQ6_3:RW+:24:6:=0x00 PHY_RX_CAL_DQ5_3:RW+:16:6:=0x00 PHY_RX_CAL_DQ4_3:RW+:8:6:=0x00 PHY_RX_CAL_DQ3_3:RW+:0:6:=0x00
-`define              DENALI_PHY_836_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_FDBK_3:RW+:24:6:=0x00 PHY_RX_CAL_DQS_3:RW+:16:6:=0x00 PHY_RX_CAL_DM_3:RW+:8:6:=0x00 PHY_RX_CAL_DQ7_3:RW+:0:6:=0x00
-`define              DENALI_PHY_837_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_LOCK_OBS_3:RD:16:9:=0x0000 PHY_RX_CAL_OBS_3:RD:0:11:=0x0000
-`define              DENALI_PHY_838_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RX_CAL_COMP_VAL_3:RW:24:1:=0x00 PHY_RX_CAL_DIFF_ADJUST_3:RW:16:4:=0x00 PHY_RX_CAL_SE_ADJUST_3:RW:8:4:=0x00 PHY_RX_CAL_DISABLE_3:RW:0:1:=0x00
-`define              DENALI_PHY_839_DATA 32'b00000111_11111111_00000000_00000000 // PHY_PAD_RX_BIAS_EN_3:RW:16:11:=0x07ff PHY_RX_CAL_INDEX_MASK_3:RW:0:12:=0x0000
-`define              DENALI_PHY_840_DATA 32'b00100000_00000000_10000000_00001000 // PHY_DATA_DC_ADJUST_START_3:RW:24:6:=0x20 PHY_DATA_DC_WEIGHT_3:RW:16:2:=0x00 PHY_DATA_DC_CAL_TIMEOUT_3:RW:8:8:=0x80 PHY_DATA_DC_CAL_SAMPLE_WAIT_3:RW:0:8:=0x08
-`define              DENALI_PHY_841_DATA 32'b00000000_00000000_00001000_00010000 // PHY_DATA_DC_CAL_POLARITY_3:RW:24:1:=0x00 PHY_DATA_DC_ADJUST_DIRECT_3:RW:16:1:=0x00 PHY_DATA_DC_ADJUST_THRSHLD_3:RW:8:8:=0x08 PHY_DATA_DC_ADJUST_SAMPLE_CNT_3:RW:0:8:=0x10
-`define              DENALI_PHY_842_DATA 32'b00000000_00000100_00000001_00000000 // PHY_SLV_DLY_CTRL_GATE_DISABLE_3:RW_D:24:1:=0x00 PHY_FDBK_PWR_CTRL_3:RW:16:3:=0x04 PHY_DATA_DC_SW_RANK_3:RW+:8:2:=0x01 PHY_DATA_DC_CAL_START_3:RW+:0:1:=0x00
-`define              DENALI_PHY_843_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SLICE_PWR_RDC_DISABLE_3:RW:16:1:=0x00 PHY_DCC_RXCAL_CTRL_GATE_DISABLE_3:RW_D:8:1:=0x00 PHY_RDPATH_GATE_DISABLE_3:RW_D:0:1:=0x00
-`define              DENALI_PHY_844_DATA 32'b00000001_10001000_00001100_00000001 // PHY_DQS_TSEL_ENABLE_3:RW+:24:3:=0x01 PHY_DQ_TSEL_SELECT_3:RW+:8:16:=0x880c PHY_DQ_TSEL_ENABLE_3:RW+:0:3:=0x01
-`define              DENALI_PHY_845_DATA 32'b00100000_00000011_10001000_00001100 // PHY_VREF_INITIAL_START_POINT_3:RW+:24:6:=0x20 PHY_TWO_CYC_PREAMBLE_3:RW+:16:2:=0x03 PHY_DQS_TSEL_SELECT_3:RW+:0:16:=0x880c
-`define              DENALI_PHY_846_DATA 32'b00100000_00000000_00000001_00100101 // PHY_NTP_WDQ_STEP_SIZE_3:RW+:24:8:=0x20 PHY_NTP_TRAIN_EN_3:RW+:16:1:=0x00 PHY_VREF_TRAINING_CTRL_3:RW+:8:2:=0x01 PHY_VREF_INITIAL_STOP_POINT_3:RW+:0:6:=0x25
-`define              DENALI_PHY_847_DATA 32'b00000111_11111111_00000010_00000000 // PHY_NTP_WDQ_STOP_3:RW+:16:11:=0x07FF PHY_NTP_WDQ_START_3:RW+:0:11:=0x0200
-`define              DENALI_PHY_848_DATA 32'b00000000_00000000_00000001_00000001 // PHY_PAD_RX_DCD_0_3:RW+:24:5:=0x00 PHY_PAD_TX_DCD_3:RW+:16:5:=0x00 PHY_FAST_LVL_EN_3:RW+:8:4:=0x01 PHY_NTP_WDQ_BIT_EN_3:RW+:0:8:=0x01
-`define              DENALI_PHY_849_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_RX_DCD_4_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_3_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_2_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_1_3:RW+:0:5:=0x00
-`define              DENALI_PHY_850_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DM_RX_DCD_3:RW+:24:5:=0x00 PHY_PAD_RX_DCD_7_3:RW+:16:5:=0x00 PHY_PAD_RX_DCD_6_3:RW+:8:5:=0x00 PHY_PAD_RX_DCD_5_3:RW+:0:5:=0x00
-`define              DENALI_PHY_851_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_DSLICE_IO_CFG_3:RW+:16:6:=0x00 PHY_PAD_FDBK_RX_DCD_3:RW+:8:5:=0x00 PHY_PAD_DQS_RX_DCD_3:RW+:0:5:=0x00
-`define              DENALI_PHY_852_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ1_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ0_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_853_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ3_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ2_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_854_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ5_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ4_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_855_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDDQ7_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_RDDQ6_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_856_DATA 32'b00000000_00000010_00000000_00000000 // PHY_DATA_DC_CAL_CLK_SEL_3:RW+:16:3:=0x02 PHY_RDDM_SLAVE_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_857_DATA 32'b01010001_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x52
-//`define              DENALI_PHY_857_DATA 32'b11111111_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x52
-//`define              DENALI_PHY_857_DATA 32'b00000000_01010001_01010000_01010010 // PHY_DQS_OE_TIMING_3:RW+:24:8:=0x51 PHY_DQ_TSEL_WR_TIMING_3:RW+:16:8:=0x51 PHY_DQ_TSEL_RD_TIMING_3:RW+:8:8:=0x50 PHY_DQ_OE_TIMING_3:RW+:0:8:=0x52
-`define              DENALI_PHY_858_DATA 32'b00110001_11000000_01100000_00000000 // PHY_DQS_TSEL_WR_TIMING_3:RW+:24:8:=0x31 PHY_DQS_OE_RD_TIMING_3:RW+:16:8:=0xc0 PHY_DQS_TSEL_RD_TIMING_3:RW+:8:8:=0x60 PHY_IO_PAD_DELAY_TIMING_3:RW+:0:4:=0x00
-`define              DENALI_PHY_859_DATA 32'b00000001_00011111_00000000_00000100 // PHY_PAD_VREF_CTRL_DQ_3:RW+:16:10:=0x011f PHY_VREF_SETTING_TIME_3:RW+:0:16:=0x0004
-`define              DENALI_PHY_860_DATA 32'b00000000_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_3:RW+:24:2:=0x00 PHY_DQS_IE_TIMING_3:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_3:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:0:1:=0x01
-//`define              DENALI_PHY_860_DATA 32'b00000010_11000000_11000000_00000001 // PHY_RDDATA_EN_IE_DLY_3:RW+:24:2:=0x02 PHY_DQS_IE_TIMING_3:RW+:16:8:=0xc0 PHY_DQ_IE_TIMING_3:RW+:8:8:=0xc0 PHY_PER_CS_TRAINING_EN_3:RW+:0:1:=0x01
-`define              DENALI_PHY_861_DATA 32'b00000100_00000000_00000000_00000000 // PHY_WDQLVL_RDDATA_EN_DLY_3:RW+:24:5:=0x04 PHY_WDQLVL_IE_ON_3:RW+:16:1:=0x00 PHY_DBI_MODE_3:RW+:8:2:=0x00 PHY_IE_MODE_3:RW+:0:2:=0x00
-`define              DENALI_PHY_862_DATA 32'b00000000_00000100_00000011_00000011 // PHY_SW_MASTER_MODE_3:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_3:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_3:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3:RW+:0:5:=0x03
-//`define              DENALI_PHY_862_DATA 32'b00000000_00000000_00000011_00000011 // PHY_SW_MASTER_MODE_3:RW+:24:4:=0x00 PHY_RDDATA_EN_OE_DLY_3:RW+:16:5:=0x04 PHY_RDDATA_EN_TSEL_DLY_3:RW+:8:5:=0x03 PHY_WDQLVL_RDDATA_EN_TSEL_DLY_3:RW+:0:5:=0x03
-`define              DENALI_PHY_863_DATA 32'b01000010_00010000_00000000_00010000 // PHY_MASTER_DELAY_WAIT_3:RW+:24:8:=0x42 PHY_MASTER_DELAY_STEP_3:RW+:16:6:=0x10 PHY_MASTER_DELAY_START_3:RW+:0:11:=0x0010
-`define              DENALI_PHY_864_DATA 32'b00000001_00001100_00000101_00111110 // PHY_WRLVL_DLY_FINE_STEP_3:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_3:RW+:16:8:=0x0c PHY_RPTR_UPDATE_3:RW+:8:4:=0x05 PHY_MASTER_DELAY_HALF_MEASURE_3:RW+:0:8:=0x3e
-//`define              DENALI_PHY_864_DATA 32'b00000001_00001100_00001001_00111110 // PHY_WRLVL_DLY_FINE_STEP_3:RW+:24:4:=0x01 PHY_WRLVL_DLY_STEP_3:RW+:16:8:=0x0c PHY_RPTR_UPDATE_3:RW+:8:4:=0x09 PHY_MASTER_DELAY_HALF_MEASURE_3:RW+:0:8:=0x3e
-`define              DENALI_PHY_865_DATA 32'b00000000_00001111_00001100_00101011 // PHY_GTLVL_RESP_WAIT_CNT_3:RW+:16:5:=0x0f PHY_GTLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_WRLVL_RESP_WAIT_CNT_3:RW+:0:6:=0x2b
-`define              DENALI_PHY_866_DATA 32'b00000001_00000000_00000001_01000000 // PHY_GTLVL_FINAL_STEP_3:RW+:16:10:=0x0100 PHY_GTLVL_BACK_STEP_3:RW+:0:10:=0x0140
-`define              DENALI_PHY_867_DATA 32'b00000000_11110101_00000001_00100000 // PHY_WDQLVL_DM_SEARCH_RANGE_3:RW+:16:9:=0x00f5 PHY_WDQLVL_QTR_DLY_STEP_3:RW+:8:4:=0x01 PHY_WDQLVL_DLY_STEP_3:RW+:0:8:=0x20
-`define              DENALI_PHY_868_DATA 32'b00000000_00000000_00001100_00000000 // PHY_RDLVL_DLY_STEP_3:RW+:8:4:=0x0c PHY_TOGGLE_PRE_SUPPORT_3:RW+:0:1:=0x00
-`define              DENALI_PHY_869_DATA 32'b00000000_00000000_00000010_10011001 // PHY_RDLVL_MAX_EDGE_3:RW+:0:10:=0x0299
-`define              DENALI_PHY_870_DATA 32'b00000000_00000000_00000010_00000000 // PHY_DATA_DC_INIT_DISABLE_3:RW+:16:2:=0x00 PHY_WRPATH_GATE_TIMING_3:RW+:8:3:=0x02 PHY_WRPATH_GATE_DISABLE_3:RW+:0:2:=0x00
-`define              DENALI_PHY_871_DATA 32'b00000010_10000000_00000000_00000000 // PHY_DATA_DC_DQ_INIT_SLV_DELAY_3:RW+:16:11:=0x0280 PHY_DATA_DC_DQS_INIT_SLV_DELAY_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_872_DATA 32'b10000000_10000000_00000001_00000001 // PHY_DATA_DC_DM_CLK_DIFF_THRSHLD_3:RW+:24:8:=0x80 PHY_DATA_DC_DM_CLK_SE_THRSHLD_3:RW+:16:8:=0x80 PHY_DATA_DC_WDQLVL_ENABLE_3:RW+:8:1:=0x01 PHY_DATA_DC_WRLVL_ENABLE_3:RW+:0:1:=0x01
-//`define              DENALI_PHY_873_DATA 32'b00000000_00000000_00000000_00000100 // PHY_RDDATA_EN_DLY_3:RW+:0:5:=0x04
-`define              DENALI_PHY_873_DATA 32'b00000000_00000000_00000000_00000110 // PHY_RDDATA_EN_DLY_3:RW+:0:5:=0x06/0x07 is ok when tDQSCK=3.5
-`define              DENALI_PHY_874_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DQ_DM_SWIZZLE0_3:RW+:0:32:=0x76543210
-`define              DENALI_PHY_875_DATA 32'b00000000_00000000_00000000_00001000 // PHY_DQ_DM_SWIZZLE1_3:RW+:0:4:=0x08
-`define              DENALI_PHY_876_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ1_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ0_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_877_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ3_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ2_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_878_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ5_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ4_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_879_DATA 32'b00000100_10000000_00000100_10000000 // PHY_CLK_WRDQ7_SLAVE_DELAY_3:RW+:16:11:=0x0280 PHY_CLK_WRDQ6_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_880_DATA 32'b00000000_00000000_00000100_10000000 // PHY_CLK_WRDQS_SLAVE_DELAY_3:RW+:16:10:=0x0000 PHY_CLK_WRDM_SLAVE_DELAY_3:RW+:0:11:=0x0280
-`define              DENALI_PHY_881_DATA 32'b00000000_00000000_10100000_00000000 // PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_3:RW+:8:10:=0x00a0 PHY_WRLVL_THRESHOLD_ADJUST_3:RW+:0:2:=0x00
-`define              DENALI_PHY_882_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_883_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_884_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_885_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_886_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_887_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_888_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_889_DATA 32'b00000000_10100000_00000000_10100000 // PHY_RDDQS_DM_RISE_SLAVE_DELAY_3:RW+:16:10:=0x00a0 PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_890_DATA 32'b00000001_00011001_00000000_10100000 // PHY_RDDQS_GATE_SLAVE_DELAY_3:RW+:16:10:=0x0119 PHY_RDDQS_DM_FALL_SLAVE_DELAY_3:RW+:0:10:=0x00a0
-`define              DENALI_PHY_891_DATA 32'b00000001_10100000_00000000_00000100 // PHY_WRLVL_DELAY_EARLY_THRESHOLD_3:RW+:16:10:=0x01A0 PHY_WRITE_PATH_LAT_ADD_3:RW+:8:3:=0x00 PHY_RDDQS_LATENCY_ADJUST_3:RW+:0:4:=0x04
-`define              DENALI_PHY_892_DATA 32'b00000000_00000000_00000000_00000000 // PHY_WRLVL_EARLY_FORCE_ZERO_3:RW+:16:1:=0x00 PHY_WRLVL_DELAY_PERIOD_THRESHOLD_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_893_DATA 32'b00000000_00000100_00000000_00000000 // PHY_GTLVL_LAT_ADJ_START_3:RW+:16:4:=0x04 PHY_GTLVL_RDDQS_SLV_DLY_START_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_894_DATA 32'b00000000_00001000_00000010_00000000 // PHY_NTP_PASS_3:RW+:24:1:=0x00 PHY_NTP_WRLAT_START_3:RW+:16:4:=0x08 PHY_WDQLVL_DQDM_SLV_DLY_START_3:RW+:0:11:=0x0200
-`define              DENALI_PHY_895_DATA 32'b00000000_00000000_00000000_00000000 // PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_3:RW+:0:10:=0x0000
-`define              DENALI_PHY_896_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ2_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ1_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ0_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQS_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_897_DATA 32'b00100000_00100000_00100000_00100000 // PHY_DATA_DC_DQ6_CLK_ADJUST_3:RW+:24:8:=0x20 PHY_DATA_DC_DQ5_CLK_ADJUST_3:RW+:16:8:=0x20 PHY_DATA_DC_DQ4_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ3_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_898_DATA 32'b00000000_00000000_00100000_00100000 // PHY_DSLICE_PAD_BOOSTPN_SETTING_3:RW+:16:16:=0x0000 PHY_DATA_DC_DM_CLK_ADJUST_3:RW+:8:8:=0x20 PHY_DATA_DC_DQ7_CLK_ADJUST_3:RW+:0:8:=0x20
-`define              DENALI_PHY_899_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DSLICE_PAD_RX_CTLE_SETTING_3:RW+:0:4:=0x00
-`define              DENALI_PHY_900_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_901_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_902_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_903_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_904_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_905_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_906_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_907_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_908_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_909_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_910_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_911_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_912_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_913_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_914_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_915_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_916_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_917_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_918_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_919_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_920_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_921_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_922_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_923_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_924_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_925_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_926_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_927_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_928_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_929_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_930_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_931_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_932_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_933_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_934_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_935_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_936_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_937_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_938_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_939_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_940_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_941_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_942_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_943_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_944_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_945_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_946_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_947_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_948_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_949_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_950_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_951_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_952_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_953_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_954_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_955_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_956_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_957_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_958_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_959_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_960_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_961_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_962_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_963_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_964_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_965_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_966_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_967_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_968_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_969_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_970_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_971_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_972_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_973_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_974_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_975_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_976_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_977_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_978_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_979_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_980_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_981_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_982_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_983_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_984_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_985_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_986_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_987_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_988_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_989_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_990_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_991_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_992_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_993_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_994_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_995_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_996_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_997_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_998_DATA 32'b00000000_00000000_00000000_00000000 //
-`define              DENALI_PHY_999_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1000_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1001_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1002_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1003_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1004_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1005_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1006_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1007_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1008_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1009_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1010_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1011_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1012_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1013_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1014_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1015_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1016_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1017_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1018_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1019_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1020_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1021_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1022_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1023_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1024_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_0:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_0:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0:RW:0:11:=0x0000
-`define             DENALI_PHY_1025_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1026_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_0:RD:0:16:=0x0000
-`define             DENALI_PHY_1027_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_0:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_0:RD:0:11:=0x0000
-`define             DENALI_PHY_1028_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_0:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_0:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0:RW:0:3:=0x00
-`define             DENALI_PHY_1029_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_0:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_0:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_0:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_0:RW:0:7:=0x00
-`define             DENALI_PHY_1030_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_0:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_0:RD:16:3:=0x00 PHY_ADR_TYPE_0:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0:RW_D:0:1:=0x00
-`define             DENALI_PHY_1031_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_0:RW:0:27:=0x00000000
-`define             DENALI_PHY_1032_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_0:RW:0:6:=0x00
-`define             DENALI_PHY_1033_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1034_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1035_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_0:RW:16:11:=0x0040 PHY_ADR_CALVL_START_0:RW:0:11:=0x0000
-`define             DENALI_PHY_1036_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_0:RW:0:11:=0x0080
-`define             DENALI_PHY_1037_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_0:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1038_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_0:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_0:RW:0:24:=0x000000
-`define             DENALI_PHY_1039_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_0:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_0:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_0:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_0:RW:0:2:=0x00
-`define             DENALI_PHY_1040_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_0:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_0:WR:0:1:=0x00
-`define             DENALI_PHY_1041_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1042_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1043_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1044_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1045_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1046_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_0:RW:0:20:=0x00002a
-`define             DENALI_PHY_1047_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_0:RW:0:20:=0x000015
-`define             DENALI_PHY_1048_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_0:RW:0:20:=0x000015
-`define             DENALI_PHY_1049_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_0:RW:0:20:=0x00002a
-`define             DENALI_PHY_1050_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_0:RW:0:20:=0x000033
-`define             DENALI_PHY_1051_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_0:RW:0:20:=0x00000c
-`define             DENALI_PHY_1052_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_0:RW:0:20:=0x00000c
-`define             DENALI_PHY_1053_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_0:RW:0:20:=0x000033
-`define             DENALI_PHY_1054_DATA 32'b00001010_01000001_10001000_00100000 // PHY_ADR_ADDR_SEL_0:RW:0:30:=0x0a418820
-`define             DENALI_PHY_1055_DATA 32'b00000000_00111111_00000000_00000000 // PHY_ADR_SEG_MASK_0:RW:24:6:=0x00 PHY_ADR_BIT_MASK_0:RW:16:6:=0x3f PHY_ADR_LP4_BOOT_SLV_DELAY_0:RW:0:10:=0x0000
-`define             DENALI_PHY_1056_DATA 32'b00000000_00000000_00000001_00111111 // PHY_ADR_SW_TXIO_CTRL_0:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_0:RW:8:6:=0x01 PHY_ADR_CALVL_TRAIN_MASK_0:RW:0:6:=0x3f
-`define             DENALI_PHY_1057_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_0:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_0:RW+:0:2:=0x00
-`define             DENALI_PHY_1058_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_0:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_0:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_0:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_0:RW+:0:8:=0x20
-`define             DENALI_PHY_1059_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_0:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_0:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_0:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define             DENALI_PHY_1060_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_0:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_0:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_0:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_0:RW:0:8:=0x10
-`define             DENALI_PHY_1061_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_0:RW+:0:1:=0x00
-`define             DENALI_PHY_1062_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_0:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_0:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_0:RW+:0:8:=0x55
-`define             DENALI_PHY_1063_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_0:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_0:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_0:RW+:0:5:=0x00
-`define             DENALI_PHY_1064_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1065_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1066_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1067_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_0:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1068_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_0:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1069_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_0:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_0:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_0:RW+:0:11:=0x0010
-`define             DENALI_PHY_1070_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_0:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_0:RW+:0:8:=0x3e
-`define             DENALI_PHY_1071_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_0:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_0:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_0:RW+:0:4:=0x02
-`define             DENALI_PHY_1072_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_0:RW+:0:8:=0x80
-`define             DENALI_PHY_1073_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1074_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1075_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1076_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1077_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1078_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1079_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1080_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1081_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1082_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1083_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1084_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1085_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1086_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1087_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1088_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1089_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1090_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1091_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1092_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1093_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1094_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1095_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1096_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1097_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1098_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1099_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1100_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1101_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1102_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1103_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1104_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1105_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1106_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1107_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1108_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1109_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1110_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1111_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1112_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1113_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1114_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1115_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1116_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1117_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1118_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1119_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1120_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1121_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1122_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1123_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1124_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1125_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1126_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1127_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1128_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1129_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1130_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1131_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1132_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1133_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1134_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1135_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1136_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1137_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1138_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1139_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1140_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1141_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1142_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1143_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1144_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1145_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1146_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1147_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1148_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1149_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1150_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1151_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1152_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1153_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1154_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1155_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1156_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1157_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1158_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1159_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1160_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1161_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1162_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1163_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1164_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1165_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1166_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1167_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1168_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1169_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1170_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1171_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1172_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1173_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1174_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1175_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1176_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1177_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1178_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1179_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1180_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1181_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1182_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1183_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1184_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1185_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1186_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1187_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1188_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1189_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1190_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1191_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1192_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1193_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1194_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1195_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1196_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1197_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1198_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1199_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1200_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1201_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1202_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1203_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1204_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1205_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1206_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1207_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1208_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1209_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1210_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1211_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1212_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1213_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1214_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1215_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1216_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1217_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1218_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1219_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1220_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1221_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1222_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1223_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1224_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1225_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1226_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1227_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1228_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1229_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1230_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1231_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1232_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1233_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1234_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1235_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1236_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1237_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1238_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1239_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1240_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1241_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1242_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1243_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1244_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1245_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1246_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1247_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1248_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1249_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1250_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1251_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1252_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1253_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1254_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1255_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1256_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1257_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1258_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1259_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1260_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1261_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1262_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1263_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1264_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1265_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1266_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1267_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1268_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1269_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1270_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1271_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1272_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1273_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1274_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1275_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1276_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1277_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1278_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1279_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1280_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_1:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_1:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1:RW:0:11:=0x0000
-`define             DENALI_PHY_1281_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1282_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_1:RD:0:16:=0x0000
-`define             DENALI_PHY_1283_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_1:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_1:RD:0:11:=0x0000
-`define             DENALI_PHY_1284_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_1:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_1:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1:RW:0:3:=0x00
-`define             DENALI_PHY_1285_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_1:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_1:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_1:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_1:RW:0:7:=0x00
-`define             DENALI_PHY_1286_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_1:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_1:RD:16:3:=0x00 PHY_ADR_TYPE_1:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1:RW_D:0:1:=0x00
-`define             DENALI_PHY_1287_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_1:RW:0:27:=0x00000000
-`define             DENALI_PHY_1288_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_1:RW:0:6:=0x00
-`define             DENALI_PHY_1289_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1290_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1291_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_1:RW:16:11:=0x0040 PHY_ADR_CALVL_START_1:RW:0:11:=0x0000
-`define             DENALI_PHY_1292_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_1:RW:0:11:=0x0080
-`define             DENALI_PHY_1293_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_1:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1294_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_1:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_1:RW:0:24:=0x000000
-`define             DENALI_PHY_1295_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_1:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_1:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_1:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_1:RW:0:2:=0x00
-`define             DENALI_PHY_1296_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_1:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_1:WR:0:1:=0x00
-`define             DENALI_PHY_1297_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1298_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1299_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1300_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1301_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1302_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_1:RW:0:20:=0x00002a
-`define             DENALI_PHY_1303_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_1:RW:0:20:=0x000015
-`define             DENALI_PHY_1304_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_1:RW:0:20:=0x000015
-`define             DENALI_PHY_1305_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_1:RW:0:20:=0x00002a
-`define             DENALI_PHY_1306_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_1:RW:0:20:=0x000033
-`define             DENALI_PHY_1307_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_1:RW:0:20:=0x00000c
-`define             DENALI_PHY_1308_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_1:RW:0:20:=0x00000c
-`define             DENALI_PHY_1309_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_1:RW:0:20:=0x000033
-`define             DENALI_PHY_1310_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDR_SEL_1:RW:0:30:=0x00000000
-`define             DENALI_PHY_1311_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SEG_MASK_1:RW:24:6:=0x00 PHY_ADR_BIT_MASK_1:RW:16:6:=0x00 PHY_ADR_LP4_BOOT_SLV_DELAY_1:RW:0:10:=0x0000
-`define             DENALI_PHY_1312_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SW_TXIO_CTRL_1:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_1:RW:8:6:=0x00 PHY_ADR_CALVL_TRAIN_MASK_1:RW:0:6:=0x00
-`define             DENALI_PHY_1313_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_1:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_1:RW+:0:2:=0x00
-`define             DENALI_PHY_1314_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_1:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_1:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_1:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_1:RW+:0:8:=0x20
-`define             DENALI_PHY_1315_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_1:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_1:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_1:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_1:RW:0:8:=0x08
-`define             DENALI_PHY_1316_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_1:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_1:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_1:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_1:RW:0:8:=0x10
-`define             DENALI_PHY_1317_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_1:RW+:0:1:=0x00
-`define             DENALI_PHY_1318_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_1:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_1:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_1:RW+:0:8:=0x55
-`define             DENALI_PHY_1319_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_1:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_1:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_1:RW+:0:5:=0x00
-`define             DENALI_PHY_1320_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1321_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1322_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1323_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_1:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1324_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_1:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1325_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_1:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_1:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_1:RW+:0:11:=0x0010
-`define             DENALI_PHY_1326_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_1:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_1:RW+:0:8:=0x3e
-`define             DENALI_PHY_1327_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_1:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_1:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_1:RW+:0:4:=0x02
-`define             DENALI_PHY_1328_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_1:RW+:0:8:=0x80
-`define             DENALI_PHY_1329_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1330_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1331_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1332_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1333_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1334_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1335_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1336_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1337_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1338_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1339_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1340_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1341_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1342_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1343_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1344_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1345_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1346_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1347_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1348_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1349_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1350_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1351_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1352_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1353_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1354_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1355_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1356_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1357_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1358_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1359_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1360_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1361_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1362_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1363_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1364_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1365_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1366_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1367_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1368_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1369_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1370_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1371_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1372_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1373_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1374_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1375_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1376_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1377_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1378_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1379_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1380_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1381_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1382_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1383_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1384_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1385_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1386_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1387_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1388_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1389_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1390_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1391_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1392_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1393_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1394_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1395_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1396_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1397_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1398_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1399_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1400_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1401_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1402_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1403_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1404_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1405_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1406_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1407_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1408_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1409_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1410_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1411_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1412_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1413_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1414_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1415_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1416_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1417_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1418_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1419_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1420_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1421_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1422_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1423_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1424_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1425_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1426_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1427_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1428_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1429_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1430_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1431_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1432_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1433_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1434_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1435_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1436_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1437_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1438_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1439_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1440_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1441_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1442_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1443_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1444_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1445_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1446_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1447_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1448_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1449_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1450_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1451_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1452_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1453_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1454_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1455_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1456_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1457_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1458_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1459_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1460_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1461_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1462_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1463_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1464_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1465_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1466_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1467_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1468_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1469_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1470_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1471_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1472_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1473_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1474_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1475_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1476_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1477_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1478_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1479_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1480_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1481_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1482_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1483_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1484_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1485_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1486_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1487_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1488_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1489_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1490_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1491_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1492_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1493_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1494_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1495_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1496_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1497_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1498_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1499_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1500_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1501_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1502_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1503_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1504_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1505_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1506_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1507_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1508_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1509_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1510_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1511_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1512_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1513_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1514_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1515_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1516_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1517_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1518_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1519_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1520_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1521_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1522_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1523_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1524_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1525_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1526_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1527_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1528_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1529_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1530_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1531_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1532_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1533_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1534_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1535_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1536_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_MANUAL_CLEAR_2:WR:24:3:=0x00 PHY_ADR_CLK_BYPASS_OVERRIDE_2:RW:16:1:=0x00 PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2:RW:0:11:=0x0000
-`define             DENALI_PHY_1537_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_LPBK_RESULT_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1538_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2:RW:16:4:=0x00 PHY_ADR_LPBK_ERROR_COUNT_OBS_2:RD:0:16:=0x0000
-`define             DENALI_PHY_1539_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2:RD:24:8:=0x00 PHY_ADR_BASE_SLV_DLY_ENC_OBS_2:RD:16:7:=0x00 PHY_ADR_MASTER_DLY_LOCK_OBS_2:RD:0:11:=0x0000
-`define             DENALI_PHY_1540_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_TSEL_ENABLE_2:RW:24:1:=0x00 SC_PHY_ADR_SNAP_OBS_REGS_2:WR:16:1:=0x00 PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2:RW:8:3:=0x00 PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2:RW:0:3:=0x00
-`define             DENALI_PHY_1541_DATA 32'b00000000_00000000_00000001_00000000 // PHY_ADR_PWR_RDC_DISABLE_2:RW:24:1:=0x00 PHY_ADR_PRBS_PATTERN_MASK_2:RW:16:5:=0x00 PHY_ADR_PRBS_PATTERN_START_2:RW_D:8:7:=0x01 PHY_ADR_LPBK_CONTROL_2:RW:0:7:=0x00
-`define             DENALI_PHY_1542_DATA 32'b00000000_00000000_00000010_00000000 // PHY_ADR_IE_MODE_2:RW:24:1:=0x00 PHY_ADR_WRADDR_SHIFT_OBS_2:RD:16:3:=0x00 PHY_ADR_TYPE_2:RW:8:2:=0x02 PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2:RW_D:0:1:=0x00
-`define             DENALI_PHY_1543_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MODE_2:RW:0:27:=0x00000000
-`define             DENALI_PHY_1544_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_MASK_2:RW:0:6:=0x00
-`define             DENALI_PHY_1545_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1546_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1547_DATA 32'b00000000_01000000_00000000_00000000 // PHY_ADR_CALVL_COARSE_DLY_2:RW:16:11:=0x0040 PHY_ADR_CALVL_START_2:RW:0:11:=0x0000
-`define             DENALI_PHY_1548_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_CALVL_QTR_2:RW:0:11:=0x0080
-`define             DENALI_PHY_1549_DATA 32'b00000000_11011100_10111010_10011000 // PHY_ADR_CALVL_SWIZZLE0_2:RW:0:24:=0xdcba98
-`define             DENALI_PHY_1550_DATA 32'b00000011_00000000_00000000_00000000 // PHY_ADR_CALVL_RANK_CTRL_2:RW:24:2:=0x03 PHY_ADR_CALVL_SWIZZLE1_2:RW:0:24:=0x000000
-`define             DENALI_PHY_1551_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_ADR_CALVL_DEBUG_CONT_2:WR:24:1:=0x00 PHY_ADR_CALVL_DEBUG_MODE_2:RW:16:1:=0x00 PHY_ADR_CALVL_RESP_WAIT_CNT_2:RW:8:4:=0x00 PHY_ADR_CALVL_NUM_PATTERNS_2:RW:0:2:=0x00
-`define             DENALI_PHY_1552_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS_SELECT_2:RW:8:3:=0x00 SC_PHY_ADR_CALVL_ERROR_CLR_2:WR:0:1:=0x00
-`define             DENALI_PHY_1553_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH0_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1554_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH1_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1555_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH2_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1556_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_CH3_OBS0_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1557_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_CALVL_OBS1_2:RD:0:32:=0x00000000
-`define             DENALI_PHY_1558_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_FG_0_2:RW:0:20:=0x00002a
-`define             DENALI_PHY_1559_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_BG_0_2:RW:0:20:=0x000015
-`define             DENALI_PHY_1560_DATA 32'b00000000_00000000_00000000_00010101 // PHY_ADR_CALVL_FG_1_2:RW:0:20:=0x000015
-`define             DENALI_PHY_1561_DATA 32'b00000000_00000000_00000000_00101010 // PHY_ADR_CALVL_BG_1_2:RW:0:20:=0x00002a
-`define             DENALI_PHY_1562_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_FG_2_2:RW:0:20:=0x000033
-`define             DENALI_PHY_1563_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_BG_2_2:RW:0:20:=0x00000c
-`define             DENALI_PHY_1564_DATA 32'b00000000_00000000_00000000_00001100 // PHY_ADR_CALVL_FG_3_2:RW:0:20:=0x00000c
-`define             DENALI_PHY_1565_DATA 32'b00000000_00000000_00000000_00110011 // PHY_ADR_CALVL_BG_3_2:RW:0:20:=0x000033
-`define             DENALI_PHY_1566_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_ADDR_SEL_2:RW:0:30:=0x00000000
-`define             DENALI_PHY_1567_DATA 32'b00010000_00000000_00000000_00000000 // PHY_ADR_SEG_MASK_2:RW:24:6:=0x10 PHY_ADR_BIT_MASK_2:RW:16:6:=0x00 PHY_ADR_LP4_BOOT_SLV_DELAY_2:RW:0:10:=0x0000
-`define             DENALI_PHY_1568_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_SW_TXIO_CTRL_2:RW:16:6:=0x00 PHY_ADR_CSLVL_TRAIN_MASK_2:RW:8:6:=0x00 PHY_ADR_CALVL_TRAIN_MASK_2:RW:0:6:=0x00
-`define             DENALI_PHY_1569_DATA 32'b00100000_00100000_00100000_00000000 // PHY_ADR_DC_ADR2_CLK_ADJUST_2:RW+:24:8:=0x20 PHY_ADR_DC_ADR1_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_ADR_DC_ADR0_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_ADR_DC_INIT_DISABLE_2:RW+:0:2:=0x00
-`define             DENALI_PHY_1570_DATA 32'b00000000_00100000_00100000_00100000 // PHY_ADR_DCC_RXCAL_CTRL_GATE_DISABLE_2:RW_D:24:1:=0x00 PHY_ADR_DC_ADR5_CLK_ADJUST_2:RW+:16:8:=0x20 PHY_ADR_DC_ADR4_CLK_ADJUST_2:RW+:8:8:=0x20 PHY_ADR_DC_ADR3_CLK_ADJUST_2:RW+:0:8:=0x20
-`define             DENALI_PHY_1571_DATA 32'b00100000_00000000_10000000_00001000 // PHY_ADR_DC_ADJUST_START_2:RW:24:6:=0x20 PHY_ADR_DC_WEIGHT_2:RW:16:2:=0x00 PHY_ADR_DC_CAL_TIMEOUT_2:RW:8:8:=0x80 PHY_ADR_DC_CAL_SAMPLE_WAIT_2:RW:0:8:=0x08
-`define             DENALI_PHY_1572_DATA 32'b00000000_00000000_00001000_00010000 // PHY_ADR_DC_CAL_POLARITY_2:RW:24:1:=0x00 PHY_ADR_DC_ADJUST_DIRECT_2:RW:16:1:=0x00 PHY_ADR_DC_ADJUST_THRSHLD_2:RW:8:8:=0x08 PHY_ADR_DC_ADJUST_SAMPLE_CNT_2:RW:0:8:=0x10
-`define             DENALI_PHY_1573_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADR_DC_CAL_START_2:RW+:0:1:=0x00
-`define             DENALI_PHY_1574_DATA 32'b00000000_00000000_00000010_01010101 // PHY_PAD_ADR_IO_CFG_2:RW+:16:11:=0x0000 PHY_ADR_DC_CAL_CLK_SEL_2:RW+:8:3:=0x02 PHY_ADR_TSEL_SELECT_2:RW+:0:8:=0x55
-`define             DENALI_PHY_1575_DATA 32'b00000000_00000011_00000000_00000000 // PHY_ADR1_SW_WRADDR_SHIFT_2:RW+:24:5:=0x00 PHY_ADR0_CLK_WR_SLAVE_DELAY_2:RW+:8:11:=0x0300 PHY_ADR0_SW_WRADDR_SHIFT_2:RW+:0:5:=0x00
-`define             DENALI_PHY_1576_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR2_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR1_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1577_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR3_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR2_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1578_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR4_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR3_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1579_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR5_SW_WRADDR_SHIFT_2:RW+:16:5:=0x00 PHY_ADR4_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1580_DATA 32'b00000000_00000000_00000011_00000000 // PHY_ADR_SW_MASTER_MODE_2:RW+:16:4:=0x00 PHY_ADR5_CLK_WR_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1581_DATA 32'b01000010_00001000_00000000_00010000 // PHY_ADR_MASTER_DELAY_WAIT_2:RW+:24:8:=0x42 PHY_ADR_MASTER_DELAY_STEP_2:RW+:16:6:=0x08 PHY_ADR_MASTER_DELAY_START_2:RW+:0:11:=0x0010
-`define             DENALI_PHY_1582_DATA 32'b00000000_00000000_00000011_00111110 // PHY_ADR_CALVL_DLY_STEP_2:RW+:8:4:=0x03 PHY_ADR_MASTER_DELAY_HALF_MEASURE_2:RW+:0:8:=0x3e
-`define             DENALI_PHY_1583_DATA 32'b00000001_00000001_00000000_00000010 // PHY_ADR_DC_CALVL_ENABLE_2:RW+:24:1:=0x01 PHY_ADR_DC_INIT_SLV_DELAY_2:RW+:8:10:=0x0100 PHY_ADR_CALVL_CAPTURE_CNT_2:RW+:0:4:=0x02
-`define             DENALI_PHY_1584_DATA 32'b00000000_00000000_00000000_10000000 // PHY_ADR_DC_DM_CLK_THRSHLD_2:RW+:0:8:=0x80
-`define             DENALI_PHY_1585_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1586_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1587_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1588_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1589_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1590_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1591_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1592_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1593_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1594_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1595_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1596_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1597_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1598_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1599_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1600_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1601_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1602_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1603_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1604_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1605_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1606_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1607_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1608_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1609_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1610_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1611_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1612_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1613_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1614_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1615_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1616_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1617_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1618_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1619_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1620_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1621_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1622_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1623_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1624_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1625_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1626_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1627_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1628_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1629_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1630_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1631_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1632_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1633_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1634_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1635_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1636_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1637_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1638_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1639_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1640_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1641_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1642_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1643_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1644_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1645_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1646_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1647_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1648_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1649_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1650_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1651_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1652_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1653_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1654_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1655_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1656_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1657_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1658_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1659_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1660_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1661_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1662_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1663_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1664_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1665_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1666_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1667_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1668_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1669_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1670_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1671_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1672_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1673_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1674_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1675_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1676_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1677_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1678_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1679_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1680_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1681_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1682_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1683_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1684_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1685_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1686_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1687_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1688_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1689_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1690_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1691_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1692_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1693_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1694_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1695_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1696_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1697_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1698_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1699_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1700_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1701_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1702_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1703_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1704_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1705_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1706_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1707_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1708_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1709_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1710_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1711_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1712_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1713_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1714_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1715_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1716_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1717_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1718_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1719_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1720_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1721_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1722_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1723_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1724_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1725_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1726_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1727_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1728_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1729_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1730_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1731_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1732_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1733_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1734_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1735_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1736_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1737_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1738_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1739_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1740_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1741_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1742_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1743_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1744_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1745_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1746_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1747_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1748_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1749_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1750_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1751_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1752_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1753_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1754_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1755_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1756_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1757_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1758_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1759_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1760_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1761_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1762_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1763_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1764_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1765_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1766_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1767_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1768_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1769_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1770_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1771_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1772_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1773_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1774_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1775_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1776_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1777_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1778_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1779_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1780_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1781_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1782_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1783_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1784_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1785_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1786_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1787_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1788_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1789_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1790_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1791_DATA 32'b00000000_00000000_00000000_00000000 //
-`define             DENALI_PHY_1792_DATA 32'b00000000_00000000_00000000_00000000 // PHY_FREQ_SEL:RW:0:2:=0x00
-`define             DENALI_PHY_1793_DATA 32'b00000000_00000000_00000001_00000000 // PHY_SW_GRP0_SHIFT_0:RW+:24:5:=0x00 PHY_FREQ_SEL_INDEX:RW+:16:2:=0x00 PHY_FREQ_SEL_MULTICAST_EN:RW+:8:1:=0x01 PHY_FREQ_SEL_FROM_REGIF:RW_D:0:1:=0x00
-`define             DENALI_PHY_1794_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_1:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_0:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_0:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_0:RW+:0:5:=0x00
-`define             DENALI_PHY_1795_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_2:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_1:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_1:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_1:RW+:0:5:=0x00
-`define             DENALI_PHY_1796_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_3:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_2:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_2:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_2:RW+:0:5:=0x00
-`define             DENALI_PHY_1797_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_4:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_3:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_3:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_3:RW+:0:5:=0x00
-`define             DENALI_PHY_1798_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP0_SHIFT_5:RW+:24:5:=0x00 PHY_SW_GRP3_SHIFT_4:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_4:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_4:RW+:0:5:=0x00
-`define             DENALI_PHY_1799_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_GRP3_SHIFT_5:RW+:16:5:=0x00 PHY_SW_GRP2_SHIFT_5:RW+:8:5:=0x00 PHY_SW_GRP1_SHIFT_5:RW+:0:5:=0x00
-`define             DENALI_PHY_1800_DATA 32'b00000000_00000101_00000000_00000000 // PHY_GRP_BYPASS_OVERRIDE:RW:24:1:=0x00 PHY_SW_GRP_BYPASS_SHIFT:RW:16:5:=0x05 PHY_GRP_BYPASS_SLAVE_DELAY:RW:0:11:=0x0000
-`define             DENALI_PHY_1801_DATA 32'b00000100_00000000_00000000_00000000 // PHY_CSLVL_START:RW:16:11:=0x0400 SC_PHY_MANUAL_UPDATE_PHYUPD_ENABLE:RW_D:8:1:=0x00 SC_PHY_MANUAL_UPDATE:WR:0:1:=0x00
-`define             DENALI_PHY_1802_DATA 32'b00000000_00000000_00000000_01010101 // SC_PHY_CSLVL_DEBUG_CONT:WR:24:1:=0x00 PHY_CSLVL_DEBUG_MODE:RW:16:1:=0x00 PHY_CSLVL_COARSE_DLY:RW:0:11:=0x0055
-`define             DENALI_PHY_1803_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_CSLVL_ERROR_CLR:WR:0:1:=0x00
-`define             DENALI_PHY_1804_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CSLVL_OBS0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1805_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CSLVL_OBS1:RD:0:32:=0x00000000
-`define             DENALI_PHY_1806_DATA 32'b00000000_00001111_00000000_00000001 // PHY_CSLVL_CS_MAP:RW:16:4:=0x0f PHY_LP4_BOOT_DISABLE:RW:8:1:=0x00 PHY_CSLVL_ENABLE:RW:0:1:=0x01
-`define             DENALI_PHY_1807_DATA 32'b00000000_00101000_00000000_01000000 // PHY_CSLVL_COARSE_CHK:RW:16:11:=0x0028 PHY_CSLVL_QTR:RW:0:11:=0x0040
-`define             DENALI_PHY_1808_DATA 32'b00000000_00000000_01010000_00000010 // PHY_ADRCTL_SNAP_OBS_REGS:WR:24:1:=0x00 PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE:RW:16:3:=0x00 PHY_CALVL_CS_MAP:RW:8:8:=0x50 PHY_CSLVL_COARSE_CAPTURE_CNT:RW:0:4:=0x02
-`define             DENALI_PHY_1809_DATA 32'b00000000_00000001_00000001_00000001 // PHY_LPDDR3_CS:RW_D:24:1:=0x00 PHY_LP4_ACTIVE:RW:16:1:=0x01 PHY_ADRCTL_LPDDR:RW:8:1:=0x01 PHY_DFI_PHYUPD_TYPE:RW:0:2:=0x01
-`define             DENALI_PHY_1810_DATA 32'b00000000_00000000_10000000_00001000 // PHY_CLK_DC_FREQ_CHG_ADJ:RW:24:1:=0x00 PHY_CLK_DC_WEIGHT:RW:16:2:=0x00 PHY_CLK_DC_CAL_TIMEOUT:RW:8:8:=0x80 PHY_CLK_DC_CAL_SAMPLE_WAIT:RW:0:8:=0x08
-`define             DENALI_PHY_1811_DATA 32'b00000000_00001000_00010000_00100000 // PHY_CLK_DC_ADJUST_DIRECT:RW:24:1:=0x00 PHY_CLK_DC_ADJUST_THRSHLD:RW:16:8:=0x08 PHY_CLK_DC_ADJUST_SAMPLE_CNT:RW:8:8:=0x10 PHY_CLK_DC_ADJUST_START:RW:0:6:=0x20
-`define             DENALI_PHY_1812_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CONTINUOUS_CLK_CAL_UPDATE:RW:24:1:=0x00 SC_PHY_UPDATE_CLK_CAL_VALUES:WR:16:1:=0x00 PHY_CLK_DC_CAL_START:RW+:8:1:=0x00 PHY_CLK_DC_CAL_POLARITY:RW:0:1:=0x00
-`define             DENALI_PHY_1813_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_TXIO_CTRL_3:RW:24:4:=0x00 PHY_SW_TXIO_CTRL_2:RW:16:4:=0x00 PHY_SW_TXIO_CTRL_1:RW:8:4:=0x00 PHY_SW_TXIO_CTRL_0:RW:0:4:=0x00
-`define             DENALI_PHY_1814_DATA 32'b00000001_00000000_00000000_00000000 // PHY_CA_SW_TXPWR_CTRL:RW:24:1:=0x01 PHY_MEMCLK_SW_TXIO_CTRL:RW:16:1:=0x00 PHY_SW_TXIO_CTRL_5:RW:8:4:=0x00 PHY_SW_TXIO_CTRL_4:RW:0:4:=0x00
-`define             DENALI_PHY_1815_DATA 32'b00000000_00000000_00000000_00000001 // PHY_MEMCLK_SW_TXPWR_CTRL:RW:0:1:=0x01
-`define             DENALI_PHY_1816_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_0:RW:0:32:=0x00000000
-`define             DENALI_PHY_1817_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_1:RW:0:32:=0x00000000
-`define             DENALI_PHY_1818_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_2:RW:0:32:=0x00000000
-`define             DENALI_PHY_1819_DATA 32'b00000000_00000000_00000000_00000000 // PHY_USER_DEF_REG_AC_3:RW:0:32:=0x00000000
-`define             DENALI_PHY_1820_DATA 32'b00000000_00000000_00000000_00000000 // PHY_LP4_BOOT_PLL_BYPASS:RW:0:1:=0x00
-`define             DENALI_PHY_1821_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CLK_SWITCH_OBS:RD:0:32:=0x00000000
-`define             DENALI_PHY_1822_DATA 32'b00000000_00000000_00000000_01100100 // PHY_PLL_WAIT:RW:0:8:=0x64
-`define             DENALI_PHY_1823_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SW_PLL_BYPASS:RW+:0:1:=0x00
-`define             DENALI_PHY_1824_DATA 32'b00000000_00000000_00000000_00000000 // PHY_SET_DFI_INPUT_3:RW:24:4:=0x00 PHY_SET_DFI_INPUT_2:RW:16:4:=0x00 PHY_SET_DFI_INPUT_1:RW:8:4:=0x00 PHY_SET_DFI_INPUT_0:RW:0:4:=0x00
-`define             DENALI_PHY_1825_DATA 32'b00000001_00000001_00000000_00000000 // PHY_CS_ACS_ALLOCATION_bit1_0:RW:24:4:=0x01 PHY_CS_ACS_ALLOCATION_bit0_0:RW:16:4:=0x01 PHY_SET_DFI_INPUT_5:RW:8:4:=0x00 PHY_SET_DFI_INPUT_4:RW:0:4:=0x00
-`define             DENALI_PHY_1826_DATA 32'b00000010_00000010_00000001_00000001 // PHY_CS_ACS_ALLOCATION_bit1_1:RW:24:4:=0x02 PHY_CS_ACS_ALLOCATION_bit0_1:RW:16:4:=0x02 PHY_CS_ACS_ALLOCATION_bit3_0:RW:8:4:=0x01 PHY_CS_ACS_ALLOCATION_bit2_0:RW:0:4:=0x01
-`define             DENALI_PHY_1827_DATA 32'b00000100_00000100_00000010_00000010 // PHY_CS_ACS_ALLOCATION_bit1_2:RW:24:4:=0x04 PHY_CS_ACS_ALLOCATION_bit0_2:RW:16:4:=0x04 PHY_CS_ACS_ALLOCATION_bit3_1:RW:8:4:=0x02 PHY_CS_ACS_ALLOCATION_bit2_1:RW:0:4:=0x02
-`define             DENALI_PHY_1828_DATA 32'b00001000_00001000_00000100_00000100 // PHY_CS_ACS_ALLOCATION_bit1_3:RW:24:4:=0x08 PHY_CS_ACS_ALLOCATION_bit0_3:RW:16:4:=0x08 PHY_CS_ACS_ALLOCATION_bit3_2:RW:8:4:=0x04 PHY_CS_ACS_ALLOCATION_bit2_2:RW:0:4:=0x04
-`define             DENALI_PHY_1829_DATA 32'b00001111_00001111_00001000_00001000 // PHY_CS_ACS_ALLOCATION_bit1_4:RW:24:4:=0x0f PHY_CS_ACS_ALLOCATION_bit0_4:RW:16:4:=0x0f PHY_CS_ACS_ALLOCATION_bit3_3:RW:8:4:=0x08 PHY_CS_ACS_ALLOCATION_bit2_3:RW:0:4:=0x08
-`define             DENALI_PHY_1830_DATA 32'b00001111_00001111_00001111_00001111 // PHY_CS_ACS_ALLOCATION_bit1_5:RW:24:4:=0x0f PHY_CS_ACS_ALLOCATION_bit0_5:RW:16:4:=0x0f PHY_CS_ACS_ALLOCATION_bit3_4:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_bit2_4:RW:0:4:=0x0f
-`define             DENALI_PHY_1831_DATA 32'b00100000_00100000_00001111_00001111 // PHY_CLK_DC_ADJUST_1:RW+:24:8:=0x20 PHY_CLK_DC_ADJUST_0:RW+:16:8:=0x20 PHY_CS_ACS_ALLOCATION_bit3_5:RW:8:4:=0x0f PHY_CS_ACS_ALLOCATION_bit2_5:RW:0:4:=0x0f
-`define             DENALI_PHY_1832_DATA 32'b00011011_01000010_10000000_00000000 // PHY_LP4_BOOT_PLL_CTRL:RW:16:13:=0x1b42 PHY_CLK_DC_DM_THRSHLD:RW+:8:8:=0x80 PHY_CLK_DC_INIT_DISABLE:RW+:0:1:=0x00
-`define             DENALI_PHY_1833_DATA 32'b00000000_00000000_00000000_00000100 // PHY_PLL_OBS_0:RD:16:16:=0x0000 PHY_PLL_CTRL_OVERRIDE:RW:0:16:=0x0004
-`define             DENALI_PHY_1834_DATA 32'b00000001_00000001_00000000_00000000 // PHY_PLL_REFOUT_SEL:RW:24:1:=0x01 PHY_PLL_TESTOUT_SEL:RW:16:1:=0x01 PHY_PLL_OBS_1:RD:0:16:=0x0000
-`define             DENALI_PHY_1835_DATA 32'b00000001_00000111_00000101_00000001 // PHY_LS_IDLE_EN:RW:24:1:=0x01 PHY_LP_WAKEUP:RW:16:8:=0x07 PHY_TCKSRE_WAIT:RW:8:4:=0x05 PHY_LP4_BOOT_LOW_FREQ_SEL:RW:0:1:=0x01
-`define             DENALI_PHY_1836_DATA 32'b00000000_00000000_00000000_01010100 // PHY_TDFI_PHY_WRDELAY:RW:16:1:=0x00 PHY_LP_CTRLUPD_CNTR_CFG:RW:0:10:=0x0054
-`define             DENALI_PHY_1837_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_FDBK_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1838_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_DATA_TERM:RW+:0:17:=0x004410
-`define             DENALI_PHY_1839_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_DQS_TERM:RW+:0:17:=0x004410
-`define             DENALI_PHY_1840_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_ADDR_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1841_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CLK_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1842_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_ERR_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1843_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CKE_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1844_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_RST_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1845_DATA 32'b00000000_00000000_01000100_00010000 // PHY_PAD_CS_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1846_DATA 32'b00000000_00000000_01000100_00010000 // PHY_ADRCTL_RX_CAL:RW:24:7:=0x00 PHY_PAD_ODT_TERM:RW+:0:18:=0x004410
-`define             DENALI_PHY_1847_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADRCTL_LP3_RX_CAL:RW:0:13:=0x0000
-`define             DENALI_PHY_1848_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL:RW:0:32:=0x00000000
-`define             DENALI_PHY_1849_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL2:RW:0:23:=0x000000
-`define             DENALI_PHY_1850_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL3:RW:0:21:=0x000000
-`define             DENALI_PHY_1851_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TST_CLK_PAD_CTRL4:RW:0:21:=0x000000
-`define             DENALI_PHY_1852_DATA 32'b00000000_00000000_00000000_01100100 // PHY_CAL_START_0:WR:24:1:=0x00 PHY_CAL_CLEAR_0:WR:16:1:=0x00 PHY_CAL_MODE_0:RW:0:13:=0x0064
-`define             DENALI_PHY_1853_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_INTERVAL_COUNT_0:RW:0:32:=0x00000000
-`define             DENALI_PHY_1854_DATA 32'b00000000_00000000_00000001_00001000 // PHY_LP4_BOOT_CAL_CLK_SELECT_0:RW:8:3:=0x01 PHY_CAL_SAMPLE_WAIT_0:RW:0:8:=0x08
-`define             DENALI_PHY_1855_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1856_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT2_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1857_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT4_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1858_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT5_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1859_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT6_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1860_DATA 32'b00000011_00000000_00000000_00000000 // PHY_CAL_CPTR_CNT_0:RW:24:7:=0x03 PHY_CAL_RESULT7_OBS_0:RD:0:24:=0x000000
-`define             DENALI_PHY_1861_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_DBG_CFG_0:RW:24:1:=0x00 PHY_CAL_RCV_FINE_ADJ_0:RW:16:8:=0x00 PHY_CAL_PD_FINE_ADJ_0:RW:8:8:=0x00 PHY_CAL_PU_FINE_ADJ_0:RW:0:8:=0x00
-`define             DENALI_PHY_1862_DATA 32'b00000000_00000000_00000000_00000000 // SC_PHY_PAD_DBG_CONT_0:WR:0:1:=0x00
-`define             DENALI_PHY_1863_DATA 32'b00000000_00000000_00000000_00000000 // PHY_CAL_RESULT3_OBS_0:RD:0:32:=0x00000000
-`define             DENALI_PHY_1864_DATA 32'b00000100_00010000_00100000_00110101 // PHY_CAL_SLOPE_ADJ_0:RW_D:8:20:=0x041020 PHY_ADRCTL_PVT_MAP_0:RW:0:7:=0x35
-`define             DENALI_PHY_1865_DATA 32'b00000000_00000100_00010000_00100000 // PHY_CAL_SLOPE_ADJ_PASS2_0:RW_D:0:20:=0x041020
-`define             DENALI_PHY_1866_DATA 32'b00000001_11001001_10001100_10011000 // PHY_CAL_TWO_PASS_CFG_0:RW_D:0:25:=0x01c98c98
-`define             DENALI_PHY_1867_DATA 32'b00111111_01000000_00000000_00000000 // PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_SW_CAL_CFG_0:RW:0:23:=0x400000
-`define             DENALI_PHY_1868_DATA 32'b00111111_00111111_00011111_00111111 // PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0:RW_D:24:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0:RW_D:16:6:=0x3f PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0:RW_D:8:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0:RW_D:0:6:=0x3f
-`define             DENALI_PHY_1869_DATA 32'b00011111_00111111_00111111_00011111 // PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0:RW:24:5:=0x1f PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0:RW:16:6:=0x3f PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0:RW_D:0:5:=0x1f
-`define             DENALI_PHY_1870_DATA 32'b00000000_00011111_00111111_00111111 // PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0:RW:16:5:=0x1f PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0:RW:8:6:=0x3f PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0:RW:0:6:=0x3f
-`define             DENALI_PHY_1871_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_ERR_CLEAR:WR:24:1:=0x00 PHY_ADRCTL_MANUAL_UPDATE:WR:16:1:=0x00 PHY_PAD_ATB_CTRL:RW:0:16:=0x0000
-`define             DENALI_PHY_1872_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_CONTROL:RW:16:9:=0x0000 PHY_AC_LPBK_ENABLE:RW:8:6:=0x00 PHY_AC_LPBK_OBS_SELECT:RW:0:3:=0x00
-`define             DENALI_PHY_1873_DATA 32'b00000000_00000000_00000000_00000001 // PHY_AC_PRBS_PATTERN_MASK:RW:8:4:=0x00 PHY_AC_PRBS_PATTERN_START:RW_D:0:7:=0x01
-`define             DENALI_PHY_1874_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_LPBK_RESULT_OBS:RD:0:32:=0x00000000
-`define             DENALI_PHY_1875_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_CLK_LPBK_CONTROL:RW:16:6:=0x00 PHY_AC_CLK_LPBK_ENABLE:RW:8:2:=0x00 PHY_AC_CLK_LPBK_OBS_SELECT:RW:0:1:=0x00
-`define             DENALI_PHY_1876_DATA 32'b00000000_00000000_00000000_00000000 // PHY_TOP_PWR_RDC_DISABLE:RW_D:24:1:=0x00 PHY_AC_PWR_RDC_DISABLE:RW:16:1:=0x00 PHY_AC_CLK_LPBK_RESULT_OBS:RD:0:16:=0x0000
-`define             DENALI_PHY_1877_DATA 32'b00000000_00000000_00000000_00000000 // PHY_AC_SLV_DLY_CTRL_GATE_DISABLE:RW_D:0:1:=0x00
-`define             DENALI_PHY_1878_DATA 32'b01110110_01010100_00110010_00010000 // PHY_DATA_BYTE_ORDER_SEL:RW:0:32:=0x76543210
-`define             DENALI_PHY_1879_DATA 32'b00000110_00000001_00000001_10011000 // PHY_ADR_DISABLE:RW:24:3:=0x06 PHY_CALVL_DEVICE_MAP:RW:16:5:=0x01 PHY_LPDDR4_CONNECT:RW:8:1:=0x01 PHY_DATA_BYTE_ORDER_SEL_HIGH:RW:0:8:=0x98
-`define             DENALI_PHY_1880_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ADRCTL_MSTR_DLY_ENC_SEL:RW:0:2:=0x00
-`define             DENALI_PHY_1881_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_AC_ENABLE:RW:0:32:=0x00000000
-`define             DENALI_PHY_1882_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DDL_AC_MODE:RW:0:26:=0x00000000
-`define             DENALI_PHY_1883_DATA 32'b00000000_00000100_00000111_00000000 // PHY_DDL_TRACK_UPD_THRESHOLD_AC:RW:16:8:=0x04 PHY_INIT_UPDATE_CONFIG:RW:8:3:=0x07 PHY_DDL_AC_MASK:RW:0:6:=0x00
-`define             DENALI_PHY_1884_DATA 32'b00000000_00000000_00000000_00000000 // PHY_ERR_STATUS:RW+:24:3:=0x00 PHY_ERR_MASK_EN:RW:16:3:=0x00 PHY_CA_PARITY_ERR_PULSE_MIN:RW:0:16:=0x0000
-`define             DENALI_PHY_1885_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS0_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1886_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS1_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1887_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS2_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1888_DATA 32'b00000000_00000000_00000000_00000000 // PHY_DS3_DQS_ERR_COUNTER:RW+:0:32:=0x00000000
-`define             DENALI_PHY_1889_DATA 32'b00000000_00000000_00000000_00000010 // PHY_DS_INIT_COMPLETE_OBS:RD:24:4:=0x00 PHY_AC_INIT_COMPLETE_OBS:RD:8:14:=0x0000 PHY_DLL_RST_EN:RW_D:0:2:=0x02
-`define             DENALI_PHY_1890_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GRP_SLV_DLY_ENC_OBS_SELECT:RW:24:6:=0x00 PHY_AC_DCC_RXCAL_CTRL_GATE_DISABLE:RW_D:16:1:=0x00 PHY_ERR_IE:RW:8:1:=0x00 PHY_UPDATE_MASK:RW:0:1:=0x00
-`define             DENALI_PHY_1891_DATA 32'b00000000_00000000_00000000_00000000 // PHY_GRP_SHIFT_OBS:RD:24:3:=0x00 PHY_GRP_SLV_DLY_ENC_OBS:RD:8:11:=0x0000 PHY_GRP_SHIFT_OBS_SELECT:RW:0:5:=0x00
-`define             DENALI_PHY_1892_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_CAL_IO_CFG_0:RW+:0:18:=0x000000
-`define             DENALI_PHY_1893_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PAD_ACS_IO_CFG:RW+:0:19:=0x000000
-`define             DENALI_PHY_1894_DATA 32'b00000000_00000000_00000000_00000000 // PHY_PLL_BYPASS:RW+:0:1:=0x00
-`define             DENALI_PHY_1895_DATA 32'b00000000_00000000_00010001_01000010 // PHY_LOW_FREQ_SEL:RW+:16:1:=0x00 PHY_PLL_CTRL:RW+:0:13:=0x1142
-`define             DENALI_PHY_1896_DATA 32'b00000011_00000010_00000001_00000000 // PHY_CSLVL_DLY_STEP:RW+:24:4:=0x03 PHY_CSLVL_CAPTURE_CNT:RW+:16:4:=0x02 PHY_PAD_VREF_CTRL_AC:RW:0:10:=0x0100
-`define             DENALI_PHY_1897_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1898_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_0:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_0:RW+:0:11:=0x0300
-`define             DENALI_PHY_1899_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1900_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_1:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_1:RW+:0:11:=0x0300
-`define             DENALI_PHY_1901_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1902_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_2:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_2:RW+:0:11:=0x0300
-`define             DENALI_PHY_1903_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_3:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_3:RW+:0:11:=0x0300
-`define             DENALI_PHY_1904_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_3:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_3:RW+:0:11:=0x0300
-`define             DENALI_PHY_1905_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_4:RW+:16:11:=0x0300 PHY_GRP0_SLAVE_DELAY_4:RW+:0:11:=0x0300
-`define             DENALI_PHY_1906_DATA 32'b00000011_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_4:RW+:16:11:=0x0300 PHY_GRP2_SLAVE_DELAY_4:RW+:0:11:=0x0300
-`define             DENALI_PHY_1907_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP0_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1908_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP1_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1909_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP2_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1910_DATA 32'b00000000_00000000_00000011_00000000 // PHY_GRP3_SLAVE_DELAY_5:RW+:0:11:=0x0300
-`define             DENALI_PHY_1911_DATA 32'b00000000_00000000_00000000_00000010 // PHY_CLK_DC_CAL_CLK_SEL:RW+:0:3:=0x02
-`define             DENALI_PHY_1912_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_FDBK_DRIVE:RW+:0:28:=0x00004011
-`define             DENALI_PHY_1913_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_FDBK_DRIVE2:RW+:0:16:=0x4011
-`define             DENALI_PHY_1914_DATA 32'b00000000_00000000_00000000_01000000 // PHY_PAD_DATA_DRIVE:RW+:0:30:=0x00000040
-`define             DENALI_PHY_1915_DATA 32'b00000000_00000000_00000000_01000000 // PHY_PAD_DQS_DRIVE:RW+:0:28:=0x00000040
-`define             DENALI_PHY_1916_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ADDR_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1917_DATA 32'b00000000_00011111_11111111_00000000 // PHY_PAD_ADDR_DRIVE2:RW+:0:22:=0x1fff00
-`define             DENALI_PHY_1918_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CLK_DRIVE:RW+:0:31:=0x00004011
-`define             DENALI_PHY_1919_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CLK_DRIVE2:RW+:0:17:=0x004011
-`define             DENALI_PHY_1920_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ERR_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1921_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ERR_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1922_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CKE_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1923_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CKE_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1924_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_RST_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1925_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_RST_DRIVE2:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1926_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CS_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1927_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_CS_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1928_DATA 32'b00000000_00000000_01000000_00010001 // PHY_PAD_ODT_DRIVE:RW+:0:29:=0x00004011
-`define             DENALI_PHY_1929_DATA 32'b00000001_00000000_01000000_00010001 // PHY_CAL_CLK_SELECT_0:RW+:24:3:=0x01 PHY_PAD_ODT_DRIVE2:RW+:0:22:=0x004011
-`define             DENALI_PHY_1930_DATA 32'b00000000_00100000_00000100_00000000 // PHY_CAL_SETTLING_PRD_0:RW+:16:7:=0x20 PHY_CAL_VREF_SWITCH_TIMER_0:RW+:0:16:=0x0400
-//* ********************************************************
-//* The below are used only for simulation phy purposes.
-//* Please ignore if using integrated Cadence PHY.
-//* SimulationValues {{{
-//* ********************************************************
-`define SIM_PHY_VALS_DEFINED 1 // Global define for simulation
-`define                        SMALL_TREF_ENABLE 8'h0 // CTL
-`define                                  MR8_VAL 8'h10 // CTL
-`define                                  MR0_VAL 8'h0 // CTL
-`define                          MR0_RL3_SUPPORT 2'h0 // CTL
-`define                            ODT_RD_TIMING 6'h0 // CTL
-`define                                  TAC_MIN 6'h0 // CTL
-`define                                  TAC_MAX 6'h0 // CTL
-`define               LPDDR1_PD_CLK_GATE_DISABLE 1'h0 // CTL
-`define                          LPDDR1_ATTACHED 1'h0 // CTL
-//* ********************************************************
-//* SimulationValues }}}
-//* ********************************************************

+ 0 - 434
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_1600_cl28_bl16/regconfig.h.sim_PI.v

@@ -1,434 +0,0 @@
-
-/* ****************************************************************
- *        CADENCE                    Copyright (c) 2001-2018      *
- *                                   Cadence Design Systems, Inc. *
- *                                   All rights reserved.         *
- ******************************************************************
- *  The values calculated from this script are meant to be        *
- *  representative programmings.   The values may not reflect the *
- *  actual required programming for production use.   Please      *
- *  closely review all programmed values for technical accuracy   *
- *  before use in production parts.                               *
- ******************************************************************
- *                                                                 
- *   Module:         regconfig.h
- *   Documentation:  Register programming header file
- *
- ******************************************************************
- ******************************************************************
- * WARNING:  This file was automatically generated.  Manual
- * editing may result in undetermined behavior.
- ******************************************************************
- ******************************************************************/
-// REL: sifive.shanghai.n1-VIC_DDR__20180206
-
-
-`timescale 10ps/10ps
-
-// ********************************************************************
-// Option: IP    : IP Mode                       = PI
-// Option: BL    : Burst Length                  = 16
-// Option: CL    : CAS Latency                   = 28
-// Option: MHZ   : Simulation MHz                = 1600
-// Option: AP    : Auto Precharge Mode     (0/1) = 0
-// Option: DLLBP : DLL Bypass Mode         (0/1) = 0
-// Option: HALF  : Half-Memory Support     (0/1) = 0
-// Option: RDIMM : Registered Dimm Support (0/1) = 0
-// Option: AL    : Additive Latency              = 0
-// Option: PREAM : Preamble Support    (0/1/2/3) = 0
-// Option: BOF   : Burst On the Fly        (0/1) = 0
-// Option: WLS   : Write Latency Set       (0/1) = 0
-// Option: TCK   : Simulation period in ns       = 
-// Option: WRDBIEN : Write DBI Enable       (0/1) = 0
-// Option: RDDBIEN : Read DBI Enable       (0/1) = 0
-// Option: RDPSTMBLE : RD Postamble En      (0/1) = 0
-// Option: WRPSTMBLE : WR Postamble En      (0/1) = 0
-// Option: CRC : CRC En      (0/1) = 0
-// Option: SOMA  : Memory-SOMA file(s)           = /proj/iprel/sifive.shanghai.n1-VIC_DDR/sifive.shanghai.n1-VIC_DDR__20180201/mcip/mem/sifive.shanghai.n1-VIC_DDR/memory/jedec_lpddr4_16gb_3200/memory.xml.sim
-// Option: PL    : CA Parity Latency              = -1
-// ********************************************************************
-// Memory: jedec_lpddr4_16gb_3200
-// ********************************************************************
-
-
-`define                DENALI_PI_00_DATA 32'b00000000_00000000_00001011_00000000 // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00
-`define                DENALI_PI_01_DATA 32'b00000000_00000000_00000001_00000001 // PI_ONBUS_MBIST:RW:24:1:=0x00 PI_NOTCARE_PHYUPD:RW:16:1:=0x00 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x01
-`define                DENALI_PI_02_DATA 32'b00000000_01100100_00000000_00000000 // PI_TRAIN_ALL_FREQ_REQ:WR:24:1:=0x00 RESERVED:RW_D:16:8:=0x64 PI_TCMD_GAP:RW:0:16:=0x0000
-`define                DENALI_PI_03_DATA 32'b00000000_00000000_00000000_00000001 // PI_DFI_PHYMSTR_STATE_SEL_R:RW:24:1:=0x00 PI_DFI_PHYMSTR_CS_STATE_R:RW:16:1:=0x00 PI_DFI_PHYMSTR_TYPE:RW:8:2:=0x00 PI_DFI_VERSION:RW:0:1:=0x01
-`define                DENALI_PI_04_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_PHYMSTR_MAX:RD:0:32:=0x00000000
-`define                DENALI_PI_05_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_PHYMSTR_RESP:RD:0:20:=0x000000
-`define                DENALI_PI_06_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_PHYUPD_RESP:RD:0:20:=0x000000
-`define                DENALI_PI_07_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_PHYUPD_MAX:RD:0:32:=0x00000000
-`define                DENALI_PI_08_DATA 32'b00000000_00000000_00000000_00000001 // PI_EXIT_AFTER_INIT_CALVL:RW_D:0:1:=0x01
-`define                DENALI_PI_09_DATA 32'b00000000_00000000_00000000_00000111 // PI_FREQ_MAP:RW:0:32:=0x00000007
-`define                DENALI_PI_10_DATA 32'b00000000_00000001_00000000_00000010 // RESERVED:RW:24:1:=0x00 PI_SW_RST_N:RW_D:16:1:=0x01 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x02
-`define                DENALI_PI_11_DATA 32'b00000011_00000000_00001000_00001111 // PI_PREAMBLE_SUPPORT:RW:24:2:=0x03 PI_TMPRR:RW:16:4:=0x00 PI_TMRR:RW:8:4:=0x08 PI_CS_MAP:RW:0:4:=0x0f
-`define                DENALI_PI_12_DATA 32'b00000000_00000000_00000000_00000001 // RESERVED:RW:8:1:=0x00 PI_MCAREF_FORWARD_ONLY:RW:0:1:=0x01
-`define                DENALI_PI_13_DATA 32'b00000000_00000000_00000000_00000101 // PI_ON_DFIBUS:RD:24:1:=0x00 PI_TREF_INTERVAL:RW:0:20:=0x000005
-`define                DENALI_PI_14_DATA 32'b00000000_00000000_00000000_00000000 // PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 PI_DATA_RETENTION:RD:0:1:=0x00
-`define                DENALI_PI_15_DATA 32'b00000000_00000000_00000000_00000000 // PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00
-`define                DENALI_PI_16_DATA 32'b00000000_00000000_00000000_00000000 // PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00
-`define                DENALI_PI_17_DATA 32'b00000000_00000000_00000000_00000000 // PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00
-`define                DENALI_PI_18_DATA 32'b00000000_00000000_00000000_00000000 // PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_0:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00
-`define                DENALI_PI_19_DATA 32'b00000000_00000000_00000000_00000000 // PI_SWLVL_WR_SLICE_2:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_1:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00
-`define                DENALI_PI_20_DATA 32'b00000000_00000000_00000000_00000000 // PI_SWLVL_WR_SLICE_3:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_2:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_2:WR:0:1:=0x00
-`define                DENALI_PI_21_DATA 32'b00000000_00000000_00000000_00000000 // PI_SWLVL_SM2_START:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_3:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_3:WR:0:1:=0x00
-`define                DENALI_PI_22_DATA 32'b00000000_00000000_00000000_00000000 // PI_DFS_PERIOD_EN:RW:24:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:16:1:=0x00 PI_SWLVL_SM2_RD:WR:8:1:=0x00 PI_SWLVL_SM2_WR:WR:0:1:=0x00
-`define                DENALI_PI_23_DATA 32'b00000001_00000001_00000000_00000000 // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_DFI40_POLARITY:RW:16:1:=0x01 PI_MPD_PERIOD_EN:RW:8:1:=0x00 PI_SRE_PERIOD_EN:RW:0:1:=0x00
-`define                DENALI_PI_24_DATA 32'b00101000_00001010_00000000_00000000 // PI_WLMRD:RW:24:6:=0x28 PI_WLDQSEN:RW:16:6:=0x0a PI_WRLVL_CS:RW:8:2:=0x00 PI_WRLVL_REQ:WR:0:1:=0x00
-`define                DENALI_PI_25_DATA 32'b00000000_00000000_00000000_00000000 // PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000
-`define                DENALI_PI_26_DATA 32'b00000000_00000000_00000000_00000001 // PI_WRLVL_ROTATE:RW:24:1:=0x00 PI_WRLVL_RESP_MASK:RW:16:4:=0x00 PI_WRLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WRLVL_ON_DPDX:RW:0:1:=0x01
-`define                DENALI_PI_27_DATA 32'b00110010_00000000_00000000_00001111 // PI_TDFI_WRLVL_EN:RW:24:8:=0x32 PI_WRLVL_ERROR_STATUS:RD:16:1:=0x00 PI_WRLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_WRLVL_CS_MAP:RW:0:4:=0x0f
-`define                DENALI_PI_28_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000
-`define                DENALI_PI_29_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000
-`define                DENALI_PI_30_DATA 32'b00000000_00000001_00000001_00000010 // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_TODTH_RD:RW:16:4:=0x01 PI_TODTH_WR:RW:8:4:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02
-`define                DENALI_PI_31_DATA 32'b00000000_00000000_00000000_00000001 // PI_ADDRESS_MIRRORING:RW:8:4:=0x00 PI_ODT_VALUE:RW:0:4:=0x01
-`define                DENALI_PI_32_DATA 32'b00000000_00000000_00000000_00000000 // PI_CA_PARITY_ERROR_INJECT:RW:0:25:=0x00000000
-`define                DENALI_PI_33_DATA 32'b00000000_00000000_00000000_00000000 // PI_RDLVL_GATE_REQ:WR:24:1:=0x00 PI_RDLVL_REQ:WR:16:1:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW+:0:3:=0x00
-`define                DENALI_PI_34_DATA 32'b00000000_00000000_00000000_00000000 // PI_RDLVL_CS:RW:0:2:=0x00
-`define                DENALI_PI_35_DATA 32'b00000000_00000000_00000000_10101010 // PI_RDLVL_PAT_0:RW:0:32:=0x000000aa
-`define                DENALI_PI_36_DATA 32'b00000000_00000000_00000000_01010101 // PI_RDLVL_PAT_1:RW:0:32:=0x00000055
-`define                DENALI_PI_37_DATA 32'b00000000_00000000_00000000_10110101 // PI_RDLVL_PAT_2:RW:0:32:=0x000000b5
-`define                DENALI_PI_38_DATA 32'b00000000_00000000_00000000_01001010 // PI_RDLVL_PAT_3:RW:0:32:=0x0000004a
-`define                DENALI_PI_39_DATA 32'b00000000_00000000_00000000_01010110 // PI_RDLVL_PAT_4:RW:0:32:=0x00000056
-`define                DENALI_PI_40_DATA 32'b00000000_00000000_00000000_10101001 // PI_RDLVL_PAT_5:RW:0:32:=0x000000a9
-`define                DENALI_PI_41_DATA 32'b00000000_00000000_00000000_10101001 // PI_RDLVL_PAT_6:RW:0:32:=0x000000a9
-`define                DENALI_PI_42_DATA 32'b00000000_00000000_00000000_10110101 // PI_RDLVL_PAT_7:RW:0:32:=0x000000b5
-`define                DENALI_PI_43_DATA 32'b00000001_00000000_00000000_00000000 // PI_RDLVL_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_SEQ_EN:RW:0:4:=0x00
-`define                DENALI_PI_44_DATA 32'b00000001_00000000_00000000_00000000 // PI_RDLVL_GATE_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_GATE_PERIODIC:RW:8:1:=0x00 PI_RDLVL_DISABLE_DFS:RW:0:1:=0x00
-`define                DENALI_PI_45_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 PI_RDLVL_GATE_ON_MPD_EXIT:RW:16:1:=0x00 PI_RDLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_RDLVL_GATE_DISABLE_DFS:RW:0:1:=0x00
-`define                DENALI_PI_46_DATA 32'b00001111_00001111_00000000_00000000 // PI_RDLVL_GATE_CS_MAP:RW:24:4:=0x0f PI_RDLVL_CS_MAP:RW:16:4:=0x0f PI_RDLVL_GATE_ROTATE:RW:8:1:=0x00 PI_RDLVL_ROTATE:RW:0:1:=0x00
-`define                DENALI_PI_47_DATA 32'b00000000_00000000_00000000_00010100 // PI_TDFI_RDLVL_RR:RW:0:10:=0x0014
-`define                DENALI_PI_48_DATA 32'b00000000_00000000_00000111_11010000 // PI_TDFI_RDLVL_RESP:RW:0:32:=0x000007d0
-`define                DENALI_PI_49_DATA 32'b00000000_00000000_00000011_00000000 // PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00
-`define                DENALI_PI_50_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000
-`define                DENALI_PI_51_DATA 32'b00000000_00000000_00000000_00000000 // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:1:=0x00
-`define                DENALI_PI_52_DATA 32'b00000001_00000000_00000000_00000000 // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000
-`define                DENALI_PI_53_DATA 32'b00000000_00000001_00000001_00000001 // PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01
-`define                DENALI_PI_54_DATA 32'b00000000_00000000_00000000_00000000 // PI_CALVL_CS:RW:24:2:=0x00 PI_CALVL_REQ:WR:16:1:=0x00 PI_TDFI_PHY_WRLAT:RD:8:8:=0x00 PI_TDFI_RDDATA_EN:RD:0:8:=0x00
-`define                DENALI_PI_55_DATA 32'b00000000_00000011_00000000_00000000 // PI_CALVL_PERIODIC:RW:24:1:=0x00 PI_CALVL_SEQ_EN:RW:16:2:=0x03 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:1:=0x00
-`define                DENALI_PI_56_DATA 32'b00000000_00000000_00000001_00000000 // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_DISABLE_DFS:RW:16:1:=0x00 PI_CALVL_ON_DPDX:RW:8:1:=0x01 PI_CALVL_ON_SREF_EXIT:RW:0:1:=0x00
-`define                DENALI_PI_57_DATA 32'b00000000_00000000_00010111_00001111 // PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x0f
-`define                DENALI_PI_58_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000
-`define                DENALI_PI_59_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000
-`define                DENALI_PI_60_DATA 32'b00000000_00000000_00000000_00000000 // PI_CALVL_INTERVAL:RW:16:16:=0x0000 PI_CALVL_ERROR_STATUS:RD:8:2:=0x00 PI_CALVL_RESP_MASK:RW:0:1:=0x00
-`define                DENALI_PI_61_DATA 32'b00001010_00010100_00001010_00000001 // PI_TCACKEH:RW:24:5:=0x0a PI_TCAMRD:RW:16:6:=0x14 PI_TCACKEL:RW:8:5:=0x0a PI_CALVL_MAX_STROBE_PEND:RW:0:4:=0x01
-`define                DENALI_PI_62_DATA 32'b00000010_00000100_00000001_00001010 // PI_CALVL_VREF_NORMAL_STEPSIZE:RW:24:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:16:4:=0x04 PI_CA_TRAIN_VREF_EN:RW:8:1:=0x01 PI_TCAEXT:RW:0:5:=0x0a
-`define                DENALI_PI_63_DATA 32'b00000010_00001000_00000101_00010000 // PI_CALVL_STROBE_NUM:RW:24:5:=0x02 PI_TCKCKEH:RW:16:4:=0x08 PI_TDFI_INIT_COMPLETE_MIN:RW:8:8:=0x05 PI_TDFI_INIT_START_MIN:RW:0:8:=0x10
-`define                DENALI_PI_64_DATA 32'b00000000_00000100_00000100_00000000 // PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:24:1:=0x00 PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:16:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:8:8:=0x04 PI_SW_CA_TRAIN_VREF:RW:0:7:=0x00
-`define                DENALI_PI_65_DATA 32'b00000001_00000000_00000001_00000001 // PI_VREFLVL_DISABLE_DFS:RW:24:1:=0x01 PI_VREF_PDA_EN:RW:16:1:=0x00 PI_VREF_CS:RW:8:2:=0x01 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:0:1:=0x01
-`define                DENALI_PI_66_DATA 32'b00000000_00000001_00000001_00000000 // PI_WDQLVL_RESP_MASK:RW:24:4:=0x00 PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_MC_DFS_PI_SET_VREF_ENABLE:RW:0:1:=0x00
-`define                DENALI_PI_67_DATA 32'b00000010_00000100_00001111_00000000 // PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:24:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:16:5:=0x04 PI_WDQLVL_CS_MAP:RW:8:4:=0x0f PI_WDQLVL_ROTATE:RW:0:1:=0x00
-`define                DENALI_PI_68_DATA 32'b00110100_00000000_00000000_00000000 // PI_TDFI_WDQLVL_EN:RW:24:8:=0x34 PI_WDQLVL_CS:RW:16:2:=0x00 PI_WDQLVL_REQ:WR:8:1:=0x00 PI_WDQLVL_PERIODIC:RW:0:1:=0x00
-`define                DENALI_PI_69_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000
-`define                DENALI_PI_70_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000
-`define                DENALI_PI_71_DATA 32'b00000001_00000000_00000000_00000000 // PI_WDQLVL_ON_DPDX:RW:24:1:=0x01 PI_WDQLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000
-`define                DENALI_PI_72_DATA 32'b00000000_00000000_00000000_00000000 // PI_WDQLVL_NEED_SAVE_RESTORE:RW:24:2:=0x00 PI_WDQLVL_ERROR_STATUS:RD:16:2:=0x00 PI_WDQLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WDQLVL_ON_MPD_EXIT:RW:0:1:=0x00
-`define                DENALI_PI_73_DATA 32'b00000000_00000000_00000000_00000000 // PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00000000
-`define                DENALI_PI_74_DATA 32'b00000000_00000000_00000000_00000000 // PI_NO_MEMORY_DM:RW:16:1:=0x00 PI_WDQLVL_DM_LEVEL_EN:RW:8:1:=0x00 PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00
-`define                DENALI_PI_75_DATA 32'b00000000_00000000_00000000_00000000 // PI_WDQLVL_NIBBLE_MODE:RW:24:1:=0x00 PI_SWLVL_SM2_DM_NIBBLE_START:WR:16:1:=0x00 PI_TDFI_WDQLVL_WW:RW:0:10:=0x0000
-`define                DENALI_PI_76_DATA 32'b00000000_00000001_00000001_00000000 // PI_DBILVL_RESP_MASK:RW:24:4:=0x00 PI_PARALLEL_WDQLVL_EN:RW:16:1:=0x01 PI_WDQLVL_PDA_VREF_TRAIN:RW:8:1:=0x01 PI_WDQLVL_PDA_EN:RW:0:1:=0x00
-`define                DENALI_PI_77_DATA 32'b00000000_00001000_00000001_00000001 // RESERVED:RW_D:24:4:=0x00 PI_TCCD:RW:16:5:=0x08 PI_ROW_DIFF:RW:8:3:=0x01 PI_BANK_DIFF:RW:0:2:=0x01
-`define                DENALI_PI_78_DATA 32'b00000010_00000000_00000010_00000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-`define                DENALI_PI_79_DATA 32'b00000001_00000000_00000001_00000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
-`define                DENALI_PI_80_DATA 32'b00000001_00000000_00000000_00000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00
-`define                DENALI_PI_81_DATA 32'b00000010_00000000_00000010_00000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-`define                DENALI_PI_82_DATA 32'b00000000_00000000_00000010_00000000 // RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-`define                DENALI_PI_83_DATA 32'b00000000_00000000_00000000_00000000 // PI_INT_STATUS:RD:0:28:=0x00000000
-`define                DENALI_PI_84_DATA 32'b00000000_00000000_00000000_00000000 // PI_INT_ACK:WR:0:27:=0x00000000
-`define                DENALI_PI_85_DATA 32'b00000000_00000000_00000000_00000000 // PI_INT_MASK:RW:0:28:=0x00000000
-`define                DENALI_PI_86_DATA 32'b00001110_00000000_00000000_00000100 // PI_PARITY_IN_MUX:RW_D:24:5:=0x0e PI_CMD_SWAP_EN:RW_D:16:1:=0x00 PI_LONG_COUNT_MASK:RW:8:5:=0x00 PI_BSTLEN:RW_D:0:5:=0x04
-`define                DENALI_PI_87_DATA 32'b00001100_00001101_00010000_00001111 // PI_CAS_N_MUX:RW_D:24:5:=0x0c PI_RAS_N_MUX:RW_D:16:5:=0x0d PI_A14_MUX:RW_D:8:5:=0x10 PI_A15_MUX:RW_D:0:5:=0x0f
-`define                DENALI_PI_88_DATA 32'b00001010_00001001_00001000_00001011 // PI_BANK_MUX_2:RW_D:24:5:=0x0a PI_BANK_MUX_1:RW_D:16:5:=0x09 PI_BANK_MUX_0:RW_D:8:5:=0x08 PI_WE_N_MUX:RW_D:0:5:=0x0b
-`define                DENALI_PI_89_DATA 32'b00000010_00000001_00000000_00000000 // PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00
-`define                DENALI_PI_90_DATA 32'b00000000_00001000_00000001_00000011 // PI_UPDATE_ERROR_STATUS:RD:24:2:=0x00 PI_TDFI_CTRLUPD_MIN:RW:16:8:=0x08 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03
-`define                DENALI_PI_91_DATA 32'b00000000_00000000_00000010_00000000 // PI_SELF_REFRESH_EN:RW:24:1:=0x00 PI_BG_ROTATE_EN:RW:16:1:=0x00 PI_COL_DIFF:RW:8:4:=0x02 PI_TDFI_PARIN_LAT:RW:0:3:=0x00
-`define                DENALI_PI_92_DATA 32'b00000000_00000000_00000000_00000000 // PI_NO_MRW_BT_INIT:RW:24:1:=0x00 PI_SREF_ENTRY_REQ:WR:16:1:=0x00 PI_SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PI_PWRUP_SREFRESH_EXIT:RW+:0:1:=0x00
-`define                DENALI_PI_93_DATA 32'b00001111_00000000_00000000_00000000 // PI_PWRUP_SREFRESH_EXIT_CS:RW:24:4:=0x0f PI_NO_AUTO_MRR_INIT:RW:16:1:=0x00 PI_NO_PHY_IND_TRAIN_INIT:RW:8:1:=0x00 PI_NO_MRW_INIT:RW:0:1:=0x00
-`define                DENALI_PI_94_DATA 32'b00000000_00000000_00000000_00000100 // PI_TRST_PWRON:RW:0:32:=0x00000004
-`define                DENALI_PI_95_DATA 32'b00000000_00000000_00000000_00001010 // PI_CKE_INACTIVE:RW:0:32:=0x0000000a
-`define                DENALI_PI_96_DATA 32'b00000000_00000000_00000000_00000000 // PI_DLL_RST_DELAY:RW:16:16:=0x0000 PI_DRAM_INIT_EN:RW:8:1:=0x00 PI_DLL_RST:RW:0:1:=0x00
-`define                DENALI_PI_97_DATA 32'b00000000_00000000_00000000_00000000 // PI_DLL_RST_ADJ_DLY:RW:0:8:=0x00
-`define                DENALI_PI_98_DATA 32'b00000000_00000000_00000000_00000000 // PI_WRITE_MODEREG:RW+:0:26:=0x00000000
-`define                DENALI_PI_99_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:8:1:=0x00 PI_MRW_STATUS:RD:0:8:=0x00
-`define               DENALI_PI_100_DATA 32'b00000000_00000000_00000000_00000000 // PI_READ_MODEREG:RW+:0:17:=0x000000
-`define               DENALI_PI_101_DATA 32'b00000000_00000000_00000000_00000000 // PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000
-`define               DENALI_PI_102_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:WR:24:4:=0x00 RESERVED:RW:16:4:=0x00 PI_NO_ZQ_INIT:RW:8:1:=0x00 PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00
-`define               DENALI_PI_103_DATA 32'b00000000_00000011_00000001_00000000 // PI_MONITOR_SRC_SEL_0:RW:24:4:=0x00 RESERVED:RW:16:3:=0x03 RESERVED:RW:8:1:=0x01 PI_ZQ_REQ_PENDING:RD:0:1:=0x00
-`define               DENALI_PI_104_DATA 32'b00000001_00000001_00000000_00000001 // PI_MONITOR_CAP_SEL_1:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_1:RW:16:4:=0x01 PI_MONITOR_0:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_0:RW:0:1:=0x01
-`define               DENALI_PI_105_DATA 32'b00000000_00000001_00000010_00000000 // PI_MONITOR_2:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_2:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_2:RW:8:4:=0x02 PI_MONITOR_1:RD:0:8:=0x00
-`define               DENALI_PI_106_DATA 32'b00000100_00000000_00000001_00000011 // PI_MONITOR_SRC_SEL_4:RW:24:4:=0x04 PI_MONITOR_3:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_3:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_3:RW:0:4:=0x03
-`define               DENALI_PI_107_DATA 32'b00000001_00000101_00000000_00000001 // PI_MONITOR_CAP_SEL_5:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_5:RW:16:4:=0x05 PI_MONITOR_4:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_4:RW:0:1:=0x01
-`define               DENALI_PI_108_DATA 32'b00000000_00000001_00000110_00000000 // PI_MONITOR_6:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_6:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_6:RW:8:4:=0x06 PI_MONITOR_5:RD:0:8:=0x00
-`define               DENALI_PI_109_DATA 32'b00000000_00000000_00000001_00000111 // PI_MONITOR_7:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_7:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_7:RW:0:4:=0x07
-`define               DENALI_PI_110_DATA 32'b00000000_00000000_00000000_00000000 // PI_MONITOR_STROBE:WR:0:8:=0x00
-`define               DENALI_PI_111_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 PI_FREQ_RETENTION_NUM:RW+:16:5:=0x00 PI_FREQ_NUMBER_STATUS:RD:8:5:=0x00 PI_DLL_LOCK:RD:0:1:=0x00
-`define               DENALI_PI_112_DATA 32'b00000000_00000001_00000000_00000001 // RESERVED:RW:24:1:=0x00 PI_POWER_REDUC_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PI_PHYMSTR_TYPE:RW:0:2:=0x01
-`define               DENALI_PI_113_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-`define               DENALI_PI_114_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-`define               DENALI_PI_115_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-`define               DENALI_PI_116_DATA 32'b00000000_00000000_00000000_00000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-`define               DENALI_PI_117_DATA 32'b00000000_00000001_00000000_00000000 // PI_WRLVL_MAX_STROBE_PEND:RW:16:8:=0x01 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-`define               DENALI_PI_118_DATA 32'b00000000_00000000_00000000_00000100 // PI_TREFBW_THR:RW:0:9:=0x0004
-`define               DENALI_PI_119_DATA 32'b00000000_00000000_00000000_00000000 // PI_FREQ_CHANGE_REG_COPY:RW:0:5:=0x00
-`define               DENALI_PI_120_DATA 32'b00000000_00000001_00000000_00000000 // PI_CATR:RW:24:4:=0x00 PI_PARALLEL_CALVL_EN:RW:16:1:=0x01 RESERVED:RW:8:5:=0x00 PI_FREQ_SEL_FROM_REGIF:RW:0:1:=0x00
-`define               DENALI_PI_121_DATA 32'b00000000_00000000_00000000_00000000 // PI_NOTCARE_MC_INIT_START:RW:24:1:=0x00 PI_DISCONNECT_MC:RW:16:1:=0x00 PI_MASK_INIT_COMPLETE:RW:8:1:=0x00 PI_NO_CATR_READ:RW:0:1:=0x00
-`define               DENALI_PI_122_DATA 32'b00000000_00111100_00000000_00000011 // PI_TVREF_F1:RW:16:16:=0x003c PI_TVREF_F0:RW:0:16:=0x0003
-`define               DENALI_PI_123_DATA 32'b00001000_00000001_00000000_11110000 // PI_TSDO_F1:RW:24:8:=0x08 PI_TSDO_F0:RW:16:8:=0x01 PI_TVREF_F2:RW:0:16:=0x00f0
-`define               DENALI_PI_124_DATA 32'b00000000_00000000_00000000_00100000 // PI_TSDO_F2:RW:0:8:=0x20
-`define               DENALI_PI_125_DATA 32'b00000000_00000000_00000000_00101100 // PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x2c
-`define               DENALI_PI_126_DATA 32'b00000000_00000000_00000000_00110011 // PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:0:8:=0x33
-`define               DENALI_PI_127_DATA 32'b00000000_00000010_00000000_01001111 // PI_ZQINIT_F0:RW_D:8:12:=0x0200 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:0:8:=0x4f
-`define               DENALI_PI_128_DATA 32'b00000010_00000000_00000010_00000000 // PI_ZQINIT_F2:RW_D:16:12:=0x0200 PI_ZQINIT_F1:RW_D:0:12:=0x0200
-`define               DENALI_PI_129_DATA 32'b00000000_00000000_00000000_00000100 // PI_TPARITY_ERROR_CMD_INHIBIT_F0:RW:24:8:=0x00 PI_CA_PARITY_LAT_F0:RW:16:4:=0x00 PI_ADDITIVE_LAT_F0:RW:8:6:=0x00 PI_WRLAT_F0:RW:0:7:=0x04
-`define               DENALI_PI_130_DATA 32'b00000000_00000000_00000110_00001100 // PI_CA_PARITY_LAT_F1:RW:24:4:=0x00 PI_ADDITIVE_LAT_F1:RW:16:6:=0x00 PI_WRLAT_F1:RW:8:7:=0x06 PI_CASLAT_LIN_F0:RW:0:7:=0x0c
-`define               DENALI_PI_131_DATA 32'b00000000_00001110_00010100_00000000 // PI_ADDITIVE_LAT_F2:RW:24:6:=0x00 PI_WRLAT_F2:RW:16:7:=0x0e PI_CASLAT_LIN_F1:RW:8:7:=0x14 PI_TPARITY_ERROR_CMD_INHIBIT_F1:RW:0:8:=0x00
-`define               DENALI_PI_132_DATA 32'b00000000_00111000_00000000_00000000 // PI_CASLAT_LIN_F2:RW:16:7:=0x38 PI_TPARITY_ERROR_CMD_INHIBIT_F2:RW:8:8:=0x00 PI_CA_PARITY_LAT_F2:RW:0:4:=0x00
-`define               DENALI_PI_133_DATA 32'b00000000_00000000_00000000_00000110 // PI_TRFC_F0:RW:0:10:=0x0006
-`define               DENALI_PI_134_DATA 32'b00000000_00000000_00000000_01000110 // PI_TREF_F0:RW:0:20:=0x000046
-`define               DENALI_PI_135_DATA 32'b00000000_00000000_00000000_01110000 // PI_TRFC_F1:RW:0:10:=0x0070
-`define               DENALI_PI_136_DATA 32'b00000000_00000000_00000110_00010000 // PI_TREF_F1:RW:0:20:=0x000610
-`define               DENALI_PI_137_DATA 32'b00000000_00000000_00000001_11000000 // PI_TRFC_F2:RW:0:10:=0x01c0
-`define               DENALI_PI_138_DATA 32'b00000100_00000000_00011000_01011000 // PI_TDFI_CTRL_DELAY_F0:RW_D:24:4:=0x04 PI_TREF_F2:RW:0:20:=0x001858
-`define               DENALI_PI_139_DATA 32'b00000001_00000001_00000100_00000100 // PI_WRLVL_EN_F1:RW:24:2:=0x01 PI_WRLVL_EN_F0:RW:16:2:=0x01 PI_TDFI_CTRL_DELAY_F2:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x04
-`define               DENALI_PI_140_DATA 32'b00000000_00000000_00100100_00000001 // PI_TDFI_WRLVL_WW_F0:RW:8:10:=0x0024 PI_WRLVL_EN_F2:RW:0:2:=0x01
-`define               DENALI_PI_141_DATA 32'b00000000_00100100_00000000_00100100 // PI_TDFI_WRLVL_WW_F2:RW:16:10:=0x0024 PI_TDFI_WRLVL_WW_F1:RW:0:10:=0x0024
-`define               DENALI_PI_142_DATA 32'b00000001_00000000_00000001_00000000 // PI_ODT_EN_F1:RW:24:1:=0x01 PI_TODTL_2CMD_F1:RW:16:8:=0x00 PI_ODT_EN_F0:RW:8:1:=0x01 PI_TODTL_2CMD_F0:RW:0:8:=0x00
-`define               DENALI_PI_143_DATA 32'b00000000_00000000_00000001_00000000 // PI_TODTON_MIN_F0:RW:24:4:=0x00 PI_ODTLON_F0:RW:16:4:=0x00 PI_ODT_EN_F2:RW:8:1:=0x01 PI_TODTL_2CMD_F2:RW:0:8:=0x00
-`define               DENALI_PI_144_DATA 32'b00000000_00000000_00000000_00000000 // PI_TODTON_MIN_F2:RW:24:4:=0x00 PI_ODTLON_F2:RW:16:4:=0x00 PI_TODTON_MIN_F1:RW:8:4:=0x00 PI_ODTLON_F1:RW:0:4:=0x00
-`define               DENALI_PI_145_DATA 32'b00000101_00001000_00000100_00000011 // PI_RD_TO_ODTH_F0:RW:24:6:=0x05 PI_WR_TO_ODTH_F2:RW:16:6:=0x08 PI_WR_TO_ODTH_F1:RW:8:6:=0x04 PI_WR_TO_ODTH_F0:RW:0:6:=0x03
-`define               DENALI_PI_146_DATA 32'b00000001_00000001_00011000_00001000 // PI_RDLVL_GATE_EN_F0:RW:24:2:=0x01 PI_RDLVL_EN_F0:RW:16:2:=0x01 PI_RD_TO_ODTH_F2:RW:8:6:=0x18 PI_RD_TO_ODTH_F1:RW:0:6:=0x08
-`define               DENALI_PI_147_DATA 32'b00000001_00000001_00000001_00000001 // PI_RDLVL_GATE_EN_F2:RW:24:2:=0x01 PI_RDLVL_EN_F2:RW:16:2:=0x01 PI_RDLVL_GATE_EN_F1:RW:8:2:=0x01 PI_RDLVL_EN_F1:RW:0:2:=0x01
-`define               DENALI_PI_148_DATA 32'b00000000_00010111_00001010_00001010 // PI_RDLVL_PAT0_EN_F0:RW:24:2:=0x00 PI_TWR_MPR_F2:RW:16:8:=0x17 PI_TWR_MPR_F1:RW:8:8:=0x0a PI_TWR_MPR_F0:RW:0:8:=0x0a
-`define               DENALI_PI_149_DATA 32'b00000000_00000000_00000000_00000000 // PI_RDLVL_PAT0_EN_F1:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F0:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F0:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F0:RW:0:2:=0x00
-`define               DENALI_PI_150_DATA 32'b00000000_00000000_00000000_00000000 // PI_RDLVL_PAT0_EN_F2:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F1:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F1:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F1:RW:0:2:=0x00
-`define               DENALI_PI_151_DATA 32'b00000100_00000000_00000000_00000000 // PI_RDLAT_ADJ_F0:RW:24:8:=0x04 PI_RDLVL_MULTI_EN_F2:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F2:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F2:RW:0:2:=0x00
-`define               DENALI_PI_152_DATA 32'b00000100_00000010_00010111_00001000 // PI_WRLAT_ADJ_F1:RW:24:8:=0x04 PI_WRLAT_ADJ_F0:RW:16:8:=0x02 PI_RDLAT_ADJ_F2:RW:8:8:=0x17 PI_RDLAT_ADJ_F1:RW:0:8:=0x08
-`define               DENALI_PI_153_DATA 32'b00000100_00000010_00000010_00001010 // PI_TDFI_PHY_WRDATA_F2:RW:24:3:=0x04 PI_TDFI_PHY_WRDATA_F1:RW:16:3:=0x02 PI_TDFI_PHY_WRDATA_F0:RW:8:3:=0x02 PI_WRLAT_ADJ_F2:RW:0:8:=0x0a
-`define               DENALI_PI_154_DATA 32'b00000000_00001100_00000000_00110100 // PI_TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x000c PI_TDFI_CALVL_CC_F0:RW:0:10:=0x0034
-`define               DENALI_PI_155_DATA 32'b00000000_00010000_00000000_00111000 // PI_TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x0010 PI_TDFI_CALVL_CC_F1:RW:0:10:=0x0038
-`define               DENALI_PI_156_DATA 32'b00000000_00011100_00000000_01000100 // PI_TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x001c PI_TDFI_CALVL_CC_F2:RW:0:10:=0x0044
-`define               DENALI_PI_157_DATA 32'b00000000_00000001_00000000_00000001 // PI_CALVL_AREF_LP3_EN_F1:RW:24:1:=0x00 PI_CALVL_EN_F1:RW:16:2:=0x01 PI_CALVL_AREF_LP3_EN_F0:RW:8:1:=0x00 PI_CALVL_EN_F0:RW:0:2:=0x01
-`define               DENALI_PI_158_DATA 32'b00000000_00000001_00000000_00000001 // PI_TMRZ_F0:RW:16:5:=0x01 PI_CALVL_AREF_LP3_EN_F2:RW:8:1:=0x00 PI_CALVL_EN_F2:RW:0:2:=0x01
-`define               DENALI_PI_159_DATA 32'b00000000_00000001_00000000_00000101 // PI_TMRZ_F1:RW:16:5:=0x01 PI_TCAENT_F0:RW:0:14:=0x0005
-`define               DENALI_PI_160_DATA 32'b00000000_00000011_00000000_01100100 // PI_TMRZ_F2:RW:16:5:=0x03 PI_TCAENT_F1:RW:0:14:=0x0064
-`define               DENALI_PI_161_DATA 32'b00000001_00000000_00000001_10010000 // PI_TDFI_CASEL_F0:RW:24:5:=0x01 PI_TDFI_CACSCA_F0:RW:16:5:=0x00 PI_TCAENT_F2:RW:0:14:=0x0190
-`define               DENALI_PI_162_DATA 32'b00000000_00000110_00000000_00000110 // PI_TVREF_LONG_F0:RW:16:10:=0x0006 PI_TVREF_SHORT_F0:RW:0:10:=0x0006
-`define               DENALI_PI_163_DATA 32'b00000000_01100101_00000001_00000000 // PI_TVREF_SHORT_F1:RW:16:10:=0x0065 PI_TDFI_CASEL_F1:RW:8:5:=0x01 PI_TDFI_CACSCA_F1:RW:0:5:=0x00
-`define               DENALI_PI_164_DATA 32'b00000001_00000000_00000000_01100101 // PI_TDFI_CASEL_F2:RW:24:5:=0x01 PI_TDFI_CACSCA_F2:RW:16:5:=0x00 PI_TVREF_LONG_F1:RW:0:10:=0x0065
-`define               DENALI_PI_165_DATA 32'b00000001_10010001_00000001_10010001 // PI_TVREF_LONG_F2:RW:16:10:=0x0191 PI_TVREF_SHORT_F2:RW:0:10:=0x0191
-`define               DENALI_PI_166_DATA 32'b00011110_00011010_00011110_00011010 // PI_CALVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_CALVL_VREF_INITIAL_STOP_POINT_F0:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F0:RW:0:7:=0x1a
-`define               DENALI_PI_167_DATA 32'b00000001_00000001_00011110_00011010 // PI_CALVL_VREF_DELTA_F1:RW:24:4:=0x01 PI_CALVL_VREF_DELTA_F0:RW:16:4:=0x01 PI_CALVL_VREF_INITIAL_STOP_POINT_F2:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F2:RW:0:7:=0x1a
-`define               DENALI_PI_168_DATA 32'b00001010_00000111_00000110_00000001 // PI_TMRWCKEL_F0:RW:24:8:=0x0a PI_TXP_F0:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_CALVL_VREF_DELTA_F2:RW:0:4:=0x01
-`define               DENALI_PI_169_DATA 32'b00001010_00000111_00000110_00001101 // PI_TMRWCKEL_F1:RW:24:8:=0x0a PI_TXP_F1:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F1:RW:8:4:=0x06 PI_TCKELCK_F0:RW:0:5:=0x0d
-`define               DENALI_PI_170_DATA 32'b00011000_00001111_00001001_00001101 // PI_TMRWCKEL_F2:RW:24:8:=0x18 PI_TXP_F2:RW:16:5:=0x0f PI_TDFI_CALVL_STROBE_F2:RW:8:4:=0x09 PI_TCKELCK_F1:RW:0:5:=0x0d
-`define               DENALI_PI_171_DATA 32'b00000000_00000000_11000000_00010001 // PI_TDFI_INIT_START_F0:RW:8:10:=0x00c0 PI_TCKELCK_F2:RW:0:5:=0x11
-`define               DENALI_PI_172_DATA 32'b00000000_11000000_00010000_00000000 // PI_TDFI_INIT_START_F1:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000
-`define               DENALI_PI_173_DATA 32'b00000000_11000000_00010000_00000000 // PI_TDFI_INIT_START_F2:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000
-`define               DENALI_PI_174_DATA 32'b00000000_00000010_00010000_00000000 // PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000
-`define               DENALI_PI_175_DATA 32'b00000000_00010010_00000000_00000101 // PI_TCKEHDQS_F1:RW:16:6:=0x12 PI_TFC_F0:RW:0:10:=0x0005
-`define               DENALI_PI_176_DATA 32'b00000000_00011110_00000000_01100100 // PI_TCKEHDQS_F2:RW:16:6:=0x1e PI_TFC_F1:RW:0:10:=0x0064
-`define               DENALI_PI_177_DATA 32'b00000000_00000000_00000001_10010000 // PI_VREF_EN_F1:RW:24:2:=0x00 PI_VREF_EN_F0:RW:16:2:=0x00 PI_TFC_F2:RW:0:10:=0x0190
-`define               DENALI_PI_178_DATA 32'b00000000_00000000_00010001_00000000 // PI_TDFI_WDQLVL_WR_F0:RW:8:10:=0x0011 PI_VREF_EN_F2:RW:0:2:=0x00
-`define               DENALI_PI_179_DATA 32'b00011110_00011010_00000000_01010110 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F0:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F0:RW:0:10:=0x0056
-`define               DENALI_PI_180_DATA 32'b00000110_00000000_00000001_00000001 // PI_WDQLVL_CL_F0:RW:24:5:=0x06 PI_NTP_TRAIN_EN_F0:RW:16:2:=0x00 PI_WDQLVL_EN_F0:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F0:RW:0:4:=0x01
-`define               DENALI_PI_181_DATA 32'b00000000_00010011_00000010_00000100 // PI_TDFI_WDQLVL_WR_F1:RW:16:10:=0x0013 PI_WDQLVL_WRLAT_ADJ_F0:RW:8:8:=0x02 PI_WDQLVL_RDLAT_ADJ_F0:RW:0:8:=0x04
-`define               DENALI_PI_182_DATA 32'b00011110_00011010_00000000_01011000 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F1:RW:0:10:=0x0058
-`define               DENALI_PI_183_DATA 32'b00000001_00000000_00000001_00000001 // PI_WDQLVL_CL_F1:RW:24:5:=0x01 PI_NTP_TRAIN_EN_F1:RW:16:2:=0x00 PI_WDQLVL_EN_F1:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F1:RW:0:4:=0x01
-`define               DENALI_PI_184_DATA 32'b00000000_00101100_00000100_00001000 // PI_TDFI_WDQLVL_WR_F2:RW:16:10:=0x002c PI_WDQLVL_WRLAT_ADJ_F1:RW:8:8:=0x04 PI_WDQLVL_RDLAT_ADJ_F1:RW:0:8:=0x08
-`define               DENALI_PI_185_DATA 32'b00011110_00011010_00000000_01100001 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F2:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F2:RW:0:10:=0x0061
-`define               DENALI_PI_186_DATA 32'b00010011_00000000_00000001_00000001 // PI_WDQLVL_CL_F2:RW:24:5:=0x13 PI_NTP_TRAIN_EN_F2:RW:16:2:=0x00 PI_WDQLVL_EN_F2:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F2:RW:0:4:=0x01
-`define               DENALI_PI_187_DATA 32'b00000000_00000000_00001010_00010111 // PI_RD_DBI_LEVEL_EN_F1:RW:24:2:=0x00 PI_RD_DBI_LEVEL_EN_F0:RW:16:2:=0x00 PI_WDQLVL_WRLAT_ADJ_F2:RW:8:8:=0x0a PI_WDQLVL_RDLAT_ADJ_F2:RW:0:8:=0x17
-`define               DENALI_PI_188_DATA 32'b00000100_00000100_00001000_00000000 // PI_TRCD_F0:RW:24:8:=0x04 PI_TRP_F0:RW:16:8:=0x04 PI_TRTP_F0:RW:8:8:=0x08 PI_RD_DBI_LEVEL_EN_F2:RW:0:2:=0x00
-`define               DENALI_PI_189_DATA 32'b00000000_00000100_00000001_00000000 // PI_TWR_F0:RW:16:8:=0x04 PI_TWTR_F0:RW:8:6:=0x01 PI_TCCD_L_F0:RW:0:5:=0x00
-`define               DENALI_PI_190_DATA 32'b00000011_00000000_00000010_01110111 // PI_TRAS_MIN_F0:RW:24:8:=0x03 PI_TRAS_MAX_F0:RW:0:20:=0x000277
-`define               DENALI_PI_191_DATA 32'b00001010_00000011_00100000_00000001 // PI_TMRD_F0:RW:24:8:=0x0a PI_TSR_F0:RW:16:8:=0x03 PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01
-`define               DENALI_PI_192_DATA 32'b00000000_00000000_00001010_00001010 // PI_TMRD_PAR_F0:RW:24:8:=0x00 PI_TMOD_PAR_F0:RW:16:8:=0x00 PI_TMOD_F0:RW:8:8:=0x0a PI_TMRW_F0:RW:0:8:=0x0a
-`define               DENALI_PI_193_DATA 32'b00000000_00001000_00001001_00001000 // PI_TCCD_L_F1:RW:24:5:=0x00 PI_TRCD_F1:RW:16:8:=0x08 PI_TRP_F1:RW:8:8:=0x09 PI_TRTP_F1:RW:0:8:=0x08
-`define               DENALI_PI_194_DATA 32'b00000000_00000000_00001001_00000001 // PI_TWR_F1:RW:8:8:=0x09 PI_TWTR_F1:RW:0:6:=0x01
-`define               DENALI_PI_195_DATA 32'b00010001_00000000_00110001_01011100 // PI_TRAS_MIN_F1:RW:24:8:=0x11 PI_TRAS_MAX_F1:RW:0:20:=0x00315c
-`define               DENALI_PI_196_DATA 32'b00001010_00000110_00100000_00000010 // PI_TMRD_F1:RW:24:8:=0x0a PI_TSR_F1:RW:16:8:=0x06 PI_TCCDMW_F1:RW:8:6:=0x20 PI_TDQSCK_MAX_F1:RW:0:4:=0x02
-`define               DENALI_PI_197_DATA 32'b00000000_00000000_00001010_00001010 // PI_TMRD_PAR_F1:RW:24:8:=0x00 PI_TMOD_PAR_F1:RW:16:8:=0x00 PI_TMOD_F1:RW:8:8:=0x0a PI_TMRW_F1:RW:0:8:=0x0a
-`define               DENALI_PI_198_DATA 32'b00000000_00011101_00100010_00001100 // PI_TCCD_L_F2:RW:24:5:=0x00 PI_TRCD_F2:RW:16:8:=0x1d PI_TRP_F2:RW:8:8:=0x22 PI_TRTP_F2:RW:0:8:=0x0c
-`define               DENALI_PI_199_DATA 32'b00000000_00000000_00011110_00010010 // PI_TWR_F2:RW:8:8:=0x1e PI_TWTR_F2:RW:0:6:=0x12
-`define               DENALI_PI_200_DATA 32'b01000100_00000000_11000101_01110000 // PI_TRAS_MIN_F2:RW:24:8:=0x44 PI_TRAS_MAX_F2:RW:0:20:=0x00c570
-`define               DENALI_PI_201_DATA 32'b00010111_00011000_00100000_00000110 // PI_TMRD_F2:RW:24:8:=0x17 PI_TSR_F2:RW:16:8:=0x18 PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x06
-`define               DENALI_PI_202_DATA 32'b00000000_00000000_00010111_00010000 // PI_TMRD_PAR_F2:RW:24:8:=0x00 PI_TMOD_PAR_F2:RW:16:8:=0x00 PI_TMOD_F2:RW:8:8:=0x17 PI_TMRW_F2:RW:0:8:=0x10
-`define               DENALI_PI_203_DATA 32'b00000000_00000000_00000000_10001100 // PI_TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x00008c
-`define               DENALI_PI_204_DATA 32'b00000000_00000000_00000101_01111000 // PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578
-`define               DENALI_PI_205_DATA 32'b00000000_00000000_00001100_00100000 // PI_TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x000c20
-`define               DENALI_PI_206_DATA 32'b00000000_00000000_01111001_01000000 // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00007940
-`define               DENALI_PI_207_DATA 32'b00000000_00000000_00110000_10110000 // PI_TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x0030b0
-`define               DENALI_PI_208_DATA 32'b00000000_00000001_11100110_11100000 // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0001e6e0
-`define               DENALI_PI_209_DATA 32'b00000000_01110011_00000000_00000110 // PI_TXSR_F1:RW:16:16:=0x0073 PI_TXSR_F0:RW:0:16:=0x0006
-`define               DENALI_PI_210_DATA 32'b00000011_00000011_00000001_11001100 // PI_TEXCKE_F1:RW:24:6:=0x03 PI_TEXCKE_F0:RW:16:6:=0x03 PI_TXSR_F2:RW:0:16:=0x01cc
-`define               DENALI_PI_211_DATA 32'b00000000_00000000_00000000_00000011 // PI_TDLL_F0:RW:8:16:=0x0000 PI_TEXCKE_F2:RW:0:6:=0x03
-`define               DENALI_PI_212_DATA 32'b00000000_00000000_00000000_00000000 // PI_TDLL_F2:RW:16:16:=0x0000 PI_TDLL_F1:RW:0:16:=0x0000
-`define               DENALI_PI_213_DATA 32'b00000000_00000000_00000000_00000100 // PI_TINIT_F0:RW:0:24:=0x000004
-`define               DENALI_PI_214_DATA 32'b00000000_00000000_00000000_00000001 // PI_TINIT3_F0:RW:0:24:=0x000001
-`define               DENALI_PI_215_DATA 32'b00000000_00000000_00000000_00000101 // PI_TINIT4_F0:RW:0:24:=0x000005
-`define               DENALI_PI_216_DATA 32'b00000000_00000000_00000000_00000010 // PI_TINIT5_F0:RW:0:24:=0x000002
-`define               DENALI_PI_217_DATA 32'b00000000_00000000_00000000_00000110 // PI_TXSNR_F0:RW:0:16:=0x0006
-`define               DENALI_PI_218_DATA 32'b00000000_00000000_00000000_01010000 // PI_TINIT_F1:RW:0:24:=0x000050
-`define               DENALI_PI_219_DATA 32'b00000000_00000000_00000000_00000001 // PI_TINIT3_F1:RW:0:24:=0x000001
-`define               DENALI_PI_220_DATA 32'b00000000_00000000_00000000_00000101 // PI_TINIT4_F1:RW:0:24:=0x000005
-`define               DENALI_PI_221_DATA 32'b00000000_00000000_00000000_00101000 // PI_TINIT5_F1:RW:0:24:=0x000028
-`define               DENALI_PI_222_DATA 32'b00000000_00000000_00000000_01110011 // PI_TXSNR_F1:RW:0:16:=0x0073
-`define               DENALI_PI_223_DATA 32'b00000000_00000000_00000001_01000000 // PI_TINIT_F2:RW:0:24:=0x000140
-`define               DENALI_PI_224_DATA 32'b00000000_00000000_00000000_00000001 // PI_TINIT3_F2:RW:0:24:=0x000001
-`define               DENALI_PI_225_DATA 32'b00000000_00000000_00000000_00000101 // PI_TINIT4_F2:RW:0:24:=0x000005
-`define               DENALI_PI_226_DATA 32'b00000000_00000000_00000000_10100000 // PI_TINIT5_F2:RW:0:24:=0x0000a0
-`define               DENALI_PI_227_DATA 32'b00000001_00000000_00000001_11001100 // RESERVED:RW:16:12:=0x0100 PI_TXSNR_F2:RW:0:16:=0x01cc
-`define               DENALI_PI_228_DATA 32'b00000000_00010100_00000000_01000000 // PI_TZQCAL_F0:RW:16:12:=0x0014 RESERVED:RW:0:12:=0x0040
-`define               DENALI_PI_229_DATA 32'b00000000_00000001_00000000_00000001 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F0:RW:0:7:=0x01
-`define               DENALI_PI_230_DATA 32'b00000001_10010000_00000000_01000000 // PI_TZQCAL_F1:RW:16:12:=0x0190 RESERVED:RW:0:12:=0x0040
-`define               DENALI_PI_231_DATA 32'b00000000_00000001_00000000_00001100 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F1:RW:0:7:=0x0c
-`define               DENALI_PI_232_DATA 32'b00000110_01000000_00000000_01000000 // PI_TZQCAL_F2:RW:16:12:=0x0640 RESERVED:RW:0:12:=0x0040
-`define               DENALI_PI_233_DATA 32'b00000000_00000000_00000011_00110000 // RESERVED:RW:8:12:=0x0003 PI_TZQLAT_F2:RW:0:7:=0x30
-`define               DENALI_PI_234_DATA 32'b00000000_01010000_00000000_00010100 // RESERVED:RW:16:12:=0x0050 RESERVED:RW:0:12:=0x0014
-`define               DENALI_PI_235_DATA 32'b00000001_00000001_00000001_00000001 // PI_MEMDATA_RATIO_3:RW:24:3:=0x01 PI_MEMDATA_RATIO_2:RW:16:3:=0x01 PI_MEMDATA_RATIO_1:RW:8:3:=0x01 PI_MEMDATA_RATIO_0:RW:0:3:=0x01
-`define               DENALI_PI_236_DATA 32'b00000010_00000010_00000001_00000001 // PI_ODT_WR_MAP_CS1:RW:24:4:=0x02 PI_ODT_RD_MAP_CS1:RW:16:4:=0x02 PI_ODT_WR_MAP_CS0:RW:8:4:=0x01 PI_ODT_RD_MAP_CS0:RW:0:4:=0x01
-`define               DENALI_PI_237_DATA 32'b00001000_00001000_00000100_00000100 // PI_ODT_WR_MAP_CS3:RW:24:4:=0x08 PI_ODT_RD_MAP_CS3:RW:16:4:=0x08 PI_ODT_WR_MAP_CS2:RW:8:4:=0x04 PI_ODT_RD_MAP_CS2:RW:0:4:=0x04
-`define               DENALI_PI_238_DATA 32'b01100111_01100111_01100111_01100111 // PI_VREF_VAL_DEV0_3:RW:24:7:=0x67 PI_VREF_VAL_DEV0_2:RW:16:7:=0x67 PI_VREF_VAL_DEV0_1:RW:8:7:=0x67 PI_VREF_VAL_DEV0_0:RW:0:7:=0x67
-`define               DENALI_PI_239_DATA 32'b01100111_01100111_01100111_01100111 // PI_VREF_VAL_DEV1_3:RW:24:7:=0x67 PI_VREF_VAL_DEV1_2:RW:16:7:=0x67 PI_VREF_VAL_DEV1_1:RW:8:7:=0x67 PI_VREF_VAL_DEV1_0:RW:0:7:=0x67
-`define               DENALI_PI_240_DATA 32'b01100111_01100111_01100111_01100111 // PI_VREF_VAL_DEV2_3:RW:24:7:=0x67 PI_VREF_VAL_DEV2_2:RW:16:7:=0x67 PI_VREF_VAL_DEV2_1:RW:8:7:=0x67 PI_VREF_VAL_DEV2_0:RW:0:7:=0x67
-`define               DENALI_PI_241_DATA 32'b01100111_01100111_01100111_01100111 // PI_VREF_VAL_DEV3_3:RW:24:7:=0x67 PI_VREF_VAL_DEV3_2:RW:16:7:=0x67 PI_VREF_VAL_DEV3_1:RW:8:7:=0x67 PI_VREF_VAL_DEV3_0:RW:0:7:=0x67
-`define               DENALI_PI_242_DATA 32'b00000000_00000000_00000000_00000000 // PI_SLICE_PER_DEV_3:RW:24:2:=0x00 PI_SLICE_PER_DEV_2:RW:16:2:=0x00 PI_SLICE_PER_DEV_1:RW:8:2:=0x00 PI_SLICE_PER_DEV_0:RW:0:2:=0x00
-`define               DENALI_PI_243_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR6_VREF_0_3:RD:24:6:=0x00 PI_MR6_VREF_0_2:RD:16:6:=0x00 PI_MR6_VREF_0_1:RD:8:6:=0x00 PI_MR6_VREF_0_0:RD:0:6:=0x00
-`define               DENALI_PI_244_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR6_VREF_1_3:RD:24:6:=0x00 PI_MR6_VREF_1_2:RD:16:6:=0x00 PI_MR6_VREF_1_1:RD:8:6:=0x00 PI_MR6_VREF_1_0:RD:0:6:=0x00
-`define               DENALI_PI_245_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR6_VREF_2_3:RD:24:6:=0x00 PI_MR6_VREF_2_2:RD:16:6:=0x00 PI_MR6_VREF_2_1:RD:8:6:=0x00 PI_MR6_VREF_2_0:RD:0:6:=0x00
-`define               DENALI_PI_246_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR6_VREF_3_3:RD:24:6:=0x00 PI_MR6_VREF_3_2:RD:16:6:=0x00 PI_MR6_VREF_3_1:RD:8:6:=0x00 PI_MR6_VREF_3_0:RD:0:6:=0x00
-`define               DENALI_PI_247_DATA 32'b00000000_00000000_01010101_00000000 // PI_MR17_DATA_0:RW:24:8:=0x00 PI_MR16_DATA_0:RW:16:8:=0x00 PI_MR15_DATA_0:RW:8:8:=0x55 PI_MR13_DATA_0:RW+:0:8:=0x00
-`define               DENALI_PI_248_DATA 32'b00000000_00000000_01011010_00000000 // PI_MR32_DATA_0:RW:8:17:=0x00005a PI_MR20_DATA_0:RW:0:8:=0x00
-`define               DENALI_PI_249_DATA 32'b00000000_01010101_00000000_00111100 // PI_MR16_DATA_1:RW:24:8:=0x00 PI_MR15_DATA_1:RW:16:8:=0x55 PI_MR13_DATA_1:RW+:8:8:=0x00 PI_MR40_DATA_0:RW:0:8:=0x3c
-`define               DENALI_PI_250_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR20_DATA_1:RW:8:8:=0x00 PI_MR17_DATA_1:RW:0:8:=0x00
-`define               DENALI_PI_251_DATA 32'b00111100_00000000_00000000_01011010 // PI_MR40_DATA_1:RW:24:8:=0x3c PI_MR32_DATA_1:RW:0:17:=0x00005a
-`define               DENALI_PI_252_DATA 32'b00000000_00000000_01010101_00000000 // PI_MR17_DATA_2:RW:24:8:=0x00 PI_MR16_DATA_2:RW:16:8:=0x00 PI_MR15_DATA_2:RW:8:8:=0x55 PI_MR13_DATA_2:RW+:0:8:=0x00
-`define               DENALI_PI_253_DATA 32'b00000000_00000000_01011010_00000000 // PI_MR32_DATA_2:RW:8:17:=0x00005a PI_MR20_DATA_2:RW:0:8:=0x00
-`define               DENALI_PI_254_DATA 32'b00000000_01010101_00000000_00111100 // PI_MR16_DATA_3:RW:24:8:=0x00 PI_MR15_DATA_3:RW:16:8:=0x55 PI_MR13_DATA_3:RW+:8:8:=0x00 PI_MR40_DATA_2:RW:0:8:=0x3c
-`define               DENALI_PI_255_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR20_DATA_3:RW:8:8:=0x00 PI_MR17_DATA_3:RW:0:8:=0x00
-`define               DENALI_PI_256_DATA 32'b00111100_00000000_00000000_01011010 // PI_MR40_DATA_3:RW:24:8:=0x3c PI_MR32_DATA_3:RW:0:17:=0x00005a
-`define               DENALI_PI_257_DATA 32'b00011000_00010111_00010110_00010101 // PI_CKE_MUX_3:RW_D:24:5:=0x18 PI_CKE_MUX_2:RW_D:16:5:=0x17 PI_CKE_MUX_1:RW_D:8:5:=0x16 PI_CKE_MUX_0:RW_D:0:5:=0x15
-`define               DENALI_PI_258_DATA 32'b00010100_00010011_00010010_00010001 // PI_CS_MUX_3:RW_D:24:5:=0x14 PI_CS_MUX_2:RW_D:16:5:=0x13 PI_CS_MUX_1:RW_D:8:5:=0x12 PI_CS_MUX_0:RW_D:0:5:=0x11
-`define               DENALI_PI_259_DATA 32'b00000111_00000110_00000101_00000100 // PI_ODT_MUX_3:RW_D:24:5:=0x07 PI_ODT_MUX_2:RW_D:16:5:=0x06 PI_ODT_MUX_1:RW_D:8:5:=0x05 PI_ODT_MUX_0:RW_D:0:5:=0x04
-`define               DENALI_PI_260_DATA 32'b00000011_00000010_00000001_00000000 // PI_RESET_N_MUX_3:RW_D:24:5:=0x03 PI_RESET_N_MUX_2:RW_D:16:5:=0x02 PI_RESET_N_MUX_1:RW_D:8:5:=0x01 PI_RESET_N_MUX_0:RW_D:0:5:=0x00
-`define               DENALI_PI_261_DATA 32'b00000000_00000000_00000000_00000000 // PI_MRSINGLE_DATA_0:RW:0:17:=0x000000
-`define               DENALI_PI_262_DATA 32'b00000000_00000000_00000000_00000000 // PI_MRSINGLE_DATA_1:RW:0:17:=0x000000
-`define               DENALI_PI_263_DATA 32'b00000000_00000000_00000000_00000000 // PI_MRSINGLE_DATA_2:RW:0:17:=0x000000
-`define               DENALI_PI_264_DATA 32'b00000001_00000000_00000000_00000000 // PI_ZQ_CAL_START_MAP_0:RW_D:24:4:=0x01 PI_MRSINGLE_DATA_3:RW:0:17:=0x000000
-`define               DENALI_PI_265_DATA 32'b00000100_00000010_00000010_00000001 // PI_ZQ_CAL_START_MAP_2:RW_D:24:4:=0x04 PI_ZQ_CAL_LATCH_MAP_1:RW_D:16:4:=0x02 PI_ZQ_CAL_START_MAP_1:RW_D:8:4:=0x02 PI_ZQ_CAL_LATCH_MAP_0:RW_D:0:4:=0x01
-`define               DENALI_PI_266_DATA 32'b00000000_00001000_00001000_00000100 // PI_ZQ_CAL_LATCH_MAP_3:RW_D:16:4:=0x08 PI_ZQ_CAL_START_MAP_3:RW_D:8:4:=0x08 PI_ZQ_CAL_LATCH_MAP_2:RW_D:0:4:=0x04
-`define               DENALI_PI_267_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F0_0:RW:0:17:=0x000000
-`define               DENALI_PI_268_DATA 32'b00000000_00000000_00000000_00000100 // PI_MR1_DATA_F0_0:RW+:0:17:=0x000004
-`define               DENALI_PI_269_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR2_DATA_F0_0:RW+:0:17:=0x000000
-`define               DENALI_PI_270_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F0_0:RW+:0:17:=0x000031
-`define               DENALI_PI_271_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F0_0:RW:0:17:=0x000031
-`define               DENALI_PI_272_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F0_0:RW:0:17:=0x000000
-`define               DENALI_PI_273_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F0_0:RW+:24:8:=0x00 PI_MR6_DATA_F0_0:RW+:0:17:=0x000000
-`define               DENALI_PI_274_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F0_0:RW+:16:8:=0x00 PI_MR14_DATA_F0_0:RW+:8:8:=0x4d PI_MR12_DATA_F0_0:RW+:0:8:=0x4d
-`define               DENALI_PI_275_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F1_0:RW:0:17:=0x000000
-`define               DENALI_PI_276_DATA 32'b00000000_00000000_00000000_00010100 // PI_MR1_DATA_F1_0:RW+:0:17:=0x000014
-`define               DENALI_PI_277_DATA 32'b00000000_00000000_00000000_00001001 // PI_MR2_DATA_F1_0:RW+:0:17:=0x000009
-`define               DENALI_PI_278_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F1_0:RW+:0:17:=0x000031
-`define               DENALI_PI_279_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F1_0:RW:0:17:=0x000031
-`define               DENALI_PI_280_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F1_0:RW:0:17:=0x000000
-`define               DENALI_PI_281_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F1_0:RW+:24:8:=0x00 PI_MR6_DATA_F1_0:RW+:0:17:=0x000000
-`define               DENALI_PI_282_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F1_0:RW+:16:8:=0x00 PI_MR14_DATA_F1_0:RW+:8:8:=0x4d PI_MR12_DATA_F1_0:RW+:0:8:=0x4d
-`define               DENALI_PI_283_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F2_0:RW:0:17:=0x000000
-`define               DENALI_PI_284_DATA 32'b00000000_00000000_00000000_01010100 // PI_MR1_DATA_F2_0:RW+:0:17:=0x000054
-`define               DENALI_PI_285_DATA 32'b00000000_00000000_00000000_00101101 // PI_MR2_DATA_F2_0:RW+:0:17:=0x00002d
-`define               DENALI_PI_286_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F2_0:RW+:0:17:=0x000031
-`define               DENALI_PI_287_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F2_0:RW:0:17:=0x000031
-`define               DENALI_PI_288_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F2_0:RW:0:17:=0x000000
-`define               DENALI_PI_289_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F2_0:RW+:24:8:=0x00 PI_MR6_DATA_F2_0:RW+:0:17:=0x000000
-`define               DENALI_PI_290_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F2_0:RW+:16:8:=0x00 PI_MR14_DATA_F2_0:RW+:8:8:=0x4d PI_MR12_DATA_F2_0:RW+:0:8:=0x4d
-`define               DENALI_PI_291_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F0_1:RW:0:17:=0x000000
-`define               DENALI_PI_292_DATA 32'b00000000_00000000_00000000_00000100 // PI_MR1_DATA_F0_1:RW+:0:17:=0x000004
-`define               DENALI_PI_293_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR2_DATA_F0_1:RW+:0:17:=0x000000
-`define               DENALI_PI_294_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F0_1:RW+:0:17:=0x000031
-`define               DENALI_PI_295_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F0_1:RW:0:17:=0x000031
-`define               DENALI_PI_296_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F0_1:RW:0:17:=0x000000
-`define               DENALI_PI_297_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR6_DATA_F0_1:RW+:0:17:=0x000000
-`define               DENALI_PI_298_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F0_1:RW+:16:8:=0x00 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d
-`define               DENALI_PI_299_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F1_1:RW:0:17:=0x000000
-`define               DENALI_PI_300_DATA 32'b00000000_00000000_00000000_00010100 // PI_MR1_DATA_F1_1:RW+:0:17:=0x000014
-`define               DENALI_PI_301_DATA 32'b00000000_00000000_00000000_00001001 // PI_MR2_DATA_F1_1:RW+:0:17:=0x000009
-`define               DENALI_PI_302_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F1_1:RW+:0:17:=0x000031
-`define               DENALI_PI_303_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F1_1:RW:0:17:=0x000031
-`define               DENALI_PI_304_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F1_1:RW:0:17:=0x000000
-`define               DENALI_PI_305_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F1_1:RW+:24:8:=0x00 PI_MR6_DATA_F1_1:RW+:0:17:=0x000000
-`define               DENALI_PI_306_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F1_1:RW+:16:8:=0x00 PI_MR14_DATA_F1_1:RW+:8:8:=0x4d PI_MR12_DATA_F1_1:RW+:0:8:=0x4d
-`define               DENALI_PI_307_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F2_1:RW:0:17:=0x000000
-`define               DENALI_PI_308_DATA 32'b00000000_00000000_00000000_01010100 // PI_MR1_DATA_F2_1:RW+:0:17:=0x000054
-`define               DENALI_PI_309_DATA 32'b00000000_00000000_00000000_00101101 // PI_MR2_DATA_F2_1:RW+:0:17:=0x00002d
-`define               DENALI_PI_310_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F2_1:RW+:0:17:=0x000031
-`define               DENALI_PI_311_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F2_1:RW:0:17:=0x000031
-`define               DENALI_PI_312_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F2_1:RW:0:17:=0x000000
-`define               DENALI_PI_313_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR6_DATA_F2_1:RW+:0:17:=0x000000
-`define               DENALI_PI_314_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F2_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d
-`define               DENALI_PI_315_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F0_2:RW:0:17:=0x000000
-`define               DENALI_PI_316_DATA 32'b00000000_00000000_00000000_00000100 // PI_MR1_DATA_F0_2:RW+:0:17:=0x000004
-`define               DENALI_PI_317_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR2_DATA_F0_2:RW+:0:17:=0x000000
-`define               DENALI_PI_318_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F0_2:RW+:0:17:=0x000031
-`define               DENALI_PI_319_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F0_2:RW:0:17:=0x000031
-`define               DENALI_PI_320_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F0_2:RW:0:17:=0x000000
-`define               DENALI_PI_321_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F0_2:RW+:24:8:=0x00 PI_MR6_DATA_F0_2:RW+:0:17:=0x000000
-`define               DENALI_PI_322_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F0_2:RW+:16:8:=0x00 PI_MR14_DATA_F0_2:RW+:8:8:=0x4d PI_MR12_DATA_F0_2:RW+:0:8:=0x4d
-`define               DENALI_PI_323_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F1_2:RW:0:17:=0x000000
-`define               DENALI_PI_324_DATA 32'b00000000_00000000_00000000_00010100 // PI_MR1_DATA_F1_2:RW+:0:17:=0x000014
-`define               DENALI_PI_325_DATA 32'b00000000_00000000_00000000_00001001 // PI_MR2_DATA_F1_2:RW+:0:17:=0x000009
-`define               DENALI_PI_326_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F1_2:RW+:0:17:=0x000031
-`define               DENALI_PI_327_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F1_2:RW:0:17:=0x000031
-`define               DENALI_PI_328_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F1_2:RW:0:17:=0x000000
-`define               DENALI_PI_329_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F1_2:RW+:24:8:=0x00 PI_MR6_DATA_F1_2:RW+:0:17:=0x000000
-`define               DENALI_PI_330_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F1_2:RW+:16:8:=0x00 PI_MR14_DATA_F1_2:RW+:8:8:=0x4d PI_MR12_DATA_F1_2:RW+:0:8:=0x4d
-`define               DENALI_PI_331_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F2_2:RW:0:17:=0x000000
-`define               DENALI_PI_332_DATA 32'b00000000_00000000_00000000_01010100 // PI_MR1_DATA_F2_2:RW+:0:17:=0x000054
-`define               DENALI_PI_333_DATA 32'b00000000_00000000_00000000_00101101 // PI_MR2_DATA_F2_2:RW+:0:17:=0x00002d
-`define               DENALI_PI_334_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F2_2:RW+:0:17:=0x000031
-`define               DENALI_PI_335_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F2_2:RW:0:17:=0x000031
-`define               DENALI_PI_336_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F2_2:RW:0:17:=0x000000
-`define               DENALI_PI_337_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F2_2:RW+:24:8:=0x00 PI_MR6_DATA_F2_2:RW+:0:17:=0x000000
-`define               DENALI_PI_338_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F2_2:RW+:16:8:=0x00 PI_MR14_DATA_F2_2:RW+:8:8:=0x4d PI_MR12_DATA_F2_2:RW+:0:8:=0x4d
-`define               DENALI_PI_339_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F0_3:RW:0:17:=0x000000
-`define               DENALI_PI_340_DATA 32'b00000000_00000000_00000000_00000100 // PI_MR1_DATA_F0_3:RW+:0:17:=0x000004
-`define               DENALI_PI_341_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR2_DATA_F0_3:RW+:0:17:=0x000000
-`define               DENALI_PI_342_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F0_3:RW+:0:17:=0x000031
-`define               DENALI_PI_343_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F0_3:RW:0:17:=0x000031
-`define               DENALI_PI_344_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F0_3:RW:0:17:=0x000000
-`define               DENALI_PI_345_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F0_3:RW+:24:8:=0x00 PI_MR6_DATA_F0_3:RW+:0:17:=0x000000
-`define               DENALI_PI_346_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F0_3:RW+:16:8:=0x00 PI_MR14_DATA_F0_3:RW+:8:8:=0x4d PI_MR12_DATA_F0_3:RW+:0:8:=0x4d
-`define               DENALI_PI_347_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F1_3:RW:0:17:=0x000000
-`define               DENALI_PI_348_DATA 32'b00000000_00000000_00000000_00010100 // PI_MR1_DATA_F1_3:RW+:0:17:=0x000014
-`define               DENALI_PI_349_DATA 32'b00000000_00000000_00000000_00001001 // PI_MR2_DATA_F1_3:RW+:0:17:=0x000009
-`define               DENALI_PI_350_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F1_3:RW+:0:17:=0x000031
-`define               DENALI_PI_351_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F1_3:RW:0:17:=0x000031
-`define               DENALI_PI_352_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F1_3:RW:0:17:=0x000000
-`define               DENALI_PI_353_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR6_DATA_F1_3:RW+:0:17:=0x000000
-`define               DENALI_PI_354_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F1_3:RW+:16:8:=0x00 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d
-`define               DENALI_PI_355_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR0_DATA_F2_3:RW:0:17:=0x000000
-`define               DENALI_PI_356_DATA 32'b00000000_00000000_00000000_01010100 // PI_MR1_DATA_F2_3:RW+:0:17:=0x000054
-`define               DENALI_PI_357_DATA 32'b00000000_00000000_00000000_00101101 // PI_MR2_DATA_F2_3:RW+:0:17:=0x00002d
-`define               DENALI_PI_358_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR3_DATA_F2_3:RW+:0:17:=0x000031
-`define               DENALI_PI_359_DATA 32'b00000000_00000000_00000000_00110001 // PI_MR4_DATA_F2_3:RW:0:17:=0x000031
-`define               DENALI_PI_360_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR5_DATA_F2_3:RW:0:17:=0x000000
-`define               DENALI_PI_361_DATA 32'b00000000_00000000_00000000_00000000 // PI_MR11_DATA_F2_3:RW+:24:8:=0x00 PI_MR6_DATA_F2_3:RW+:0:17:=0x000000
-`define               DENALI_PI_362_DATA 32'b00000000_00000000_01001101_01001101 // PI_MR22_DATA_F2_3:RW+:16:8:=0x00 PI_MR14_DATA_F2_3:RW+:8:8:=0x4d PI_MR12_DATA_F2_3:RW+:0:8:=0x4d
-//* ********************************************************
-//* The below are used only for simulation phy purposes.
-//* Please ignore if using integrated Cadence PHY.
-//* SimulationValues {{{
-//* ********************************************************
-`define SIM_PHY_VALS_DEFINED 1 // Global define for simulation
-`define                        SMALL_TREF_ENABLE 8'h0 // CTL
-`define                                  MR8_VAL 8'h10 // CTL
-`define                                  MR0_VAL 8'h0 // CTL
-`define                          MR0_RL3_SUPPORT 2'h0 // CTL
-`define                            ODT_RD_TIMING 6'h0 // CTL
-`define                                  TAC_MIN 6'h0 // CTL
-`define                                  TAC_MAX 6'h0 // CTL
-`define               LPDDR1_PD_CLK_GATE_DISABLE 1'h0 // CTL
-`define                          LPDDR1_ATTACHED 1'h0 // CTL
-//* ********************************************************
-//* SimulationValues }}}
-//* ********************************************************

+ 0 - 434
ddrphy_cfg/memory/jedec_lpddr4_16gb_3200/regconfig_sim_800_cl14_bl16/regconfig.h.sim_PI_bak.h

@@ -1,434 +0,0 @@
-
-/* ****************************************************************
- *        CADENCE                    Copyright (c) 2001-2018      *
- *                                   Cadence Design Systems, Inc. *
- *                                   All rights reserved.         *
- ******************************************************************
- *  The values calculated from this script are meant to be        *
- *  representative programmings.   The values may not reflect the *
- *  actual required programming for production use.   Please      *
- *  closely review all programmed values for technical accuracy   *
- *  before use in production parts.                               *
- ******************************************************************
- *                                                                 
- *   Module:         regconfig.h
- *   Documentation:  Register programming header file
- *
- ******************************************************************
- ******************************************************************
- * WARNING:  This file was automatically generated.  Manual
- * editing may result in undetermined behavior.
- ******************************************************************
- ******************************************************************/
-// REL: sifive.shanghai.n1-VIC_DDR__20180206
-
-
-//`timescale 10ps/10ps
-
-// ********************************************************************
-// Option: IP    : IP Mode                       = PI
-// Option: BL    : Burst Length                  = 16
-// Option: CL    : CAS Latency                   = 14
-// Option: MHZ   : Simulation MHz                = 800
-// Option: AP    : Auto Precharge Mode     (0/1) = 0
-// Option: DLLBP : DLL Bypass Mode         (0/1) = 0
-// Option: HALF  : Half-Memory Support     (0/1) = 0
-// Option: RDIMM : Registered Dimm Support (0/1) = 0
-// Option: AL    : Additive Latency              = 0
-// Option: PREAM : Preamble Support    (0/1/2/3) = 0
-// Option: BOF   : Burst On the Fly        (0/1) = 0
-// Option: WLS   : Write Latency Set       (0/1) = 0
-// Option: TCK   : Simulation period in ns       = 
-// Option: WRDBIEN : Write DBI Enable       (0/1) = 0
-// Option: RDDBIEN : Read DBI Enable       (0/1) = 0
-// Option: RDPSTMBLE : RD Postamble En      (0/1) = 0
-// Option: WRPSTMBLE : WR Postamble En      (0/1) = 0
-// Option: CRC : CRC En      (0/1) = 0
-// Option: SOMA  : Memory-SOMA file(s)           = /proj/iprel/sifive.shanghai.n1-VIC_DDR/sifive.shanghai.n1-VIC_DDR__20180201/mcip/mem/sifive.shanghai.n1-VIC_DDR/memory/jedec_lpddr4_16gb_3200/memory.xml.sim
-// Option: PL    : CA Parity Latency              = -1
-// ********************************************************************
-// Memory: jedec_lpddr4_16gb_3200
-// ********************************************************************
-
-
-#define                DENALI_PI_00_DATA 0b00000000000000000000101100000000 // PI_VERSION:RD:16:16:=0x0000 PI_DRAM_CLASS:RW:8:4:=0x0b PI_START:RW:0:1:=0x00
-#define                DENALI_PI_01_DATA 0b00000000000000000000000100000001 // PI_ONBUS_MBIST:RW:24:1:=0x00 PI_NOTCARE_PHYUPD:RW:16:1:=0x00 PI_INIT_LVL_EN:RW:8:1:=0x01 PI_NORMAL_LVL_SEQ:RW:0:1:=0x01
-#define                DENALI_PI_02_DATA 0b00000000011001000000000000000000 // PI_TRAIN_ALL_FREQ_REQ:WR:24:1:=0x00 RESERVED:RW_D:16:8:=0x64 PI_TCMD_GAP:RW:0:16:=0x0000
-#define                DENALI_PI_03_DATA 0b00000000000000000000000000000001 // PI_DFI_PHYMSTR_STATE_SEL_R:RW:24:1:=0x00 PI_DFI_PHYMSTR_CS_STATE_R:RW:16:1:=0x00 PI_DFI_PHYMSTR_TYPE:RW:8:2:=0x00 PI_DFI_VERSION:RW:0:1:=0x01
-#define                DENALI_PI_04_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYMSTR_MAX:RD:0:32:=0x00000000
-#define                DENALI_PI_05_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYMSTR_RESP:RD:0:20:=0x000000
-#define                DENALI_PI_06_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYUPD_RESP:RD:0:20:=0x000000
-#define                DENALI_PI_07_DATA 0b00000000000000000000000000000000 // PI_TDFI_PHYUPD_MAX:RD:0:32:=0x00000000
-#define                DENALI_PI_08_DATA 0b00000000000000000000000000000001 // PI_EXIT_AFTER_INIT_CALVL:RW_D:0:1:=0x01
-#define                DENALI_PI_09_DATA 0b00000000000000000000000000000111 // PI_FREQ_MAP:RW:0:32:=0x00000007
-#define                DENALI_PI_10_DATA 0b00000000000000010000000000000010 // RESERVED:RW:24:1:=0x00 PI_SW_RST_N:RW_D:16:1:=0x01 PI_INIT_DFS_CALVL_ONLY:RW:8:1:=0x00 PI_INIT_WORK_FREQ:RW:0:5:=0x02
-#define                DENALI_PI_11_DATA 0b00000011000000000000100000001111 // PI_PREAMBLE_SUPPORT:RW:24:2:=0x03 PI_TMPRR:RW:16:4:=0x00 PI_TMRR:RW:8:4:=0x08 PI_CS_MAP:RW:0:4:=0x0f
-#define                DENALI_PI_12_DATA 0b00000000000000000000000000000001 // RESERVED:RW:8:1:=0x00 PI_MCAREF_FORWARD_ONLY:RW:0:1:=0x01
-#define                DENALI_PI_13_DATA 0b00000000000000000000000000000101 // PI_ON_DFIBUS:RD:24:1:=0x00 PI_TREF_INTERVAL:RW:0:20:=0x000005
-#define                DENALI_PI_14_DATA 0b00000000000000000000000000000000 // PI_SW_WRLVL_RESP_0:RD:24:1:=0x00 PI_SWLVL_OP_DONE:RD:16:1:=0x00 PI_SWLVL_LOAD:WR:8:1:=0x00 PI_DATA_RETENTION:RD:0:1:=0x00
-#define                DENALI_PI_15_DATA 0b00000000000000000000000000000000 // PI_SW_RDLVL_RESP_0:RD:24:2:=0x00 PI_SW_WRLVL_RESP_3:RD:16:1:=0x00 PI_SW_WRLVL_RESP_2:RD:8:1:=0x00 PI_SW_WRLVL_RESP_1:RD:0:1:=0x00
-#define                DENALI_PI_16_DATA 0b00000000000000000000000000000000 // PI_SW_CALVL_RESP_0:RD:24:2:=0x00 PI_SW_RDLVL_RESP_3:RD:16:2:=0x00 PI_SW_RDLVL_RESP_2:RD:8:2:=0x00 PI_SW_RDLVL_RESP_1:RD:0:2:=0x00
-#define                DENALI_PI_17_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_0:WR:24:1:=0x00 PI_SWLVL_EXIT:WR:16:1:=0x00 PI_SWLVL_START:WR:8:1:=0x00 PI_SW_LEVELING_MODE:RW:0:3:=0x00
-#define                DENALI_PI_18_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_1:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_0:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_0:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_0:WR:0:1:=0x00
-#define                DENALI_PI_19_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_2:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_1:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_1:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_1:WR:0:1:=0x00
-#define                DENALI_PI_20_DATA 0b00000000000000000000000000000000 // PI_SWLVL_WR_SLICE_3:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_2:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_2:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_2:WR:0:1:=0x00
-#define                DENALI_PI_21_DATA 0b00000000000000000000000000000000 // PI_SWLVL_SM2_START:WR:24:1:=0x00 PI_SW_WDQLVL_RESP_3:RD:16:2:=0x00 PI_SWLVL_VREF_UPDATE_SLICE_3:WR:8:1:=0x00 PI_SWLVL_RD_SLICE_3:WR:0:1:=0x00
-#define                DENALI_PI_22_DATA 0b00000000000000000000000000000000 // PI_DFS_PERIOD_EN:RW:24:1:=0x00 PI_SEQUENTIAL_LVL_REQ:WR:16:1:=0x00 PI_SWLVL_SM2_RD:WR:8:1:=0x00 PI_SWLVL_SM2_WR:WR:0:1:=0x00
-#define                DENALI_PI_23_DATA 0b00000001000000010000000000000000 // PI_16BIT_DRAM_CONNECT:RW_D:24:1:=0x01 PI_DFI40_POLARITY:RW:16:1:=0x01 PI_MPD_PERIOD_EN:RW:8:1:=0x00 PI_SRE_PERIOD_EN:RW:0:1:=0x00
-#define                DENALI_PI_24_DATA 0b00101000000010100000000000000000 // PI_WLMRD:RW:24:6:=0x28 PI_WLDQSEN:RW:16:6:=0x0a PI_WRLVL_CS:RW:8:2:=0x00 PI_WRLVL_REQ:WR:0:1:=0x00
-#define                DENALI_PI_25_DATA 0b00000000000000000000000000000000 // PI_WRLVL_ON_SREF_EXIT:RW:24:1:=0x00 PI_WRLVL_PERIODIC:RW:16:1:=0x00 PI_WRLVL_INTERVAL:RW:0:16:=0x0000
-#define                DENALI_PI_26_DATA 0b00000000000000000000000000000001 // PI_WRLVL_ROTATE:RW:24:1:=0x00 PI_WRLVL_RESP_MASK:RW:16:4:=0x00 PI_WRLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WRLVL_ON_DPDX:RW:0:1:=0x01
-#define                DENALI_PI_27_DATA 0b00110010000000000000000000001111 // PI_TDFI_WRLVL_EN:RW:24:8:=0x32 PI_WRLVL_ERROR_STATUS:RD:16:1:=0x00 PI_WRLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_WRLVL_CS_MAP:RW:0:4:=0x0f
-#define                DENALI_PI_28_DATA 0b00000000000000000000000000000000 // PI_TDFI_WRLVL_RESP:RW:0:32:=0x00000000
-#define                DENALI_PI_29_DATA 0b00000000000000000000000000000000 // PI_TDFI_WRLVL_MAX:RW:0:32:=0x00000000
-#define                DENALI_PI_30_DATA 0b00000000000000010000000100000010 // PI_EN_ODT_ASSERT_EXCEPT_RD:RW:24:1:=0x00 PI_TODTH_RD:RW:16:4:=0x01 PI_TODTH_WR:RW:8:4:=0x01 PI_WRLVL_STROBE_NUM:RW:0:5:=0x02
-#define                DENALI_PI_31_DATA 0b00000000000000000000000000000001 // PI_ADDRESS_MIRRORING:RW:8:4:=0x00 PI_ODT_VALUE:RW:0:4:=0x01
-#define                DENALI_PI_32_DATA 0b00000000000000000000000000000000 // PI_CA_PARITY_ERROR_INJECT:RW:0:25:=0x00000000
-#define                DENALI_PI_33_DATA 0b00000000000000000000000000000000 // PI_RDLVL_GATE_REQ:WR:24:1:=0x00 PI_RDLVL_REQ:WR:16:1:=0x00 RESERVED:RW:8:4:=0x00 RESERVED:RW+:0:3:=0x00
-#define                DENALI_PI_34_DATA 0b00000000000000000000000000000000 // PI_RDLVL_CS:RW:0:2:=0x00
-#define                DENALI_PI_35_DATA 0b00000000000000000000000010101010 // PI_RDLVL_PAT_0:RW:0:32:=0x000000aa
-#define                DENALI_PI_36_DATA 0b00000000000000000000000001010101 // PI_RDLVL_PAT_1:RW:0:32:=0x00000055
-#define                DENALI_PI_37_DATA 0b00000000000000000000000010110101 // PI_RDLVL_PAT_2:RW:0:32:=0x000000b5
-#define                DENALI_PI_38_DATA 0b00000000000000000000000001001010 // PI_RDLVL_PAT_3:RW:0:32:=0x0000004a
-#define                DENALI_PI_39_DATA 0b00000000000000000000000001010110 // PI_RDLVL_PAT_4:RW:0:32:=0x00000056
-#define                DENALI_PI_40_DATA 0b00000000000000000000000010101001 // PI_RDLVL_PAT_5:RW:0:32:=0x000000a9
-#define                DENALI_PI_41_DATA 0b00000000000000000000000010101001 // PI_RDLVL_PAT_6:RW:0:32:=0x000000a9
-#define                DENALI_PI_42_DATA 0b00000000000000000000000010110101 // PI_RDLVL_PAT_7:RW:0:32:=0x000000b5
-#define                DENALI_PI_43_DATA 0b00000001000000000000000000000000 // PI_RDLVL_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_PERIODIC:RW:8:1:=0x00 PI_RDLVL_SEQ_EN:RW:0:4:=0x00
-#define                DENALI_PI_44_DATA 0b00000001000000000000000000000000 // PI_RDLVL_GATE_ON_DPDX:RW:24:1:=0x01 PI_RDLVL_GATE_ON_SREF_EXIT:RW:16:1:=0x00 PI_RDLVL_GATE_PERIODIC:RW:8:1:=0x00 PI_RDLVL_DISABLE_DFS:RW:0:1:=0x00
-#define                DENALI_PI_45_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 PI_RDLVL_GATE_ON_MPD_EXIT:RW:16:1:=0x00 PI_RDLVL_ON_MPD_EXIT:RW:8:1:=0x00 PI_RDLVL_GATE_DISABLE_DFS:RW:0:1:=0x00
-#define                DENALI_PI_46_DATA 0b00001111000011110000000000000000 // PI_RDLVL_GATE_CS_MAP:RW:24:4:=0x0f PI_RDLVL_CS_MAP:RW:16:4:=0x0f PI_RDLVL_GATE_ROTATE:RW:8:1:=0x00 PI_RDLVL_ROTATE:RW:0:1:=0x00
-#define                DENALI_PI_47_DATA 0b00000000000000000000000000010011 // PI_TDFI_RDLVL_RR:RW:0:10:=0x0013
-#define                DENALI_PI_48_DATA 0b00000000000000000000011111010000 // PI_TDFI_RDLVL_RESP:RW:0:32:=0x000007d0
-#define                DENALI_PI_49_DATA 0b00000000000000000000001100000000 // PI_TDFI_RDLVL_EN:RW:8:8:=0x03 PI_RDLVL_RESP_MASK:RW:0:4:=0x00
-#define                DENALI_PI_50_DATA 0b00000000000000000000000000000000 // PI_TDFI_RDLVL_MAX:RW:0:32:=0x00000000
-#define                DENALI_PI_51_DATA 0b00000000000000000000000000000000 // PI_RDLVL_INTERVAL:RW:8:16:=0x0000 PI_RDLVL_ERROR_STATUS:RD:0:1:=0x00
-#define                DENALI_PI_52_DATA 0b00000001000000000000000000000000 // PI_RDLVL_PATTERN_NUM:RW:24:4:=0x01 PI_RDLVL_PATTERN_START:RW:16:4:=0x00 PI_RDLVL_GATE_INTERVAL:RW:0:16:=0x0000
-#define                DENALI_PI_53_DATA 0b00000000000000010000000100000001 // PI_REG_DIMM_ENABLE:RW:24:1:=0x00 PI_RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01 PI_RDLVL_GATE_STROBE_NUM:RW:8:5:=0x01 PI_RDLVL_STROBE_NUM:RW:0:5:=0x01
-#define                DENALI_PI_54_DATA 0b00000000000000000000000000000000 // PI_CALVL_CS:RW:24:2:=0x00 PI_CALVL_REQ:WR:16:1:=0x00 PI_TDFI_PHY_WRLAT:RD:8:8:=0x00 PI_TDFI_RDDATA_EN:RD:0:8:=0x00
-#define                DENALI_PI_55_DATA 0b00000000000000110000000000000000 // PI_CALVL_PERIODIC:RW:24:1:=0x00 PI_CALVL_SEQ_EN:RW:16:2:=0x03 RESERVED:RW:8:4:=0x00 RESERVED:RW:0:1:=0x00
-#define                DENALI_PI_56_DATA 0b00000000000000000000000100000000 // PI_CALVL_ROTATE:RW:24:1:=0x00 PI_CALVL_DISABLE_DFS:RW:16:1:=0x00 PI_CALVL_ON_DPDX:RW:8:1:=0x01 PI_CALVL_ON_SREF_EXIT:RW:0:1:=0x00
-#define                DENALI_PI_57_DATA 0b00000000000000000001011100001111 // PI_TDFI_CALVL_EN:RW:8:8:=0x17 PI_CALVL_CS_MAP:RW:0:4:=0x0f
-#define                DENALI_PI_58_DATA 0b00000000000000000000000000000000 // PI_TDFI_CALVL_RESP:RW:0:32:=0x00000000
-#define                DENALI_PI_59_DATA 0b00000000000000000000000000000000 // PI_TDFI_CALVL_MAX:RW:0:32:=0x00000000
-#define                DENALI_PI_60_DATA 0b00000000000000000000000000000000 // PI_CALVL_INTERVAL:RW:16:16:=0x0000 PI_CALVL_ERROR_STATUS:RD:8:2:=0x00 PI_CALVL_RESP_MASK:RW:0:1:=0x00
-#define                DENALI_PI_61_DATA 0b00001010000101000000101000000001 // PI_TCACKEH:RW:24:5:=0x0a PI_TCAMRD:RW:16:6:=0x14 PI_TCACKEL:RW:8:5:=0x0a PI_CALVL_MAX_STROBE_PEND:RW:0:4:=0x01
-#define                DENALI_PI_62_DATA 0b00000010000001000000000100001010 // PI_CALVL_VREF_NORMAL_STEPSIZE:RW:24:4:=0x02 PI_CALVL_VREF_INITIAL_STEPSIZE:RW:16:4:=0x04 PI_CA_TRAIN_VREF_EN:RW:8:1:=0x01 PI_TCAEXT:RW:0:5:=0x0a
-#define                DENALI_PI_63_DATA 0b00000010000010000000010100010000 // PI_CALVL_STROBE_NUM:RW:24:5:=0x02 PI_TCKCKEH:RW:16:4:=0x08 PI_TDFI_INIT_COMPLETE_MIN:RW:8:8:=0x05 PI_TDFI_INIT_START_MIN:RW:0:8:=0x10
-#define                DENALI_PI_64_DATA 0b00000000000001000000010000000000 // PI_DRAM_CLK_DISABLE_DEASSERT_SEL:RW:24:1:=0x00 PI_INIT_STARTORCOMPLETE_2_CLKDISABLE:RW:16:8:=0x04 PI_CLKDISABLE_2_INIT_START:RW:8:8:=0x04 PI_SW_CA_TRAIN_VREF:RW:0:7:=0x00
-#define                DENALI_PI_65_DATA 0b00000001000000000000000100000001 // PI_VREFLVL_DISABLE_DFS:RW:24:1:=0x01 PI_VREF_PDA_EN:RW:16:1:=0x00 PI_VREF_CS:RW:8:2:=0x01 PI_REFRESH_BETWEEN_SEGMENT_DISABLE:RW_D:0:1:=0x01
-#define                DENALI_PI_66_DATA 0b00000000000000010000000100000000 // PI_WDQLVL_RESP_MASK:RW:24:4:=0x00 PI_WDQLVL_BST_NUM:RW:16:3:=0x01 PI_WDQLVL_VREF_EN:RW:8:1:=0x01 PI_MC_DFS_PI_SET_VREF_ENABLE:RW:0:1:=0x00
-#define                DENALI_PI_67_DATA 0b00000010000001000000111100000000 // PI_WDQLVL_VREF_NORMAL_STEPSIZE:RW:24:5:=0x02 PI_WDQLVL_VREF_INITIAL_STEPSIZE:RW:16:5:=0x04 PI_WDQLVL_CS_MAP:RW:8:4:=0x0f PI_WDQLVL_ROTATE:RW:0:1:=0x00
-#define                DENALI_PI_68_DATA 0b00110100000000000000000000000000 // PI_TDFI_WDQLVL_EN:RW:24:8:=0x34 PI_WDQLVL_CS:RW:16:2:=0x00 PI_WDQLVL_REQ:WR:8:1:=0x00 PI_WDQLVL_PERIODIC:RW:0:1:=0x00
-#define                DENALI_PI_69_DATA 0b00000000000000000000000000000000 // PI_TDFI_WDQLVL_RESP:RW:0:32:=0x00000000
-#define                DENALI_PI_70_DATA 0b00000000000000000000000000000000 // PI_TDFI_WDQLVL_MAX:RW:0:32:=0x00000000
-#define                DENALI_PI_71_DATA 0b00000001000000000000000000000000 // PI_WDQLVL_ON_DPDX:RW:24:1:=0x01 PI_WDQLVL_ON_SREF_EXIT:RW:16:1:=0x00 PI_WDQLVL_INTERVAL:RW:0:16:=0x0000
-#define                DENALI_PI_72_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_NEED_SAVE_RESTORE:RW:24:2:=0x00 PI_WDQLVL_ERROR_STATUS:RD:16:2:=0x00 PI_WDQLVL_DISABLE_DFS:RW:8:1:=0x00 PI_WDQLVL_ON_MPD_EXIT:RW:0:1:=0x00
-#define                DENALI_PI_73_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00000000
-#define                DENALI_PI_74_DATA 0b00000000000000000000000000000000 // PI_NO_MEMORY_DM:RW:16:1:=0x00 PI_WDQLVL_DM_LEVEL_EN:RW:8:1:=0x00 PI_WDQLVL_DRAM_LVL_START_ADDR:RW:0:36:=0x00
-#define                DENALI_PI_75_DATA 0b00000000000000000000000000000000 // PI_WDQLVL_NIBBLE_MODE:RW:24:1:=0x00 PI_SWLVL_SM2_DM_NIBBLE_START:WR:16:1:=0x00 PI_TDFI_WDQLVL_WW:RW:0:10:=0x0000
-#define                DENALI_PI_76_DATA 0b00000000000000010000000100000000 // PI_DBILVL_RESP_MASK:RW:24:4:=0x00 PI_PARALLEL_WDQLVL_EN:RW:16:1:=0x01 PI_WDQLVL_PDA_VREF_TRAIN:RW:8:1:=0x01 PI_WDQLVL_PDA_EN:RW:0:1:=0x00
-#define                DENALI_PI_77_DATA 0b00000000000010000000000100000001 // RESERVED:RW_D:24:4:=0x00 PI_TCCD:RW:16:5:=0x08 PI_ROW_DIFF:RW:8:3:=0x01 PI_BANK_DIFF:RW:0:2:=0x01
-#define                DENALI_PI_78_DATA 0b00000010000000000000001000000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-#define                DENALI_PI_79_DATA 0b00000001000000000000000100000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x01 RESERVED:RW_D:0:4:=0x00
-#define                DENALI_PI_80_DATA 0b00000001000000000000000000000000 // RESERVED:RW_D:24:4:=0x01 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x00 RESERVED:RW_D:0:4:=0x00
-#define                DENALI_PI_81_DATA 0b00000010000000000000001000000000 // RESERVED:RW_D:24:4:=0x02 RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-#define                DENALI_PI_82_DATA 0b00000000000000000000001000000000 // RESERVED:RW_D:16:4:=0x00 RESERVED:RW_D:8:4:=0x02 RESERVED:RW_D:0:4:=0x00
-#define                DENALI_PI_83_DATA 0b00000000000000000000000000000000 // PI_INT_STATUS:RD:0:28:=0x00000000
-#define                DENALI_PI_84_DATA 0b00000000000000000000000000000000 // PI_INT_ACK:WR:0:27:=0x00000000
-#define                DENALI_PI_85_DATA 0b00000000000000000000000000000000 // PI_INT_MASK:RW:0:28:=0x00000000
-#define                DENALI_PI_86_DATA 0b00001110000000000000000000000100 // PI_PARITY_IN_MUX:RW_D:24:5:=0x0e PI_CMD_SWAP_EN:RW_D:16:1:=0x00 PI_LONG_COUNT_MASK:RW:8:5:=0x00 PI_BSTLEN:RW_D:0:5:=0x04
-#define                DENALI_PI_87_DATA 0b00001100000011010001000000001111 // PI_CAS_N_MUX:RW_D:24:5:=0x0c PI_RAS_N_MUX:RW_D:16:5:=0x0d PI_A14_MUX:RW_D:8:5:=0x10 PI_A15_MUX:RW_D:0:5:=0x0f
-#define                DENALI_PI_88_DATA 0b00001010000010010000100000001011 // PI_BANK_MUX_2:RW_D:24:5:=0x0a PI_BANK_MUX_1:RW_D:16:5:=0x09 PI_BANK_MUX_0:RW_D:8:5:=0x08 PI_WE_N_MUX:RW_D:0:5:=0x0b
-#define                DENALI_PI_89_DATA 0b00000010000000010000000000000000 // PI_DATA_BYTE_SWAP_SLICE2:RW_D:24:2:=0x02 PI_DATA_BYTE_SWAP_SLICE1:RW_D:16:2:=0x01 PI_DATA_BYTE_SWAP_SLICE0:RW_D:8:2:=0x00 PI_DATA_BYTE_SWAP_EN:RW_D:0:1:=0x00
-#define                DENALI_PI_90_DATA 0b00000000000010000000000100000011 // PI_UPDATE_ERROR_STATUS:RD:24:2:=0x00 PI_TDFI_CTRLUPD_MIN:RW:16:8:=0x08 PI_CTRLUPD_REQ_PER_AREF_EN:RW:8:1:=0x01 PI_DATA_BYTE_SWAP_SLICE3:RW_D:0:2:=0x03
-#define                DENALI_PI_91_DATA 0b00000000000000000000001000000000 // PI_SELF_REFRESH_EN:RW:24:1:=0x00 PI_BG_ROTATE_EN:RW:16:1:=0x00 PI_COL_DIFF:RW:8:4:=0x02 PI_TDFI_PARIN_LAT:RW:0:3:=0x00
-#define                DENALI_PI_92_DATA 0b00000000000000000000000000000000 // PI_NO_MRW_BT_INIT:RW:24:1:=0x00 PI_SREF_ENTRY_REQ:WR:16:1:=0x00 PI_SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00 PI_PWRUP_SREFRESH_EXIT:RW+:0:1:=0x00
-#define                DENALI_PI_93_DATA 0b00001111000000000000000000000000 // PI_PWRUP_SREFRESH_EXIT_CS:RW:24:4:=0x0f PI_NO_AUTO_MRR_INIT:RW:16:1:=0x00 PI_NO_PHY_IND_TRAIN_INIT:RW:8:1:=0x00 PI_NO_MRW_INIT:RW:0:1:=0x00
-#define                DENALI_PI_94_DATA 0b00000000000000000000000000000100 // PI_TRST_PWRON:RW:0:32:=0x00000004
-#define                DENALI_PI_95_DATA 0b00000000000000000000000000001010 // PI_CKE_INACTIVE:RW:0:32:=0x0000000a
-#define                DENALI_PI_96_DATA 0b00000000000000000000000000000000 // PI_DLL_RST_DELAY:RW:16:16:=0x0000 PI_DRAM_INIT_EN:RW:8:1:=0x00 PI_DLL_RST:RW:0:1:=0x00
-#define                DENALI_PI_97_DATA 0b00000000000000000000000000000000 // PI_DLL_RST_ADJ_DLY:RW:0:8:=0x00
-#define                DENALI_PI_98_DATA 0b00000000000000000000000000000000 // PI_WRITE_MODEREG:RW+:0:26:=0x00000000
-#define                DENALI_PI_99_DATA 0b00000000000000000000000000000000 // RESERVED:RW:8:1:=0x00 PI_MRW_STATUS:RD:0:8:=0x00
-#define               DENALI_PI_100_DATA 0b00000000000000000000000000000000 // PI_READ_MODEREG:RW+:0:17:=0x000000
-#define               DENALI_PI_101_DATA 0b00000000000000000000000000000000 // PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00000000
-#define               DENALI_PI_102_DATA 0b00000000000000000000000000000000 // RESERVED:WR:24:4:=0x00 RESERVED:RW:16:4:=0x00 PI_NO_ZQ_INIT:RW:8:1:=0x00 PI_PERIPHERAL_MRR_DATA:RD:0:40:=0x00
-#define               DENALI_PI_103_DATA 0b00000000000000110000000100000000 // PI_MONITOR_SRC_SEL_0:RW:24:4:=0x00 RESERVED:RW:16:3:=0x03 RESERVED:RW:8:1:=0x01 PI_ZQ_REQ_PENDING:RD:0:1:=0x00
-#define               DENALI_PI_104_DATA 0b00000001000000010000000000000001 // PI_MONITOR_CAP_SEL_1:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_1:RW:16:4:=0x01 PI_MONITOR_0:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_0:RW:0:1:=0x01
-#define               DENALI_PI_105_DATA 0b00000000000000010000001000000000 // PI_MONITOR_2:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_2:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_2:RW:8:4:=0x02 PI_MONITOR_1:RD:0:8:=0x00
-#define               DENALI_PI_106_DATA 0b00000100000000000000000100000011 // PI_MONITOR_SRC_SEL_4:RW:24:4:=0x04 PI_MONITOR_3:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_3:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_3:RW:0:4:=0x03
-#define               DENALI_PI_107_DATA 0b00000001000001010000000000000001 // PI_MONITOR_CAP_SEL_5:RW:24:1:=0x01 PI_MONITOR_SRC_SEL_5:RW:16:4:=0x05 PI_MONITOR_4:RD:8:8:=0x00 PI_MONITOR_CAP_SEL_4:RW:0:1:=0x01
-#define               DENALI_PI_108_DATA 0b00000000000000010000011000000000 // PI_MONITOR_6:RD:24:8:=0x00 PI_MONITOR_CAP_SEL_6:RW:16:1:=0x01 PI_MONITOR_SRC_SEL_6:RW:8:4:=0x06 PI_MONITOR_5:RD:0:8:=0x00
-#define               DENALI_PI_109_DATA 0b00000000000000000000000100000111 // PI_MONITOR_7:RD:16:8:=0x00 PI_MONITOR_CAP_SEL_7:RW:8:1:=0x01 PI_MONITOR_SRC_SEL_7:RW:0:4:=0x07
-#define               DENALI_PI_110_DATA 0b00000000000000000000000000000000 // PI_MONITOR_STROBE:WR:0:8:=0x00
-#define               DENALI_PI_111_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 PI_FREQ_RETENTION_NUM:RW+:16:5:=0x00 PI_FREQ_NUMBER_STATUS:RD:8:5:=0x00 PI_DLL_LOCK:RD:0:1:=0x00
-#define               DENALI_PI_112_DATA 0b00000000000000010000000000000001 // RESERVED:RW:24:1:=0x00 PI_POWER_REDUC_EN:RW:16:1:=0x01 RESERVED:RW:8:1:=0x00 PI_PHYMSTR_TYPE:RW:0:2:=0x01
-#define               DENALI_PI_113_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-#define               DENALI_PI_114_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-#define               DENALI_PI_115_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-#define               DENALI_PI_116_DATA 0b00000000000000000000000000000000 // RESERVED:RW:24:1:=0x00 RESERVED:RW:16:1:=0x00 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-#define               DENALI_PI_117_DATA 0b00000000000000010000000000000000 // PI_WRLVL_MAX_STROBE_PEND:RW:16:8:=0x01 RESERVED:RW:8:1:=0x00 RESERVED:RW:0:1:=0x00
-#define               DENALI_PI_118_DATA 0b00000000000000000000000000000100 // PI_TREFBW_THR:RW:0:9:=0x0004
-#define               DENALI_PI_119_DATA 0b00000000000000000000000000000000 // PI_FREQ_CHANGE_REG_COPY:RW:0:5:=0x00
-#define               DENALI_PI_120_DATA 0b00000000000000010000000000000000 // PI_CATR:RW:24:4:=0x00 PI_PARALLEL_CALVL_EN:RW:16:1:=0x01 RESERVED:RW:8:5:=0x00 PI_FREQ_SEL_FROM_REGIF:RW:0:1:=0x00
-#define               DENALI_PI_121_DATA 0b00000000000000000000000000000000 // PI_NOTCARE_MC_INIT_START:RW:24:1:=0x00 PI_DISCONNECT_MC:RW:16:1:=0x00 PI_MASK_INIT_COMPLETE:RW:8:1:=0x00 PI_NO_CATR_READ:RW:0:1:=0x00
-#define               DENALI_PI_122_DATA 0b00000000001111000000000000000011 // PI_TVREF_F1:RW:16:16:=0x003c PI_TVREF_F0:RW:0:16:=0x0003
-#define               DENALI_PI_123_DATA 0b00001000000000010000000001111000 // PI_TSDO_F1:RW:24:8:=0x08 PI_TSDO_F0:RW:16:8:=0x01 PI_TVREF_F2:RW:0:16:=0x0078
-#define               DENALI_PI_124_DATA 0b00000000000000000000000000010000 // PI_TSDO_F2:RW:0:8:=0x10
-#define               DENALI_PI_125_DATA 0b00000000000000000000000000101100 // PI_TDELAY_RDWR_2_BUS_IDLE_F0:RW:0:8:=0x2c
-#define               DENALI_PI_126_DATA 0b00000000000000000000000000110011 // PI_TDELAY_RDWR_2_BUS_IDLE_F1:RW:0:8:=0x33
-#define               DENALI_PI_127_DATA 0b00000000000000100000000000111010 // PI_ZQINIT_F0:RW_D:8:12:=0x0200 PI_TDELAY_RDWR_2_BUS_IDLE_F2:RW:0:8:=0x3a
-#define               DENALI_PI_128_DATA 0b00000010000000000000001000000000 // PI_ZQINIT_F2:RW_D:16:12:=0x0200 PI_ZQINIT_F1:RW_D:0:12:=0x0200
-#define               DENALI_PI_129_DATA 0b00000000000000000000000000000100 // PI_TPARITY_ERROR_CMD_INHIBIT_F0:RW:24:8:=0x00 PI_CA_PARITY_LAT_F0:RW:16:4:=0x00 PI_ADDITIVE_LAT_F0:RW:8:6:=0x00 PI_WRLAT_F0:RW:0:7:=0x04
-#define               DENALI_PI_130_DATA 0b00000000000000000000011000001100 // PI_CA_PARITY_LAT_F1:RW:24:4:=0x00 PI_ADDITIVE_LAT_F1:RW:16:6:=0x00 PI_WRLAT_F1:RW:8:7:=0x06 PI_CASLAT_LIN_F0:RW:0:7:=0x0c
-#define               DENALI_PI_131_DATA 0b00000000000010000001010000000000 // PI_ADDITIVE_LAT_F2:RW:24:6:=0x00 PI_WRLAT_F2:RW:16:7:=0x08 PI_CASLAT_LIN_F1:RW:8:7:=0x14 PI_TPARITY_ERROR_CMD_INHIBIT_F1:RW:0:8:=0x00
-#define               DENALI_PI_132_DATA 0b00000000000111000000000000000000 // PI_CASLAT_LIN_F2:RW:16:7:=0x1c PI_TPARITY_ERROR_CMD_INHIBIT_F2:RW:8:8:=0x00 PI_CA_PARITY_LAT_F2:RW:0:4:=0x00
-#define               DENALI_PI_133_DATA 0b00000000000000000000000000000110 // PI_TRFC_F0:RW:0:10:=0x0006
-#define               DENALI_PI_134_DATA 0b00000000000000000000000001000110 // PI_TREF_F0:RW:0:20:=0x000046
-#define               DENALI_PI_135_DATA 0b00000000000000000000000001110000 // PI_TRFC_F1:RW:0:10:=0x0070
-#define               DENALI_PI_136_DATA 0b00000000000000000000011000010000 // PI_TREF_F1:RW:0:20:=0x000610
-#define               DENALI_PI_137_DATA 0b00000000000000000000000011100000 // PI_TRFC_F2:RW:0:10:=0x00e0
-#define               DENALI_PI_138_DATA 0b00000100000000000000110000101000 // PI_TDFI_CTRL_DELAY_F0:RW_D:24:4:=0x04 PI_TREF_F2:RW:0:20:=0x000c28
-#define               DENALI_PI_139_DATA 0b00000001000000010000010000000100 // PI_WRLVL_EN_F1:RW:24:2:=0x01 PI_WRLVL_EN_F0:RW:16:2:=0x01 PI_TDFI_CTRL_DELAY_F2:RW_D:8:4:=0x04 PI_TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x04
-#define               DENALI_PI_140_DATA 0b00000000000000000001110000000001 // PI_TDFI_WRLVL_WW_F0:RW:8:10:=0x001c PI_WRLVL_EN_F2:RW:0:2:=0x01
-#define               DENALI_PI_141_DATA 0b00000000000111000000000000011100 // PI_TDFI_WRLVL_WW_F2:RW:16:10:=0x001c PI_TDFI_WRLVL_WW_F1:RW:0:10:=0x001c
-#define               DENALI_PI_142_DATA 0b00000001000000000000000100000000 // PI_ODT_EN_F1:RW:24:1:=0x01 PI_TODTL_2CMD_F1:RW:16:8:=0x00 PI_ODT_EN_F0:RW:8:1:=0x01 PI_TODTL_2CMD_F0:RW:0:8:=0x00
-#define               DENALI_PI_143_DATA 0b00000000000000000000000100000000 // PI_TODTON_MIN_F0:RW:24:4:=0x00 PI_ODTLON_F0:RW:16:4:=0x00 PI_ODT_EN_F2:RW:8:1:=0x01 PI_TODTL_2CMD_F2:RW:0:8:=0x00
-#define               DENALI_PI_144_DATA 0b00000000000000000000000000000000 // PI_TODTON_MIN_F2:RW:24:4:=0x00 PI_ODTLON_F2:RW:16:4:=0x00 PI_TODTON_MIN_F1:RW:8:4:=0x00 PI_ODTLON_F1:RW:0:4:=0x00
-#define               DENALI_PI_145_DATA 0b00000101000001010000010000000011 // PI_RD_TO_ODTH_F0:RW:24:6:=0x05 PI_WR_TO_ODTH_F2:RW:16:6:=0x05 PI_WR_TO_ODTH_F1:RW:8:6:=0x04 PI_WR_TO_ODTH_F0:RW:0:6:=0x03
-#define               DENALI_PI_146_DATA 0b00000001000000010000110000001000 // PI_RDLVL_GATE_EN_F0:RW:24:2:=0x01 PI_RDLVL_EN_F0:RW:16:2:=0x01 PI_RD_TO_ODTH_F2:RW:8:6:=0x0c PI_RD_TO_ODTH_F1:RW:0:6:=0x08
-#define               DENALI_PI_147_DATA 0b00000001000000010000000100000001 // PI_RDLVL_GATE_EN_F2:RW:24:2:=0x01 PI_RDLVL_EN_F2:RW:16:2:=0x01 PI_RDLVL_GATE_EN_F1:RW:8:2:=0x01 PI_RDLVL_EN_F1:RW:0:2:=0x01
-#define               DENALI_PI_148_DATA 0b00000000000011000000101000001010 // PI_RDLVL_PAT0_EN_F0:RW:24:2:=0x00 PI_TWR_MPR_F2:RW:16:8:=0x0c PI_TWR_MPR_F1:RW:8:8:=0x0a PI_TWR_MPR_F0:RW:0:8:=0x0a
-#define               DENALI_PI_149_DATA 0b00000000000000000000000000000000 // PI_RDLVL_PAT0_EN_F1:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F0:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F0:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F0:RW:0:2:=0x00
-#define               DENALI_PI_150_DATA 0b00000000000000000000000000000000 // PI_RDLVL_PAT0_EN_F2:RW:24:2:=0x00 PI_RDLVL_MULTI_EN_F1:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F1:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F1:RW:0:2:=0x00
-#define               DENALI_PI_151_DATA 0b00000100000000000000000000000000 // PI_RDLAT_ADJ_F0:RW:24:8:=0x04 PI_RDLVL_MULTI_EN_F2:RW:16:2:=0x00 PI_RDLVL_DFE_EN_F2:RW:8:2:=0x00 PI_RDLVL_RXCAL_EN_F2:RW:0:2:=0x00
-#define               DENALI_PI_152_DATA 0b00000100000000100000101100001000 // PI_WRLAT_ADJ_F1:RW:24:8:=0x04 PI_WRLAT_ADJ_F0:RW:16:8:=0x02 PI_RDLAT_ADJ_F2:RW:8:8:=0x0b PI_RDLAT_ADJ_F1:RW:0:8:=0x08
-#define               DENALI_PI_153_DATA 0b00000100000000100000001000000100 // PI_TDFI_PHY_WRDATA_F2:RW:24:3:=0x04 PI_TDFI_PHY_WRDATA_F1:RW:16:3:=0x02 PI_TDFI_PHY_WRDATA_F0:RW:8:3:=0x02 PI_WRLAT_ADJ_F2:RW:0:8:=0x04
-#define               DENALI_PI_154_DATA 0b00000000000011000000000000110100 // PI_TDFI_CALVL_CAPTURE_F0:RW:16:10:=0x000c PI_TDFI_CALVL_CC_F0:RW:0:10:=0x0034
-#define               DENALI_PI_155_DATA 0b00000000000100000000000000111000 // PI_TDFI_CALVL_CAPTURE_F1:RW:16:10:=0x0010 PI_TDFI_CALVL_CC_F1:RW:0:10:=0x0038
-#define               DENALI_PI_156_DATA 0b00000000000101000000000000111100 // PI_TDFI_CALVL_CAPTURE_F2:RW:16:10:=0x0014 PI_TDFI_CALVL_CC_F2:RW:0:10:=0x003c
-#define               DENALI_PI_157_DATA 0b00000000000000010000000000000001 // PI_CALVL_AREF_LP3_EN_F1:RW:24:1:=0x00 PI_CALVL_EN_F1:RW:16:2:=0x01 PI_CALVL_AREF_LP3_EN_F0:RW:8:1:=0x00 PI_CALVL_EN_F0:RW:0:2:=0x01
-#define               DENALI_PI_158_DATA 0b00000000000000010000000000000001 // PI_TMRZ_F0:RW:16:5:=0x01 PI_CALVL_AREF_LP3_EN_F2:RW:8:1:=0x00 PI_CALVL_EN_F2:RW:0:2:=0x01
-#define               DENALI_PI_159_DATA 0b00000000000000010000000000000101 // PI_TMRZ_F1:RW:16:5:=0x01 PI_TCAENT_F0:RW:0:14:=0x0005
-#define               DENALI_PI_160_DATA 0b00000000000000100000000001100100 // PI_TMRZ_F2:RW:16:5:=0x02 PI_TCAENT_F1:RW:0:14:=0x0064
-#define               DENALI_PI_161_DATA 0b00000001000000000000000011001000 // PI_TDFI_CASEL_F0:RW:24:5:=0x01 PI_TDFI_CACSCA_F0:RW:16:5:=0x00 PI_TCAENT_F2:RW:0:14:=0x00c8
-#define               DENALI_PI_162_DATA 0b00000000000001100000000000000110 // PI_TVREF_LONG_F0:RW:16:10:=0x0006 PI_TVREF_SHORT_F0:RW:0:10:=0x0006
-#define               DENALI_PI_163_DATA 0b00000000011001010000000100000000 // PI_TVREF_SHORT_F1:RW:16:10:=0x0065 PI_TDFI_CASEL_F1:RW:8:5:=0x01 PI_TDFI_CACSCA_F1:RW:0:5:=0x00
-#define               DENALI_PI_164_DATA 0b00000001000000000000000001100101 // PI_TDFI_CASEL_F2:RW:24:5:=0x01 PI_TDFI_CACSCA_F2:RW:16:5:=0x00 PI_TVREF_LONG_F1:RW:0:10:=0x0065
-#define               DENALI_PI_165_DATA 0b00000000110010010000000011001001 // PI_TVREF_LONG_F2:RW:16:10:=0x00c9 PI_TVREF_SHORT_F2:RW:0:10:=0x00c9
-#define               DENALI_PI_166_DATA 0b00011110000110100001111000011010 // PI_CALVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_CALVL_VREF_INITIAL_STOP_POINT_F0:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F0:RW:0:7:=0x1a
-#define               DENALI_PI_167_DATA 0b00000001000000010001111000011010 // PI_CALVL_VREF_DELTA_F1:RW:24:4:=0x01 PI_CALVL_VREF_DELTA_F0:RW:16:4:=0x01 PI_CALVL_VREF_INITIAL_STOP_POINT_F2:RW:8:7:=0x1e PI_CALVL_VREF_INITIAL_START_POINT_F2:RW:0:7:=0x1a
-#define               DENALI_PI_168_DATA 0b00001010000001110000011000000001 // PI_TMRWCKEL_F0:RW:24:8:=0x0a PI_TXP_F0:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F0:RW:8:4:=0x06 PI_CALVL_VREF_DELTA_F2:RW:0:4:=0x01
-#define               DENALI_PI_169_DATA 0b00001010000001110000011000001101 // PI_TMRWCKEL_F1:RW:24:8:=0x0a PI_TXP_F1:RW:16:5:=0x07 PI_TDFI_CALVL_STROBE_F1:RW:8:4:=0x06 PI_TCKELCK_F0:RW:0:5:=0x0d
-#define               DENALI_PI_170_DATA 0b00001101000010010000011100001101 // PI_TMRWCKEL_F2:RW:24:8:=0x0d PI_TXP_F2:RW:16:5:=0x09 PI_TDFI_CALVL_STROBE_F2:RW:8:4:=0x07 PI_TCKELCK_F1:RW:0:5:=0x0d
-#define               DENALI_PI_171_DATA 0b00000000000000001100000000001101 // PI_TDFI_INIT_START_F0:RW:8:10:=0x00c0 PI_TCKELCK_F2:RW:0:5:=0x0d
-#define               DENALI_PI_172_DATA 0b00000000110000000001000000000000 // PI_TDFI_INIT_START_F1:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F0:RW:0:16:=0x1000
-#define               DENALI_PI_173_DATA 0b00000000110000000001000000000000 // PI_TDFI_INIT_START_F2:RW:16:10:=0x00c0 PI_TDFI_INIT_COMPLETE_F1:RW:0:16:=0x1000
-#define               DENALI_PI_174_DATA 0b00000000000000100001000000000000 // PI_TCKEHDQS_F0:RW:16:6:=0x02 PI_TDFI_INIT_COMPLETE_F2:RW:0:16:=0x1000
-#define               DENALI_PI_175_DATA 0b00000000000100100000000000000101 // PI_TCKEHDQS_F1:RW:16:6:=0x12 PI_TFC_F0:RW:0:10:=0x0005
-#define               DENALI_PI_176_DATA 0b00000000000101100000000001100100 // PI_TCKEHDQS_F2:RW:16:6:=0x16 PI_TFC_F1:RW:0:10:=0x0064
-#define               DENALI_PI_177_DATA 0b00000000000000000000000011001000 // PI_VREF_EN_F1:RW:24:2:=0x00 PI_VREF_EN_F0:RW:16:2:=0x00 PI_TFC_F2:RW:0:10:=0x00c8
-#define               DENALI_PI_178_DATA 0b00000000000000000001000100000000 // PI_TDFI_WDQLVL_WR_F0:RW:8:10:=0x0011 PI_VREF_EN_F2:RW:0:2:=0x00
-#define               DENALI_PI_179_DATA 0b00011110000110100000000001010110 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F0:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F0:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F0:RW:0:10:=0x0056
-#define               DENALI_PI_180_DATA 0b00000110000000000000000100000001 // PI_WDQLVL_CL_F0:RW:24:5:=0x06 PI_NTP_TRAIN_EN_F0:RW:16:2:=0x00 PI_WDQLVL_EN_F0:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F0:RW:0:4:=0x01
-#define               DENALI_PI_181_DATA 0b00000000000100110000001000000100 // PI_TDFI_WDQLVL_WR_F1:RW:16:10:=0x0013 PI_WDQLVL_WRLAT_ADJ_F0:RW:8:8:=0x02 PI_WDQLVL_RDLAT_ADJ_F0:RW:0:8:=0x04
-#define               DENALI_PI_182_DATA 0b00011110000110100000000001011000 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F1:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F1:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F1:RW:0:10:=0x0058
-#define               DENALI_PI_183_DATA 0b00000001000000000000000100000001 // PI_WDQLVL_CL_F1:RW:24:5:=0x01 PI_NTP_TRAIN_EN_F1:RW:16:2:=0x00 PI_WDQLVL_EN_F1:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F1:RW:0:4:=0x01
-#define               DENALI_PI_184_DATA 0b00000000000101010000010000001000 // PI_TDFI_WDQLVL_WR_F2:RW:16:10:=0x0015 PI_WDQLVL_WRLAT_ADJ_F1:RW:8:8:=0x04 PI_WDQLVL_RDLAT_ADJ_F1:RW:0:8:=0x08
-#define               DENALI_PI_185_DATA 0b00011110000110100000000001011011 // PI_WDQLVL_VREF_INITIAL_STOP_POINT_F2:RW:24:7:=0x1e PI_WDQLVL_VREF_INITIAL_START_POINT_F2:RW:16:7:=0x1a PI_TDFI_WDQLVL_RW_F2:RW:0:10:=0x005b
-#define               DENALI_PI_186_DATA 0b00000101000000000000000100000001 // PI_WDQLVL_CL_F2:RW:24:5:=0x05 PI_NTP_TRAIN_EN_F2:RW:16:2:=0x00 PI_WDQLVL_EN_F2:RW:8:2:=0x01 PI_WDQLVL_VREF_DELTA_F2:RW:0:4:=0x01
-#define               DENALI_PI_187_DATA 0b00000000000000000000010000001011 // PI_RD_DBI_LEVEL_EN_F1:RW:24:2:=0x00 PI_RD_DBI_LEVEL_EN_F0:RW:16:2:=0x00 PI_WDQLVL_WRLAT_ADJ_F2:RW:8:8:=0x04 PI_WDQLVL_RDLAT_ADJ_F2:RW:0:8:=0x0b
-#define               DENALI_PI_188_DATA 0b00000100000001000000100000000000 // PI_TRCD_F0:RW:24:8:=0x04 PI_TRP_F0:RW:16:8:=0x04 PI_TRTP_F0:RW:8:8:=0x08 PI_RD_DBI_LEVEL_EN_F2:RW:0:2:=0x00
-#define               DENALI_PI_189_DATA 0b00000000000001000000000100000000 // PI_TWR_F0:RW:16:8:=0x04 PI_TWTR_F0:RW:8:6:=0x01 PI_TCCD_L_F0:RW:0:5:=0x00
-#define               DENALI_PI_190_DATA 0b00000011000000000000001001110111 // PI_TRAS_MIN_F0:RW:24:8:=0x03 PI_TRAS_MAX_F0:RW:0:20:=0x000277
-#define               DENALI_PI_191_DATA 0b00001010000000110010000000000001 // PI_TMRD_F0:RW:24:8:=0x0a PI_TSR_F0:RW:16:8:=0x03 PI_TCCDMW_F0:RW:8:6:=0x20 PI_TDQSCK_MAX_F0:RW:0:4:=0x01
-#define               DENALI_PI_192_DATA 0b00000000000000000000101000001010 // PI_TMRD_PAR_F0:RW:24:8:=0x00 PI_TMOD_PAR_F0:RW:16:8:=0x00 PI_TMOD_F0:RW:8:8:=0x0a PI_TMRW_F0:RW:0:8:=0x0a
-#define               DENALI_PI_193_DATA 0b00000000000010000000100100001000 // PI_TCCD_L_F1:RW:24:5:=0x00 PI_TRCD_F1:RW:16:8:=0x08 PI_TRP_F1:RW:8:8:=0x09 PI_TRTP_F1:RW:0:8:=0x08
-#define               DENALI_PI_194_DATA 0b00000000000000000000100100000001 // PI_TWR_F1:RW:8:8:=0x09 PI_TWTR_F1:RW:0:6:=0x01
-#define               DENALI_PI_195_DATA 0b00010001000000000011000101011100 // PI_TRAS_MIN_F1:RW:24:8:=0x11 PI_TRAS_MAX_F1:RW:0:20:=0x00315c
-#define               DENALI_PI_196_DATA 0b00001010000001100010000000000010 // PI_TMRD_F1:RW:24:8:=0x0a PI_TSR_F1:RW:16:8:=0x06 PI_TCCDMW_F1:RW:8:6:=0x20 PI_TDQSCK_MAX_F1:RW:0:4:=0x02
-#define               DENALI_PI_197_DATA 0b00000000000000000000101000001010 // PI_TMRD_PAR_F1:RW:24:8:=0x00 PI_TMOD_PAR_F1:RW:16:8:=0x00 PI_TMOD_F1:RW:8:8:=0x0a PI_TMRW_F1:RW:0:8:=0x0a
-#define               DENALI_PI_198_DATA 0b00000000000011110001000100001000 // PI_TCCD_L_F2:RW:24:5:=0x00 PI_TRCD_F2:RW:16:8:=0x0f PI_TRP_F2:RW:8:8:=0x11 PI_TRTP_F2:RW:0:8:=0x08
-#define               DENALI_PI_199_DATA 0b00000000000000000001000000000001 // PI_TWR_F2:RW:8:8:=0x10 PI_TWTR_F2:RW:0:6:=0x01
-#define               DENALI_PI_200_DATA 0b00100010000000000110001010111000 // PI_TRAS_MIN_F2:RW:24:8:=0x22 PI_TRAS_MAX_F2:RW:0:20:=0x0062b8
-#define               DENALI_PI_201_DATA 0b00001100000011000010000000000011 // PI_TMRD_F2:RW:24:8:=0x0c PI_TSR_F2:RW:16:8:=0x0c PI_TCCDMW_F2:RW:8:6:=0x20 PI_TDQSCK_MAX_F2:RW:0:4:=0x03
-#define               DENALI_PI_202_DATA 0b00000000000000000000110000001010 // PI_TMRD_PAR_F2:RW:24:8:=0x00 PI_TMOD_PAR_F2:RW:16:8:=0x00 PI_TMOD_F2:RW:8:8:=0x0c PI_TMRW_F2:RW:0:8:=0x0a
-#define               DENALI_PI_203_DATA 0b00000000000000000000000010001100 // PI_TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x00008c
-#define               DENALI_PI_204_DATA 0b00000000000000000000010101111000 // PI_TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00000578
-#define               DENALI_PI_205_DATA 0b00000000000000000000110000100000 // PI_TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x000c20
-#define               DENALI_PI_206_DATA 0b00000000000000000111100101000000 // PI_TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00007940
-#define               DENALI_PI_207_DATA 0b00000000000000000001100001010000 // PI_TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x001850
-#define               DENALI_PI_208_DATA 0b00000000000000001111001100100000 // PI_TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x0000f320
-#define               DENALI_PI_209_DATA 0b00000000011100110000000000000110 // PI_TXSR_F1:RW:16:16:=0x0073 PI_TXSR_F0:RW:0:16:=0x0006
-#define               DENALI_PI_210_DATA 0b00000011000000110000000011100110 // PI_TEXCKE_F1:RW:24:6:=0x03 PI_TEXCKE_F0:RW:16:6:=0x03 PI_TXSR_F2:RW:0:16:=0x00e6
-#define               DENALI_PI_211_DATA 0b00000000000000000000000000000011 // PI_TDLL_F0:RW:8:16:=0x0000 PI_TEXCKE_F2:RW:0:6:=0x03
-#define               DENALI_PI_212_DATA 0b00000000000000000000000000000000 // PI_TDLL_F2:RW:16:16:=0x0000 PI_TDLL_F1:RW:0:16:=0x0000
-#define               DENALI_PI_213_DATA 0b00000000000000000000000000000100 // PI_TINIT_F0:RW:0:24:=0x000004
-#define               DENALI_PI_214_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F0:RW:0:24:=0x000001
-#define               DENALI_PI_215_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F0:RW:0:24:=0x000005
-#define               DENALI_PI_216_DATA 0b00000000000000000000000000000010 // PI_TINIT5_F0:RW:0:24:=0x000002
-#define               DENALI_PI_217_DATA 0b00000000000000000000000000000110 // PI_TXSNR_F0:RW:0:16:=0x0006
-#define               DENALI_PI_218_DATA 0b00000000000000000000000001010000 // PI_TINIT_F1:RW:0:24:=0x000050
-#define               DENALI_PI_219_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F1:RW:0:24:=0x000001
-#define               DENALI_PI_220_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F1:RW:0:24:=0x000005
-#define               DENALI_PI_221_DATA 0b00000000000000000000000000101000 // PI_TINIT5_F1:RW:0:24:=0x000028
-#define               DENALI_PI_222_DATA 0b00000000000000000000000001110011 // PI_TXSNR_F1:RW:0:16:=0x0073
-#define               DENALI_PI_223_DATA 0b00000000000000000000000010100000 // PI_TINIT_F2:RW:0:24:=0x0000a0
-#define               DENALI_PI_224_DATA 0b00000000000000000000000000000001 // PI_TINIT3_F2:RW:0:24:=0x000001
-#define               DENALI_PI_225_DATA 0b00000000000000000000000000000101 // PI_TINIT4_F2:RW:0:24:=0x000005
-#define               DENALI_PI_226_DATA 0b00000000000000000000000001010000 // PI_TINIT5_F2:RW:0:24:=0x000050
-#define               DENALI_PI_227_DATA 0b00000001000000000000000011100110 // RESERVED:RW:16:12:=0x0100 PI_TXSNR_F2:RW:0:16:=0x00e6
-#define               DENALI_PI_228_DATA 0b00000000000101000000000001000000 // PI_TZQCAL_F0:RW:16:12:=0x0014 RESERVED:RW:0:12:=0x0040
-#define               DENALI_PI_229_DATA 0b00000000000000010000000000000001 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F0:RW:0:7:=0x01
-#define               DENALI_PI_230_DATA 0b00000001100100000000000001000000 // PI_TZQCAL_F1:RW:16:12:=0x0190 RESERVED:RW:0:12:=0x0040
-#define               DENALI_PI_231_DATA 0b00000000000000010000000000001100 // RESERVED:RW:8:12:=0x0100 PI_TZQLAT_F1:RW:0:7:=0x0c
-#define               DENALI_PI_232_DATA 0b00000011001000000000000001000000 // PI_TZQCAL_F2:RW:16:12:=0x0320 RESERVED:RW:0:12:=0x0040
-#define               DENALI_PI_233_DATA 0b00000000000000000000001100011000 // RESERVED:RW:8:12:=0x0003 PI_TZQLAT_F2:RW:0:7:=0x18
-#define               DENALI_PI_234_DATA 0b00000000001010000000000000010100 // RESERVED:RW:16:12:=0x0028 RESERVED:RW:0:12:=0x0014
-#define               DENALI_PI_235_DATA 0b00000001000000010000000100000001 // PI_MEMDATA_RATIO_3:RW:24:3:=0x01 PI_MEMDATA_RATIO_2:RW:16:3:=0x01 PI_MEMDATA_RATIO_1:RW:8:3:=0x01 PI_MEMDATA_RATIO_0:RW:0:3:=0x01
-#define               DENALI_PI_236_DATA 0b00000010000000100000000100000001 // PI_ODT_WR_MAP_CS1:RW:24:4:=0x02 PI_ODT_RD_MAP_CS1:RW:16:4:=0x02 PI_ODT_WR_MAP_CS0:RW:8:4:=0x01 PI_ODT_RD_MAP_CS0:RW:0:4:=0x01
-#define               DENALI_PI_237_DATA 0b00001000000010000000010000000100 // PI_ODT_WR_MAP_CS3:RW:24:4:=0x08 PI_ODT_RD_MAP_CS3:RW:16:4:=0x08 PI_ODT_WR_MAP_CS2:RW:8:4:=0x04 PI_ODT_RD_MAP_CS2:RW:0:4:=0x04
-#define               DENALI_PI_238_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV0_3:RW:24:7:=0x67 PI_VREF_VAL_DEV0_2:RW:16:7:=0x67 PI_VREF_VAL_DEV0_1:RW:8:7:=0x67 PI_VREF_VAL_DEV0_0:RW:0:7:=0x67
-#define               DENALI_PI_239_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV1_3:RW:24:7:=0x67 PI_VREF_VAL_DEV1_2:RW:16:7:=0x67 PI_VREF_VAL_DEV1_1:RW:8:7:=0x67 PI_VREF_VAL_DEV1_0:RW:0:7:=0x67
-#define               DENALI_PI_240_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV2_3:RW:24:7:=0x67 PI_VREF_VAL_DEV2_2:RW:16:7:=0x67 PI_VREF_VAL_DEV2_1:RW:8:7:=0x67 PI_VREF_VAL_DEV2_0:RW:0:7:=0x67
-#define               DENALI_PI_241_DATA 0b01100111011001110110011101100111 // PI_VREF_VAL_DEV3_3:RW:24:7:=0x67 PI_VREF_VAL_DEV3_2:RW:16:7:=0x67 PI_VREF_VAL_DEV3_1:RW:8:7:=0x67 PI_VREF_VAL_DEV3_0:RW:0:7:=0x67
-#define               DENALI_PI_242_DATA 0b00000000000000000000000000000000 // PI_SLICE_PER_DEV_3:RW:24:2:=0x00 PI_SLICE_PER_DEV_2:RW:16:2:=0x00 PI_SLICE_PER_DEV_1:RW:8:2:=0x00 PI_SLICE_PER_DEV_0:RW:0:2:=0x00
-#define               DENALI_PI_243_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_0_3:RD:24:6:=0x00 PI_MR6_VREF_0_2:RD:16:6:=0x00 PI_MR6_VREF_0_1:RD:8:6:=0x00 PI_MR6_VREF_0_0:RD:0:6:=0x00
-#define               DENALI_PI_244_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_1_3:RD:24:6:=0x00 PI_MR6_VREF_1_2:RD:16:6:=0x00 PI_MR6_VREF_1_1:RD:8:6:=0x00 PI_MR6_VREF_1_0:RD:0:6:=0x00
-#define               DENALI_PI_245_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_2_3:RD:24:6:=0x00 PI_MR6_VREF_2_2:RD:16:6:=0x00 PI_MR6_VREF_2_1:RD:8:6:=0x00 PI_MR6_VREF_2_0:RD:0:6:=0x00
-#define               DENALI_PI_246_DATA 0b00000000000000000000000000000000 // PI_MR6_VREF_3_3:RD:24:6:=0x00 PI_MR6_VREF_3_2:RD:16:6:=0x00 PI_MR6_VREF_3_1:RD:8:6:=0x00 PI_MR6_VREF_3_0:RD:0:6:=0x00
-#define               DENALI_PI_247_DATA 0b00000000000000000101010100000000 // PI_MR17_DATA_0:RW:24:8:=0x00 PI_MR16_DATA_0:RW:16:8:=0x00 PI_MR15_DATA_0:RW:8:8:=0x55 PI_MR13_DATA_0:RW+:0:8:=0x00
-#define               DENALI_PI_248_DATA 0b00000000000000000101101000000000 // PI_MR32_DATA_0:RW:8:17:=0x00005a PI_MR20_DATA_0:RW:0:8:=0x00
-#define               DENALI_PI_249_DATA 0b00000000010101010000000000111100 // PI_MR16_DATA_1:RW:24:8:=0x00 PI_MR15_DATA_1:RW:16:8:=0x55 PI_MR13_DATA_1:RW+:8:8:=0x00 PI_MR40_DATA_0:RW:0:8:=0x3c
-#define               DENALI_PI_250_DATA 0b00000000000000000000000000000000 // PI_MR20_DATA_1:RW:8:8:=0x00 PI_MR17_DATA_1:RW:0:8:=0x00
-#define               DENALI_PI_251_DATA 0b00111100000000000000000001011010 // PI_MR40_DATA_1:RW:24:8:=0x3c PI_MR32_DATA_1:RW:0:17:=0x00005a
-#define               DENALI_PI_252_DATA 0b00000000000000000101010100000000 // PI_MR17_DATA_2:RW:24:8:=0x00 PI_MR16_DATA_2:RW:16:8:=0x00 PI_MR15_DATA_2:RW:8:8:=0x55 PI_MR13_DATA_2:RW+:0:8:=0x00
-#define               DENALI_PI_253_DATA 0b00000000000000000101101000000000 // PI_MR32_DATA_2:RW:8:17:=0x00005a PI_MR20_DATA_2:RW:0:8:=0x00
-#define               DENALI_PI_254_DATA 0b00000000010101010000000000111100 // PI_MR16_DATA_3:RW:24:8:=0x00 PI_MR15_DATA_3:RW:16:8:=0x55 PI_MR13_DATA_3:RW+:8:8:=0x00 PI_MR40_DATA_2:RW:0:8:=0x3c
-#define               DENALI_PI_255_DATA 0b00000000000000000000000000000000 // PI_MR20_DATA_3:RW:8:8:=0x00 PI_MR17_DATA_3:RW:0:8:=0x00
-#define               DENALI_PI_256_DATA 0b00111100000000000000000001011010 // PI_MR40_DATA_3:RW:24:8:=0x3c PI_MR32_DATA_3:RW:0:17:=0x00005a
-#define               DENALI_PI_257_DATA 0b00011000000101110001011000010101 // PI_CKE_MUX_3:RW_D:24:5:=0x18 PI_CKE_MUX_2:RW_D:16:5:=0x17 PI_CKE_MUX_1:RW_D:8:5:=0x16 PI_CKE_MUX_0:RW_D:0:5:=0x15
-#define               DENALI_PI_258_DATA 0b00010100000100110001001000010001 // PI_CS_MUX_3:RW_D:24:5:=0x14 PI_CS_MUX_2:RW_D:16:5:=0x13 PI_CS_MUX_1:RW_D:8:5:=0x12 PI_CS_MUX_0:RW_D:0:5:=0x11
-#define               DENALI_PI_259_DATA 0b00000111000001100000010100000100 // PI_ODT_MUX_3:RW_D:24:5:=0x07 PI_ODT_MUX_2:RW_D:16:5:=0x06 PI_ODT_MUX_1:RW_D:8:5:=0x05 PI_ODT_MUX_0:RW_D:0:5:=0x04
-#define               DENALI_PI_260_DATA 0b00000011000000100000000100000000 // PI_RESET_N_MUX_3:RW_D:24:5:=0x03 PI_RESET_N_MUX_2:RW_D:16:5:=0x02 PI_RESET_N_MUX_1:RW_D:8:5:=0x01 PI_RESET_N_MUX_0:RW_D:0:5:=0x00
-#define               DENALI_PI_261_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_0:RW:0:17:=0x000000
-#define               DENALI_PI_262_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_1:RW:0:17:=0x000000
-#define               DENALI_PI_263_DATA 0b00000000000000000000000000000000 // PI_MRSINGLE_DATA_2:RW:0:17:=0x000000
-#define               DENALI_PI_264_DATA 0b00000001000000000000000000000000 // PI_ZQ_CAL_START_MAP_0:RW_D:24:4:=0x01 PI_MRSINGLE_DATA_3:RW:0:17:=0x000000
-#define               DENALI_PI_265_DATA 0b00000100000000100000001000000001 // PI_ZQ_CAL_START_MAP_2:RW_D:24:4:=0x04 PI_ZQ_CAL_LATCH_MAP_1:RW_D:16:4:=0x02 PI_ZQ_CAL_START_MAP_1:RW_D:8:4:=0x02 PI_ZQ_CAL_LATCH_MAP_0:RW_D:0:4:=0x01
-#define               DENALI_PI_266_DATA 0b00000000000010000000100000000100 // PI_ZQ_CAL_LATCH_MAP_3:RW_D:16:4:=0x08 PI_ZQ_CAL_START_MAP_3:RW_D:8:4:=0x08 PI_ZQ_CAL_LATCH_MAP_2:RW_D:0:4:=0x04
-#define               DENALI_PI_267_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_0:RW:0:17:=0x000000
-#define               DENALI_PI_268_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_0:RW+:0:17:=0x000004
-#define               DENALI_PI_269_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_0:RW+:0:17:=0x000000
-#define               DENALI_PI_270_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_0:RW+:0:17:=0x000031
-#define               DENALI_PI_271_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_0:RW:0:17:=0x000031
-#define               DENALI_PI_272_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_0:RW:0:17:=0x000000
-#define               DENALI_PI_273_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_0:RW+:24:8:=0x00 PI_MR6_DATA_F0_0:RW+:0:17:=0x000000
-#define               DENALI_PI_274_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_0:RW+:16:8:=0x00 PI_MR14_DATA_F0_0:RW+:8:8:=0x4d PI_MR12_DATA_F0_0:RW+:0:8:=0x4d
-#define               DENALI_PI_275_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_0:RW:0:17:=0x000000
-#define               DENALI_PI_276_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_0:RW+:0:17:=0x000014
-#define               DENALI_PI_277_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_0:RW+:0:17:=0x000009
-#define               DENALI_PI_278_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_0:RW+:0:17:=0x000031
-#define               DENALI_PI_279_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_0:RW:0:17:=0x000031
-#define               DENALI_PI_280_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_0:RW:0:17:=0x000000
-#define               DENALI_PI_281_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_0:RW+:24:8:=0x00 PI_MR6_DATA_F1_0:RW+:0:17:=0x000000
-#define               DENALI_PI_282_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_0:RW+:16:8:=0x00 PI_MR14_DATA_F1_0:RW+:8:8:=0x4d PI_MR12_DATA_F1_0:RW+:0:8:=0x4d
-#define               DENALI_PI_283_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_0:RW:0:17:=0x000000
-#define               DENALI_PI_284_DATA 0b00000000000000000000000000100100 // PI_MR1_DATA_F2_0:RW+:0:17:=0x000024
-#define               DENALI_PI_285_DATA 0b00000000000000000000000000010010 // PI_MR2_DATA_F2_0:RW+:0:17:=0x000012
-#define               DENALI_PI_286_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_0:RW+:0:17:=0x000031
-#define               DENALI_PI_287_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_0:RW:0:17:=0x000031
-#define               DENALI_PI_288_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_0:RW:0:17:=0x000000
-#define               DENALI_PI_289_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_0:RW+:24:8:=0x00 PI_MR6_DATA_F2_0:RW+:0:17:=0x000000
-#define               DENALI_PI_290_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_0:RW+:16:8:=0x00 PI_MR14_DATA_F2_0:RW+:8:8:=0x4d PI_MR12_DATA_F2_0:RW+:0:8:=0x4d
-#define               DENALI_PI_291_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_1:RW:0:17:=0x000000
-#define               DENALI_PI_292_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_1:RW+:0:17:=0x000004
-#define               DENALI_PI_293_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_1:RW+:0:17:=0x000000
-#define               DENALI_PI_294_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_1:RW+:0:17:=0x000031
-#define               DENALI_PI_295_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_1:RW:0:17:=0x000031
-#define               DENALI_PI_296_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_1:RW:0:17:=0x000000
-#define               DENALI_PI_297_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_1:RW+:24:8:=0x00 PI_MR6_DATA_F0_1:RW+:0:17:=0x000000
-#define               DENALI_PI_298_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_1:RW+:16:8:=0x00 PI_MR14_DATA_F0_1:RW+:8:8:=0x4d PI_MR12_DATA_F0_1:RW+:0:8:=0x4d
-#define               DENALI_PI_299_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_1:RW:0:17:=0x000000
-#define               DENALI_PI_300_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_1:RW+:0:17:=0x000014
-#define               DENALI_PI_301_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_1:RW+:0:17:=0x000009
-#define               DENALI_PI_302_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_1:RW+:0:17:=0x000031
-#define               DENALI_PI_303_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_1:RW:0:17:=0x000031
-#define               DENALI_PI_304_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_1:RW:0:17:=0x000000
-#define               DENALI_PI_305_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_1:RW+:24:8:=0x00 PI_MR6_DATA_F1_1:RW+:0:17:=0x000000
-#define               DENALI_PI_306_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_1:RW+:16:8:=0x00 PI_MR14_DATA_F1_1:RW+:8:8:=0x4d PI_MR12_DATA_F1_1:RW+:0:8:=0x4d
-#define               DENALI_PI_307_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_1:RW:0:17:=0x000000
-#define               DENALI_PI_308_DATA 0b00000000000000000000000000100100 // PI_MR1_DATA_F2_1:RW+:0:17:=0x000024
-#define               DENALI_PI_309_DATA 0b00000000000000000000000000010010 // PI_MR2_DATA_F2_1:RW+:0:17:=0x000012
-#define               DENALI_PI_310_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_1:RW+:0:17:=0x000031
-#define               DENALI_PI_311_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_1:RW:0:17:=0x000031
-#define               DENALI_PI_312_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_1:RW:0:17:=0x000000
-#define               DENALI_PI_313_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_1:RW+:24:8:=0x00 PI_MR6_DATA_F2_1:RW+:0:17:=0x000000
-#define               DENALI_PI_314_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_1:RW+:16:8:=0x00 PI_MR14_DATA_F2_1:RW+:8:8:=0x4d PI_MR12_DATA_F2_1:RW+:0:8:=0x4d
-#define               DENALI_PI_315_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_2:RW:0:17:=0x000000
-#define               DENALI_PI_316_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_2:RW+:0:17:=0x000004
-#define               DENALI_PI_317_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_2:RW+:0:17:=0x000000
-#define               DENALI_PI_318_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_2:RW+:0:17:=0x000031
-#define               DENALI_PI_319_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_2:RW:0:17:=0x000031
-#define               DENALI_PI_320_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_2:RW:0:17:=0x000000
-#define               DENALI_PI_321_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_2:RW+:24:8:=0x00 PI_MR6_DATA_F0_2:RW+:0:17:=0x000000
-#define               DENALI_PI_322_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_2:RW+:16:8:=0x00 PI_MR14_DATA_F0_2:RW+:8:8:=0x4d PI_MR12_DATA_F0_2:RW+:0:8:=0x4d
-#define               DENALI_PI_323_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_2:RW:0:17:=0x000000
-#define               DENALI_PI_324_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_2:RW+:0:17:=0x000014
-#define               DENALI_PI_325_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_2:RW+:0:17:=0x000009
-#define               DENALI_PI_326_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_2:RW+:0:17:=0x000031
-#define               DENALI_PI_327_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_2:RW:0:17:=0x000031
-#define               DENALI_PI_328_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_2:RW:0:17:=0x000000
-#define               DENALI_PI_329_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_2:RW+:24:8:=0x00 PI_MR6_DATA_F1_2:RW+:0:17:=0x000000
-#define               DENALI_PI_330_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_2:RW+:16:8:=0x00 PI_MR14_DATA_F1_2:RW+:8:8:=0x4d PI_MR12_DATA_F1_2:RW+:0:8:=0x4d
-#define               DENALI_PI_331_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_2:RW:0:17:=0x000000
-#define               DENALI_PI_332_DATA 0b00000000000000000000000000100100 // PI_MR1_DATA_F2_2:RW+:0:17:=0x000024
-#define               DENALI_PI_333_DATA 0b00000000000000000000000000010010 // PI_MR2_DATA_F2_2:RW+:0:17:=0x000012
-#define               DENALI_PI_334_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_2:RW+:0:17:=0x000031
-#define               DENALI_PI_335_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_2:RW:0:17:=0x000031
-#define               DENALI_PI_336_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_2:RW:0:17:=0x000000
-#define               DENALI_PI_337_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_2:RW+:24:8:=0x00 PI_MR6_DATA_F2_2:RW+:0:17:=0x000000
-#define               DENALI_PI_338_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_2:RW+:16:8:=0x00 PI_MR14_DATA_F2_2:RW+:8:8:=0x4d PI_MR12_DATA_F2_2:RW+:0:8:=0x4d
-#define               DENALI_PI_339_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F0_3:RW:0:17:=0x000000
-#define               DENALI_PI_340_DATA 0b00000000000000000000000000000100 // PI_MR1_DATA_F0_3:RW+:0:17:=0x000004
-#define               DENALI_PI_341_DATA 0b00000000000000000000000000000000 // PI_MR2_DATA_F0_3:RW+:0:17:=0x000000
-#define               DENALI_PI_342_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F0_3:RW+:0:17:=0x000031
-#define               DENALI_PI_343_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F0_3:RW:0:17:=0x000031
-#define               DENALI_PI_344_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F0_3:RW:0:17:=0x000000
-#define               DENALI_PI_345_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F0_3:RW+:24:8:=0x00 PI_MR6_DATA_F0_3:RW+:0:17:=0x000000
-#define               DENALI_PI_346_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F0_3:RW+:16:8:=0x00 PI_MR14_DATA_F0_3:RW+:8:8:=0x4d PI_MR12_DATA_F0_3:RW+:0:8:=0x4d
-#define               DENALI_PI_347_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F1_3:RW:0:17:=0x000000
-#define               DENALI_PI_348_DATA 0b00000000000000000000000000010100 // PI_MR1_DATA_F1_3:RW+:0:17:=0x000014
-#define               DENALI_PI_349_DATA 0b00000000000000000000000000001001 // PI_MR2_DATA_F1_3:RW+:0:17:=0x000009
-#define               DENALI_PI_350_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F1_3:RW+:0:17:=0x000031
-#define               DENALI_PI_351_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F1_3:RW:0:17:=0x000031
-#define               DENALI_PI_352_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F1_3:RW:0:17:=0x000000
-#define               DENALI_PI_353_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F1_3:RW+:24:8:=0x00 PI_MR6_DATA_F1_3:RW+:0:17:=0x000000
-#define               DENALI_PI_354_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F1_3:RW+:16:8:=0x00 PI_MR14_DATA_F1_3:RW+:8:8:=0x4d PI_MR12_DATA_F1_3:RW+:0:8:=0x4d
-#define               DENALI_PI_355_DATA 0b00000000000000000000000000000000 // PI_MR0_DATA_F2_3:RW:0:17:=0x000000
-#define               DENALI_PI_356_DATA 0b00000000000000000000000000100100 // PI_MR1_DATA_F2_3:RW+:0:17:=0x000024
-#define               DENALI_PI_357_DATA 0b00000000000000000000000000010010 // PI_MR2_DATA_F2_3:RW+:0:17:=0x000012
-#define               DENALI_PI_358_DATA 0b00000000000000000000000000110001 // PI_MR3_DATA_F2_3:RW+:0:17:=0x000031
-#define               DENALI_PI_359_DATA 0b00000000000000000000000000110001 // PI_MR4_DATA_F2_3:RW:0:17:=0x000031
-#define               DENALI_PI_360_DATA 0b00000000000000000000000000000000 // PI_MR5_DATA_F2_3:RW:0:17:=0x000000
-#define               DENALI_PI_361_DATA 0b00000000000000000000000000000000 // PI_MR11_DATA_F2_3:RW+:24:8:=0x00 PI_MR6_DATA_F2_3:RW+:0:17:=0x000000
-#define               DENALI_PI_362_DATA 0b00000000000000000100110101001101 // PI_MR22_DATA_F2_3:RW+:16:8:=0x00 PI_MR14_DATA_F2_3:RW+:8:8:=0x4d PI_MR12_DATA_F2_3:RW+:0:8:=0x4d
-//* ********************************************************
-//* The below are used only for simulation phy purposes.
-//* Please ignore if using integrated Cadence PHY.
-//* SimulationValues {{{
-//* ********************************************************
-#define SIM_PHY_VALS_DEFINED 1 // Global define for simulation
-#define                        SMALL_TREF_ENABLE 0x0 // CTL
-#define                                  MR8_VAL 0x10 // CTL
-#define                                  MR0_VAL 0x0 // CTL
-#define                          MR0_RL3_SUPPORT 0x0 // CTL
-#define                            ODT_RD_TIMING 0x0 // CTL
-#define                                  TAC_MIN 0x0 // CTL
-#define                                  TAC_MAX 0x0 // CTL
-#define               LPDDR1_PD_CLK_GATE_DISABLE 0x0 // CTL
-#define                          LPDDR1_ATTACHED 0x0 // CTL
-//* ********************************************************
-//* SimulationValues }}}
-//* ********************************************************