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Fix I and D cache synchronization issue

I-cache is not coherent with memory and also with
D-cache so after copying data from flash and before
jumping to next software stack we must use the
Instruction-Fetch Fence to make sure I and D caches
are synchronized to PoU.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
Rajnesh Kanwal 2 years ago
parent
commit
3b3c12d9cd
1 changed files with 2 additions and 0 deletions
  1. 2 0
      boot/start.S

+ 2 - 0
boot/start.S

@@ -108,6 +108,8 @@ _start:
 	j .LwaitOtherHart
 
 .enter_uboot:
+	# Synchronize the instruction and data caches.
+	fence.i
 	li t0, DEFAULT_UBOOT_ADDR
 	csrr a0, mhartid
 	la a1, 0