m68k.h 6.3 KB

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  1. /* m68k.h: Definitions for M68000 code fixup
  2. Copyright (C) 2003 Sebastian Reichelt
  3. Copyright (C) 2003 Kevin Kofler
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2, or (at your option)
  7. any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; if not, write to the Free Software Foundation,
  14. Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
  15. #ifndef BINCODE_M68K_H
  16. #define BINCODE_M68K_H
  17. #include "../generic.h"
  18. // *** Generic Definitions ***
  19. // Maximum distance for a relative reloc of the specified size.
  20. #define M68K_REL_MAX_2 0x7FFF
  21. #define M68K_REL_MIN_2 (-0x8000)
  22. #define M68K_REL_MAX_1 0x7F
  23. #define M68K_REL_MIN_1 (-0x7F)
  24. #define M68K_REL_MAX M68K_REL_MAX_2
  25. #define M68K_REL_MIN M68K_REL_MIN_2
  26. #define M68K_REL_OK(Distance,Size) (((Distance) >= M68K_REL_MIN_##Size) && ((Distance) <= M68K_REL_MAX_##Size))
  27. // Make a relative opcode out of an absolute one.
  28. #define M68K_MAKE_REL_OPCODE_1(Opcode_1) ((Opcode_1)++)
  29. // *** General Branches ***
  30. // Opcode of the unconditional absolute JMP instruction.
  31. #define M68K_JMP_0 0x4E
  32. #define M68K_JMP_1 0xF9
  33. #define M68K_BRA_W_0 0x60
  34. #define M68K_BRA_W_1 0x00
  35. #define M68K_BRA_S_0 0x60
  36. // Opcode of the Bcc.W instruction family (including BRA.W and BSR.W).
  37. #define M68K_Bcc_W_0 0x60
  38. #define M68K_Bcc_W_1 0x00
  39. // Opcode of the Bcc.S instruction family (including BRA.S and BSR.S).
  40. #define M68K_Bcc_S_0 0x60
  41. // Mask for the Bcc instruction family.
  42. #define M68K_Bcc_MASK_0 0xF0
  43. // *** Subroutine Branches ***
  44. // Opcode of the absolute JSR instruction.
  45. #define M68K_JSR_0 0x4E
  46. #define M68K_JSR_1 0xB9
  47. // Opcode of the BSR.W instruction.
  48. #define M68K_BSR_W_0 0x61
  49. #define M68K_BSR_W_1 0x00
  50. // Opcode of the BSR.S instruction.
  51. #define M68K_BSR_S_0 0x61
  52. // *** Move Instructions ***
  53. // Opcode of MOVE.x var.L,reg/(reg)/(reg)+.
  54. #define M68K_MOVE_ABS_REG_0 0x00
  55. #define M68K_MOVE_ABS_REG_1 0x39
  56. // Mask for MOVE.x var.L,reg/(reg)/(reg)+: 11000001 00111111.
  57. #define M68K_MOVE_ABS_REG_MASK_0 0xC1
  58. #define M68K_MOVE_ABS_REG_MASK_1 0x3F
  59. // Invalid instructions for MOVE.x var.L,reg/(reg)/(reg)+.
  60. // Everything starting with 0 on the first hex number is not a MOVE (0x0???).
  61. #define M68K_MOVE_ABS_REG_INV_0_0 0x00
  62. #define M68K_MOVE_ABS_REG_INV_0_MASK_0 0xF0
  63. // MOVE.B var.L,reg cannot use address registers for reg (0x1?7?).
  64. #define M68K_MOVE_ABS_REG_INV_1_0 0x10
  65. #define M68K_MOVE_ABS_REG_INV_1_1 0x70
  66. #define M68K_MOVE_ABS_REG_INV_1_MASK_0 0xF0
  67. #define M68K_MOVE_ABS_REG_INV_1_MASK_1 0xF0
  68. // Opcode of MOVE.x var.L,-(reg).
  69. #define M68K_MOVE_ABS_PREDEC_0 0x01
  70. #define M68K_MOVE_ABS_PREDEC_1 0x39
  71. // Mask for MOVE.x var.L,-(reg): 11000001 11111111.
  72. #define M68K_MOVE_ABS_PREDEC_MASK_0 0xC1
  73. #define M68K_MOVE_ABS_PREDEC_MASK_1 0xFF
  74. // Invalid instructions for MOVE.x var.L,-(reg).
  75. // Everything starting with 0 on the first hex number is not a MOVE (0x0???).
  76. #define M68K_MOVE_ABS_PREDEC_INV_0_0 0x00
  77. #define M68K_MOVE_ABS_PREDEC_INV_0_MASK_0 0xF0
  78. // Opcode of MOVE.x var.L,ofs(reg).
  79. #define M68K_MOVE_ABS_OFSREG_0 0x01
  80. #define M68K_MOVE_ABS_OFSREG_1 0x79
  81. // Mask for MOVE.x var.L,ofs(reg): 11000001 11111111.
  82. #define M68K_MOVE_ABS_OFSREG_MASK_0 0xC1
  83. #define M68K_MOVE_ABS_OFSREG_MASK_1 0xFF
  84. // Invalid instructions for MOVE.x var.L,ofs(reg).
  85. // Everything starting with 0 on the first hex number is not a MOVE (0x0???).
  86. #define M68K_MOVE_ABS_OFSREG_INV_0_0 0x00
  87. #define M68K_MOVE_ABS_OFSREG_INV_0_MASK_0 0xF0
  88. // Opcode of MOVEM.x var.L,regs
  89. #define M68K_MOVEM_ABS_REGS_0 0x4C
  90. #define M68K_MOVEM_ABS_REGS_1 0xB9
  91. // Mask for MOVEM.x var.L,regs: 11111111 10111111.
  92. #define M68K_MOVEM_ABS_REGS_MASK_0 0xFF
  93. #define M68K_MOVEM_ABS_REGS_MASK_1 0xBF
  94. // Opcode of LEA(.L) var.L,reg.
  95. #define M68K_LEA_ABS_0 0x41
  96. #define M68K_LEA_ABS_1 0xF9
  97. // Mask for LEA(.L) var.L,reg: 11110001 11111111.
  98. #define M68K_LEA_ABS_MASK_0 0xF1
  99. #define M68K_LEA_ABS_MASK_1 0xFF
  100. // Opcode of PEA(.L) var.L.
  101. #define M68K_PEA_ABS_0 0x48
  102. #define M68K_PEA_ABS_1 0x79
  103. // *** Test Instructions ***
  104. // Opcode of CMP.x var.L,reg.
  105. #define M68K_CMP_ABS_REG_0 0xB0
  106. #define M68K_CMP_ABS_REG_1 0x39
  107. // Mask for CMP.x var.L,reg: 11110001 00111111.
  108. #define M68K_CMP_ABS_REG_MASK_0 0xF1
  109. #define M68K_CMP_ABS_REG_MASK_1 0x3F
  110. // The second byte cannot start with F (0x??F?).
  111. #define M68K_CMP_ABS_REG_INV_0_1 0xF0
  112. #define M68K_CMP_ABS_REG_INV_0_MASK_1 0xF0
  113. // Opcode of BTST reg,var.L.
  114. #define M68K_BTST_REG_ABS_0 0x01
  115. #define M68K_BTST_REG_ABS_1 0x39
  116. // Mask for BTST reg,var.L: 11110001 11111111.
  117. #define M68K_BTST_REG_ABS_MASK_0 0xF1
  118. #define M68K_BTST_REG_ABS_MASK_1 0xFF
  119. // Opcode of BTST #num,var.L.
  120. #define M68K_BTST_IMM_ABS_0 0x08
  121. #define M68K_BTST_IMM_ABS_1 0x39
  122. #define M68K_BTST_IMM_ABS_2 0x00
  123. // *** Calculation Instructions ***
  124. // 1st Opcode of ADD/SUB.x var.L,reg.
  125. #define M68K_ADDSUB_ABS_REG_0_0 0x90
  126. #define M68K_ADDSUB_ABS_REG_0_1 0x39
  127. // 1st Mask for ADD/SUB.x var.L,reg: 10110001 00111111.
  128. #define M68K_ADDSUB_ABS_REG_0_MASK_0 0xB1
  129. #define M68K_ADDSUB_ABS_REG_0_MASK_1 0x3F
  130. // 2nd Opcode of ADD/SUB.x var.L,reg.
  131. #define M68K_ADDSUB_ABS_REG_1_0 0x91
  132. #define M68K_ADDSUB_ABS_REG_1_1 0xF9
  133. // 2nd Mask for ADD/SUB.x var.L,reg: 10110001 11111111.
  134. #define M68K_ADDSUB_ABS_REG_1_MASK_0 0xB1
  135. #define M68K_ADDSUB_ABS_REG_1_MASK_1 0xFF
  136. // Opcode of MULx/DIVx.x var.L,reg.
  137. #define M68K_MULDIV_ABS_REG_0 0x80
  138. #define M68K_MULDIV_ABS_REG_1 0xF9
  139. // Mask for MULx/DIVx.x var.L,reg.: 10110000 11111111.
  140. #define M68K_MULDIV_ABS_REG_MASK_0 0xB0
  141. #define M68K_MULDIV_ABS_REG_MASK_1 0xFF
  142. // Opcode of AND/OR.x var.L,reg.
  143. #define M68K_ANDOR_ABS_REG_0 0x80
  144. #define M68K_ANDOR_ABS_REG_1 0x39
  145. // Mask for AND/OR.x var.L,reg.: 10110001 00111111.
  146. #define M68K_ANDOR_ABS_REG_MASK_0 0xB1
  147. #define M68K_ANDOR_ABS_REG_MASK_1 0x3F
  148. // The second byte cannot start with F (0x??F?). Otherwise it is a MULx/DIVx.
  149. #define M68K_ANDOR_ABS_REG_INV_0_1 0xF0
  150. #define M68K_ANDOR_ABS_REG_INV_0_MASK_1 0xF0
  151. // *** Other Instructions ***
  152. // Opcode of the NOP instruction.
  153. #define M68K_NOP_0 0x4E
  154. #define M68K_NOP_1 0x71
  155. // Opcode of the RTS instruction.
  156. #define M68K_RTS_0 0x4E
  157. #define M68K_RTS_1 0x75
  158. #endif