m68k.h 14 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368
  1. /* Opcode table header for m680[01234]0/m6888[12]/m68851.
  2. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001,
  3. 2003, 2004, 2006 Free Software Foundation, Inc.
  4. This file is part of GDB, GAS, and the GNU binutils.
  5. GDB, GAS, and the GNU binutils are free software; you can redistribute
  6. them and/or modify them under the terms of the GNU General Public
  7. License as published by the Free Software Foundation; either version
  8. 1, or (at your option) any later version.
  9. GDB, GAS, and the GNU binutils are distributed in the hope that they
  10. will be useful, but WITHOUT ANY WARRANTY; without even the implied
  11. warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
  12. the GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this file; see the file COPYING. If not, write to the Free
  15. Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
  16. 02110-1301, USA. */
  17. /* These are used as bit flags for the arch field in the m68k_opcode
  18. structure. */
  19. #define _m68k_undef 0
  20. #define m68000 0x001
  21. #define m68010 0x002
  22. #define m68020 0x004
  23. #define m68030 0x008
  24. #define m68040 0x010
  25. #define m68060 0x020
  26. #define m68881 0x040
  27. #define m68851 0x080
  28. #define cpu32 0x100 /* e.g., 68332 */
  29. #define m68k_mask 0x1ff
  30. #define mcfmac 0x200 /* ColdFire MAC. */
  31. #define mcfemac 0x400 /* ColdFire EMAC. */
  32. #define cfloat 0x800 /* ColdFire FPU. */
  33. #define mcfhwdiv 0x1000 /* ColdFire hardware divide. */
  34. #define mcfisa_a 0x2000 /* ColdFire ISA_A. */
  35. #define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */
  36. #define mcfisa_b 0x8000 /* ColdFire ISA_B. */
  37. #define mcfusp 0x10000 /* ColdFire USP instructions. */
  38. #define mcf_mask 0x1f200
  39. /* Handy aliases. */
  40. #define m68040up (m68040 | m68060)
  41. #define m68030up (m68030 | m68040up)
  42. #define m68020up (m68020 | m68030up)
  43. #define m68010up (m68010 | cpu32 | m68020up)
  44. #define m68000up (m68000 | m68010up)
  45. #define mfloat (m68881 | m68040 | m68060)
  46. #define mmmu (m68851 | m68030 | m68040 | m68060)
  47. /* The structure used to hold information for an opcode. */
  48. struct m68k_opcode
  49. {
  50. /* The opcode name. */
  51. const char *name;
  52. /* The pseudo-size of the instruction(in bytes). Used to determine
  53. number of bytes necessary to disassemble the instruction. */
  54. unsigned int size;
  55. /* The opcode itself. */
  56. unsigned long opcode;
  57. /* The mask used by the disassembler. */
  58. unsigned long match;
  59. /* The arguments. */
  60. const char *args;
  61. /* The architectures which support this opcode. */
  62. unsigned int arch;
  63. };
  64. /* The structure used to hold information for an opcode alias. */
  65. struct m68k_opcode_alias
  66. {
  67. /* The alias name. */
  68. const char *alias;
  69. /* The instruction for which this is an alias. */
  70. const char *primary;
  71. };
  72. /* We store four bytes of opcode for all opcodes because that is the
  73. most any of them need. The actual length of an instruction is
  74. always at least 2 bytes, and is as much longer as necessary to hold
  75. the operands it has.
  76. The match field is a mask saying which bits must match particular
  77. opcode in order for an instruction to be an instance of that
  78. opcode.
  79. The args field is a string containing two characters for each
  80. operand of the instruction. The first specifies the kind of
  81. operand; the second, the place it is stored. */
  82. /* Kinds of operands:
  83. Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+-
  84. D data register only. Stored as 3 bits.
  85. A address register only. Stored as 3 bits.
  86. a address register indirect only. Stored as 3 bits.
  87. R either kind of register. Stored as 4 bits.
  88. r either kind of register indirect only. Stored as 4 bits.
  89. At the moment, used only for cas2 instruction.
  90. F floating point coprocessor register only. Stored as 3 bits.
  91. O an offset (or width): immediate data 0-31 or data register.
  92. Stored as 6 bits in special format for BF... insns.
  93. + autoincrement only. Stored as 3 bits (number of the address register).
  94. - autodecrement only. Stored as 3 bits (number of the address register).
  95. Q quick immediate data. Stored as 3 bits.
  96. This matches an immediate operand only when value is in range 1 .. 8.
  97. M moveq immediate data. Stored as 8 bits.
  98. This matches an immediate operand only when value is in range -128..127
  99. T trap vector immediate data. Stored as 4 bits.
  100. k K-factor for fmove.p instruction. Stored as a 7-bit constant or
  101. a three bit register offset, depending on the field type.
  102. # immediate data. Stored in special places (b, w or l)
  103. which say how many bits to store.
  104. ^ immediate data for floating point instructions. Special places
  105. are offset by 2 bytes from '#'...
  106. B pc-relative address, converted to an offset
  107. that is treated as immediate data.
  108. d displacement and register. Stores the register as 3 bits
  109. and stores the displacement in the entire second word.
  110. C the CCR. No need to store it; this is just for filtering validity.
  111. S the SR. No need to store, just as with CCR.
  112. U the USP. No need to store, just as with CCR.
  113. E the MAC ACC. No need to store, just as with CCR.
  114. e the EMAC ACC[0123].
  115. G the MAC/EMAC MACSR. No need to store, just as with CCR.
  116. g the EMAC ACCEXT{01,23}.
  117. H the MASK. No need to store, just as with CCR.
  118. i the MAC/EMAC scale factor.
  119. I Coprocessor ID. Not printed if 1. The Coprocessor ID is always
  120. extracted from the 'd' field of word one, which means that an extended
  121. coprocessor opcode can be skipped using the 'i' place, if needed.
  122. s System Control register for the floating point coprocessor.
  123. J Misc register for movec instruction, stored in 'j' format.
  124. Possible values:
  125. 0x000 SFC Source Function Code reg [60, 40, 30, 20, 10]
  126. 0x001 DFC Data Function Code reg [60, 40, 30, 20, 10]
  127. 0x002 CACR Cache Control Register [60, 40, 30, 20, mcf]
  128. 0x003 TC MMU Translation Control [60, 40]
  129. 0x004 ITT0 Instruction Transparent
  130. Translation reg 0 [60, 40]
  131. 0x005 ITT1 Instruction Transparent
  132. Translation reg 1 [60, 40]
  133. 0x006 DTT0 Data Transparent
  134. Translation reg 0 [60, 40]
  135. 0x007 DTT1 Data Transparent
  136. Translation reg 1 [60, 40]
  137. 0x008 BUSCR Bus Control Register [60]
  138. 0x800 USP User Stack Pointer [60, 40, 30, 20, 10]
  139. 0x801 VBR Vector Base reg [60, 40, 30, 20, 10, mcf]
  140. 0x802 CAAR Cache Address Register [ 30, 20]
  141. 0x803 MSP Master Stack Pointer [ 40, 30, 20]
  142. 0x804 ISP Interrupt Stack Pointer [ 40, 30, 20]
  143. 0x805 MMUSR MMU Status reg [ 40]
  144. 0x806 URP User Root Pointer [60, 40]
  145. 0x807 SRP Supervisor Root Pointer [60, 40]
  146. 0x808 PCR Processor Configuration reg [60]
  147. 0xC00 ROMBAR ROM Base Address Register [520X]
  148. 0xC04 RAMBAR0 RAM Base Address Register 0 [520X]
  149. 0xC05 RAMBAR1 RAM Base Address Register 0 [520X]
  150. 0xC0F MBAR0 RAM Base Address Register 0 [520X]
  151. 0xC04 FLASHBAR FLASH Base Address Register [mcf528x]
  152. 0xC05 RAMBAR Static RAM Base Address Register [mcf528x]
  153. L Register list of the type d0-d7/a0-a7 etc.
  154. (New! Improved! Can also hold fp0-fp7, as well!)
  155. The assembler tries to see if the registers match the insn by
  156. looking at where the insn wants them stored.
  157. l Register list like L, but with all the bits reversed.
  158. Used for going the other way. . .
  159. c cache identifier which may be "nc" for no cache, "ic"
  160. for instruction cache, "dc" for data cache, or "bc"
  161. for both caches. Used in cinv and cpush. Always
  162. stored in position "d".
  163. u Any register, with ``upper'' or ``lower'' specification. Used
  164. in the mac instructions with size word.
  165. The remainder are all stored as 6 bits using an address mode and a
  166. register number; they differ in which addressing modes they match.
  167. * all (modes 0-6,7.0-4)
  168. ~ alterable memory (modes 2-6,7.0,7.1)
  169. (not 0,1,7.2-4)
  170. % alterable (modes 0-6,7.0,7.1)
  171. (not 7.2-4)
  172. ; data (modes 0,2-6,7.0-4)
  173. (not 1)
  174. @ data, but not immediate (modes 0,2-6,7.0-3)
  175. (not 1,7.4)
  176. ! control (modes 2,5,6,7.0-3)
  177. (not 0,1,3,4,7.4)
  178. & alterable control (modes 2,5,6,7.0,7.1)
  179. (not 0,1,3,4,7.2-4)
  180. $ alterable data (modes 0,2-6,7.0,7.1)
  181. (not 1,7.2-4)
  182. ? alterable control, or data register (modes 0,2,5,6,7.0,7.1)
  183. (not 1,3,4,7.2-4)
  184. / control, or data register (modes 0,2,5,6,7.0-3)
  185. (not 1,3,4,7.4)
  186. > *save operands (modes 2,4,5,6,7.0,7.1)
  187. (not 0,1,3,7.2-4)
  188. < *restore operands (modes 2,3,5,6,7.0-3)
  189. (not 0,1,4,7.4)
  190. coldfire move operands:
  191. m (modes 0-4)
  192. n (modes 5,7.2)
  193. o (modes 6,7.0,7.1,7.3,7.4)
  194. p (modes 0-5)
  195. coldfire bset/bclr/btst/mulsl/mulul operands:
  196. q (modes 0,2-5)
  197. v (modes 0,2-5,7.0,7.1)
  198. b (modes 0,2-5,7.2)
  199. w (modes 2-5,7.2)
  200. y (modes 2,5)
  201. z (modes 2,5,7.2)
  202. x mov3q immediate operand.
  203. 4 (modes 2,3,4,5)
  204. */
  205. /* For the 68851: */
  206. /* I didn't use much imagination in choosing the
  207. following codes, so many of them aren't very
  208. mnemonic. -rab
  209. 0 32 bit pmmu register
  210. Possible values:
  211. 000 TC Translation Control Register (68030, 68851)
  212. 1 16 bit pmmu register
  213. 111 AC Access Control (68851)
  214. 2 8 bit pmmu register
  215. 100 CAL Current Access Level (68851)
  216. 101 VAL Validate Access Level (68851)
  217. 110 SCC Stack Change Control (68851)
  218. 3 68030-only pmmu registers (32 bit)
  219. 010 TT0 Transparent Translation reg 0
  220. (aka Access Control reg 0 -- AC0 -- on 68ec030)
  221. 011 TT1 Transparent Translation reg 1
  222. (aka Access Control reg 1 -- AC1 -- on 68ec030)
  223. W wide pmmu registers
  224. Possible values:
  225. 001 DRP Dma Root Pointer (68851)
  226. 010 SRP Supervisor Root Pointer (68030, 68851)
  227. 011 CRP Cpu Root Pointer (68030, 68851)
  228. f function code register (68030, 68851)
  229. 0 SFC
  230. 1 DFC
  231. V VAL register only (68851)
  232. X BADx, BACx (16 bit)
  233. 100 BAD Breakpoint Acknowledge Data (68851)
  234. 101 BAC Breakpoint Acknowledge Control (68851)
  235. Y PSR (68851) (MMUSR on 68030) (ACUSR on 68ec030)
  236. Z PCSR (68851)
  237. | memory (modes 2-6, 7.*)
  238. t address test level (68030 only)
  239. Stored as 3 bits, range 0-7.
  240. Also used for breakpoint instruction now.
  241. */
  242. /* Places to put an operand, for non-general operands:
  243. Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/
  244. s source, low bits of first word.
  245. d dest, shifted 9 in first word
  246. 1 second word, shifted 12
  247. 2 second word, shifted 6
  248. 3 second word, shifted 0
  249. 4 third word, shifted 12
  250. 5 third word, shifted 6
  251. 6 third word, shifted 0
  252. 7 second word, shifted 7
  253. 8 second word, shifted 10
  254. 9 second word, shifted 5
  255. D store in both place 1 and place 3; for divul and divsl.
  256. B first word, low byte, for branch displacements
  257. W second word (entire), for branch displacements
  258. L second and third words (entire), for branch displacements
  259. (also overloaded for move16)
  260. b second word, low byte
  261. w second word (entire) [variable word/long branch offset for dbra]
  262. W second word (entire) (must be signed 16 bit value)
  263. l second and third word (entire)
  264. g variable branch offset for bra and similar instructions.
  265. The place to store depends on the magnitude of offset.
  266. t store in both place 7 and place 8; for floating point operations
  267. c branch offset for cpBcc operations.
  268. The place to store is word two if bit six of word one is zero,
  269. and words two and three if bit six of word one is one.
  270. i Increment by two, to skip over coprocessor extended operands. Only
  271. works with the 'I' format.
  272. k Dynamic K-factor field. Bits 6-4 of word 2, used as a register number.
  273. Also used for dynamic fmovem instruction.
  274. C floating point coprocessor constant - 7 bits. Also used for static
  275. K-factors...
  276. j Movec register #, stored in 12 low bits of second word.
  277. m For M[S]ACx; 4 bits split with MSB shifted 6 bits in first word
  278. and remaining 3 bits of register shifted 9 bits in first word.
  279. Indicate upper/lower in 1 bit shifted 7 bits in second word.
  280. Use with `R' or `u' format.
  281. n `m' withouth upper/lower indication. (For M[S]ACx; 4 bits split
  282. with MSB shifted 6 bits in first word and remaining 3 bits of
  283. register shifted 9 bits in first word. No upper/lower
  284. indication is done.) Use with `R' or `u' format.
  285. o For M[S]ACw; 4 bits shifted 12 in second word (like `1').
  286. Indicate upper/lower in 1 bit shifted 7 bits in second word.
  287. Use with `R' or `u' format.
  288. M For M[S]ACw; 4 bits in low bits of first word. Indicate
  289. upper/lower in 1 bit shifted 6 bits in second word. Use with
  290. `R' or `u' format.
  291. N For M[S]ACw; 4 bits in low bits of second word. Indicate
  292. upper/lower in 1 bit shifted 6 bits in second word. Use with
  293. `R' or `u' format.
  294. h shift indicator (scale factor), 1 bit shifted 10 in second word
  295. Places to put operand, for general operands:
  296. d destination, shifted 6 bits in first word
  297. b source, at low bit of first word, and immediate uses one byte
  298. w source, at low bit of first word, and immediate uses two bytes
  299. l source, at low bit of first word, and immediate uses four bytes
  300. s source, at low bit of first word.
  301. Used sometimes in contexts where immediate is not allowed anyway.
  302. f single precision float, low bit of 1st word, immediate uses 4 bytes
  303. F double precision float, low bit of 1st word, immediate uses 8 bytes
  304. x extended precision float, low bit of 1st word, immediate uses 12 bytes
  305. p packed float, low bit of 1st word, immediate uses 12 bytes
  306. G EMAC accumulator, load (bit 4 2nd word, !bit8 first word)
  307. H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word)
  308. F EMAC ACCx
  309. f EMAC ACCy
  310. I MAC/EMAC scale factor
  311. / Like 's', but set 2nd word, bit 5 if trailing_ampersand set
  312. ] first word, bit 10
  313. */
  314. extern const struct m68k_opcode m68k_opcodes[];
  315. extern const struct m68k_opcode_alias m68k_opcode_aliases[];
  316. extern const int m68k_numopcodes, m68k_numaliases;
  317. /* end of m68k-opcode.h */