s3c6400-ac97.c 12 KB

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  1. /*
  2. * s3c6400-ac97.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
  5. *
  6. * (c) 2007 Wolfson Microelectronics PLC.
  7. * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
  8. *
  9. * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
  10. * All rights reserved.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. *
  16. * Revision history
  17. * 21st Mar 2007 Initial Version
  18. * 20th Sep 2007 Apply at s3c6400
  19. */
  20. #include <linux/init.h>
  21. #include <linux/module.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/wait.h>
  25. #include <linux/delay.h>
  26. #include <linux/clk.h>
  27. #include <sound/driver.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/ac97_codec.h>
  31. #include <sound/initval.h>
  32. #include <sound/soc.h>
  33. #include <asm/hardware.h>
  34. #include <asm/io.h>
  35. #include <asm/arch/regs-ac97.h>
  36. #include <asm/arch/regs-gpio.h>
  37. #include <asm/arch/regs-s3c6400-clock.h>
  38. #include <asm/arch/audio.h>
  39. #include <asm/dma.h>
  40. #include <asm/arch/dma.h>
  41. #include "s3c-pcm.h"
  42. #include "s3c6400-ac97.h"
  43. #ifdef CONFIG_SND_DEBUG
  44. #define s3cdbg(x...) printk(x)
  45. #else
  46. #define s3cdbg(x...)
  47. #endif
  48. extern struct clk *clk_get(struct device *dev, const char *id);
  49. extern int clk_enable(struct clk *clk);
  50. extern void clk_disable(struct clk *clk);
  51. struct s3c24xx_ac97_info {
  52. void __iomem *regs;
  53. struct clk *ac97_clk;
  54. };
  55. static struct s3c24xx_ac97_info s3c24xx_ac97;
  56. static u32 codec_ready;
  57. static DEFINE_MUTEX(ac97_mutex);
  58. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  59. static unsigned short s3c6400_ac97_read(struct snd_ac97 *ac97,
  60. unsigned short reg)
  61. {
  62. u32 ac_glbctrl;
  63. u32 ac_codec_cmd;
  64. u32 stat, addr, data;
  65. s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg);
  66. mutex_lock(&ac97_mutex);
  67. codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  68. ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  69. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  70. udelay(1000);
  71. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  72. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  73. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  74. stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
  75. addr = (stat >> 16) & 0x7f;
  76. data = (stat & 0xffff);
  77. wait_event_timeout(gsr_wq,addr==reg,1);
  78. if(addr!=reg){
  79. printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr);
  80. printk(KERN_ERR"Check audio codec jumpper settings\n\n");
  81. goto out;
  82. }
  83. out: mutex_unlock(&ac97_mutex);
  84. return (unsigned short)data;
  85. }
  86. static void s3c6400_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  87. unsigned short val)
  88. {
  89. u32 ac_glbctrl;
  90. u32 ac_codec_cmd;
  91. u32 stat, data;
  92. s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val);
  93. mutex_lock(&ac97_mutex);
  94. codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  95. ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  96. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  97. udelay(50);
  98. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  99. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  100. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  101. ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
  102. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  103. stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  104. data = (stat & 0xffff);
  105. wait_event_timeout(gsr_wq,data==val,1);
  106. if(data!=val){
  107. printk("%s: write error (ac97_val=%x data=%x)\n",
  108. __FUNCTION__, val, data);
  109. }
  110. mutex_unlock(&ac97_mutex);
  111. }
  112. static void s3c6400_ac97_warm_reset(struct snd_ac97 *ac97)
  113. {
  114. u32 ac_glbctrl;
  115. s3cdbg("Entered %s\n", __FUNCTION__);
  116. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  117. ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET;
  118. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  119. msleep(1);
  120. ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET;
  121. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  122. msleep(1);
  123. ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
  124. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  125. msleep(1);
  126. ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
  127. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  128. msleep(1);
  129. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
  130. S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
  131. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  132. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  133. ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON;
  134. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  135. udelay(1000);
  136. }
  137. static void s3c6400_ac97_cold_reset(struct snd_ac97 *ac97)
  138. {
  139. u32 ac_glbctrl;
  140. s3cdbg("Entered %s\n", __FUNCTION__);
  141. ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
  142. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  143. msleep(1);
  144. ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
  145. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  146. msleep(1);
  147. ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
  148. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  149. msleep(1);
  150. ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
  151. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  152. msleep(1);
  153. }
  154. static irqreturn_t s3c6400_ac97_irq(int irq, void *dev_id)
  155. {
  156. int status;
  157. u32 ac_glbctrl, ac_glbstat;
  158. ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT);
  159. s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat);
  160. status = ac_glbstat & codec_ready;
  161. if (status) {
  162. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  163. ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
  164. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  165. wake_up(&gsr_wq);
  166. }
  167. return IRQ_HANDLED;
  168. }
  169. struct snd_ac97_bus_ops soc_ac97_ops = {
  170. .read = s3c6400_ac97_read,
  171. .write = s3c6400_ac97_write,
  172. .warm_reset = s3c6400_ac97_warm_reset,
  173. .reset = s3c6400_ac97_cold_reset,
  174. };
  175. static struct s3c2410_dma_client s3c6400_dma_client_out = {
  176. .name = "AC97 PCM Stereo out"
  177. };
  178. static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_out = {
  179. .client = &s3c6400_dma_client_out,
  180. .channel = DMACH_AC97_PCM_OUT,
  181. .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA,
  182. .dma_size = 4,
  183. };
  184. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  185. static struct s3c2410_dma_client s3c6400_dma_client_micin = {
  186. .name = "AC97 Mic Mono in"
  187. };
  188. static struct s3c24xx_pcm_dma_params s3c6400_ac97_mic_mono_in = {
  189. .client = &s3c6400_dma_client_micin,
  190. .channel = DMACH_AC97_MIC_IN,
  191. .dma_addr = S3C6400_PA_AC97 + S3C_AC97_MIC_DATA,
  192. .dma_size = 4,
  193. };
  194. #else /* Input Stream is LINE-IN */
  195. static struct s3c2410_dma_client s3c6400_dma_client_in = {
  196. .name = "AC97 PCM Stereo Line in"
  197. };
  198. static struct s3c24xx_pcm_dma_params s3c6400_ac97_pcm_stereo_in = {
  199. .client = &s3c6400_dma_client_in,
  200. .channel = DMACH_AC97_PCM_IN,
  201. .dma_addr = S3C6400_PA_AC97 + S3C_AC97_PCM_DATA,
  202. .dma_size = 4,
  203. };
  204. #endif
  205. static int s3c6400_ac97_probe(struct platform_device *pdev)
  206. {
  207. int ret;
  208. s3cdbg("Entered %s\n", __FUNCTION__);
  209. s3c24xx_ac97.regs = ioremap(S3C6400_PA_AC97, 0x100);
  210. if (s3c24xx_ac97.regs == NULL)
  211. return -ENXIO;
  212. s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
  213. if (s3c24xx_ac97.ac97_clk == NULL) {
  214. printk(KERN_ERR "s3c6400-ac97 failed to get ac97_clock\n");
  215. iounmap(s3c24xx_ac97.regs);
  216. return -ENODEV;
  217. }
  218. clk_enable(s3c24xx_ac97.ac97_clk);
  219. s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_AC97_BITCLK);
  220. s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_AC97_RESET);
  221. s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_AC97_SYNC);
  222. s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_AC97_SDI);
  223. s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_AC97_SDO);
  224. s3c_gpio_pullup(S3C_GPD0,0);
  225. s3c_gpio_pullup(S3C_GPD1,0);
  226. s3c_gpio_pullup(S3C_GPD2,0);
  227. s3c_gpio_pullup(S3C_GPD3,0);
  228. s3c_gpio_pullup(S3C_GPD4,0);
  229. ret = request_irq(IRQ_AC97, s3c6400_ac97_irq,
  230. IRQF_DISABLED, "AC97", NULL);
  231. if (ret < 0) {
  232. printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
  233. clk_disable(s3c24xx_ac97.ac97_clk);
  234. clk_put(s3c24xx_ac97.ac97_clk);
  235. iounmap(s3c24xx_ac97.regs);
  236. }
  237. return ret;
  238. }
  239. static void s3c6400_ac97_remove(struct platform_device *pdev)
  240. {
  241. s3cdbg("Entered %s\n", __FUNCTION__);
  242. free_irq(IRQ_AC97, NULL);
  243. clk_disable(s3c24xx_ac97.ac97_clk);
  244. clk_put(s3c24xx_ac97.ac97_clk);
  245. iounmap(s3c24xx_ac97.regs);
  246. }
  247. static int s3c6400_ac97_hw_params(struct snd_pcm_substream *substream,
  248. struct snd_pcm_hw_params *params)
  249. {
  250. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  251. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  252. s3cdbg("Entered %s\n", __FUNCTION__);
  253. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  254. cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_out;
  255. else
  256. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  257. cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in;
  258. #else /* Input Stream is LINE-IN */
  259. cpu_dai->dma_data = &s3c6400_ac97_pcm_stereo_in;
  260. #endif
  261. return 0;
  262. }
  263. static int s3c6400_ac97_hifi_prepare(struct snd_pcm_substream *substream)
  264. {
  265. /*
  266. * To support full duplex
  267. * Tested by cat /dev/dsp > /dev/dsp
  268. */
  269. s3cdbg("Entered %s\n", __FUNCTION__);
  270. s3c6400_ac97_write(0,0x26,0x0);
  271. s3c6400_ac97_write(0, 0x0c, 0x0808);
  272. s3c6400_ac97_write(0,0x3c, 0xf803);
  273. s3c6400_ac97_write(0,0x3e,0xb990);
  274. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  275. s3c6400_ac97_write(0,0x02, 0x8080);
  276. s3c6400_ac97_write(0, 0x04, 0x0606);
  277. s3c6400_ac97_write(0,0x1c, 0x00aa);
  278. }
  279. else
  280. {
  281. s3c6400_ac97_write(0, 0x12, 0x0f0f);
  282. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  283. s3c6400_ac97_write(0,0x5c,0x2);
  284. s3c6400_ac97_write(0,0x10,0x68);
  285. s3c6400_ac97_write(0,0x14,0xfe00);
  286. #else /* Input Stream is LINE-IN */
  287. s3c6400_ac97_write(0, 0x14, 0xd612);
  288. #endif
  289. }
  290. return 0;
  291. }
  292. static int s3c6400_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
  293. {
  294. u32 ac_glbctrl;
  295. s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
  296. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  297. switch(cmd) {
  298. case SNDRV_PCM_TRIGGER_START:
  299. case SNDRV_PCM_TRIGGER_RESUME:
  300. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  301. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  302. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  303. else
  304. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
  305. break;
  306. case SNDRV_PCM_TRIGGER_STOP:
  307. case SNDRV_PCM_TRIGGER_SUSPEND:
  308. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  309. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  310. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  311. else
  312. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
  313. break;
  314. }
  315. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  316. return 0;
  317. }
  318. #if 0
  319. static int s3c6400_ac97_hw_mic_params(struct snd_pcm_substream *substream,
  320. struct snd_pcm_hw_params *params)
  321. {
  322. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  323. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  324. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  325. return -ENODEV;
  326. else
  327. cpu_dai->dma_data = &s3c6400_ac97_mic_mono_in;
  328. return 0;
  329. }
  330. static int s3c6400_ac97_mic_trigger(struct snd_pcm_substream *substream,
  331. int cmd)
  332. {
  333. u32 ac_glbctrl;
  334. s3cdbg("Entered %s\n", __FUNCTION__);
  335. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  336. switch(cmd) {
  337. case SNDRV_PCM_TRIGGER_START:
  338. case SNDRV_PCM_TRIGGER_RESUME:
  339. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  340. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  341. break;
  342. case SNDRV_PCM_TRIGGER_STOP:
  343. case SNDRV_PCM_TRIGGER_SUSPEND:
  344. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  345. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  346. }
  347. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  348. return 0;
  349. }
  350. #endif
  351. #define s3c6400_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  352. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  353. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  354. struct snd_soc_cpu_dai s3c6400_ac97_dai[] = {
  355. {
  356. .name = "s3c6400-ac97",
  357. .id = 0,
  358. .type = SND_SOC_DAI_AC97,
  359. .probe = s3c6400_ac97_probe,
  360. .remove = s3c6400_ac97_remove,
  361. .playback = {
  362. .stream_name = "AC97 Playback",
  363. .channels_min = 2,
  364. .channels_max = 2,
  365. .rates = s3c6400_AC97_RATES,
  366. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  367. .capture = {
  368. .stream_name = "AC97 Capture",
  369. .channels_min = 2,
  370. .channels_max = 2,
  371. .rates = s3c6400_AC97_RATES,
  372. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  373. .ops = {
  374. .hw_params = s3c6400_ac97_hw_params,
  375. .prepare = s3c6400_ac97_hifi_prepare,
  376. .trigger = s3c6400_ac97_trigger},
  377. },
  378. #if 0
  379. {
  380. .name = "s3c6400-ac97-mic",
  381. .id = 1,
  382. .type = SND_SOC_DAI_AC97,
  383. .capture = {
  384. .stream_name = "AC97 Mic Capture",
  385. .channels_min = 1,
  386. .channels_max = 1,
  387. .rates = s3c6400_AC97_RATES,
  388. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  389. .ops = {
  390. .hw_params = s3c6400_ac97_hw_mic_params,
  391. .trigger = s3c6400_ac97_mic_trigger,},
  392. },
  393. #endif
  394. };
  395. EXPORT_SYMBOL_GPL(s3c6400_ac97_dai);
  396. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  397. MODULE_AUTHOR("Ryu Euiyoul");
  398. MODULE_DESCRIPTION("AC97 driver for the Samsung s3c6400 chip");
  399. MODULE_LICENSE("GPL");