s3c2450-ac97.c 14 KB

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  1. /*
  2. * s3c2450-ac97.c -- ALSA Soc Audio Layer
  3. *
  4. * (c) 2007 Wolfson Microelectronics PLC.
  5. * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
  6. *
  7. * Copyright (C) 2007, Ryu Euiyoul <ryu.real@gmail.com>
  8. * All rights reserved.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * Revision history
  15. * 21st Mar 2007 Initial Version
  16. */
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/wait.h>
  22. #include <linux/delay.h>
  23. #include <linux/clk.h>
  24. #include <sound/driver.h>
  25. #include <sound/core.h>
  26. #include <sound/pcm.h>
  27. #include <sound/ac97_codec.h>
  28. #include <sound/initval.h>
  29. #include <sound/soc.h>
  30. #include <asm/hardware.h>
  31. #include <asm/io.h>
  32. #include <asm/arch/regs-ac97.h>
  33. #include <asm/arch/regs-gpio.h>
  34. #include <asm/arch/regs-s3c2450-clock.h>
  35. #include <asm/arch/audio.h>
  36. #include <asm/dma.h>
  37. #include <asm/arch/dma.h>
  38. #include "s3c-pcm.h"
  39. #include "s3c24xx-ac97.h"
  40. #ifdef CONFIG_SND_DEBUG
  41. #define s3cdbg(x...) printk(x)
  42. #else
  43. #define s3cdbg(x...)
  44. #endif
  45. extern struct clk *clk_get(struct device *dev, const char *id);
  46. extern int clk_enable(struct clk *clk);
  47. extern void clk_disable(struct clk *clk);
  48. struct s3c24xx_ac97_info {
  49. void __iomem *regs;
  50. struct clk *ac97_clk;
  51. };
  52. static struct s3c24xx_ac97_info s3c24xx_ac97;
  53. static u32 codec_ready;
  54. static DEFINE_MUTEX(ac97_mutex);
  55. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  56. static unsigned short s3c24xx_ac97_read(struct snd_ac97 *ac97,
  57. unsigned short reg)
  58. {
  59. u32 ac_glbctrl;
  60. u32 ac_codec_cmd;
  61. u32 stat, addr, data;
  62. s3cdbg("Entered %s: reg=0x%x\n", __FUNCTION__, reg);
  63. mutex_lock(&ac97_mutex);
  64. codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  65. ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
  66. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  67. udelay(1000);
  68. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  69. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  70. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  71. stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
  72. addr = (stat >> 16) & 0x7f;
  73. data = (stat & 0xffff);
  74. wait_event_timeout(gsr_wq,addr==reg,1);
  75. if(addr!=reg){
  76. printk(KERN_ERR"AC97: read error (ac97_reg=%x addr=%x)\n", reg, addr);
  77. printk(KERN_ERR"Check audio codec jumpper settings\n\n");
  78. goto out;
  79. }
  80. out: mutex_unlock(&ac97_mutex);
  81. return (unsigned short)data;
  82. }
  83. static void s3c24xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  84. unsigned short val)
  85. {
  86. u32 ac_glbctrl;
  87. u32 ac_codec_cmd;
  88. u32 stat, data;
  89. s3cdbg("Entered %s: reg=0x%x, val=0x%x\n", __FUNCTION__,reg,val);
  90. mutex_lock(&ac97_mutex);
  91. codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
  92. ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
  93. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  94. udelay(50);
  95. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  96. ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
  97. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  98. ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
  99. writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  100. stat = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
  101. data = (stat & 0xffff);
  102. wait_event_timeout(gsr_wq,data==val,1);
  103. if(data!=val){
  104. printk("%s: write error (ac97_val=%x data=%x)\n",
  105. __FUNCTION__, val, data);
  106. }
  107. mutex_unlock(&ac97_mutex);
  108. }
  109. static void s3c24xx_ac97_warm_reset(struct snd_ac97 *ac97)
  110. {
  111. u32 ac_glbctrl;
  112. s3cdbg("Entered %s\n", __FUNCTION__);
  113. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  114. ac_glbctrl |= S3C_AC97_GLBCTRL_WARMRESET;
  115. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  116. msleep(1);
  117. ac_glbctrl &= ~S3C_AC97_GLBCTRL_WARMRESET;
  118. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  119. msleep(1);
  120. ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
  121. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  122. msleep(1);
  123. ac_glbctrl = S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
  124. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  125. msleep(1);
  126. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
  127. S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
  128. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  129. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  130. ac_glbctrl |= S3C_AC97_GLBCTRL_ACLINKON;
  131. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  132. udelay(1000);
  133. }
  134. static void s3c24xx_ac97_cold_reset(struct snd_ac97 *ac97)
  135. {
  136. u32 ac_glbctrl;
  137. s3cdbg("Entered %s\n", __FUNCTION__);
  138. ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
  139. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  140. msleep(1);
  141. ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
  142. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  143. msleep(1);
  144. ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
  145. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  146. msleep(1);
  147. ac_glbctrl &= ~S3C_AC97_GLBCTRL_COLDRESET;
  148. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  149. msleep(1);
  150. }
  151. static irqreturn_t s3c24xx_ac97_irq(int irq, void *dev_id)
  152. {
  153. int status;
  154. u32 ac_glbctrl, ac_glbstat;
  155. ac_glbstat = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT);
  156. s3cdbg("Entered %s: AC_GLBSTAT = 0x%x\n", __FUNCTION__, ac_glbstat);
  157. status = ac_glbstat & codec_ready;
  158. if (status) {
  159. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  160. ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
  161. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  162. wake_up(&gsr_wq);
  163. }
  164. return IRQ_HANDLED;
  165. }
  166. struct snd_ac97_bus_ops soc_ac97_ops = {
  167. .read = s3c24xx_ac97_read,
  168. .write = s3c24xx_ac97_write,
  169. .warm_reset = s3c24xx_ac97_warm_reset,
  170. .reset = s3c24xx_ac97_cold_reset,
  171. };
  172. static struct s3c2410_dma_client s3c24xx_dma_client_out = {
  173. .name = "AC97 PCM Stereo out"
  174. };
  175. static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_out = {
  176. .client = &s3c24xx_dma_client_out,
  177. .channel = DMACH_PCM_OUT,
  178. .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  179. .dma_size = 4,
  180. };
  181. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  182. static struct s3c2410_dma_client s3c24xx_dma_client_micin = {
  183. .name = "AC97 Mic Mono in"
  184. };
  185. static struct s3c24xx_pcm_dma_params s3c24xx_ac97_mic_mono_in = {
  186. .client = &s3c24xx_dma_client_micin,
  187. .channel = DMACH_MIC_IN,
  188. .dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  189. .dma_size = 4,
  190. };
  191. #else /* Input Stream is LINE-IN */
  192. static struct s3c2410_dma_client s3c24xx_dma_client_in = {
  193. .name = "AC97 PCM Stereo Line in"
  194. };
  195. static struct s3c24xx_pcm_dma_params s3c24xx_ac97_pcm_stereo_in = {
  196. .client = &s3c24xx_dma_client_in,
  197. .channel = DMACH_PCM_IN,
  198. .dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  199. .dma_size = 4,
  200. };
  201. #endif
  202. static int s3c24xx_ac97_probe(struct platform_device *pdev)
  203. {
  204. int ret;
  205. s3cdbg("Entered %s\n", __FUNCTION__);
  206. s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
  207. if (s3c24xx_ac97.regs == NULL)
  208. return -ENXIO;
  209. s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
  210. if (s3c24xx_ac97.ac97_clk == NULL) {
  211. printk(KERN_ERR "s3c24xx-ac97 failed to get ac97_clock\n");
  212. iounmap(s3c24xx_ac97.regs);
  213. return -ENODEV;
  214. }
  215. clk_enable(s3c24xx_ac97.ac97_clk);
  216. s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
  217. s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
  218. s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
  219. s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
  220. s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
  221. ret = request_irq(IRQ_S3C2443_AC97, s3c24xx_ac97_irq,
  222. IRQF_DISABLED, "AC97", NULL);
  223. if (ret < 0) {
  224. printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
  225. clk_disable(s3c24xx_ac97.ac97_clk);
  226. clk_put(s3c24xx_ac97.ac97_clk);
  227. iounmap(s3c24xx_ac97.regs);
  228. }
  229. return ret;
  230. }
  231. static void s3c24xx_ac97_remove(struct platform_device *pdev)
  232. {
  233. s3cdbg("Entered %s\n", __FUNCTION__);
  234. free_irq(IRQ_S3C2443_AC97, NULL);
  235. clk_disable(s3c24xx_ac97.ac97_clk);
  236. clk_put(s3c24xx_ac97.ac97_clk);
  237. iounmap(s3c24xx_ac97.regs);
  238. }
  239. static int s3c24xx_ac97_hw_params(struct snd_pcm_substream *substream,
  240. struct snd_pcm_hw_params *params)
  241. {
  242. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  243. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  244. s3cdbg("Entered %s\n", __FUNCTION__);
  245. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  246. cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_out;
  247. else
  248. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  249. cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
  250. #else /* Input Stream is LINE-IN */
  251. cpu_dai->dma_data = &s3c24xx_ac97_pcm_stereo_in;
  252. #endif
  253. return 0;
  254. }
  255. static int s3c24xx_ac97_hifi_prepare(struct snd_pcm_substream *substream)
  256. {
  257. s3cdbg("Entered %s\n", __FUNCTION__);
  258. /*
  259. * register 26h : standard power down control register
  260. * now set 0x0 is all power on. Need to optimize if reduce power condition
  261. */
  262. s3c24xx_ac97_write(0,0x26,0x0);
  263. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  264. /*
  265. * register 02h : speaker volume
  266. * now set 0x8080 is mute speaker left and right.
  267. */
  268. s3c24xx_ac97_write(0,0x02,0x8080);
  269. /*
  270. * register 04h : Headphone volume
  271. * now set 0x0606 is Un-Mute headphone and volume set.
  272. */
  273. s3c24xx_ac97_write(0,0x04,0x0606);
  274. /*
  275. * register 0Ch : DAC Volume
  276. * now set 0x6808 is only ON the path to headphone mixer
  277. * and set the DAC volume.
  278. */
  279. s3c24xx_ac97_write(0,0x0c,0x6808);
  280. /*
  281. * register 1Ch : Output PGA Mux select
  282. * now set 0x00aa is headphone mixer and OUT3, OUT4 enable
  283. * to roud sound?
  284. */
  285. s3c24xx_ac97_write(0,0x1c,0x00aa);
  286. /*
  287. * register 3Ch : Power management
  288. * now set 0xf933 enables headphone mixer, DAC, PLL and Vref.
  289. */
  290. s3c24xx_ac97_write(0,0x3c,0xf933);
  291. /*
  292. * register 3Eh : Power management
  293. * now set 0xf9ff only enables headphone output PGA.
  294. */
  295. s3c24xx_ac97_write(0,0x3e,0xf9ff);
  296. }
  297. else
  298. {
  299. /*
  300. * register 0Ch : DAC Volume
  301. * now set 0xe808 is Mute DAC path to headphone,speaker,mono mixer
  302. * and set the DAC volume.
  303. */
  304. s3c24xx_ac97_write(0,0x0c,0xe808);
  305. /*
  306. * register 12h : Record Gain
  307. * 0x0F0F set right and left ADC recording volume as +22.5dB.
  308. */
  309. s3c24xx_ac97_write(0,0x12,0x0f0f);
  310. /*
  311. * register 3Ch : Power management
  312. * now set 0xf933 enables ADC, PLL and Vref.
  313. */
  314. s3c24xx_ac97_write(0,0x3c,0xf8cf);
  315. #ifdef CONFIG_SOUND_WM9713_INPUT_STREAM_MIC
  316. /*
  317. * register 5Ch : ADC SLOT Mapping
  318. * now set 0x2 is Left = slot7, Right = slot8.
  319. */
  320. s3c24xx_ac97_write(0,0x5c,0x2);
  321. /*
  322. * register 22h : MIC input select
  323. */
  324. s3c24xx_ac97_write(0,0x22,0x4060);
  325. /*
  326. * register 10h : MIC Routing
  327. */
  328. s3c24xx_ac97_write(0,0x10,0x68);
  329. /*
  330. * register 14h : Record Routing & Mux select
  331. * Default value 0xD600 is MIC
  332. */
  333. s3c24xx_ac97_write(0,0x14,0xfe00);
  334. /*
  335. * register 3Eh : Power management
  336. * now set 0xff9f only enables LINE PGA.
  337. */
  338. s3c24xx_ac97_write(0,0x3e,0xbff0);
  339. #else /* Input Stream is LINE-IN */
  340. /*
  341. * register 14h : Record Routing & Mux select
  342. * 0xD612 set record mux source as LINE
  343. * and mute headphone, mono mixer path.
  344. * Default value 0xD600 is MIC
  345. */
  346. s3c24xx_ac97_write(0,0x14,0xd612);
  347. /*
  348. * register 3Eh : Power management
  349. * now set 0xff9f only enables LINE PGA.
  350. */
  351. s3c24xx_ac97_write(0,0x3e,0xff9f);
  352. #endif
  353. }
  354. return 0;
  355. }
  356. static int s3c24xx_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
  357. {
  358. u32 ac_glbctrl;
  359. s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
  360. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  361. switch(cmd) {
  362. case SNDRV_PCM_TRIGGER_START:
  363. case SNDRV_PCM_TRIGGER_RESUME:
  364. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  365. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  366. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  367. else
  368. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
  369. break;
  370. case SNDRV_PCM_TRIGGER_STOP:
  371. case SNDRV_PCM_TRIGGER_SUSPEND:
  372. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  373. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  374. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  375. else
  376. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
  377. break;
  378. }
  379. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  380. return 0;
  381. }
  382. #if 0
  383. static int s3c24xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
  384. struct snd_pcm_hw_params *params)
  385. {
  386. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  387. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  388. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  389. return -ENODEV;
  390. else
  391. cpu_dai->dma_data = &s3c24xx_ac97_mic_mono_in;
  392. return 0;
  393. }
  394. static int s3c24xx_ac97_mic_trigger(struct snd_pcm_substream *substream,
  395. int cmd)
  396. {
  397. u32 ac_glbctrl;
  398. s3cdbg("Entered %s\n", __FUNCTION__);
  399. ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  400. switch(cmd) {
  401. case SNDRV_PCM_TRIGGER_START:
  402. case SNDRV_PCM_TRIGGER_RESUME:
  403. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  404. ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
  405. break;
  406. case SNDRV_PCM_TRIGGER_STOP:
  407. case SNDRV_PCM_TRIGGER_SUSPEND:
  408. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  409. ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
  410. }
  411. writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
  412. return 0;
  413. }
  414. #endif
  415. #define s3c24xx_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  416. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
  417. SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
  418. struct snd_soc_cpu_dai s3c24xx_ac97_dai[] = {
  419. {
  420. .name = "s3c24xx-ac97",
  421. .id = 0,
  422. .type = SND_SOC_DAI_AC97,
  423. .probe = s3c24xx_ac97_probe,
  424. .remove = s3c24xx_ac97_remove,
  425. .playback = {
  426. .stream_name = "AC97 Playback",
  427. .channels_min = 2,
  428. .channels_max = 2,
  429. .rates = s3c24xx_AC97_RATES,
  430. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  431. .capture = {
  432. .stream_name = "AC97 Capture",
  433. .channels_min = 2,
  434. .channels_max = 2,
  435. .rates = s3c24xx_AC97_RATES,
  436. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  437. .ops = {
  438. .hw_params = s3c24xx_ac97_hw_params,
  439. .prepare = s3c24xx_ac97_hifi_prepare,
  440. .trigger = s3c24xx_ac97_trigger},
  441. },
  442. #if 0
  443. {
  444. .name = "s3c24xx-ac97-mic",
  445. .id = 1,
  446. .type = SND_SOC_DAI_AC97,
  447. .capture = {
  448. .stream_name = "AC97 Mic Capture",
  449. .channels_min = 1,
  450. .channels_max = 1,
  451. .rates = s3c24xx_AC97_RATES,
  452. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  453. .ops = {
  454. .hw_params = s3c24xx_ac97_hw_mic_params,
  455. .trigger = s3c24xx_ac97_mic_trigger,},
  456. },
  457. #endif
  458. };
  459. EXPORT_SYMBOL_GPL(s3c24xx_ac97_dai);
  460. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  461. MODULE_AUTHOR("Ryu Euiyoul");
  462. MODULE_DESCRIPTION("AC97 driver for the Samsung s3c24xx chip");
  463. MODULE_LICENSE("GPL");