s3c-i2s.c 17 KB

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  1. /*
  2. * s3c-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * (c) 2006 Wolfson Microelectronics PLC.
  5. * Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
  6. *
  7. * (c) 2004-2005 Simtec Electronics
  8. * http://armlinux.simtec.co.uk/
  9. * Ben Dooks <ben@simtec.co.uk>
  10. * Ryu Euiyoul <ryu.real@gmail.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. *
  18. * Revision history
  19. * 11th Dec 2006 Merged with Simtec driver
  20. * 10th Nov 2006 Initial version.
  21. */
  22. #include <linux/init.h>
  23. #include <linux/module.h>
  24. #include <linux/device.h>
  25. #include <linux/delay.h>
  26. #include <linux/clk.h>
  27. #include <sound/driver.h>
  28. #include <sound/core.h>
  29. #include <sound/pcm.h>
  30. #include <sound/pcm_params.h>
  31. #include <sound/initval.h>
  32. #include <sound/soc.h>
  33. #include <asm/hardware.h>
  34. #include <asm/io.h>
  35. #include <asm/dma.h>
  36. #include <asm/arch/regs-iis.h>
  37. #include <asm/arch/regs-gpio.h>
  38. #include <asm/arch/audio.h>
  39. #include <asm/arch/dma.h>
  40. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  41. #include <asm/arch/regs-clock.h>
  42. #else
  43. #include <asm/arch/regs-s3c6400-clock.h>
  44. #endif
  45. #include "s3c-pcm.h"
  46. #include "s3c-i2s.h"
  47. #ifdef CONFIG_SND_DEBUG
  48. #define s3cdbg(x...) printk(x)
  49. #else
  50. #define s3cdbg(x...)
  51. #endif
  52. /* used to disable sysclk if external crystal is used */
  53. static int extclk = 0;
  54. module_param(extclk, int, 0);
  55. MODULE_PARM_DESC(extclk, "set to 1 to disable s3c24XX i2s sysclk");
  56. static struct s3c2410_dma_client s3c24xx_dma_client_out = {
  57. .name = "I2S PCM Stereo out"
  58. };
  59. static struct s3c2410_dma_client s3c24xx_dma_client_in = {
  60. .name = "I2S PCM Stereo in"
  61. };
  62. static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_out = {
  63. .client = &s3c24xx_dma_client_out,
  64. .channel = DMACH_I2S_OUT,
  65. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  66. .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFO,
  67. .dma_size = 2,
  68. #else
  69. .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFO,
  70. .dma_size = 4,
  71. #endif
  72. };
  73. static struct s3c24xx_pcm_dma_params s3c24xx_i2s_pcm_stereo_in = {
  74. .client = &s3c24xx_dma_client_in,
  75. .channel = DMACH_I2S_IN,
  76. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  77. .dma_addr = S3C2410_PA_IIS + S3C2410_IISFIFORX,
  78. .dma_size = 2,
  79. #else
  80. .dma_addr = S3C6400_PA_IIS + S3C2410_IISFIFORX,
  81. .dma_size = 4,
  82. #endif
  83. };
  84. struct s3c24xx_i2s_info {
  85. void __iomem *regs;
  86. struct clk *iis_clk;
  87. int master;
  88. };
  89. static struct s3c24xx_i2s_info s3c24xx_i2s;
  90. static void s3c24xx_snd_txctrl(int on)
  91. {
  92. u32 iisfcon;
  93. u32 iiscon;
  94. u32 iismod;
  95. s3cdbg("Entered %s : on = %d \n", __FUNCTION__, on);
  96. iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
  97. iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
  98. iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
  99. s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
  100. if (on) {
  101. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  102. iisfcon |= S3C2410_IISFCON_TXDMA | S3C2410_IISFCON_TXENABLE;
  103. iiscon |= S3C2410_IISCON_TXDMAEN | S3C2410_IISCON_IISEN;
  104. iiscon &= ~S3C2410_IISCON_TXIDLE;
  105. iismod |= S3C2410_IISMOD_TXMODE;
  106. #else
  107. iiscon |= S3C_IIS0CON_I2SACTIVE;
  108. #endif
  109. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  110. writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
  111. writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
  112. } else {
  113. /* note, we have to disable the FIFOs otherwise bad things
  114. * seem to happen when the DMA stops. According to the
  115. * Samsung supplied kernel, this should allow the DMA
  116. * engine and FIFOs to reset. If this isn't allowed, the
  117. * DMA engine will simply freeze randomly.
  118. */
  119. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  120. iisfcon &= ~S3C2410_IISFCON_TXENABLE;
  121. iisfcon &= ~S3C2410_IISFCON_TXDMA;
  122. iiscon |= S3C2410_IISCON_TXIDLE;
  123. iiscon &= ~S3C2410_IISCON_TXDMAEN;
  124. iismod &= ~S3C2410_IISMOD_TXMODE;
  125. #else
  126. iiscon &=~(S3C_IIS0CON_I2SACTIVE);
  127. iismod &= ~S3C_IIS0MOD_TXMODE;
  128. #endif
  129. writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
  130. writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
  131. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  132. }
  133. s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
  134. }
  135. static void s3c24xx_snd_rxctrl(int on)
  136. {
  137. u32 iisfcon;
  138. u32 iiscon;
  139. u32 iismod;
  140. s3cdbg("Entered %s: on = %d\n", __FUNCTION__, on);
  141. iisfcon = readl(s3c24xx_i2s.regs + S3C2410_IISFCON);
  142. iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
  143. iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
  144. s3cdbg("r: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
  145. if (on) {
  146. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  147. iisfcon |= S3C2410_IISFCON_RXDMA | S3C2410_IISFCON_RXENABLE;
  148. iiscon |= S3C2410_IISCON_RXDMAEN | S3C2410_IISCON_IISEN;
  149. iiscon &= ~S3C2410_IISCON_RXIDLE;
  150. iismod |= S3C2410_IISMOD_RXMODE;
  151. #else
  152. iiscon |= S3C_IIS0CON_I2SACTIVE;
  153. #endif
  154. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  155. writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
  156. writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
  157. } else {
  158. /* note, we have to disable the FIFOs otherwise bad things
  159. * seem to happen when the DMA stops. According to the
  160. * Samsung supplied kernel, this should allow the DMA
  161. * engine and FIFOs to reset. If this isn't allowed, the
  162. * DMA engine will simply freeze randomly.
  163. */
  164. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  165. iisfcon &= ~S3C2410_IISFCON_RXENABLE;
  166. iisfcon &= ~S3C2410_IISFCON_RXDMA;
  167. iiscon |= S3C2410_IISCON_RXIDLE;
  168. iiscon &= ~S3C2410_IISCON_RXDMAEN;
  169. iismod &= ~S3C2410_IISMOD_RXMODE;
  170. #else
  171. iiscon &=~ S3C_IIS0CON_I2SACTIVE;
  172. iismod &= ~S3C_IIS0MOD_RXMODE;
  173. #endif
  174. writel(iisfcon, s3c24xx_i2s.regs + S3C2410_IISFCON);
  175. writel(iiscon, s3c24xx_i2s.regs + S3C2410_IISCON);
  176. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  177. }
  178. s3cdbg("w: IISCON: %x IISMOD: %x IISFCON: %x\n", iiscon, iismod, iisfcon);
  179. }
  180. /*
  181. * Wait for the LR signal to allow synchronisation to the L/R clock
  182. * from the codec. May only be needed for slave mode.
  183. */
  184. static int s3c24xx_snd_lrsync(void)
  185. {
  186. u32 iiscon;
  187. unsigned long timeout = jiffies + msecs_to_jiffies(5);
  188. s3cdbg("Entered %s\n", __FUNCTION__);
  189. while (1) {
  190. iiscon = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
  191. if (iiscon & S3C2410_IISCON_LRINDEX)
  192. break;
  193. if (timeout < jiffies)
  194. return -ETIMEDOUT;
  195. }
  196. return 0;
  197. }
  198. /*
  199. * Check whether CPU is the master or slave
  200. */
  201. static inline int s3c24xx_snd_is_clkmaster(void)
  202. {
  203. s3cdbg("Entered %s\n", __FUNCTION__);
  204. return (readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & S3C2410_IISMOD_SLAVE) ? 0:1;
  205. }
  206. /*
  207. * Set S3C24xx I2S DAI format
  208. */
  209. static int s3c_i2s_set_fmt(struct snd_soc_cpu_dai *cpu_dai,
  210. unsigned int fmt)
  211. {
  212. #if 0
  213. u32 iismod;
  214. s3cdbg("Entered %s: fmt = %d\n", __FUNCTION__, fmt);
  215. iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
  216. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  217. case SND_SOC_DAIFMT_CBM_CFM:
  218. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  219. iismod |= S3C2410_IISMOD_SLAVE;
  220. #else
  221. iismod |= S3C2410_IISMOD_MASTER;
  222. #endif
  223. break;
  224. case SND_SOC_DAIFMT_CBS_CFS:
  225. break;
  226. default:
  227. return -EINVAL;
  228. }
  229. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  230. case SND_SOC_DAIFMT_LEFT_J:
  231. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  232. iismod |= S3C2410_IISMOD_MSB;
  233. #else
  234. iismod |= S3C_IIS0MOD_MSB;
  235. #endif
  236. break;
  237. case SND_SOC_DAIFMT_I2S:
  238. break;
  239. default:
  240. return -EINVAL;
  241. }
  242. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  243. #endif
  244. return 0;
  245. }
  246. static int s3c_i2s_hw_params(struct snd_pcm_substream *substream,
  247. struct snd_pcm_hw_params *params)
  248. {
  249. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  250. unsigned long iiscon;
  251. unsigned long iismod;
  252. unsigned long iisfcon;
  253. s3cdbg("Entered %s\n", __FUNCTION__);
  254. /*Set I2C port to controll WM8753 codec*/
  255. s3c_gpio_pullup(S3C_GPB5, 0);
  256. s3c_gpio_pullup(S3C_GPB6, 0);
  257. s3c_gpio_cfgpin(S3C_GPB5, S3C_GPB5_I2C_SCL);
  258. s3c_gpio_cfgpin(S3C_GPB6, S3C_GPB6_I2C_SDA);
  259. s3c24xx_i2s.master = 1;
  260. /* Configure the I2S pins in correct mode */
  261. s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
  262. if (s3c24xx_i2s.master && !extclk){
  263. s3cdbg("Setting Clock Output as we are Master\n");
  264. s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
  265. }
  266. s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
  267. s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_I2S_DI0);
  268. s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_I2S_DO0);
  269. /* pull-up-enable, pull-down-disable*/
  270. s3c_gpio_pullup(S3C_GPD0, 0x2);
  271. s3c_gpio_pullup(S3C_GPD1, 0x2);
  272. s3c_gpio_pullup(S3C_GPD2, 0x2);
  273. s3c_gpio_pullup(S3C_GPD3, 0x2);
  274. s3c_gpio_pullup(S3C_GPD4, 0x2);
  275. s3cdbg("substream->stream : %d\n", substream->stream);
  276. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  277. rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_out;
  278. } else {
  279. rtd->dai->cpu_dai->dma_data = &s3c24xx_i2s_pcm_stereo_in;
  280. }
  281. /* Working copies of registers */
  282. iiscon = readl(S3C_IIS0CON);
  283. iismod = readl(S3C_IIS0MOD);
  284. iisfcon = readl(S3C_IIS0FIC);
  285. /* is port used by another stream */
  286. if (!(iiscon & S3C_IIS0CON_I2SACTIVE)) {
  287. iismod |= S3C_IIS0MOD_INTERNAL_CLK;
  288. if (!s3c24xx_i2s.master)
  289. iismod |= S3C_IIS0MOD_IMS_SLAVE;
  290. else
  291. iismod |= S3C_IIS0MOD_IMS_EXTERNAL_MASTER;
  292. }
  293. /* enable TX & RX all to support Full-duplex */
  294. iismod |= S3C_IIS0MOD_TXRXMODE;
  295. iiscon |= S3C_IIS0CON_TXDMACTIVE;
  296. iisfcon |= S3C_IIS_TX_FLUSH;
  297. iiscon |= S3C_IIS0CON_RXDMACTIVE;
  298. iisfcon |= S3C_IIS_RX_FLUSH;
  299. /* Set the bit rate */
  300. iismod &= ~0x6000;
  301. switch (params_format(params)) {
  302. case SNDRV_PCM_FORMAT_S16_LE:
  303. iismod |= S3C_IIS0MOD_16BIT;
  304. break;
  305. #ifdef CONFIG_CPU_S3C6410
  306. case SNDRV_PCM_FORMAT_S8:
  307. iismod |= S3C_IIS0MOD_8BIT;
  308. break;
  309. case SNDRV_PCM_FORMAT_S24_LE:
  310. iismod |= S3C_IIS0MOD_24BIT;
  311. break;
  312. #endif
  313. default:
  314. return -EINVAL;
  315. }
  316. writel(iiscon, S3C_IIS0CON);
  317. writel(iismod, S3C_IIS0MOD);
  318. writel(iisfcon, S3C_IIS0FIC);
  319. // Tx, Rx fifo flush bit clear
  320. iisfcon &= ~(S3C_IIS_TX_FLUSH | S3C_IIS_RX_FLUSH);
  321. writel(iisfcon, S3C_IIS0FIC);
  322. s3cdbg("IISCON: %lx IISMOD: %lx", iiscon, iismod);
  323. return 0;
  324. }
  325. static int s3c_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  326. {
  327. int ret = 0;
  328. s3cdbg("Entered %s: cmd = %d\n", __FUNCTION__, cmd);
  329. switch (cmd) {
  330. case SNDRV_PCM_TRIGGER_START:
  331. case SNDRV_PCM_TRIGGER_RESUME:
  332. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  333. if (!s3c24xx_snd_is_clkmaster()) {
  334. ret = s3c24xx_snd_lrsync();
  335. if (ret)
  336. goto exit_err;
  337. }
  338. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  339. s3c24xx_snd_rxctrl(1);
  340. else
  341. s3c24xx_snd_txctrl(1);
  342. break;
  343. case SNDRV_PCM_TRIGGER_STOP:
  344. case SNDRV_PCM_TRIGGER_SUSPEND:
  345. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  346. if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
  347. s3c24xx_snd_rxctrl(0);
  348. else
  349. s3c24xx_snd_txctrl(0);
  350. break;
  351. default:
  352. ret = -EINVAL;
  353. break;
  354. }
  355. exit_err:
  356. return ret;
  357. }
  358. static void s3c64xx_i2s_shutdown(struct snd_pcm_substream *substream)
  359. {
  360. unsigned long iismod, iiscon;
  361. s3cdbg("Entered %s\n", __FUNCTION__);
  362. iismod=readl(S3C_IIS0MOD);
  363. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  364. iismod &= ~S3C_IIS0MOD_TXMODE;
  365. } else {
  366. iismod &= ~S3C_IIS0MOD_RXMODE;
  367. }
  368. writel(iismod,S3C_IIS0MOD);
  369. iiscon=readl(S3C_IIS0CON);
  370. iiscon &= !S3C_IIS0CON_I2SACTIVE;
  371. writel(iiscon,S3C_IIS0CON);
  372. /* Clock disable
  373. * PCLK & SCLK gating disable
  374. */
  375. __raw_writel(__raw_readl(S3C_PCLK_GATE)&~(S3C_CLKCON_PCLK_IIS0), S3C_PCLK_GATE);
  376. __raw_writel(__raw_readl(S3C_SCLK_GATE)&~(S3C_CLKCON_SCLK_AUDIO0), S3C_SCLK_GATE);
  377. /* EPLL disable */
  378. __raw_writel(__raw_readl(S3C_EPLL_CON0)&~(1<<31) ,S3C_EPLL_CON0);
  379. }
  380. /*
  381. * Set S3C24xx Clock source
  382. */
  383. static int s3c_i2s_set_sysclk(struct snd_soc_cpu_dai *cpu_dai,
  384. int clk_id, unsigned int freq, int dir)
  385. {
  386. u32 iismod = readl(s3c24xx_i2s.regs + S3C2410_IISMOD);
  387. s3cdbg("Entered %s : clk_id = %d\n", __FUNCTION__, clk_id);
  388. iismod &= ~S3C2440_IISMOD_MPLL;
  389. switch (clk_id) {
  390. case S3C24XX_CLKSRC_PCLK:
  391. break;
  392. case S3C24XX_CLKSRC_MPLL:
  393. iismod |= S3C2440_IISMOD_MPLL;
  394. break;
  395. default:
  396. return -EINVAL;
  397. }
  398. writel(iismod, s3c24xx_i2s.regs + S3C2410_IISMOD);
  399. return 0;
  400. }
  401. /*
  402. * Set S3C24xx Clock dividers
  403. */
  404. static int s3c_i2s_set_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
  405. int div_id, int div)
  406. {
  407. u32 reg;
  408. s3cdbg("Entered %s : div_id = %d, div = %d\n", __FUNCTION__, div_id, div);
  409. switch (div_id) {
  410. case S3C24XX_DIV_MCLK:
  411. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  412. reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~S3C2410_IISMOD_FS_MASK;
  413. writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
  414. #endif
  415. break;
  416. case S3C24XX_DIV_BCLK:
  417. reg = readl(s3c24xx_i2s.regs + S3C2410_IISMOD) & ~(S3C2410_IISMOD_384FS);
  418. writel(reg | div, s3c24xx_i2s.regs + S3C2410_IISMOD);
  419. break;
  420. case S3C24XX_DIV_PRESCALER:
  421. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  422. writel(div, s3c24xx_i2s.regs + S3C2410_IISPSR);
  423. reg = readl(s3c24xx_i2s.regs + S3C2410_IISCON);
  424. writel(reg | S3C2410_IISCON_PSCEN, s3c24xx_i2s.regs + S3C2410_IISCON);
  425. #else
  426. writel(div|(1<<15),S3C_IIS0PSR);
  427. #endif
  428. break;
  429. default:
  430. return -EINVAL;
  431. }
  432. return 0;
  433. }
  434. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  435. /*
  436. * To avoid duplicating clock code, allow machine driver to
  437. * get the clockrate from here.
  438. */
  439. u32 s3c24xx_i2s_get_clockrate(void)
  440. {
  441. return clk_get_rate(s3c24xx_i2s.iis_clk);
  442. }
  443. EXPORT_SYMBOL_GPL(s3c24xx_i2s_get_clockrate);
  444. #endif
  445. static int s3c_i2s_probe(struct platform_device *pdev)
  446. {
  447. s3cdbg("Entered %s\n", __FUNCTION__);
  448. s3c24xx_i2s.regs = ioremap(S3C24XX_PA_IIS, 0x100);
  449. if (s3c24xx_i2s.regs == NULL)
  450. return -ENXIO;
  451. #if !defined (CONFIG_CPU_S3C6400) && !defined (CONFIG_CPU_S3C6410)
  452. s3c24xx_i2s.iis_clk=clk_get(&pdev->dev, "iis");
  453. if (s3c24xx_i2s.iis_clk == NULL) {
  454. s3cdbg("failed to get iis_clock\n");
  455. return -ENODEV;
  456. }
  457. clk_enable(s3c24xx_i2s.iis_clk);
  458. /* Configure the I2S pins in correct mode */
  459. s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2410_GPE0_I2SLRCK);
  460. s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2410_GPE1_I2SSCLK);
  461. s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2410_GPE2_CDCLK);
  462. s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2410_GPE3_I2SSDI);
  463. s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2410_GPE4_I2SSDO);
  464. writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
  465. /* Configure the I2S pins in correct mode */
  466. s3c_gpio_cfgpin(S3C_GPD2,S3C_GPD2_I2S_LRCLK0);
  467. s3c_gpio_cfgpin(S3C_GPD0,S3C_GPD0_I2S_CLK0);
  468. s3c_gpio_cfgpin(S3C_GPD1,S3C_GPD1_I2S_CDCLK0);
  469. s3c_gpio_cfgpin(S3C_GPD3,S3C_GPD3_I2S_DI0);
  470. s3c_gpio_cfgpin(S3C_GPD4,S3C_GPD4_I2S_DO0);
  471. /* pull-up-enable, pull-down-disable*/
  472. s3c_gpio_pullup(S3C_GPD0, 0x2);
  473. s3c_gpio_pullup(S3C_GPD1, 0x2);
  474. s3c_gpio_pullup(S3C_GPD2, 0x2);
  475. s3c_gpio_pullup(S3C_GPD3, 0x2);
  476. s3c_gpio_pullup(S3C_GPD4, 0x2);
  477. writel(S3C2410_IISCON_IISEN, s3c24xx_i2s.regs + S3C2410_IISCON);
  478. s3c24xx_snd_txctrl(0);
  479. s3c24xx_snd_rxctrl(0);
  480. #endif
  481. return 0;
  482. }
  483. #ifdef CONFIG_PM
  484. static int s3c_i2s_suspend(struct platform_device *dev,
  485. struct snd_soc_cpu_dai *dai)
  486. {
  487. s3cdbg("Entered %s\n", __FUNCTION__);
  488. return 0;
  489. }
  490. static int s3c_i2s_resume(struct platform_device *pdev,
  491. struct snd_soc_cpu_dai *dai)
  492. {
  493. s3cdbg("Entered %s\n", __FUNCTION__);
  494. return 0;
  495. }
  496. #else
  497. #define s3c_i2s_suspend NULL
  498. #define s3c_i2s_resume NULL
  499. #endif
  500. #define S3C24XX_I2S_RATES \
  501. (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 | SNDRV_PCM_RATE_16000 | \
  502. SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | \
  503. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
  504. struct snd_soc_cpu_dai s3c_i2s_dai = {
  505. .name = "s3c-i2s",
  506. .id = 0,
  507. .type = SND_SOC_DAI_I2S,
  508. .probe = s3c_i2s_probe,
  509. .suspend = s3c_i2s_suspend,
  510. .resume = s3c_i2s_resume,
  511. .playback = {
  512. .channels_min = 2,
  513. .channels_max = 2,
  514. .rates = S3C24XX_I2S_RATES,
  515. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,},
  516. .capture = {
  517. .channels_min = 2,
  518. .channels_max = 2,
  519. .rates = S3C24XX_I2S_RATES,
  520. .formats = SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE,},
  521. .ops = {
  522. .shutdown = s3c64xx_i2s_shutdown,
  523. .trigger = s3c_i2s_trigger,
  524. .hw_params = s3c_i2s_hw_params,},
  525. .dai_ops = {
  526. .set_fmt = s3c_i2s_set_fmt,
  527. .set_clkdiv = s3c_i2s_set_clkdiv,
  528. .set_sysclk = s3c_i2s_set_sysclk,
  529. },
  530. };
  531. EXPORT_SYMBOL_GPL(s3c_i2s_dai);
  532. static int __init s3c_i2s_init(void)
  533. {
  534. /* Add in 24 bit audio support - FIXME, detect at runtime */
  535. #ifdef CONFIG_CPU_S3C6410
  536. s3c_i2s_dai.playback.formats |= SNDRV_PCM_FMTBIT_S24_LE;
  537. s3c_i2s_dai.capture.formats |= SNDRV_PCM_FMTBIT_S24_LE;
  538. #endif
  539. return 0;
  540. }
  541. module_init(s3c_i2s_init);
  542. /* Module information */
  543. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  544. MODULE_DESCRIPTION("s3c24xx I2S SoC Interface");
  545. MODULE_LICENSE("GPL");