pxa2xx-i2s.c 6.8 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. * Revision history
  14. * 12th Aug 2005 Initial version.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/device.h>
  19. #include <linux/delay.h>
  20. #include <sound/driver.h>
  21. #include <sound/core.h>
  22. #include <sound/pcm.h>
  23. #include <sound/initval.h>
  24. #include <sound/soc.h>
  25. #include <asm/hardware.h>
  26. #include <asm/arch/pxa-regs.h>
  27. #include <asm/arch/audio.h>
  28. #include "pxa2xx-pcm.h"
  29. #include "pxa2xx-i2s.h"
  30. struct pxa_i2s_port {
  31. u32 sadiv;
  32. u32 sacr0;
  33. u32 sacr1;
  34. u32 saimr;
  35. int master;
  36. u32 fmt;
  37. };
  38. static struct pxa_i2s_port pxa_i2s;
  39. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  40. .name = "I2S PCM Stereo out",
  41. .dev_addr = __PREG(SADR),
  42. .drcmr = &DRCMRTXSADR,
  43. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  44. DCMD_BURST32 | DCMD_WIDTH4,
  45. };
  46. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  47. .name = "I2S PCM Stereo in",
  48. .dev_addr = __PREG(SADR),
  49. .drcmr = &DRCMRRXSADR,
  50. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  51. DCMD_BURST32 | DCMD_WIDTH4,
  52. };
  53. static struct pxa2xx_gpio gpio_bus[] = {
  54. { /* I2S SoC Slave */
  55. .rx = GPIO29_SDATA_IN_I2S_MD,
  56. .tx = GPIO30_SDATA_OUT_I2S_MD,
  57. .clk = GPIO28_BITCLK_IN_I2S_MD,
  58. .frm = GPIO31_SYNC_I2S_MD,
  59. },
  60. { /* I2S SoC Master */
  61. #ifdef CONFIG_PXA27x
  62. .sys = GPIO113_I2S_SYSCLK_MD,
  63. #else
  64. .sys = GPIO32_SYSCLK_I2S_MD,
  65. #endif
  66. .rx = GPIO29_SDATA_IN_I2S_MD,
  67. .tx = GPIO30_SDATA_OUT_I2S_MD,
  68. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  69. .frm = GPIO31_SYNC_I2S_MD,
  70. },
  71. };
  72. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  73. {
  74. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  75. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  76. if (!cpu_dai->active) {
  77. SACR0 |= SACR0_RST;
  78. SACR0 = 0;
  79. }
  80. return 0;
  81. }
  82. /* wait for I2S controller to be ready */
  83. static int pxa_i2s_wait(void)
  84. {
  85. int i;
  86. /* flush the Rx FIFO */
  87. for(i = 0; i < 16; i++)
  88. SADR;
  89. return 0;
  90. }
  91. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
  92. unsigned int fmt)
  93. {
  94. /* interface format */
  95. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  96. case SND_SOC_DAIFMT_I2S:
  97. pxa_i2s.fmt = 0;
  98. break;
  99. case SND_SOC_DAIFMT_LEFT_J:
  100. pxa_i2s.fmt = SACR1_AMSL;
  101. break;
  102. }
  103. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  104. case SND_SOC_DAIFMT_CBS_CFS:
  105. pxa_i2s.master = 1;
  106. break;
  107. case SND_SOC_DAIFMT_CBM_CFS:
  108. pxa_i2s.master = 0;
  109. break;
  110. default:
  111. break;
  112. }
  113. return 0;
  114. }
  115. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
  116. int clk_id, unsigned int freq, int dir)
  117. {
  118. if (clk_id != PXA2XX_I2S_SYSCLK)
  119. return -ENODEV;
  120. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  121. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  122. return 0;
  123. }
  124. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  125. struct snd_pcm_hw_params *params)
  126. {
  127. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  128. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  129. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  130. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  131. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  132. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  133. pxa_set_cken(CKEN8_I2S, 1);
  134. pxa_i2s_wait();
  135. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  136. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  137. else
  138. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  139. /* is port used by another stream */
  140. if (!(SACR0 & SACR0_ENB)) {
  141. SACR0 = 0;
  142. SACR1 = 0;
  143. if (pxa_i2s.master)
  144. SACR0 |= SACR0_BCKD;
  145. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  146. SACR1 |= pxa_i2s.fmt;
  147. }
  148. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  149. SAIMR |= SAIMR_TFS;
  150. else
  151. SAIMR |= SAIMR_RFS;
  152. switch (params_rate(params)) {
  153. case 8000:
  154. SADIV = 0x48;
  155. break;
  156. case 11025:
  157. SADIV = 0x34;
  158. break;
  159. case 16000:
  160. SADIV = 0x24;
  161. break;
  162. case 22050:
  163. SADIV = 0x1a;
  164. break;
  165. case 44100:
  166. SADIV = 0xd;
  167. break;
  168. case 48000:
  169. SADIV = 0xc;
  170. break;
  171. case 96000: /* not in manual and possibly slightly inaccurate */
  172. SADIV = 0x6;
  173. break;
  174. }
  175. return 0;
  176. }
  177. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  178. {
  179. int ret = 0;
  180. switch (cmd) {
  181. case SNDRV_PCM_TRIGGER_START:
  182. SACR0 |= SACR0_ENB;
  183. break;
  184. case SNDRV_PCM_TRIGGER_RESUME:
  185. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  186. case SNDRV_PCM_TRIGGER_STOP:
  187. case SNDRV_PCM_TRIGGER_SUSPEND:
  188. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  189. break;
  190. default:
  191. ret = -EINVAL;
  192. }
  193. return ret;
  194. }
  195. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  196. {
  197. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  198. SACR1 |= SACR1_DRPL;
  199. SAIMR &= ~SAIMR_TFS;
  200. } else {
  201. SACR1 |= SACR1_DREC;
  202. SAIMR &= ~SAIMR_RFS;
  203. }
  204. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  205. SACR0 &= ~SACR0_ENB;
  206. pxa_i2s_wait();
  207. pxa_set_cken(CKEN8_I2S, 0);
  208. }
  209. }
  210. #ifdef CONFIG_PM
  211. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  212. struct snd_soc_cpu_dai *dai)
  213. {
  214. if (!dai->active)
  215. return 0;
  216. /* store registers */
  217. pxa_i2s.sacr0 = SACR0;
  218. pxa_i2s.sacr1 = SACR1;
  219. pxa_i2s.saimr = SAIMR;
  220. pxa_i2s.sadiv = SADIV;
  221. /* deactivate link */
  222. SACR0 &= ~SACR0_ENB;
  223. pxa_i2s_wait();
  224. return 0;
  225. }
  226. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  227. struct snd_soc_cpu_dai *dai)
  228. {
  229. if (!dai->active)
  230. return 0;
  231. pxa_i2s_wait();
  232. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  233. SACR1 = pxa_i2s.sacr1;
  234. SAIMR = pxa_i2s.saimr;
  235. SADIV = pxa_i2s.sadiv;
  236. SACR0 |= SACR0_ENB;
  237. return 0;
  238. }
  239. #else
  240. #define pxa2xx_i2s_suspend NULL
  241. #define pxa2xx_i2s_resume NULL
  242. #endif
  243. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  244. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  245. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  246. struct snd_soc_cpu_dai pxa_i2s_dai = {
  247. .name = "pxa2xx-i2s",
  248. .id = 0,
  249. .type = SND_SOC_DAI_I2S,
  250. .suspend = pxa2xx_i2s_suspend,
  251. .resume = pxa2xx_i2s_resume,
  252. .playback = {
  253. .channels_min = 2,
  254. .channels_max = 2,
  255. .rates = PXA2XX_I2S_RATES,
  256. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  257. .capture = {
  258. .channels_min = 2,
  259. .channels_max = 2,
  260. .rates = PXA2XX_I2S_RATES,
  261. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  262. .ops = {
  263. .startup = pxa2xx_i2s_startup,
  264. .shutdown = pxa2xx_i2s_shutdown,
  265. .trigger = pxa2xx_i2s_trigger,
  266. .hw_params = pxa2xx_i2s_hw_params,},
  267. .dai_ops = {
  268. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  269. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  270. },
  271. };
  272. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  273. /* Module information */
  274. MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
  275. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  276. MODULE_LICENSE("GPL");