pxa2xx-ac97.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431
  1. /*
  2. * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: Dec 02, 2004
  6. * Copyright: MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/wait.h>
  17. #include <linux/delay.h>
  18. #include <sound/driver.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/ac97_codec.h>
  22. #include <sound/initval.h>
  23. #include <sound/soc.h>
  24. #include <asm/irq.h>
  25. #include <linux/mutex.h>
  26. #include <asm/hardware.h>
  27. #include <asm/arch/pxa-regs.h>
  28. #include <asm/arch/audio.h>
  29. #include "pxa2xx-pcm.h"
  30. #include "pxa2xx-ac97.h"
  31. static DEFINE_MUTEX(car_mutex);
  32. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  33. static volatile long gsr_bits;
  34. /*
  35. * Beware PXA27x bugs:
  36. *
  37. * o Slot 12 read from modem space will hang controller.
  38. * o CDONE, SDONE interrupt fails after any slot 12 IO.
  39. *
  40. * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  41. * 1 jiffy timeout if interrupt never comes).
  42. */
  43. static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97,
  44. unsigned short reg)
  45. {
  46. unsigned short val = -1;
  47. volatile u32 *reg_addr;
  48. mutex_lock(&car_mutex);
  49. /* set up primary or secondary codec/modem space */
  50. #ifdef CONFIG_PXA27x
  51. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  52. #else
  53. if (reg == AC97_GPIO_STATUS)
  54. reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  55. else
  56. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  57. #endif
  58. reg_addr += (reg >> 1);
  59. #ifndef CONFIG_PXA27x
  60. if (reg == AC97_GPIO_STATUS) {
  61. /* read from controller cache */
  62. val = *reg_addr;
  63. goto out;
  64. }
  65. #endif
  66. /* start read access across the ac97 link */
  67. GSR = GSR_CDONE | GSR_SDONE;
  68. gsr_bits = 0;
  69. val = *reg_addr;
  70. wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  71. if (!((GSR | gsr_bits) & GSR_SDONE)) {
  72. printk(KERN_ERR "%s: read error (ac97_reg=%x GSR=%#lx)\n",
  73. __FUNCTION__, reg, GSR | gsr_bits);
  74. val = -1;
  75. goto out;
  76. }
  77. /* valid data now */
  78. GSR = GSR_CDONE | GSR_SDONE;
  79. gsr_bits = 0;
  80. val = *reg_addr;
  81. /* but we've just started another cycle... */
  82. wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  83. out: mutex_unlock(&car_mutex);
  84. return val;
  85. }
  86. static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  87. unsigned short val)
  88. {
  89. volatile u32 *reg_addr;
  90. mutex_lock(&car_mutex);
  91. /* set up primary or secondary codec/modem space */
  92. #ifdef CONFIG_PXA27x
  93. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  94. #else
  95. if (reg == AC97_GPIO_STATUS)
  96. reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  97. else
  98. reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  99. #endif
  100. reg_addr += (reg >> 1);
  101. GSR = GSR_CDONE | GSR_SDONE;
  102. gsr_bits = 0;
  103. *reg_addr = val;
  104. wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1);
  105. if (!((GSR | gsr_bits) & GSR_CDONE))
  106. printk(KERN_ERR "%s: write error (ac97_reg=%x GSR=%#lx)\n",
  107. __FUNCTION__, reg, GSR | gsr_bits);
  108. mutex_unlock(&car_mutex);
  109. }
  110. static void pxa2xx_ac97_warm_reset(struct snd_ac97 *ac97)
  111. {
  112. gsr_bits = 0;
  113. #ifdef CONFIG_PXA27x
  114. /* warm reset broken on Bulverde,
  115. so manually keep AC97 reset high */
  116. pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
  117. udelay(10);
  118. GCR |= GCR_WARM_RST;
  119. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  120. udelay(500);
  121. #else
  122. GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
  123. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  124. #endif
  125. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
  126. printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
  127. __FUNCTION__, gsr_bits);
  128. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  129. GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
  130. }
  131. static void pxa2xx_ac97_cold_reset(struct snd_ac97 *ac97)
  132. {
  133. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  134. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  135. gsr_bits = 0;
  136. #ifdef CONFIG_PXA27x
  137. /* PXA27x Developers Manual section 13.5.2.2.1 */
  138. pxa_set_cken(1 << 31, 1);
  139. udelay(5);
  140. pxa_set_cken(1 << 31, 0);
  141. GCR = GCR_COLD_RST;
  142. udelay(50);
  143. #else
  144. GCR = GCR_COLD_RST;
  145. GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
  146. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  147. #endif
  148. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
  149. printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
  150. __FUNCTION__, gsr_bits);
  151. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  152. GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
  153. }
  154. static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
  155. {
  156. long status;
  157. status = GSR;
  158. if (status) {
  159. GSR = status;
  160. gsr_bits |= status;
  161. wake_up(&gsr_wq);
  162. #ifdef CONFIG_PXA27x
  163. /* Although we don't use those we still need to clear them
  164. since they tend to spuriously trigger when MMC is used
  165. (hardware bug? go figure)... */
  166. MISR = MISR_EOC;
  167. PISR = PISR_EOC;
  168. MCSR = MCSR_EOC;
  169. #endif
  170. return IRQ_HANDLED;
  171. }
  172. return IRQ_NONE;
  173. }
  174. struct snd_ac97_bus_ops soc_ac97_ops = {
  175. .read = pxa2xx_ac97_read,
  176. .write = pxa2xx_ac97_write,
  177. .warm_reset = pxa2xx_ac97_warm_reset,
  178. .reset = pxa2xx_ac97_cold_reset,
  179. };
  180. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_out = {
  181. .name = "AC97 PCM Stereo out",
  182. .dev_addr = __PREG(PCDR),
  183. .drcmr = &DRCMRTXPCDR,
  184. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  185. DCMD_BURST32 | DCMD_WIDTH4,
  186. };
  187. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_stereo_in = {
  188. .name = "AC97 PCM Stereo in",
  189. .dev_addr = __PREG(PCDR),
  190. .drcmr = &DRCMRRXPCDR,
  191. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  192. DCMD_BURST32 | DCMD_WIDTH4,
  193. };
  194. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_out = {
  195. .name = "AC97 Aux PCM (Slot 5) Mono out",
  196. .dev_addr = __PREG(MODR),
  197. .drcmr = &DRCMRTXMODR,
  198. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  199. DCMD_BURST16 | DCMD_WIDTH2,
  200. };
  201. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_aux_mono_in = {
  202. .name = "AC97 Aux PCM (Slot 5) Mono in",
  203. .dev_addr = __PREG(MODR),
  204. .drcmr = &DRCMRRXMODR,
  205. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  206. DCMD_BURST16 | DCMD_WIDTH2,
  207. };
  208. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_mic_mono_in = {
  209. .name = "AC97 Mic PCM (Slot 6) Mono in",
  210. .dev_addr = __PREG(MCDR),
  211. .drcmr = &DRCMRRXMCDR,
  212. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  213. DCMD_BURST16 | DCMD_WIDTH2,
  214. };
  215. #ifdef CONFIG_PM
  216. static int pxa2xx_ac97_suspend(struct platform_device *pdev,
  217. struct snd_soc_cpu_dai *dai)
  218. {
  219. GCR |= GCR_ACLINK_OFF;
  220. pxa_set_cken(CKEN2_AC97, 0);
  221. return 0;
  222. }
  223. static int pxa2xx_ac97_resume(struct platform_device *pdev,
  224. struct snd_soc_cpu_dai *dai)
  225. {
  226. pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
  227. pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
  228. pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
  229. pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
  230. #ifdef CONFIG_PXA27x
  231. /* Use GPIO 113 as AC97 Reset on Bulverde */
  232. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  233. #endif
  234. pxa_set_cken(CKEN2_AC97, 1);
  235. return 0;
  236. }
  237. #else
  238. #define pxa2xx_ac97_suspend NULL
  239. #define pxa2xx_ac97_resume NULL
  240. #endif
  241. static int pxa2xx_ac97_probe(struct platform_device *pdev)
  242. {
  243. int ret;
  244. ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
  245. if (ret < 0)
  246. goto err;
  247. pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
  248. pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
  249. pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
  250. pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
  251. #ifdef CONFIG_PXA27x
  252. /* Use GPIO 113 as AC97 Reset on Bulverde */
  253. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  254. #endif
  255. pxa_set_cken(CKEN2_AC97, 1);
  256. return 0;
  257. err:
  258. if (CKEN & CKEN2_AC97) {
  259. GCR |= GCR_ACLINK_OFF;
  260. free_irq(IRQ_AC97, NULL);
  261. pxa_set_cken(CKEN2_AC97, 0);
  262. }
  263. return ret;
  264. }
  265. static void pxa2xx_ac97_remove(struct platform_device *pdev)
  266. {
  267. GCR |= GCR_ACLINK_OFF;
  268. free_irq(IRQ_AC97, NULL);
  269. pxa_set_cken(CKEN2_AC97, 0);
  270. }
  271. static int pxa2xx_ac97_hw_params(struct snd_pcm_substream *substream,
  272. struct snd_pcm_hw_params *params)
  273. {
  274. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  275. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  276. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  277. cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_out;
  278. else
  279. cpu_dai->dma_data = &pxa2xx_ac97_pcm_stereo_in;
  280. return 0;
  281. }
  282. static int pxa2xx_ac97_hw_aux_params(struct snd_pcm_substream *substream,
  283. struct snd_pcm_hw_params *params)
  284. {
  285. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  286. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  287. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  288. cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_out;
  289. else
  290. cpu_dai->dma_data = &pxa2xx_ac97_pcm_aux_mono_in;
  291. return 0;
  292. }
  293. static int pxa2xx_ac97_hw_mic_params(struct snd_pcm_substream *substream,
  294. struct snd_pcm_hw_params *params)
  295. {
  296. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  297. struct snd_soc_cpu_dai *cpu_dai = rtd->dai->cpu_dai;
  298. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  299. return -ENODEV;
  300. else
  301. cpu_dai->dma_data = &pxa2xx_ac97_pcm_mic_mono_in;
  302. return 0;
  303. }
  304. #define PXA2XX_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  305. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  306. SNDRV_PCM_RATE_48000)
  307. /*
  308. * There is only 1 physical AC97 interface for pxa2xx, but it
  309. * has extra fifo's that can be used for aux DACs and ADCs.
  310. */
  311. struct snd_soc_cpu_dai pxa_ac97_dai[] = {
  312. {
  313. .name = "pxa2xx-ac97",
  314. .id = 0,
  315. .type = SND_SOC_DAI_AC97,
  316. .probe = pxa2xx_ac97_probe,
  317. .remove = pxa2xx_ac97_remove,
  318. .suspend = pxa2xx_ac97_suspend,
  319. .resume = pxa2xx_ac97_resume,
  320. .playback = {
  321. .stream_name = "AC97 Playback",
  322. .channels_min = 2,
  323. .channels_max = 2,
  324. .rates = PXA2XX_AC97_RATES,
  325. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  326. .capture = {
  327. .stream_name = "AC97 Capture",
  328. .channels_min = 2,
  329. .channels_max = 2,
  330. .rates = PXA2XX_AC97_RATES,
  331. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  332. .ops = {
  333. .hw_params = pxa2xx_ac97_hw_params,},
  334. },
  335. {
  336. .name = "pxa2xx-ac97-aux",
  337. .id = 1,
  338. .type = SND_SOC_DAI_AC97,
  339. .playback = {
  340. .stream_name = "AC97 Aux Playback",
  341. .channels_min = 1,
  342. .channels_max = 1,
  343. .rates = PXA2XX_AC97_RATES,
  344. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  345. .capture = {
  346. .stream_name = "AC97 Aux Capture",
  347. .channels_min = 1,
  348. .channels_max = 1,
  349. .rates = PXA2XX_AC97_RATES,
  350. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  351. .ops = {
  352. .hw_params = pxa2xx_ac97_hw_aux_params,},
  353. },
  354. {
  355. .name = "pxa2xx-ac97-mic",
  356. .id = 2,
  357. .type = SND_SOC_DAI_AC97,
  358. .capture = {
  359. .stream_name = "AC97 Mic Capture",
  360. .channels_min = 1,
  361. .channels_max = 1,
  362. .rates = PXA2XX_AC97_RATES,
  363. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  364. .ops = {
  365. .hw_params = pxa2xx_ac97_hw_mic_params,},
  366. },
  367. };
  368. EXPORT_SYMBOL_GPL(pxa_ac97_dai);
  369. EXPORT_SYMBOL_GPL(soc_ac97_ops);
  370. MODULE_AUTHOR("Nicolas Pitre");
  371. MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
  372. MODULE_LICENSE("GPL");