wm8580.h 5.7 KB

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  1. /*
  2. * wm8580.h -- audio driver for WM8580
  3. *
  4. * Copyright 2008 Samsung Electronics.
  5. * Author: Ryu Euiyoul
  6. * ryu.real@gmail.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #ifndef _WM8580_H
  15. #define _WM8580_H
  16. #define WM8580_PLLA 1
  17. #define WM8580_PLLB 2
  18. #define WM8580_MCLK 1
  19. #define WM8580_DAC_CLKSEL 2
  20. #define WM8580_CLKOUTSRC 3
  21. #define WM8580_CLKSRC_MCLK 1
  22. #define WM8580_CLKSRC_PLLA 2
  23. #define WM8580_CLKSRC_PLLB 3
  24. #define WM8580_CLKSRC_OSC 4
  25. #define WM8580_CLKSRC_NONE 5
  26. /* WM8580 register space */
  27. #define WM8580_PLLA1 0x00
  28. #define WM8580_PLLA2 0x01
  29. #define WM8580_PLLA3 0x02
  30. #define WM8580_PLLA4 0x03
  31. #define WM8580_PLLB1 0x04
  32. #define WM8580_PLLB2 0x05
  33. #define WM8580_PLLB3 0x06
  34. #define WM8580_PLLB4 0x07
  35. #define WM8580_CLKSEL 0x08
  36. #define WM8580_PAIF1 0x09
  37. #define WM8580_PAIF2 0x0A
  38. #define WM8580_SAIF1 0x0B
  39. #define WM8580_PAIF3 0x0C
  40. #define WM8580_PAIF4 0x0D
  41. #define WM8580_SAIF2 0x0E
  42. #define WM8580_DAC_CONTROL1 0x0F
  43. #define WM8580_DAC_CONTROL2 0x10
  44. #define WM8580_DAC_CONTROL3 0x11
  45. #define WM8580_DAC_CONTROL4 0x12
  46. #define WM8580_DAC_CONTROL5 0x13
  47. #define WM8580_DIGITAL_ATTENUATION_DACL1 0x14
  48. #define WM8580_DIGITAL_ATTENUATION_DACR1 0x15
  49. #define WM8580_DIGITAL_ATTENUATION_DACL2 0x16
  50. #define WM8580_DIGITAL_ATTENUATION_DACR2 0x17
  51. #define WM8580_DIGITAL_ATTENUATION_DACL3 0x18
  52. #define WM8580_DIGITAL_ATTENUATION_DACR3 0x19
  53. #define WM8580_MASTER_DIGITAL_ATTENUATION 0x1C
  54. #define WM8580_ADC_CONTROL1 0x1D
  55. #define WM8580_SPDTXCHAN0 0x1E
  56. #define WM8580_SPDTXCHAN1 0x1F
  57. #define WM8580_SPDTXCHAN2 0x20
  58. #define WM8580_SPDTXCHAN3 0x21
  59. #define WM8580_SPDTXCHAN4 0x22
  60. #define WM8580_SPDTXCHAN5 0x23
  61. #define WM8580_SPDMODE 0x24
  62. #define WM8580_INTMASK 0x25
  63. #define WM8580_GPO1 0x26
  64. #define WM8580_GPO2 0x27
  65. #define WM8580_GPO3 0x28
  66. #define WM8580_GPO4 0x29
  67. #define WM8580_GPO5 0x2A
  68. #define WM8580_INTSTAT 0x2B
  69. #define WM8580_SPDRXCHAN1 0x2C
  70. #define WM8580_SPDRXCHAN2 0x2D
  71. #define WM8580_SPDRXCHAN3 0x2E
  72. #define WM8580_SPDRXCHAN4 0x2F
  73. #define WM8580_SPDRXCHAN5 0x30
  74. #define WM8580_SPDSTAT 0x31
  75. #define WM8580_PWRDN1 0x32
  76. #define WM8580_PWRDN2 0x33
  77. #define WM8580_READBACK 0x34
  78. #define WM8580_RESET 0x35
  79. /* PLLB4 (register 7h) */
  80. #define WM8580_PLLB4_MCLKOUTSRC_MASK 0x60
  81. #define WM8580_PLLB4_MCLKOUTSRC_PLLA 0x20
  82. #define WM8580_PLLB4_MCLKOUTSRC_PLLB 0x40
  83. #define WM8580_PLLB4_MCLKOUTSRC_OSC 0x60
  84. #define WM8580_PLLB4_CLKOUTSRC_MASK 0x180
  85. #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
  86. #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
  87. #define WM8580_PLLB4_CLKOUTSRC_OSCCLK 0x180
  88. /* CLKSEL (register 8h) */
  89. #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
  90. #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
  91. #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
  92. /* AIF control 1 (registers 9h-bh) */
  93. #define WM8580_AIF_RATE_MASK 0x7
  94. #define WM8580_AIF_RATE_128 0x0
  95. #define WM8580_AIF_RATE_192 0x1
  96. #define WM8580_AIF_RATE_256 0x2
  97. #define WM8580_AIF_RATE_384 0x3
  98. #define WM8580_AIF_RATE_512 0x4
  99. #define WM8580_AIF_RATE_768 0x5
  100. #define WM8580_AIF_RATE_1152 0x6
  101. #define WM8580_AIF_BCLKSEL_MASK 0x18
  102. #define WM8580_AIF_BCLKSEL_64 0x00
  103. #define WM8580_AIF_BCLKSEL_128 0x08
  104. #define WM8580_AIF_BCLKSEL_256 0x10
  105. #define WM8580_AIF_BCLKSEL_SYSCLK 0x18
  106. #define WM8580_AIF_MS 0x20
  107. #define WM8580_AIF_CLKSRC_MASK 0xc0
  108. #define WM8580_AIF_CLKSRC_PLLA 0x40
  109. #define WM8580_AIF_CLKSRC_PLLB 0x40
  110. #define WM8580_AIF_CLKSRC_MCLK 0xc0
  111. /* AIF control 2 (registers ch-eh) */
  112. #define WM8580_AIF_FMT_MASK 0x03
  113. #define WM8580_AIF_FMT_RIGHTJ 0x00
  114. #define WM8580_AIF_FMT_LEFTJ 0x01
  115. #define WM8580_AIF_FMT_I2S 0x02
  116. #define WM8580_AIF_FMT_DSP 0x03
  117. #define WM8580_AIF_LENGTH_MASK 0x0c
  118. #define WM8580_AIF_LENGTH_16 0x00
  119. #define WM8580_AIF_LENGTH_20 0x04
  120. #define WM8580_AIF_LENGTH_24 0x08
  121. #define WM8580_AIF_LENGTH_32 0x0c
  122. #define WM8580_AIF_LRP 0x10
  123. #define WM8580_AIF_BCP 0x20
  124. /* Powerdown Register 1 (register 32h) */
  125. #define WM8580_PWRDN1_PWDN 0x001
  126. #define WM8580_PWRDN1_ALLDACPD 0x040
  127. /* Powerdown Register 2 (register 33h) */
  128. #define WM8580_PWRDN2_OSSCPD 0x001
  129. #define WM8580_PWRDN2_PLLAPD 0x002
  130. #define WM8580_PWRDN2_PLLBPD 0x004
  131. #define WM8580_PWRDN2_SPDIFPD 0x008
  132. #define WM8580_PWRDN2_SPDIFTXD 0x010
  133. #define WM8580_PWRDN2_SPDIFRXD 0x020
  134. extern struct snd_soc_codec_device soc_codec_dev_wm8580;
  135. struct wm8580_setup_data {
  136. unsigned short i2c_address;
  137. };
  138. #define WM8580_DAI_PAIFRX 0
  139. #define WM8580_DAI_PAIFTX 1
  140. #define WM8580_DAI_SAIF 2
  141. extern struct snd_soc_codec_dai wm8580_dai[];
  142. extern struct snd_soc_codec_device soc_codec_dev_wm8580;
  143. #endif