at91-i2s.c 19 KB

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  1. /*
  2. * at91-i2s.c -- ALSA SoC I2S Audio Layer Platform driver
  3. *
  4. * Author: Frank Mandarino <fmandarino@endrelia.com>
  5. * Endrelia Technologies Inc.
  6. *
  7. * Based on pxa2xx Platform drivers by
  8. * Liam Girdwood <liam.girdwood@wolfsonmicro.com>
  9. *
  10. * This program is free software; you can redistribute it and/or modify it
  11. * under the terms of the GNU General Public License as published by the
  12. * Free Software Foundation; either version 2 of the License, or (at your
  13. * option) any later version.
  14. *
  15. */
  16. #include <linux/init.h>
  17. #include <linux/module.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/device.h>
  20. #include <linux/delay.h>
  21. #include <linux/clk.h>
  22. #include <linux/atmel_pdc.h>
  23. #include <sound/driver.h>
  24. #include <sound/core.h>
  25. #include <sound/pcm.h>
  26. #include <sound/initval.h>
  27. #include <sound/soc.h>
  28. #include <asm/arch/hardware.h>
  29. #include <asm/arch/at91_pmc.h>
  30. #include <asm/arch/at91_ssc.h>
  31. #include "at91-pcm.h"
  32. #include "at91-i2s.h"
  33. #if 0
  34. #define DBG(x...) printk(KERN_DEBUG "at91-i2s:" x)
  35. #else
  36. #define DBG(x...)
  37. #endif
  38. #if defined(CONFIG_ARCH_AT91SAM9260)
  39. #define NUM_SSC_DEVICES 1
  40. #else
  41. #define NUM_SSC_DEVICES 3
  42. #endif
  43. /*
  44. * SSC PDC registers required by the PCM DMA engine.
  45. */
  46. static struct at91_pdc_regs pdc_tx_reg = {
  47. .xpr = ATMEL_PDC_TPR,
  48. .xcr = ATMEL_PDC_TCR,
  49. .xnpr = ATMEL_PDC_TNPR,
  50. .xncr = ATMEL_PDC_TNCR,
  51. };
  52. static struct at91_pdc_regs pdc_rx_reg = {
  53. .xpr = ATMEL_PDC_RPR,
  54. .xcr = ATMEL_PDC_RCR,
  55. .xnpr = ATMEL_PDC_RNPR,
  56. .xncr = ATMEL_PDC_RNCR,
  57. };
  58. /*
  59. * SSC & PDC status bits for transmit and receive.
  60. */
  61. static struct at91_ssc_mask ssc_tx_mask = {
  62. .ssc_enable = AT91_SSC_TXEN,
  63. .ssc_disable = AT91_SSC_TXDIS,
  64. .ssc_endx = AT91_SSC_ENDTX,
  65. .ssc_endbuf = AT91_SSC_TXBUFE,
  66. .pdc_enable = ATMEL_PDC_TXTEN,
  67. .pdc_disable = ATMEL_PDC_TXTDIS,
  68. };
  69. static struct at91_ssc_mask ssc_rx_mask = {
  70. .ssc_enable = AT91_SSC_RXEN,
  71. .ssc_disable = AT91_SSC_RXDIS,
  72. .ssc_endx = AT91_SSC_ENDRX,
  73. .ssc_endbuf = AT91_SSC_RXBUFF,
  74. .pdc_enable = ATMEL_PDC_RXTEN,
  75. .pdc_disable = ATMEL_PDC_RXTDIS,
  76. };
  77. /*
  78. * DMA parameters.
  79. */
  80. static struct at91_pcm_dma_params ssc_dma_params[NUM_SSC_DEVICES][2] = {
  81. {{
  82. .name = "SSC0/I2S PCM Stereo out",
  83. .pdc = &pdc_tx_reg,
  84. .mask = &ssc_tx_mask,
  85. },
  86. {
  87. .name = "SSC0/I2S PCM Stereo in",
  88. .pdc = &pdc_rx_reg,
  89. .mask = &ssc_rx_mask,
  90. }},
  91. #if NUM_SSC_DEVICES == 3
  92. {{
  93. .name = "SSC1/I2S PCM Stereo out",
  94. .pdc = &pdc_tx_reg,
  95. .mask = &ssc_tx_mask,
  96. },
  97. {
  98. .name = "SSC1/I2S PCM Stereo in",
  99. .pdc = &pdc_rx_reg,
  100. .mask = &ssc_rx_mask,
  101. }},
  102. {{
  103. .name = "SSC2/I2S PCM Stereo out",
  104. .pdc = &pdc_tx_reg,
  105. .mask = &ssc_tx_mask,
  106. },
  107. {
  108. .name = "SSC1/I2S PCM Stereo in",
  109. .pdc = &pdc_rx_reg,
  110. .mask = &ssc_rx_mask,
  111. }},
  112. #endif
  113. };
  114. struct at91_ssc_state {
  115. u32 ssc_cmr;
  116. u32 ssc_rcmr;
  117. u32 ssc_rfmr;
  118. u32 ssc_tcmr;
  119. u32 ssc_tfmr;
  120. u32 ssc_sr;
  121. u32 ssc_imr;
  122. };
  123. static struct at91_ssc_info {
  124. char *name;
  125. struct at91_ssc_periph ssc;
  126. spinlock_t lock; /* lock for dir_mask */
  127. unsigned short dir_mask; /* 0=unused, 1=playback, 2=capture */
  128. unsigned short initialized; /* 1=SSC has been initialized */
  129. unsigned short daifmt;
  130. unsigned short cmr_div;
  131. unsigned short tcmr_period;
  132. unsigned short rcmr_period;
  133. struct at91_pcm_dma_params *dma_params[2];
  134. struct at91_ssc_state ssc_state;
  135. } ssc_info[NUM_SSC_DEVICES] = {
  136. {
  137. .name = "ssc0",
  138. .lock = SPIN_LOCK_UNLOCKED,
  139. .dir_mask = 0,
  140. .initialized = 0,
  141. },
  142. #if NUM_SSC_DEVICES == 3
  143. {
  144. .name = "ssc1",
  145. .lock = SPIN_LOCK_UNLOCKED,
  146. .dir_mask = 0,
  147. .initialized = 0,
  148. },
  149. {
  150. .name = "ssc2",
  151. .lock = SPIN_LOCK_UNLOCKED,
  152. .dir_mask = 0,
  153. .initialized = 0,
  154. },
  155. #endif
  156. };
  157. static unsigned int at91_i2s_sysclk;
  158. /*
  159. * SSC interrupt handler. Passes PDC interrupts to the DMA
  160. * interrupt handler in the PCM driver.
  161. */
  162. static irqreturn_t at91_i2s_interrupt(int irq, void *dev_id)
  163. {
  164. struct at91_ssc_info *ssc_p = dev_id;
  165. struct at91_pcm_dma_params *dma_params;
  166. u32 ssc_sr;
  167. int i;
  168. ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR)
  169. & at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
  170. /*
  171. * Loop through the substreams attached to this SSC. If
  172. * a DMA-related interrupt occurred on that substream, call
  173. * the DMA interrupt handler function, if one has been
  174. * registered in the dma_params structure by the PCM driver.
  175. */
  176. for (i = 0; i < ARRAY_SIZE(ssc_p->dma_params); i++) {
  177. dma_params = ssc_p->dma_params[i];
  178. if (dma_params != NULL && dma_params->dma_intr_handler != NULL &&
  179. (ssc_sr &
  180. (dma_params->mask->ssc_endx | dma_params->mask->ssc_endbuf)))
  181. dma_params->dma_intr_handler(ssc_sr, dma_params->substream);
  182. }
  183. return IRQ_HANDLED;
  184. }
  185. /*
  186. * Startup. Only that one substream allowed in each direction.
  187. */
  188. static int at91_i2s_startup(struct snd_pcm_substream *substream)
  189. {
  190. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  191. struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  192. int dir_mask;
  193. DBG("i2s_startup: SSC_SR=0x%08lx\n",
  194. at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
  195. dir_mask = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0x1 : 0x2;
  196. spin_lock_irq(&ssc_p->lock);
  197. if (ssc_p->dir_mask & dir_mask) {
  198. spin_unlock_irq(&ssc_p->lock);
  199. return -EBUSY;
  200. }
  201. ssc_p->dir_mask |= dir_mask;
  202. spin_unlock_irq(&ssc_p->lock);
  203. return 0;
  204. }
  205. /*
  206. * Shutdown. Clear DMA parameters and shutdown the SSC if there
  207. * are no other substreams open.
  208. */
  209. static void at91_i2s_shutdown(struct snd_pcm_substream *substream)
  210. {
  211. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  212. struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  213. struct at91_pcm_dma_params *dma_params;
  214. int dir, dir_mask;
  215. dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
  216. dma_params = ssc_p->dma_params[dir];
  217. if (dma_params != NULL) {
  218. at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
  219. dma_params->mask->ssc_disable);
  220. DBG("%s disabled SSC_SR=0x%08lx\n", (dir ? "receive" : "transmit"),
  221. at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR));
  222. dma_params->ssc_base = NULL;
  223. dma_params->substream = NULL;
  224. ssc_p->dma_params[dir] = NULL;
  225. }
  226. dir_mask = 1 << dir;
  227. spin_lock_irq(&ssc_p->lock);
  228. ssc_p->dir_mask &= ~dir_mask;
  229. if (!ssc_p->dir_mask) {
  230. /* Shutdown the SSC clock. */
  231. DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
  232. at91_sys_write(AT91_PMC_PCDR, 1<<ssc_p->ssc.pid);
  233. if (ssc_p->initialized) {
  234. free_irq(ssc_p->ssc.pid, ssc_p);
  235. ssc_p->initialized = 0;
  236. }
  237. /* Reset the SSC */
  238. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
  239. /* Clear the SSC dividers */
  240. ssc_p->cmr_div = ssc_p->tcmr_period = ssc_p->rcmr_period = 0;
  241. }
  242. spin_unlock_irq(&ssc_p->lock);
  243. }
  244. /*
  245. * Record the SSC system clock rate.
  246. */
  247. static int at91_i2s_set_dai_sysclk(struct snd_soc_cpu_dai *cpu_dai,
  248. int clk_id, unsigned int freq, int dir)
  249. {
  250. /*
  251. * The only clock supplied to the SSC is the AT91 master clock,
  252. * which is only used if the SSC is generating BCLK and/or
  253. * LRC clocks.
  254. */
  255. switch (clk_id) {
  256. case AT91_SYSCLK_MCK:
  257. at91_i2s_sysclk = freq;
  258. break;
  259. default:
  260. return -EINVAL;
  261. }
  262. return 0;
  263. }
  264. /*
  265. * Record the DAI format for use in hw_params().
  266. */
  267. static int at91_i2s_set_dai_fmt(struct snd_soc_cpu_dai *cpu_dai,
  268. unsigned int fmt)
  269. {
  270. struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
  271. if ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_I2S)
  272. return -EINVAL;
  273. ssc_p->daifmt = fmt;
  274. return 0;
  275. }
  276. /*
  277. * Record SSC clock dividers for use in hw_params().
  278. */
  279. static int at91_i2s_set_dai_clkdiv(struct snd_soc_cpu_dai *cpu_dai,
  280. int div_id, int div)
  281. {
  282. struct at91_ssc_info *ssc_p = &ssc_info[cpu_dai->id];
  283. switch (div_id) {
  284. case AT91SSC_CMR_DIV:
  285. /*
  286. * The same master clock divider is used for both
  287. * transmit and receive, so if a value has already
  288. * been set, it must match this value.
  289. */
  290. if (ssc_p->cmr_div == 0)
  291. ssc_p->cmr_div = div;
  292. else
  293. if (div != ssc_p->cmr_div)
  294. return -EBUSY;
  295. break;
  296. case AT91SSC_TCMR_PERIOD:
  297. ssc_p->tcmr_period = div;
  298. break;
  299. case AT91SSC_RCMR_PERIOD:
  300. ssc_p->rcmr_period = div;
  301. break;
  302. default:
  303. return -EINVAL;
  304. }
  305. return 0;
  306. }
  307. /*
  308. * Configure the SSC.
  309. */
  310. static int at91_i2s_hw_params(struct snd_pcm_substream *substream,
  311. struct snd_pcm_hw_params *params)
  312. {
  313. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  314. int id = rtd->dai->cpu_dai->id;
  315. struct at91_ssc_info *ssc_p = &ssc_info[id];
  316. struct at91_pcm_dma_params *dma_params;
  317. int dir, channels, bits;
  318. u32 tfmr, rfmr, tcmr, rcmr;
  319. int start_event;
  320. int ret;
  321. /*
  322. * Currently, there is only one set of dma params for
  323. * each direction. If more are added, this code will
  324. * have to be changed to select the proper set.
  325. */
  326. dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
  327. dma_params = &ssc_dma_params[id][dir];
  328. dma_params->ssc_base = ssc_p->ssc.base;
  329. dma_params->substream = substream;
  330. ssc_p->dma_params[dir] = dma_params;
  331. /*
  332. * The cpu_dai->dma_data field is only used to communicate the
  333. * appropriate DMA parameters to the pcm driver hw_params()
  334. * function. It should not be used for other purposes
  335. * as it is common to all substreams.
  336. */
  337. rtd->dai->cpu_dai->dma_data = dma_params;
  338. channels = params_channels(params);
  339. /*
  340. * The SSC only supports up to 16-bit samples in I2S format, due
  341. * to the size of the Frame Mode Register FSLEN field. Also, I2S
  342. * implies signed data.
  343. */
  344. bits = 16;
  345. dma_params->pdc_xfer_size = 2;
  346. /*
  347. * Compute SSC register settings.
  348. */
  349. switch (ssc_p->daifmt) {
  350. case SND_SOC_DAIFMT_CBS_CFS:
  351. /*
  352. * SSC provides BCLK and LRC clocks.
  353. *
  354. * The SSC transmit and receive clocks are generated from the
  355. * MCK divider, and the BCLK signal is output on the SSC TK line.
  356. */
  357. rcmr = (( ssc_p->rcmr_period << 24) & AT91_SSC_PERIOD)
  358. | (( 1 << 16) & AT91_SSC_STTDLY)
  359. | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
  360. | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
  361. | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
  362. | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
  363. rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
  364. | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
  365. | (((bits - 1) << 16) & AT91_SSC_FSLEN)
  366. | (((channels - 1) << 8) & AT91_SSC_DATNB)
  367. | (( 1 << 7) & AT91_SSC_MSBF)
  368. | (( 0 << 5) & AT91_SSC_LOOP)
  369. | (((bits - 1) << 0) & AT91_SSC_DATALEN);
  370. tcmr = (( ssc_p->tcmr_period << 24) & AT91_SSC_PERIOD)
  371. | (( 1 << 16) & AT91_SSC_STTDLY)
  372. | (( AT91_SSC_START_FALLING_RF ) & AT91_SSC_START)
  373. | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
  374. | (( AT91_SSC_CKO_CONTINUOUS ) & AT91_SSC_CKO)
  375. | (( AT91_SSC_CKS_DIV ) & AT91_SSC_CKS);
  376. tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
  377. | (( 0 << 23) & AT91_SSC_FSDEN)
  378. | (( AT91_SSC_FSOS_NEGATIVE ) & AT91_SSC_FSOS)
  379. | (((bits - 1) << 16) & AT91_SSC_FSLEN)
  380. | (((channels - 1) << 8) & AT91_SSC_DATNB)
  381. | (( 1 << 7) & AT91_SSC_MSBF)
  382. | (( 0 << 5) & AT91_SSC_DATDEF)
  383. | (((bits - 1) << 0) & AT91_SSC_DATALEN);
  384. break;
  385. case SND_SOC_DAIFMT_CBM_CFM:
  386. /*
  387. * CODEC supplies BCLK and LRC clocks.
  388. *
  389. * The SSC transmit clock is obtained from the BCLK signal on
  390. * on the TK line, and the SSC receive clock is generated from the
  391. * transmit clock.
  392. *
  393. * For single channel data, one sample is transferred on the falling
  394. * edge of the LRC clock. For two channel data, one sample is
  395. * transferred on both edges of the LRC clock.
  396. */
  397. start_event = channels == 1
  398. ? AT91_SSC_START_FALLING_RF
  399. : AT91_SSC_START_EDGE_RF;
  400. rcmr = (( 0 << 24) & AT91_SSC_PERIOD)
  401. | (( 1 << 16) & AT91_SSC_STTDLY)
  402. | (( start_event ) & AT91_SSC_START)
  403. | (( AT91_SSC_CK_RISING ) & AT91_SSC_CKI)
  404. | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
  405. | (( AT91_SSC_CKS_CLOCK ) & AT91_SSC_CKS);
  406. rfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
  407. | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
  408. | (( 0 << 16) & AT91_SSC_FSLEN)
  409. | (( 0 << 8) & AT91_SSC_DATNB)
  410. | (( 1 << 7) & AT91_SSC_MSBF)
  411. | (( 0 << 5) & AT91_SSC_LOOP)
  412. | (((bits - 1) << 0) & AT91_SSC_DATALEN);
  413. tcmr = (( 0 << 24) & AT91_SSC_PERIOD)
  414. | (( 1 << 16) & AT91_SSC_STTDLY)
  415. | (( start_event ) & AT91_SSC_START)
  416. | (( AT91_SSC_CKI_FALLING ) & AT91_SSC_CKI)
  417. | (( AT91_SSC_CKO_NONE ) & AT91_SSC_CKO)
  418. | (( AT91_SSC_CKS_PIN ) & AT91_SSC_CKS);
  419. tfmr = (( AT91_SSC_FSEDGE_POSITIVE ) & AT91_SSC_FSEDGE)
  420. | (( 0 << 23) & AT91_SSC_FSDEN)
  421. | (( AT91_SSC_FSOS_NONE ) & AT91_SSC_FSOS)
  422. | (( 0 << 16) & AT91_SSC_FSLEN)
  423. | (( 0 << 8) & AT91_SSC_DATNB)
  424. | (( 1 << 7) & AT91_SSC_MSBF)
  425. | (( 0 << 5) & AT91_SSC_DATDEF)
  426. | (((bits - 1) << 0) & AT91_SSC_DATALEN);
  427. break;
  428. case SND_SOC_DAIFMT_CBS_CFM:
  429. case SND_SOC_DAIFMT_CBM_CFS:
  430. default:
  431. printk(KERN_WARNING "at91-i2s: unsupported DAI format 0x%x.\n",
  432. ssc_p->daifmt);
  433. return -EINVAL;
  434. break;
  435. }
  436. DBG("RCMR=%08x RFMR=%08x TCMR=%08x TFMR=%08x\n", rcmr, rfmr, tcmr, tfmr);
  437. if (!ssc_p->initialized) {
  438. /* Enable PMC peripheral clock for this SSC */
  439. DBG("Starting pid %d clock\n", ssc_p->ssc.pid);
  440. at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
  441. /* Reset the SSC and its PDC registers */
  442. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR, AT91_SSC_SWRST);
  443. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RPR, 0);
  444. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RCR, 0);
  445. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNPR, 0);
  446. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_RNCR, 0);
  447. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TPR, 0);
  448. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TCR, 0);
  449. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNPR, 0);
  450. at91_ssc_write(ssc_p->ssc.base + ATMEL_PDC_TNCR, 0);
  451. if ((ret = request_irq(ssc_p->ssc.pid, at91_i2s_interrupt,
  452. 0, ssc_p->name, ssc_p)) < 0) {
  453. printk(KERN_WARNING "at91-i2s: request_irq failure\n");
  454. DBG("Stopping pid %d clock\n", ssc_p->ssc.pid);
  455. at91_sys_write(AT91_PMC_PCER, 1<<ssc_p->ssc.pid);
  456. return ret;
  457. }
  458. ssc_p->initialized = 1;
  459. }
  460. /* set SSC clock mode register */
  461. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->cmr_div);
  462. /* set receive clock mode and format */
  463. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, rcmr);
  464. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, rfmr);
  465. /* set transmit clock mode and format */
  466. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, tcmr);
  467. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, tfmr);
  468. DBG("hw_params: SSC initialized\n");
  469. return 0;
  470. }
  471. static int at91_i2s_prepare(struct snd_pcm_substream *substream)
  472. {
  473. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  474. struct at91_ssc_info *ssc_p = &ssc_info[rtd->dai->cpu_dai->id];
  475. struct at91_pcm_dma_params *dma_params;
  476. int dir;
  477. dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
  478. dma_params = ssc_p->dma_params[dir];
  479. at91_ssc_write(dma_params->ssc_base + AT91_SSC_CR,
  480. dma_params->mask->ssc_enable);
  481. DBG("%s enabled SSC_SR=0x%08lx\n", dir ? "receive" : "transmit",
  482. at91_ssc_read(dma_params->ssc_base + AT91_SSC_SR));
  483. return 0;
  484. }
  485. #ifdef CONFIG_PM
  486. static int at91_i2s_suspend(struct platform_device *pdev,
  487. struct snd_soc_cpu_dai *cpu_dai)
  488. {
  489. struct at91_ssc_info *ssc_p;
  490. if(!cpu_dai->active)
  491. return 0;
  492. ssc_p = &ssc_info[cpu_dai->id];
  493. /* Save the status register before disabling transmit and receive. */
  494. ssc_p->ssc_state.ssc_sr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_SR);
  495. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
  496. AT91_SSC_TXDIS | AT91_SSC_RXDIS);
  497. /* Save the current interrupt mask, then disable unmasked interrupts. */
  498. ssc_p->ssc_state.ssc_imr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_IMR);
  499. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IDR, ssc_p->ssc_state.ssc_imr);
  500. ssc_p->ssc_state.ssc_cmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_CMR);
  501. ssc_p->ssc_state.ssc_rcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RCMR);
  502. ssc_p->ssc_state.ssc_rfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_RFMR);
  503. ssc_p->ssc_state.ssc_tcmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TCMR);
  504. ssc_p->ssc_state.ssc_tfmr = at91_ssc_read(ssc_p->ssc.base + AT91_SSC_TFMR);
  505. return 0;
  506. }
  507. static int at91_i2s_resume(struct platform_device *pdev,
  508. struct snd_soc_cpu_dai *cpu_dai)
  509. {
  510. struct at91_ssc_info *ssc_p;
  511. if(!cpu_dai->active)
  512. return 0;
  513. ssc_p = &ssc_info[cpu_dai->id];
  514. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TFMR, ssc_p->ssc_state.ssc_tfmr);
  515. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_TCMR, ssc_p->ssc_state.ssc_tcmr);
  516. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RFMR, ssc_p->ssc_state.ssc_rfmr);
  517. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_RCMR, ssc_p->ssc_state.ssc_rcmr);
  518. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CMR, ssc_p->ssc_state.ssc_cmr);
  519. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_IER, ssc_p->ssc_state.ssc_imr);
  520. at91_ssc_write(ssc_p->ssc.base + AT91_SSC_CR,
  521. ((ssc_p->ssc_state.ssc_sr & AT91_SSC_RXENA) ? AT91_SSC_RXEN : 0) |
  522. ((ssc_p->ssc_state.ssc_sr & AT91_SSC_TXENA) ? AT91_SSC_TXEN : 0));
  523. return 0;
  524. }
  525. #else
  526. #define at91_i2s_suspend NULL
  527. #define at91_i2s_resume NULL
  528. #endif
  529. #define AT91_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  530. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 |\
  531. SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |\
  532. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |\
  533. SNDRV_PCM_RATE_96000)
  534. struct snd_soc_cpu_dai at91_i2s_dai[NUM_SSC_DEVICES] = {
  535. { .name = "at91_ssc0/i2s",
  536. .id = 0,
  537. .type = SND_SOC_DAI_I2S,
  538. .suspend = at91_i2s_suspend,
  539. .resume = at91_i2s_resume,
  540. .playback = {
  541. .channels_min = 1,
  542. .channels_max = 2,
  543. .rates = AT91_I2S_RATES,
  544. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  545. .capture = {
  546. .channels_min = 1,
  547. .channels_max = 2,
  548. .rates = AT91_I2S_RATES,
  549. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  550. .ops = {
  551. .startup = at91_i2s_startup,
  552. .shutdown = at91_i2s_shutdown,
  553. .prepare = at91_i2s_prepare,
  554. .hw_params = at91_i2s_hw_params,},
  555. .dai_ops = {
  556. .set_sysclk = at91_i2s_set_dai_sysclk,
  557. .set_fmt = at91_i2s_set_dai_fmt,
  558. .set_clkdiv = at91_i2s_set_dai_clkdiv,},
  559. .private_data = &ssc_info[0].ssc,
  560. },
  561. #if NUM_SSC_DEVICES == 3
  562. { .name = "at91_ssc1/i2s",
  563. .id = 1,
  564. .type = SND_SOC_DAI_I2S,
  565. .suspend = at91_i2s_suspend,
  566. .resume = at91_i2s_resume,
  567. .playback = {
  568. .channels_min = 1,
  569. .channels_max = 2,
  570. .rates = AT91_I2S_RATES,
  571. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  572. .capture = {
  573. .channels_min = 1,
  574. .channels_max = 2,
  575. .rates = AT91_I2S_RATES,
  576. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  577. .ops = {
  578. .startup = at91_i2s_startup,
  579. .shutdown = at91_i2s_shutdown,
  580. .prepare = at91_i2s_prepare,
  581. .hw_params = at91_i2s_hw_params,},
  582. .dai_ops = {
  583. .set_sysclk = at91_i2s_set_dai_sysclk,
  584. .set_fmt = at91_i2s_set_dai_fmt,
  585. .set_clkdiv = at91_i2s_set_dai_clkdiv,},
  586. .private_data = &ssc_info[1].ssc,
  587. },
  588. { .name = "at91_ssc2/i2s",
  589. .id = 2,
  590. .type = SND_SOC_DAI_I2S,
  591. .suspend = at91_i2s_suspend,
  592. .resume = at91_i2s_resume,
  593. .playback = {
  594. .channels_min = 1,
  595. .channels_max = 2,
  596. .rates = AT91_I2S_RATES,
  597. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  598. .capture = {
  599. .channels_min = 1,
  600. .channels_max = 2,
  601. .rates = AT91_I2S_RATES,
  602. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  603. .ops = {
  604. .startup = at91_i2s_startup,
  605. .shutdown = at91_i2s_shutdown,
  606. .prepare = at91_i2s_prepare,
  607. .hw_params = at91_i2s_hw_params,},
  608. .dai_ops = {
  609. .set_sysclk = at91_i2s_set_dai_sysclk,
  610. .set_fmt = at91_i2s_set_dai_fmt,
  611. .set_clkdiv = at91_i2s_set_dai_clkdiv,},
  612. .private_data = &ssc_info[2].ssc,
  613. },
  614. #endif
  615. };
  616. EXPORT_SYMBOL_GPL(at91_i2s_dai);
  617. /* Module information */
  618. MODULE_AUTHOR("Frank Mandarino, fmandarino@endrelia.com, www.endrelia.com");
  619. MODULE_DESCRIPTION("AT91 I2S ASoC Interface");
  620. MODULE_LICENSE("GPL");