rme96.c 67 KB

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  1. /*
  2. * ALSA driver for RME Digi96, Digi96/8 and Digi96/8 PRO/PAD/PST audio
  3. * interfaces
  4. *
  5. * Copyright (c) 2000, 2001 Anders Torger <torger@ludd.luth.se>
  6. *
  7. * Thanks to Henk Hesselink <henk@anda.nl> for the analog volume control
  8. * code.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. *
  24. */
  25. #include <sound/driver.h>
  26. #include <linux/delay.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/pci.h>
  30. #include <linux/slab.h>
  31. #include <linux/moduleparam.h>
  32. #include <sound/core.h>
  33. #include <sound/info.h>
  34. #include <sound/control.h>
  35. #include <sound/pcm.h>
  36. #include <sound/pcm_params.h>
  37. #include <sound/asoundef.h>
  38. #include <sound/initval.h>
  39. #include <asm/io.h>
  40. /* note, two last pcis should be equal, it is not a bug */
  41. MODULE_AUTHOR("Anders Torger <torger@ludd.luth.se>");
  42. MODULE_DESCRIPTION("RME Digi96, Digi96/8, Digi96/8 PRO, Digi96/8 PST, "
  43. "Digi96/8 PAD");
  44. MODULE_LICENSE("GPL");
  45. MODULE_SUPPORTED_DEVICE("{{RME,Digi96},"
  46. "{RME,Digi96/8},"
  47. "{RME,Digi96/8 PRO},"
  48. "{RME,Digi96/8 PST},"
  49. "{RME,Digi96/8 PAD}}");
  50. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  51. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  52. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  53. module_param_array(index, int, NULL, 0444);
  54. MODULE_PARM_DESC(index, "Index value for RME Digi96 soundcard.");
  55. module_param_array(id, charp, NULL, 0444);
  56. MODULE_PARM_DESC(id, "ID string for RME Digi96 soundcard.");
  57. module_param_array(enable, bool, NULL, 0444);
  58. MODULE_PARM_DESC(enable, "Enable RME Digi96 soundcard.");
  59. /*
  60. * Defines for RME Digi96 series, from internal RME reference documents
  61. * dated 12.01.00
  62. */
  63. #define RME96_SPDIF_NCHANNELS 2
  64. /* Playback and capture buffer size */
  65. #define RME96_BUFFER_SIZE 0x10000
  66. /* IO area size */
  67. #define RME96_IO_SIZE 0x60000
  68. /* IO area offsets */
  69. #define RME96_IO_PLAY_BUFFER 0x0
  70. #define RME96_IO_REC_BUFFER 0x10000
  71. #define RME96_IO_CONTROL_REGISTER 0x20000
  72. #define RME96_IO_ADDITIONAL_REG 0x20004
  73. #define RME96_IO_CONFIRM_PLAY_IRQ 0x20008
  74. #define RME96_IO_CONFIRM_REC_IRQ 0x2000C
  75. #define RME96_IO_SET_PLAY_POS 0x40000
  76. #define RME96_IO_RESET_PLAY_POS 0x4FFFC
  77. #define RME96_IO_SET_REC_POS 0x50000
  78. #define RME96_IO_RESET_REC_POS 0x5FFFC
  79. #define RME96_IO_GET_PLAY_POS 0x20000
  80. #define RME96_IO_GET_REC_POS 0x30000
  81. /* Write control register bits */
  82. #define RME96_WCR_START (1 << 0)
  83. #define RME96_WCR_START_2 (1 << 1)
  84. #define RME96_WCR_GAIN_0 (1 << 2)
  85. #define RME96_WCR_GAIN_1 (1 << 3)
  86. #define RME96_WCR_MODE24 (1 << 4)
  87. #define RME96_WCR_MODE24_2 (1 << 5)
  88. #define RME96_WCR_BM (1 << 6)
  89. #define RME96_WCR_BM_2 (1 << 7)
  90. #define RME96_WCR_ADAT (1 << 8)
  91. #define RME96_WCR_FREQ_0 (1 << 9)
  92. #define RME96_WCR_FREQ_1 (1 << 10)
  93. #define RME96_WCR_DS (1 << 11)
  94. #define RME96_WCR_PRO (1 << 12)
  95. #define RME96_WCR_EMP (1 << 13)
  96. #define RME96_WCR_SEL (1 << 14)
  97. #define RME96_WCR_MASTER (1 << 15)
  98. #define RME96_WCR_PD (1 << 16)
  99. #define RME96_WCR_INP_0 (1 << 17)
  100. #define RME96_WCR_INP_1 (1 << 18)
  101. #define RME96_WCR_THRU_0 (1 << 19)
  102. #define RME96_WCR_THRU_1 (1 << 20)
  103. #define RME96_WCR_THRU_2 (1 << 21)
  104. #define RME96_WCR_THRU_3 (1 << 22)
  105. #define RME96_WCR_THRU_4 (1 << 23)
  106. #define RME96_WCR_THRU_5 (1 << 24)
  107. #define RME96_WCR_THRU_6 (1 << 25)
  108. #define RME96_WCR_THRU_7 (1 << 26)
  109. #define RME96_WCR_DOLBY (1 << 27)
  110. #define RME96_WCR_MONITOR_0 (1 << 28)
  111. #define RME96_WCR_MONITOR_1 (1 << 29)
  112. #define RME96_WCR_ISEL (1 << 30)
  113. #define RME96_WCR_IDIS (1 << 31)
  114. #define RME96_WCR_BITPOS_GAIN_0 2
  115. #define RME96_WCR_BITPOS_GAIN_1 3
  116. #define RME96_WCR_BITPOS_FREQ_0 9
  117. #define RME96_WCR_BITPOS_FREQ_1 10
  118. #define RME96_WCR_BITPOS_INP_0 17
  119. #define RME96_WCR_BITPOS_INP_1 18
  120. #define RME96_WCR_BITPOS_MONITOR_0 28
  121. #define RME96_WCR_BITPOS_MONITOR_1 29
  122. /* Read control register bits */
  123. #define RME96_RCR_AUDIO_ADDR_MASK 0xFFFF
  124. #define RME96_RCR_IRQ_2 (1 << 16)
  125. #define RME96_RCR_T_OUT (1 << 17)
  126. #define RME96_RCR_DEV_ID_0 (1 << 21)
  127. #define RME96_RCR_DEV_ID_1 (1 << 22)
  128. #define RME96_RCR_LOCK (1 << 23)
  129. #define RME96_RCR_VERF (1 << 26)
  130. #define RME96_RCR_F0 (1 << 27)
  131. #define RME96_RCR_F1 (1 << 28)
  132. #define RME96_RCR_F2 (1 << 29)
  133. #define RME96_RCR_AUTOSYNC (1 << 30)
  134. #define RME96_RCR_IRQ (1 << 31)
  135. #define RME96_RCR_BITPOS_F0 27
  136. #define RME96_RCR_BITPOS_F1 28
  137. #define RME96_RCR_BITPOS_F2 29
  138. /* Additonal register bits */
  139. #define RME96_AR_WSEL (1 << 0)
  140. #define RME96_AR_ANALOG (1 << 1)
  141. #define RME96_AR_FREQPAD_0 (1 << 2)
  142. #define RME96_AR_FREQPAD_1 (1 << 3)
  143. #define RME96_AR_FREQPAD_2 (1 << 4)
  144. #define RME96_AR_PD2 (1 << 5)
  145. #define RME96_AR_DAC_EN (1 << 6)
  146. #define RME96_AR_CLATCH (1 << 7)
  147. #define RME96_AR_CCLK (1 << 8)
  148. #define RME96_AR_CDATA (1 << 9)
  149. #define RME96_AR_BITPOS_F0 2
  150. #define RME96_AR_BITPOS_F1 3
  151. #define RME96_AR_BITPOS_F2 4
  152. /* Monitor tracks */
  153. #define RME96_MONITOR_TRACKS_1_2 0
  154. #define RME96_MONITOR_TRACKS_3_4 1
  155. #define RME96_MONITOR_TRACKS_5_6 2
  156. #define RME96_MONITOR_TRACKS_7_8 3
  157. /* Attenuation */
  158. #define RME96_ATTENUATION_0 0
  159. #define RME96_ATTENUATION_6 1
  160. #define RME96_ATTENUATION_12 2
  161. #define RME96_ATTENUATION_18 3
  162. /* Input types */
  163. #define RME96_INPUT_OPTICAL 0
  164. #define RME96_INPUT_COAXIAL 1
  165. #define RME96_INPUT_INTERNAL 2
  166. #define RME96_INPUT_XLR 3
  167. #define RME96_INPUT_ANALOG 4
  168. /* Clock modes */
  169. #define RME96_CLOCKMODE_SLAVE 0
  170. #define RME96_CLOCKMODE_MASTER 1
  171. #define RME96_CLOCKMODE_WORDCLOCK 2
  172. /* Block sizes in bytes */
  173. #define RME96_SMALL_BLOCK_SIZE 2048
  174. #define RME96_LARGE_BLOCK_SIZE 8192
  175. /* Volume control */
  176. #define RME96_AD1852_VOL_BITS 14
  177. #define RME96_AD1855_VOL_BITS 10
  178. struct rme96 {
  179. spinlock_t lock;
  180. int irq;
  181. unsigned long port;
  182. void __iomem *iobase;
  183. u32 wcreg; /* cached write control register value */
  184. u32 wcreg_spdif; /* S/PDIF setup */
  185. u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
  186. u32 rcreg; /* cached read control register value */
  187. u32 areg; /* cached additional register value */
  188. u16 vol[2]; /* cached volume of analog output */
  189. u8 rev; /* card revision number */
  190. struct snd_pcm_substream *playback_substream;
  191. struct snd_pcm_substream *capture_substream;
  192. int playback_frlog; /* log2 of framesize */
  193. int capture_frlog;
  194. size_t playback_periodsize; /* in bytes, zero if not used */
  195. size_t capture_periodsize; /* in bytes, zero if not used */
  196. struct snd_card *card;
  197. struct snd_pcm *spdif_pcm;
  198. struct snd_pcm *adat_pcm;
  199. struct pci_dev *pci;
  200. struct snd_kcontrol *spdif_ctl;
  201. };
  202. static struct pci_device_id snd_rme96_ids[] = {
  203. { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96,
  204. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
  205. { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8,
  206. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
  207. { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PRO,
  208. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
  209. { PCI_VENDOR_ID_XILINX, PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST,
  210. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0, },
  211. { 0, }
  212. };
  213. MODULE_DEVICE_TABLE(pci, snd_rme96_ids);
  214. #define RME96_ISPLAYING(rme96) ((rme96)->wcreg & RME96_WCR_START)
  215. #define RME96_ISRECORDING(rme96) ((rme96)->wcreg & RME96_WCR_START_2)
  216. #define RME96_HAS_ANALOG_IN(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
  217. #define RME96_HAS_ANALOG_OUT(rme96) ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO || \
  218. (rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST)
  219. #define RME96_DAC_IS_1852(rme96) (RME96_HAS_ANALOG_OUT(rme96) && (rme96)->rev >= 4)
  220. #define RME96_DAC_IS_1855(rme96) (((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && (rme96)->rev < 4) || \
  221. ((rme96)->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PRO && (rme96)->rev == 2))
  222. #define RME96_185X_MAX_OUT(rme96) ((1 << (RME96_DAC_IS_1852(rme96) ? RME96_AD1852_VOL_BITS : RME96_AD1855_VOL_BITS)) - 1)
  223. static int
  224. snd_rme96_playback_prepare(struct snd_pcm_substream *substream);
  225. static int
  226. snd_rme96_capture_prepare(struct snd_pcm_substream *substream);
  227. static int
  228. snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
  229. int cmd);
  230. static int
  231. snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
  232. int cmd);
  233. static snd_pcm_uframes_t
  234. snd_rme96_playback_pointer(struct snd_pcm_substream *substream);
  235. static snd_pcm_uframes_t
  236. snd_rme96_capture_pointer(struct snd_pcm_substream *substream);
  237. static void __devinit
  238. snd_rme96_proc_init(struct rme96 *rme96);
  239. static int
  240. snd_rme96_create_switches(struct snd_card *card,
  241. struct rme96 *rme96);
  242. static int
  243. snd_rme96_getinputtype(struct rme96 *rme96);
  244. static inline unsigned int
  245. snd_rme96_playback_ptr(struct rme96 *rme96)
  246. {
  247. return (readl(rme96->iobase + RME96_IO_GET_PLAY_POS)
  248. & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->playback_frlog;
  249. }
  250. static inline unsigned int
  251. snd_rme96_capture_ptr(struct rme96 *rme96)
  252. {
  253. return (readl(rme96->iobase + RME96_IO_GET_REC_POS)
  254. & RME96_RCR_AUDIO_ADDR_MASK) >> rme96->capture_frlog;
  255. }
  256. static int
  257. snd_rme96_ratecode(int rate)
  258. {
  259. switch (rate) {
  260. case 32000: return SNDRV_PCM_RATE_32000;
  261. case 44100: return SNDRV_PCM_RATE_44100;
  262. case 48000: return SNDRV_PCM_RATE_48000;
  263. case 64000: return SNDRV_PCM_RATE_64000;
  264. case 88200: return SNDRV_PCM_RATE_88200;
  265. case 96000: return SNDRV_PCM_RATE_96000;
  266. }
  267. return 0;
  268. }
  269. static int
  270. snd_rme96_playback_silence(struct snd_pcm_substream *substream,
  271. int channel, /* not used (interleaved data) */
  272. snd_pcm_uframes_t pos,
  273. snd_pcm_uframes_t count)
  274. {
  275. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  276. count <<= rme96->playback_frlog;
  277. pos <<= rme96->playback_frlog;
  278. memset_io(rme96->iobase + RME96_IO_PLAY_BUFFER + pos,
  279. 0, count);
  280. return 0;
  281. }
  282. static int
  283. snd_rme96_playback_copy(struct snd_pcm_substream *substream,
  284. int channel, /* not used (interleaved data) */
  285. snd_pcm_uframes_t pos,
  286. void __user *src,
  287. snd_pcm_uframes_t count)
  288. {
  289. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  290. count <<= rme96->playback_frlog;
  291. pos <<= rme96->playback_frlog;
  292. copy_from_user_toio(rme96->iobase + RME96_IO_PLAY_BUFFER + pos, src,
  293. count);
  294. return 0;
  295. }
  296. static int
  297. snd_rme96_capture_copy(struct snd_pcm_substream *substream,
  298. int channel, /* not used (interleaved data) */
  299. snd_pcm_uframes_t pos,
  300. void __user *dst,
  301. snd_pcm_uframes_t count)
  302. {
  303. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  304. count <<= rme96->capture_frlog;
  305. pos <<= rme96->capture_frlog;
  306. copy_to_user_fromio(dst, rme96->iobase + RME96_IO_REC_BUFFER + pos,
  307. count);
  308. return 0;
  309. }
  310. /*
  311. * Digital output capabilities (S/PDIF)
  312. */
  313. static struct snd_pcm_hardware snd_rme96_playback_spdif_info =
  314. {
  315. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  316. SNDRV_PCM_INFO_MMAP_VALID |
  317. SNDRV_PCM_INFO_INTERLEAVED |
  318. SNDRV_PCM_INFO_PAUSE),
  319. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  320. SNDRV_PCM_FMTBIT_S32_LE),
  321. .rates = (SNDRV_PCM_RATE_32000 |
  322. SNDRV_PCM_RATE_44100 |
  323. SNDRV_PCM_RATE_48000 |
  324. SNDRV_PCM_RATE_64000 |
  325. SNDRV_PCM_RATE_88200 |
  326. SNDRV_PCM_RATE_96000),
  327. .rate_min = 32000,
  328. .rate_max = 96000,
  329. .channels_min = 2,
  330. .channels_max = 2,
  331. .buffer_bytes_max = RME96_BUFFER_SIZE,
  332. .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
  333. .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
  334. .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
  335. .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
  336. .fifo_size = 0,
  337. };
  338. /*
  339. * Digital input capabilities (S/PDIF)
  340. */
  341. static struct snd_pcm_hardware snd_rme96_capture_spdif_info =
  342. {
  343. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  344. SNDRV_PCM_INFO_MMAP_VALID |
  345. SNDRV_PCM_INFO_INTERLEAVED |
  346. SNDRV_PCM_INFO_PAUSE),
  347. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  348. SNDRV_PCM_FMTBIT_S32_LE),
  349. .rates = (SNDRV_PCM_RATE_32000 |
  350. SNDRV_PCM_RATE_44100 |
  351. SNDRV_PCM_RATE_48000 |
  352. SNDRV_PCM_RATE_64000 |
  353. SNDRV_PCM_RATE_88200 |
  354. SNDRV_PCM_RATE_96000),
  355. .rate_min = 32000,
  356. .rate_max = 96000,
  357. .channels_min = 2,
  358. .channels_max = 2,
  359. .buffer_bytes_max = RME96_BUFFER_SIZE,
  360. .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
  361. .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
  362. .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
  363. .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
  364. .fifo_size = 0,
  365. };
  366. /*
  367. * Digital output capabilities (ADAT)
  368. */
  369. static struct snd_pcm_hardware snd_rme96_playback_adat_info =
  370. {
  371. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  372. SNDRV_PCM_INFO_MMAP_VALID |
  373. SNDRV_PCM_INFO_INTERLEAVED |
  374. SNDRV_PCM_INFO_PAUSE),
  375. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  376. SNDRV_PCM_FMTBIT_S32_LE),
  377. .rates = (SNDRV_PCM_RATE_44100 |
  378. SNDRV_PCM_RATE_48000),
  379. .rate_min = 44100,
  380. .rate_max = 48000,
  381. .channels_min = 8,
  382. .channels_max = 8,
  383. .buffer_bytes_max = RME96_BUFFER_SIZE,
  384. .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
  385. .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
  386. .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
  387. .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
  388. .fifo_size = 0,
  389. };
  390. /*
  391. * Digital input capabilities (ADAT)
  392. */
  393. static struct snd_pcm_hardware snd_rme96_capture_adat_info =
  394. {
  395. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  396. SNDRV_PCM_INFO_MMAP_VALID |
  397. SNDRV_PCM_INFO_INTERLEAVED |
  398. SNDRV_PCM_INFO_PAUSE),
  399. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  400. SNDRV_PCM_FMTBIT_S32_LE),
  401. .rates = (SNDRV_PCM_RATE_44100 |
  402. SNDRV_PCM_RATE_48000),
  403. .rate_min = 44100,
  404. .rate_max = 48000,
  405. .channels_min = 8,
  406. .channels_max = 8,
  407. .buffer_bytes_max = RME96_BUFFER_SIZE,
  408. .period_bytes_min = RME96_SMALL_BLOCK_SIZE,
  409. .period_bytes_max = RME96_LARGE_BLOCK_SIZE,
  410. .periods_min = RME96_BUFFER_SIZE / RME96_LARGE_BLOCK_SIZE,
  411. .periods_max = RME96_BUFFER_SIZE / RME96_SMALL_BLOCK_SIZE,
  412. .fifo_size = 0,
  413. };
  414. /*
  415. * The CDATA, CCLK and CLATCH bits can be used to write to the SPI interface
  416. * of the AD1852 or AD1852 D/A converter on the board. CDATA must be set up
  417. * on the falling edge of CCLK and be stable on the rising edge. The rising
  418. * edge of CLATCH after the last data bit clocks in the whole data word.
  419. * A fast processor could probably drive the SPI interface faster than the
  420. * DAC can handle (3MHz for the 1855, unknown for the 1852). The udelay(1)
  421. * limits the data rate to 500KHz and only causes a delay of 33 microsecs.
  422. *
  423. * NOTE: increased delay from 1 to 10, since there where problems setting
  424. * the volume.
  425. */
  426. static void
  427. snd_rme96_write_SPI(struct rme96 *rme96, u16 val)
  428. {
  429. int i;
  430. for (i = 0; i < 16; i++) {
  431. if (val & 0x8000) {
  432. rme96->areg |= RME96_AR_CDATA;
  433. } else {
  434. rme96->areg &= ~RME96_AR_CDATA;
  435. }
  436. rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CLATCH);
  437. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  438. udelay(10);
  439. rme96->areg |= RME96_AR_CCLK;
  440. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  441. udelay(10);
  442. val <<= 1;
  443. }
  444. rme96->areg &= ~(RME96_AR_CCLK | RME96_AR_CDATA);
  445. rme96->areg |= RME96_AR_CLATCH;
  446. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  447. udelay(10);
  448. rme96->areg &= ~RME96_AR_CLATCH;
  449. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  450. }
  451. static void
  452. snd_rme96_apply_dac_volume(struct rme96 *rme96)
  453. {
  454. if (RME96_DAC_IS_1852(rme96)) {
  455. snd_rme96_write_SPI(rme96, (rme96->vol[0] << 2) | 0x0);
  456. snd_rme96_write_SPI(rme96, (rme96->vol[1] << 2) | 0x2);
  457. } else if (RME96_DAC_IS_1855(rme96)) {
  458. snd_rme96_write_SPI(rme96, (rme96->vol[0] & 0x3FF) | 0x000);
  459. snd_rme96_write_SPI(rme96, (rme96->vol[1] & 0x3FF) | 0x400);
  460. }
  461. }
  462. static void
  463. snd_rme96_reset_dac(struct rme96 *rme96)
  464. {
  465. writel(rme96->wcreg | RME96_WCR_PD,
  466. rme96->iobase + RME96_IO_CONTROL_REGISTER);
  467. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  468. }
  469. static int
  470. snd_rme96_getmontracks(struct rme96 *rme96)
  471. {
  472. return ((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_0) & 1) +
  473. (((rme96->wcreg >> RME96_WCR_BITPOS_MONITOR_1) & 1) << 1);
  474. }
  475. static int
  476. snd_rme96_setmontracks(struct rme96 *rme96,
  477. int montracks)
  478. {
  479. if (montracks & 1) {
  480. rme96->wcreg |= RME96_WCR_MONITOR_0;
  481. } else {
  482. rme96->wcreg &= ~RME96_WCR_MONITOR_0;
  483. }
  484. if (montracks & 2) {
  485. rme96->wcreg |= RME96_WCR_MONITOR_1;
  486. } else {
  487. rme96->wcreg &= ~RME96_WCR_MONITOR_1;
  488. }
  489. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  490. return 0;
  491. }
  492. static int
  493. snd_rme96_getattenuation(struct rme96 *rme96)
  494. {
  495. return ((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_0) & 1) +
  496. (((rme96->wcreg >> RME96_WCR_BITPOS_GAIN_1) & 1) << 1);
  497. }
  498. static int
  499. snd_rme96_setattenuation(struct rme96 *rme96,
  500. int attenuation)
  501. {
  502. switch (attenuation) {
  503. case 0:
  504. rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) &
  505. ~RME96_WCR_GAIN_1;
  506. break;
  507. case 1:
  508. rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) &
  509. ~RME96_WCR_GAIN_1;
  510. break;
  511. case 2:
  512. rme96->wcreg = (rme96->wcreg & ~RME96_WCR_GAIN_0) |
  513. RME96_WCR_GAIN_1;
  514. break;
  515. case 3:
  516. rme96->wcreg = (rme96->wcreg | RME96_WCR_GAIN_0) |
  517. RME96_WCR_GAIN_1;
  518. break;
  519. default:
  520. return -EINVAL;
  521. }
  522. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  523. return 0;
  524. }
  525. static int
  526. snd_rme96_capture_getrate(struct rme96 *rme96,
  527. int *is_adat)
  528. {
  529. int n, rate;
  530. *is_adat = 0;
  531. if (rme96->areg & RME96_AR_ANALOG) {
  532. /* Analog input, overrides S/PDIF setting */
  533. n = ((rme96->areg >> RME96_AR_BITPOS_F0) & 1) +
  534. (((rme96->areg >> RME96_AR_BITPOS_F1) & 1) << 1);
  535. switch (n) {
  536. case 1:
  537. rate = 32000;
  538. break;
  539. case 2:
  540. rate = 44100;
  541. break;
  542. case 3:
  543. rate = 48000;
  544. break;
  545. default:
  546. return -1;
  547. }
  548. return (rme96->areg & RME96_AR_BITPOS_F2) ? rate << 1 : rate;
  549. }
  550. rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
  551. if (rme96->rcreg & RME96_RCR_LOCK) {
  552. /* ADAT rate */
  553. *is_adat = 1;
  554. if (rme96->rcreg & RME96_RCR_T_OUT) {
  555. return 48000;
  556. }
  557. return 44100;
  558. }
  559. if (rme96->rcreg & RME96_RCR_VERF) {
  560. return -1;
  561. }
  562. /* S/PDIF rate */
  563. n = ((rme96->rcreg >> RME96_RCR_BITPOS_F0) & 1) +
  564. (((rme96->rcreg >> RME96_RCR_BITPOS_F1) & 1) << 1) +
  565. (((rme96->rcreg >> RME96_RCR_BITPOS_F2) & 1) << 2);
  566. switch (n) {
  567. case 0:
  568. if (rme96->rcreg & RME96_RCR_T_OUT) {
  569. return 64000;
  570. }
  571. return -1;
  572. case 3: return 96000;
  573. case 4: return 88200;
  574. case 5: return 48000;
  575. case 6: return 44100;
  576. case 7: return 32000;
  577. default:
  578. break;
  579. }
  580. return -1;
  581. }
  582. static int
  583. snd_rme96_playback_getrate(struct rme96 *rme96)
  584. {
  585. int rate, dummy;
  586. if (!(rme96->wcreg & RME96_WCR_MASTER) &&
  587. snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
  588. (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
  589. {
  590. /* slave clock */
  591. return rate;
  592. }
  593. rate = ((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_0) & 1) +
  594. (((rme96->wcreg >> RME96_WCR_BITPOS_FREQ_1) & 1) << 1);
  595. switch (rate) {
  596. case 1:
  597. rate = 32000;
  598. break;
  599. case 2:
  600. rate = 44100;
  601. break;
  602. case 3:
  603. rate = 48000;
  604. break;
  605. default:
  606. return -1;
  607. }
  608. return (rme96->wcreg & RME96_WCR_DS) ? rate << 1 : rate;
  609. }
  610. static int
  611. snd_rme96_playback_setrate(struct rme96 *rme96,
  612. int rate)
  613. {
  614. int ds;
  615. ds = rme96->wcreg & RME96_WCR_DS;
  616. switch (rate) {
  617. case 32000:
  618. rme96->wcreg &= ~RME96_WCR_DS;
  619. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
  620. ~RME96_WCR_FREQ_1;
  621. break;
  622. case 44100:
  623. rme96->wcreg &= ~RME96_WCR_DS;
  624. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
  625. ~RME96_WCR_FREQ_0;
  626. break;
  627. case 48000:
  628. rme96->wcreg &= ~RME96_WCR_DS;
  629. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
  630. RME96_WCR_FREQ_1;
  631. break;
  632. case 64000:
  633. rme96->wcreg |= RME96_WCR_DS;
  634. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) &
  635. ~RME96_WCR_FREQ_1;
  636. break;
  637. case 88200:
  638. rme96->wcreg |= RME96_WCR_DS;
  639. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_1) &
  640. ~RME96_WCR_FREQ_0;
  641. break;
  642. case 96000:
  643. rme96->wcreg |= RME96_WCR_DS;
  644. rme96->wcreg = (rme96->wcreg | RME96_WCR_FREQ_0) |
  645. RME96_WCR_FREQ_1;
  646. break;
  647. default:
  648. return -EINVAL;
  649. }
  650. if ((!ds && rme96->wcreg & RME96_WCR_DS) ||
  651. (ds && !(rme96->wcreg & RME96_WCR_DS)))
  652. {
  653. /* change to/from double-speed: reset the DAC (if available) */
  654. snd_rme96_reset_dac(rme96);
  655. } else {
  656. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  657. }
  658. return 0;
  659. }
  660. static int
  661. snd_rme96_capture_analog_setrate(struct rme96 *rme96,
  662. int rate)
  663. {
  664. switch (rate) {
  665. case 32000:
  666. rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
  667. ~RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
  668. break;
  669. case 44100:
  670. rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
  671. RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
  672. break;
  673. case 48000:
  674. rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
  675. RME96_AR_FREQPAD_1) & ~RME96_AR_FREQPAD_2;
  676. break;
  677. case 64000:
  678. if (rme96->rev < 4) {
  679. return -EINVAL;
  680. }
  681. rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) &
  682. ~RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
  683. break;
  684. case 88200:
  685. if (rme96->rev < 4) {
  686. return -EINVAL;
  687. }
  688. rme96->areg = ((rme96->areg & ~RME96_AR_FREQPAD_0) |
  689. RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
  690. break;
  691. case 96000:
  692. rme96->areg = ((rme96->areg | RME96_AR_FREQPAD_0) |
  693. RME96_AR_FREQPAD_1) | RME96_AR_FREQPAD_2;
  694. break;
  695. default:
  696. return -EINVAL;
  697. }
  698. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  699. return 0;
  700. }
  701. static int
  702. snd_rme96_setclockmode(struct rme96 *rme96,
  703. int mode)
  704. {
  705. switch (mode) {
  706. case RME96_CLOCKMODE_SLAVE:
  707. /* AutoSync */
  708. rme96->wcreg &= ~RME96_WCR_MASTER;
  709. rme96->areg &= ~RME96_AR_WSEL;
  710. break;
  711. case RME96_CLOCKMODE_MASTER:
  712. /* Internal */
  713. rme96->wcreg |= RME96_WCR_MASTER;
  714. rme96->areg &= ~RME96_AR_WSEL;
  715. break;
  716. case RME96_CLOCKMODE_WORDCLOCK:
  717. /* Word clock is a master mode */
  718. rme96->wcreg |= RME96_WCR_MASTER;
  719. rme96->areg |= RME96_AR_WSEL;
  720. break;
  721. default:
  722. return -EINVAL;
  723. }
  724. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  725. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  726. return 0;
  727. }
  728. static int
  729. snd_rme96_getclockmode(struct rme96 *rme96)
  730. {
  731. if (rme96->areg & RME96_AR_WSEL) {
  732. return RME96_CLOCKMODE_WORDCLOCK;
  733. }
  734. return (rme96->wcreg & RME96_WCR_MASTER) ? RME96_CLOCKMODE_MASTER :
  735. RME96_CLOCKMODE_SLAVE;
  736. }
  737. static int
  738. snd_rme96_setinputtype(struct rme96 *rme96,
  739. int type)
  740. {
  741. int n;
  742. switch (type) {
  743. case RME96_INPUT_OPTICAL:
  744. rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) &
  745. ~RME96_WCR_INP_1;
  746. break;
  747. case RME96_INPUT_COAXIAL:
  748. rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) &
  749. ~RME96_WCR_INP_1;
  750. break;
  751. case RME96_INPUT_INTERNAL:
  752. rme96->wcreg = (rme96->wcreg & ~RME96_WCR_INP_0) |
  753. RME96_WCR_INP_1;
  754. break;
  755. case RME96_INPUT_XLR:
  756. if ((rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
  757. rme96->pci->device != PCI_DEVICE_ID_RME_DIGI96_8_PRO) ||
  758. (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST &&
  759. rme96->rev > 4))
  760. {
  761. /* Only Digi96/8 PRO and Digi96/8 PAD supports XLR */
  762. return -EINVAL;
  763. }
  764. rme96->wcreg = (rme96->wcreg | RME96_WCR_INP_0) |
  765. RME96_WCR_INP_1;
  766. break;
  767. case RME96_INPUT_ANALOG:
  768. if (!RME96_HAS_ANALOG_IN(rme96)) {
  769. return -EINVAL;
  770. }
  771. rme96->areg |= RME96_AR_ANALOG;
  772. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  773. if (rme96->rev < 4) {
  774. /*
  775. * Revision less than 004 does not support 64 and
  776. * 88.2 kHz
  777. */
  778. if (snd_rme96_capture_getrate(rme96, &n) == 88200) {
  779. snd_rme96_capture_analog_setrate(rme96, 44100);
  780. }
  781. if (snd_rme96_capture_getrate(rme96, &n) == 64000) {
  782. snd_rme96_capture_analog_setrate(rme96, 32000);
  783. }
  784. }
  785. return 0;
  786. default:
  787. return -EINVAL;
  788. }
  789. if (type != RME96_INPUT_ANALOG && RME96_HAS_ANALOG_IN(rme96)) {
  790. rme96->areg &= ~RME96_AR_ANALOG;
  791. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  792. }
  793. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  794. return 0;
  795. }
  796. static int
  797. snd_rme96_getinputtype(struct rme96 *rme96)
  798. {
  799. if (rme96->areg & RME96_AR_ANALOG) {
  800. return RME96_INPUT_ANALOG;
  801. }
  802. return ((rme96->wcreg >> RME96_WCR_BITPOS_INP_0) & 1) +
  803. (((rme96->wcreg >> RME96_WCR_BITPOS_INP_1) & 1) << 1);
  804. }
  805. static void
  806. snd_rme96_setframelog(struct rme96 *rme96,
  807. int n_channels,
  808. int is_playback)
  809. {
  810. int frlog;
  811. if (n_channels == 2) {
  812. frlog = 1;
  813. } else {
  814. /* assume 8 channels */
  815. frlog = 3;
  816. }
  817. if (is_playback) {
  818. frlog += (rme96->wcreg & RME96_WCR_MODE24) ? 2 : 1;
  819. rme96->playback_frlog = frlog;
  820. } else {
  821. frlog += (rme96->wcreg & RME96_WCR_MODE24_2) ? 2 : 1;
  822. rme96->capture_frlog = frlog;
  823. }
  824. }
  825. static int
  826. snd_rme96_playback_setformat(struct rme96 *rme96,
  827. int format)
  828. {
  829. switch (format) {
  830. case SNDRV_PCM_FORMAT_S16_LE:
  831. rme96->wcreg &= ~RME96_WCR_MODE24;
  832. break;
  833. case SNDRV_PCM_FORMAT_S32_LE:
  834. rme96->wcreg |= RME96_WCR_MODE24;
  835. break;
  836. default:
  837. return -EINVAL;
  838. }
  839. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  840. return 0;
  841. }
  842. static int
  843. snd_rme96_capture_setformat(struct rme96 *rme96,
  844. int format)
  845. {
  846. switch (format) {
  847. case SNDRV_PCM_FORMAT_S16_LE:
  848. rme96->wcreg &= ~RME96_WCR_MODE24_2;
  849. break;
  850. case SNDRV_PCM_FORMAT_S32_LE:
  851. rme96->wcreg |= RME96_WCR_MODE24_2;
  852. break;
  853. default:
  854. return -EINVAL;
  855. }
  856. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  857. return 0;
  858. }
  859. static void
  860. snd_rme96_set_period_properties(struct rme96 *rme96,
  861. size_t period_bytes)
  862. {
  863. switch (period_bytes) {
  864. case RME96_LARGE_BLOCK_SIZE:
  865. rme96->wcreg &= ~RME96_WCR_ISEL;
  866. break;
  867. case RME96_SMALL_BLOCK_SIZE:
  868. rme96->wcreg |= RME96_WCR_ISEL;
  869. break;
  870. default:
  871. snd_BUG();
  872. break;
  873. }
  874. rme96->wcreg &= ~RME96_WCR_IDIS;
  875. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  876. }
  877. static int
  878. snd_rme96_playback_hw_params(struct snd_pcm_substream *substream,
  879. struct snd_pcm_hw_params *params)
  880. {
  881. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  882. struct snd_pcm_runtime *runtime = substream->runtime;
  883. int err, rate, dummy;
  884. runtime->dma_area = (void __force *)(rme96->iobase +
  885. RME96_IO_PLAY_BUFFER);
  886. runtime->dma_addr = rme96->port + RME96_IO_PLAY_BUFFER;
  887. runtime->dma_bytes = RME96_BUFFER_SIZE;
  888. spin_lock_irq(&rme96->lock);
  889. if (!(rme96->wcreg & RME96_WCR_MASTER) &&
  890. snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
  891. (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
  892. {
  893. /* slave clock */
  894. if ((int)params_rate(params) != rate) {
  895. spin_unlock_irq(&rme96->lock);
  896. return -EIO;
  897. }
  898. } else if ((err = snd_rme96_playback_setrate(rme96, params_rate(params))) < 0) {
  899. spin_unlock_irq(&rme96->lock);
  900. return err;
  901. }
  902. if ((err = snd_rme96_playback_setformat(rme96, params_format(params))) < 0) {
  903. spin_unlock_irq(&rme96->lock);
  904. return err;
  905. }
  906. snd_rme96_setframelog(rme96, params_channels(params), 1);
  907. if (rme96->capture_periodsize != 0) {
  908. if (params_period_size(params) << rme96->playback_frlog !=
  909. rme96->capture_periodsize)
  910. {
  911. spin_unlock_irq(&rme96->lock);
  912. return -EBUSY;
  913. }
  914. }
  915. rme96->playback_periodsize =
  916. params_period_size(params) << rme96->playback_frlog;
  917. snd_rme96_set_period_properties(rme96, rme96->playback_periodsize);
  918. /* S/PDIF setup */
  919. if ((rme96->wcreg & RME96_WCR_ADAT) == 0) {
  920. rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
  921. writel(rme96->wcreg |= rme96->wcreg_spdif_stream, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  922. }
  923. spin_unlock_irq(&rme96->lock);
  924. return 0;
  925. }
  926. static int
  927. snd_rme96_capture_hw_params(struct snd_pcm_substream *substream,
  928. struct snd_pcm_hw_params *params)
  929. {
  930. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  931. struct snd_pcm_runtime *runtime = substream->runtime;
  932. int err, isadat, rate;
  933. runtime->dma_area = (void __force *)(rme96->iobase +
  934. RME96_IO_REC_BUFFER);
  935. runtime->dma_addr = rme96->port + RME96_IO_REC_BUFFER;
  936. runtime->dma_bytes = RME96_BUFFER_SIZE;
  937. spin_lock_irq(&rme96->lock);
  938. if ((err = snd_rme96_capture_setformat(rme96, params_format(params))) < 0) {
  939. spin_unlock_irq(&rme96->lock);
  940. return err;
  941. }
  942. if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
  943. if ((err = snd_rme96_capture_analog_setrate(rme96,
  944. params_rate(params))) < 0)
  945. {
  946. spin_unlock_irq(&rme96->lock);
  947. return err;
  948. }
  949. } else if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
  950. if ((int)params_rate(params) != rate) {
  951. spin_unlock_irq(&rme96->lock);
  952. return -EIO;
  953. }
  954. if ((isadat && runtime->hw.channels_min == 2) ||
  955. (!isadat && runtime->hw.channels_min == 8))
  956. {
  957. spin_unlock_irq(&rme96->lock);
  958. return -EIO;
  959. }
  960. }
  961. snd_rme96_setframelog(rme96, params_channels(params), 0);
  962. if (rme96->playback_periodsize != 0) {
  963. if (params_period_size(params) << rme96->capture_frlog !=
  964. rme96->playback_periodsize)
  965. {
  966. spin_unlock_irq(&rme96->lock);
  967. return -EBUSY;
  968. }
  969. }
  970. rme96->capture_periodsize =
  971. params_period_size(params) << rme96->capture_frlog;
  972. snd_rme96_set_period_properties(rme96, rme96->capture_periodsize);
  973. spin_unlock_irq(&rme96->lock);
  974. return 0;
  975. }
  976. static void
  977. snd_rme96_playback_start(struct rme96 *rme96,
  978. int from_pause)
  979. {
  980. if (!from_pause) {
  981. writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
  982. }
  983. rme96->wcreg |= RME96_WCR_START;
  984. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  985. }
  986. static void
  987. snd_rme96_capture_start(struct rme96 *rme96,
  988. int from_pause)
  989. {
  990. if (!from_pause) {
  991. writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
  992. }
  993. rme96->wcreg |= RME96_WCR_START_2;
  994. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  995. }
  996. static void
  997. snd_rme96_playback_stop(struct rme96 *rme96)
  998. {
  999. /*
  1000. * Check if there is an unconfirmed IRQ, if so confirm it, or else
  1001. * the hardware will not stop generating interrupts
  1002. */
  1003. rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1004. if (rme96->rcreg & RME96_RCR_IRQ) {
  1005. writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
  1006. }
  1007. rme96->wcreg &= ~RME96_WCR_START;
  1008. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1009. }
  1010. static void
  1011. snd_rme96_capture_stop(struct rme96 *rme96)
  1012. {
  1013. rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1014. if (rme96->rcreg & RME96_RCR_IRQ_2) {
  1015. writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
  1016. }
  1017. rme96->wcreg &= ~RME96_WCR_START_2;
  1018. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1019. }
  1020. static irqreturn_t
  1021. snd_rme96_interrupt(int irq,
  1022. void *dev_id)
  1023. {
  1024. struct rme96 *rme96 = (struct rme96 *)dev_id;
  1025. rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1026. /* fastpath out, to ease interrupt sharing */
  1027. if (!((rme96->rcreg & RME96_RCR_IRQ) ||
  1028. (rme96->rcreg & RME96_RCR_IRQ_2)))
  1029. {
  1030. return IRQ_NONE;
  1031. }
  1032. if (rme96->rcreg & RME96_RCR_IRQ) {
  1033. /* playback */
  1034. snd_pcm_period_elapsed(rme96->playback_substream);
  1035. writel(0, rme96->iobase + RME96_IO_CONFIRM_PLAY_IRQ);
  1036. }
  1037. if (rme96->rcreg & RME96_RCR_IRQ_2) {
  1038. /* capture */
  1039. snd_pcm_period_elapsed(rme96->capture_substream);
  1040. writel(0, rme96->iobase + RME96_IO_CONFIRM_REC_IRQ);
  1041. }
  1042. return IRQ_HANDLED;
  1043. }
  1044. static unsigned int period_bytes[] = { RME96_SMALL_BLOCK_SIZE, RME96_LARGE_BLOCK_SIZE };
  1045. static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
  1046. .count = ARRAY_SIZE(period_bytes),
  1047. .list = period_bytes,
  1048. .mask = 0
  1049. };
  1050. static void
  1051. rme96_set_buffer_size_constraint(struct rme96 *rme96,
  1052. struct snd_pcm_runtime *runtime)
  1053. {
  1054. unsigned int size;
  1055. snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1056. RME96_BUFFER_SIZE, RME96_BUFFER_SIZE);
  1057. if ((size = rme96->playback_periodsize) != 0 ||
  1058. (size = rme96->capture_periodsize) != 0)
  1059. snd_pcm_hw_constraint_minmax(runtime,
  1060. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1061. size, size);
  1062. else
  1063. snd_pcm_hw_constraint_list(runtime, 0,
  1064. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1065. &hw_constraints_period_bytes);
  1066. }
  1067. static int
  1068. snd_rme96_playback_spdif_open(struct snd_pcm_substream *substream)
  1069. {
  1070. int rate, dummy;
  1071. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1072. struct snd_pcm_runtime *runtime = substream->runtime;
  1073. snd_pcm_set_sync(substream);
  1074. spin_lock_irq(&rme96->lock);
  1075. if (rme96->playback_substream != NULL) {
  1076. spin_unlock_irq(&rme96->lock);
  1077. return -EBUSY;
  1078. }
  1079. rme96->wcreg &= ~RME96_WCR_ADAT;
  1080. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1081. rme96->playback_substream = substream;
  1082. spin_unlock_irq(&rme96->lock);
  1083. runtime->hw = snd_rme96_playback_spdif_info;
  1084. if (!(rme96->wcreg & RME96_WCR_MASTER) &&
  1085. snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
  1086. (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
  1087. {
  1088. /* slave clock */
  1089. runtime->hw.rates = snd_rme96_ratecode(rate);
  1090. runtime->hw.rate_min = rate;
  1091. runtime->hw.rate_max = rate;
  1092. }
  1093. rme96_set_buffer_size_constraint(rme96, runtime);
  1094. rme96->wcreg_spdif_stream = rme96->wcreg_spdif;
  1095. rme96->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  1096. snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
  1097. SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
  1098. return 0;
  1099. }
  1100. static int
  1101. snd_rme96_capture_spdif_open(struct snd_pcm_substream *substream)
  1102. {
  1103. int isadat, rate;
  1104. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1105. struct snd_pcm_runtime *runtime = substream->runtime;
  1106. snd_pcm_set_sync(substream);
  1107. runtime->hw = snd_rme96_capture_spdif_info;
  1108. if (snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
  1109. (rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0)
  1110. {
  1111. if (isadat) {
  1112. return -EIO;
  1113. }
  1114. runtime->hw.rates = snd_rme96_ratecode(rate);
  1115. runtime->hw.rate_min = rate;
  1116. runtime->hw.rate_max = rate;
  1117. }
  1118. spin_lock_irq(&rme96->lock);
  1119. if (rme96->capture_substream != NULL) {
  1120. spin_unlock_irq(&rme96->lock);
  1121. return -EBUSY;
  1122. }
  1123. rme96->capture_substream = substream;
  1124. spin_unlock_irq(&rme96->lock);
  1125. rme96_set_buffer_size_constraint(rme96, runtime);
  1126. return 0;
  1127. }
  1128. static int
  1129. snd_rme96_playback_adat_open(struct snd_pcm_substream *substream)
  1130. {
  1131. int rate, dummy;
  1132. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1133. struct snd_pcm_runtime *runtime = substream->runtime;
  1134. snd_pcm_set_sync(substream);
  1135. spin_lock_irq(&rme96->lock);
  1136. if (rme96->playback_substream != NULL) {
  1137. spin_unlock_irq(&rme96->lock);
  1138. return -EBUSY;
  1139. }
  1140. rme96->wcreg |= RME96_WCR_ADAT;
  1141. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1142. rme96->playback_substream = substream;
  1143. spin_unlock_irq(&rme96->lock);
  1144. runtime->hw = snd_rme96_playback_adat_info;
  1145. if (!(rme96->wcreg & RME96_WCR_MASTER) &&
  1146. snd_rme96_getinputtype(rme96) != RME96_INPUT_ANALOG &&
  1147. (rate = snd_rme96_capture_getrate(rme96, &dummy)) > 0)
  1148. {
  1149. /* slave clock */
  1150. runtime->hw.rates = snd_rme96_ratecode(rate);
  1151. runtime->hw.rate_min = rate;
  1152. runtime->hw.rate_max = rate;
  1153. }
  1154. rme96_set_buffer_size_constraint(rme96, runtime);
  1155. return 0;
  1156. }
  1157. static int
  1158. snd_rme96_capture_adat_open(struct snd_pcm_substream *substream)
  1159. {
  1160. int isadat, rate;
  1161. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1162. struct snd_pcm_runtime *runtime = substream->runtime;
  1163. snd_pcm_set_sync(substream);
  1164. runtime->hw = snd_rme96_capture_adat_info;
  1165. if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
  1166. /* makes no sense to use analog input. Note that analog
  1167. expension cards AEB4/8-I are RME96_INPUT_INTERNAL */
  1168. return -EIO;
  1169. }
  1170. if ((rate = snd_rme96_capture_getrate(rme96, &isadat)) > 0) {
  1171. if (!isadat) {
  1172. return -EIO;
  1173. }
  1174. runtime->hw.rates = snd_rme96_ratecode(rate);
  1175. runtime->hw.rate_min = rate;
  1176. runtime->hw.rate_max = rate;
  1177. }
  1178. spin_lock_irq(&rme96->lock);
  1179. if (rme96->capture_substream != NULL) {
  1180. spin_unlock_irq(&rme96->lock);
  1181. return -EBUSY;
  1182. }
  1183. rme96->capture_substream = substream;
  1184. spin_unlock_irq(&rme96->lock);
  1185. rme96_set_buffer_size_constraint(rme96, runtime);
  1186. return 0;
  1187. }
  1188. static int
  1189. snd_rme96_playback_close(struct snd_pcm_substream *substream)
  1190. {
  1191. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1192. int spdif = 0;
  1193. spin_lock_irq(&rme96->lock);
  1194. if (RME96_ISPLAYING(rme96)) {
  1195. snd_rme96_playback_stop(rme96);
  1196. }
  1197. rme96->playback_substream = NULL;
  1198. rme96->playback_periodsize = 0;
  1199. spdif = (rme96->wcreg & RME96_WCR_ADAT) == 0;
  1200. spin_unlock_irq(&rme96->lock);
  1201. if (spdif) {
  1202. rme96->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  1203. snd_ctl_notify(rme96->card, SNDRV_CTL_EVENT_MASK_VALUE |
  1204. SNDRV_CTL_EVENT_MASK_INFO, &rme96->spdif_ctl->id);
  1205. }
  1206. return 0;
  1207. }
  1208. static int
  1209. snd_rme96_capture_close(struct snd_pcm_substream *substream)
  1210. {
  1211. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1212. spin_lock_irq(&rme96->lock);
  1213. if (RME96_ISRECORDING(rme96)) {
  1214. snd_rme96_capture_stop(rme96);
  1215. }
  1216. rme96->capture_substream = NULL;
  1217. rme96->capture_periodsize = 0;
  1218. spin_unlock_irq(&rme96->lock);
  1219. return 0;
  1220. }
  1221. static int
  1222. snd_rme96_playback_prepare(struct snd_pcm_substream *substream)
  1223. {
  1224. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1225. spin_lock_irq(&rme96->lock);
  1226. if (RME96_ISPLAYING(rme96)) {
  1227. snd_rme96_playback_stop(rme96);
  1228. }
  1229. writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
  1230. spin_unlock_irq(&rme96->lock);
  1231. return 0;
  1232. }
  1233. static int
  1234. snd_rme96_capture_prepare(struct snd_pcm_substream *substream)
  1235. {
  1236. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1237. spin_lock_irq(&rme96->lock);
  1238. if (RME96_ISRECORDING(rme96)) {
  1239. snd_rme96_capture_stop(rme96);
  1240. }
  1241. writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
  1242. spin_unlock_irq(&rme96->lock);
  1243. return 0;
  1244. }
  1245. static int
  1246. snd_rme96_playback_trigger(struct snd_pcm_substream *substream,
  1247. int cmd)
  1248. {
  1249. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1250. switch (cmd) {
  1251. case SNDRV_PCM_TRIGGER_START:
  1252. if (!RME96_ISPLAYING(rme96)) {
  1253. if (substream != rme96->playback_substream) {
  1254. return -EBUSY;
  1255. }
  1256. snd_rme96_playback_start(rme96, 0);
  1257. }
  1258. break;
  1259. case SNDRV_PCM_TRIGGER_STOP:
  1260. if (RME96_ISPLAYING(rme96)) {
  1261. if (substream != rme96->playback_substream) {
  1262. return -EBUSY;
  1263. }
  1264. snd_rme96_playback_stop(rme96);
  1265. }
  1266. break;
  1267. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1268. if (RME96_ISPLAYING(rme96)) {
  1269. snd_rme96_playback_stop(rme96);
  1270. }
  1271. break;
  1272. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1273. if (!RME96_ISPLAYING(rme96)) {
  1274. snd_rme96_playback_start(rme96, 1);
  1275. }
  1276. break;
  1277. default:
  1278. return -EINVAL;
  1279. }
  1280. return 0;
  1281. }
  1282. static int
  1283. snd_rme96_capture_trigger(struct snd_pcm_substream *substream,
  1284. int cmd)
  1285. {
  1286. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1287. switch (cmd) {
  1288. case SNDRV_PCM_TRIGGER_START:
  1289. if (!RME96_ISRECORDING(rme96)) {
  1290. if (substream != rme96->capture_substream) {
  1291. return -EBUSY;
  1292. }
  1293. snd_rme96_capture_start(rme96, 0);
  1294. }
  1295. break;
  1296. case SNDRV_PCM_TRIGGER_STOP:
  1297. if (RME96_ISRECORDING(rme96)) {
  1298. if (substream != rme96->capture_substream) {
  1299. return -EBUSY;
  1300. }
  1301. snd_rme96_capture_stop(rme96);
  1302. }
  1303. break;
  1304. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1305. if (RME96_ISRECORDING(rme96)) {
  1306. snd_rme96_capture_stop(rme96);
  1307. }
  1308. break;
  1309. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1310. if (!RME96_ISRECORDING(rme96)) {
  1311. snd_rme96_capture_start(rme96, 1);
  1312. }
  1313. break;
  1314. default:
  1315. return -EINVAL;
  1316. }
  1317. return 0;
  1318. }
  1319. static snd_pcm_uframes_t
  1320. snd_rme96_playback_pointer(struct snd_pcm_substream *substream)
  1321. {
  1322. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1323. return snd_rme96_playback_ptr(rme96);
  1324. }
  1325. static snd_pcm_uframes_t
  1326. snd_rme96_capture_pointer(struct snd_pcm_substream *substream)
  1327. {
  1328. struct rme96 *rme96 = snd_pcm_substream_chip(substream);
  1329. return snd_rme96_capture_ptr(rme96);
  1330. }
  1331. static struct snd_pcm_ops snd_rme96_playback_spdif_ops = {
  1332. .open = snd_rme96_playback_spdif_open,
  1333. .close = snd_rme96_playback_close,
  1334. .ioctl = snd_pcm_lib_ioctl,
  1335. .hw_params = snd_rme96_playback_hw_params,
  1336. .prepare = snd_rme96_playback_prepare,
  1337. .trigger = snd_rme96_playback_trigger,
  1338. .pointer = snd_rme96_playback_pointer,
  1339. .copy = snd_rme96_playback_copy,
  1340. .silence = snd_rme96_playback_silence,
  1341. .mmap = snd_pcm_lib_mmap_iomem,
  1342. };
  1343. static struct snd_pcm_ops snd_rme96_capture_spdif_ops = {
  1344. .open = snd_rme96_capture_spdif_open,
  1345. .close = snd_rme96_capture_close,
  1346. .ioctl = snd_pcm_lib_ioctl,
  1347. .hw_params = snd_rme96_capture_hw_params,
  1348. .prepare = snd_rme96_capture_prepare,
  1349. .trigger = snd_rme96_capture_trigger,
  1350. .pointer = snd_rme96_capture_pointer,
  1351. .copy = snd_rme96_capture_copy,
  1352. .mmap = snd_pcm_lib_mmap_iomem,
  1353. };
  1354. static struct snd_pcm_ops snd_rme96_playback_adat_ops = {
  1355. .open = snd_rme96_playback_adat_open,
  1356. .close = snd_rme96_playback_close,
  1357. .ioctl = snd_pcm_lib_ioctl,
  1358. .hw_params = snd_rme96_playback_hw_params,
  1359. .prepare = snd_rme96_playback_prepare,
  1360. .trigger = snd_rme96_playback_trigger,
  1361. .pointer = snd_rme96_playback_pointer,
  1362. .copy = snd_rme96_playback_copy,
  1363. .silence = snd_rme96_playback_silence,
  1364. .mmap = snd_pcm_lib_mmap_iomem,
  1365. };
  1366. static struct snd_pcm_ops snd_rme96_capture_adat_ops = {
  1367. .open = snd_rme96_capture_adat_open,
  1368. .close = snd_rme96_capture_close,
  1369. .ioctl = snd_pcm_lib_ioctl,
  1370. .hw_params = snd_rme96_capture_hw_params,
  1371. .prepare = snd_rme96_capture_prepare,
  1372. .trigger = snd_rme96_capture_trigger,
  1373. .pointer = snd_rme96_capture_pointer,
  1374. .copy = snd_rme96_capture_copy,
  1375. .mmap = snd_pcm_lib_mmap_iomem,
  1376. };
  1377. static void
  1378. snd_rme96_free(void *private_data)
  1379. {
  1380. struct rme96 *rme96 = (struct rme96 *)private_data;
  1381. if (rme96 == NULL) {
  1382. return;
  1383. }
  1384. if (rme96->irq >= 0) {
  1385. snd_rme96_playback_stop(rme96);
  1386. snd_rme96_capture_stop(rme96);
  1387. rme96->areg &= ~RME96_AR_DAC_EN;
  1388. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  1389. free_irq(rme96->irq, (void *)rme96);
  1390. rme96->irq = -1;
  1391. }
  1392. if (rme96->iobase) {
  1393. iounmap(rme96->iobase);
  1394. rme96->iobase = NULL;
  1395. }
  1396. if (rme96->port) {
  1397. pci_release_regions(rme96->pci);
  1398. rme96->port = 0;
  1399. }
  1400. pci_disable_device(rme96->pci);
  1401. }
  1402. static void
  1403. snd_rme96_free_spdif_pcm(struct snd_pcm *pcm)
  1404. {
  1405. struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
  1406. rme96->spdif_pcm = NULL;
  1407. }
  1408. static void
  1409. snd_rme96_free_adat_pcm(struct snd_pcm *pcm)
  1410. {
  1411. struct rme96 *rme96 = (struct rme96 *) pcm->private_data;
  1412. rme96->adat_pcm = NULL;
  1413. }
  1414. static int __devinit
  1415. snd_rme96_create(struct rme96 *rme96)
  1416. {
  1417. struct pci_dev *pci = rme96->pci;
  1418. int err;
  1419. rme96->irq = -1;
  1420. spin_lock_init(&rme96->lock);
  1421. if ((err = pci_enable_device(pci)) < 0)
  1422. return err;
  1423. if ((err = pci_request_regions(pci, "RME96")) < 0)
  1424. return err;
  1425. rme96->port = pci_resource_start(rme96->pci, 0);
  1426. if ((rme96->iobase = ioremap_nocache(rme96->port, RME96_IO_SIZE)) == 0) {
  1427. snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n", rme96->port, rme96->port + RME96_IO_SIZE - 1);
  1428. return -ENOMEM;
  1429. }
  1430. if (request_irq(pci->irq, snd_rme96_interrupt, IRQF_SHARED,
  1431. "RME96", rme96)) {
  1432. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1433. return -EBUSY;
  1434. }
  1435. rme96->irq = pci->irq;
  1436. /* read the card's revision number */
  1437. pci_read_config_byte(pci, 8, &rme96->rev);
  1438. /* set up ALSA pcm device for S/PDIF */
  1439. if ((err = snd_pcm_new(rme96->card, "Digi96 IEC958", 0,
  1440. 1, 1, &rme96->spdif_pcm)) < 0)
  1441. {
  1442. return err;
  1443. }
  1444. rme96->spdif_pcm->private_data = rme96;
  1445. rme96->spdif_pcm->private_free = snd_rme96_free_spdif_pcm;
  1446. strcpy(rme96->spdif_pcm->name, "Digi96 IEC958");
  1447. snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_spdif_ops);
  1448. snd_pcm_set_ops(rme96->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_spdif_ops);
  1449. rme96->spdif_pcm->info_flags = 0;
  1450. /* set up ALSA pcm device for ADAT */
  1451. if (pci->device == PCI_DEVICE_ID_RME_DIGI96) {
  1452. /* ADAT is not available on the base model */
  1453. rme96->adat_pcm = NULL;
  1454. } else {
  1455. if ((err = snd_pcm_new(rme96->card, "Digi96 ADAT", 1,
  1456. 1, 1, &rme96->adat_pcm)) < 0)
  1457. {
  1458. return err;
  1459. }
  1460. rme96->adat_pcm->private_data = rme96;
  1461. rme96->adat_pcm->private_free = snd_rme96_free_adat_pcm;
  1462. strcpy(rme96->adat_pcm->name, "Digi96 ADAT");
  1463. snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_rme96_playback_adat_ops);
  1464. snd_pcm_set_ops(rme96->adat_pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_rme96_capture_adat_ops);
  1465. rme96->adat_pcm->info_flags = 0;
  1466. }
  1467. rme96->playback_periodsize = 0;
  1468. rme96->capture_periodsize = 0;
  1469. /* make sure playback/capture is stopped, if by some reason active */
  1470. snd_rme96_playback_stop(rme96);
  1471. snd_rme96_capture_stop(rme96);
  1472. /* set default values in registers */
  1473. rme96->wcreg =
  1474. RME96_WCR_FREQ_1 | /* set 44.1 kHz playback */
  1475. RME96_WCR_SEL | /* normal playback */
  1476. RME96_WCR_MASTER | /* set to master clock mode */
  1477. RME96_WCR_INP_0; /* set coaxial input */
  1478. rme96->areg = RME96_AR_FREQPAD_1; /* set 44.1 kHz analog capture */
  1479. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1480. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  1481. /* reset the ADC */
  1482. writel(rme96->areg | RME96_AR_PD2,
  1483. rme96->iobase + RME96_IO_ADDITIONAL_REG);
  1484. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  1485. /* reset and enable the DAC (order is important). */
  1486. snd_rme96_reset_dac(rme96);
  1487. rme96->areg |= RME96_AR_DAC_EN;
  1488. writel(rme96->areg, rme96->iobase + RME96_IO_ADDITIONAL_REG);
  1489. /* reset playback and record buffer pointers */
  1490. writel(0, rme96->iobase + RME96_IO_RESET_PLAY_POS);
  1491. writel(0, rme96->iobase + RME96_IO_RESET_REC_POS);
  1492. /* reset volume */
  1493. rme96->vol[0] = rme96->vol[1] = 0;
  1494. if (RME96_HAS_ANALOG_OUT(rme96)) {
  1495. snd_rme96_apply_dac_volume(rme96);
  1496. }
  1497. /* init switch interface */
  1498. if ((err = snd_rme96_create_switches(rme96->card, rme96)) < 0) {
  1499. return err;
  1500. }
  1501. /* init proc interface */
  1502. snd_rme96_proc_init(rme96);
  1503. return 0;
  1504. }
  1505. /*
  1506. * proc interface
  1507. */
  1508. static void
  1509. snd_rme96_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  1510. {
  1511. int n;
  1512. struct rme96 *rme96 = (struct rme96 *)entry->private_data;
  1513. rme96->rcreg = readl(rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1514. snd_iprintf(buffer, rme96->card->longname);
  1515. snd_iprintf(buffer, " (index #%d)\n", rme96->card->number + 1);
  1516. snd_iprintf(buffer, "\nGeneral settings\n");
  1517. if (rme96->wcreg & RME96_WCR_IDIS) {
  1518. snd_iprintf(buffer, " period size: N/A (interrupts "
  1519. "disabled)\n");
  1520. } else if (rme96->wcreg & RME96_WCR_ISEL) {
  1521. snd_iprintf(buffer, " period size: 2048 bytes\n");
  1522. } else {
  1523. snd_iprintf(buffer, " period size: 8192 bytes\n");
  1524. }
  1525. snd_iprintf(buffer, "\nInput settings\n");
  1526. switch (snd_rme96_getinputtype(rme96)) {
  1527. case RME96_INPUT_OPTICAL:
  1528. snd_iprintf(buffer, " input: optical");
  1529. break;
  1530. case RME96_INPUT_COAXIAL:
  1531. snd_iprintf(buffer, " input: coaxial");
  1532. break;
  1533. case RME96_INPUT_INTERNAL:
  1534. snd_iprintf(buffer, " input: internal");
  1535. break;
  1536. case RME96_INPUT_XLR:
  1537. snd_iprintf(buffer, " input: XLR");
  1538. break;
  1539. case RME96_INPUT_ANALOG:
  1540. snd_iprintf(buffer, " input: analog");
  1541. break;
  1542. }
  1543. if (snd_rme96_capture_getrate(rme96, &n) < 0) {
  1544. snd_iprintf(buffer, "\n sample rate: no valid signal\n");
  1545. } else {
  1546. if (n) {
  1547. snd_iprintf(buffer, " (8 channels)\n");
  1548. } else {
  1549. snd_iprintf(buffer, " (2 channels)\n");
  1550. }
  1551. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1552. snd_rme96_capture_getrate(rme96, &n));
  1553. }
  1554. if (rme96->wcreg & RME96_WCR_MODE24_2) {
  1555. snd_iprintf(buffer, " sample format: 24 bit\n");
  1556. } else {
  1557. snd_iprintf(buffer, " sample format: 16 bit\n");
  1558. }
  1559. snd_iprintf(buffer, "\nOutput settings\n");
  1560. if (rme96->wcreg & RME96_WCR_SEL) {
  1561. snd_iprintf(buffer, " output signal: normal playback\n");
  1562. } else {
  1563. snd_iprintf(buffer, " output signal: same as input\n");
  1564. }
  1565. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1566. snd_rme96_playback_getrate(rme96));
  1567. if (rme96->wcreg & RME96_WCR_MODE24) {
  1568. snd_iprintf(buffer, " sample format: 24 bit\n");
  1569. } else {
  1570. snd_iprintf(buffer, " sample format: 16 bit\n");
  1571. }
  1572. if (rme96->areg & RME96_AR_WSEL) {
  1573. snd_iprintf(buffer, " sample clock source: word clock\n");
  1574. } else if (rme96->wcreg & RME96_WCR_MASTER) {
  1575. snd_iprintf(buffer, " sample clock source: internal\n");
  1576. } else if (snd_rme96_getinputtype(rme96) == RME96_INPUT_ANALOG) {
  1577. snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to analog input setting)\n");
  1578. } else if (snd_rme96_capture_getrate(rme96, &n) < 0) {
  1579. snd_iprintf(buffer, " sample clock source: autosync (internal anyway due to no valid signal)\n");
  1580. } else {
  1581. snd_iprintf(buffer, " sample clock source: autosync\n");
  1582. }
  1583. if (rme96->wcreg & RME96_WCR_PRO) {
  1584. snd_iprintf(buffer, " format: AES/EBU (professional)\n");
  1585. } else {
  1586. snd_iprintf(buffer, " format: IEC958 (consumer)\n");
  1587. }
  1588. if (rme96->wcreg & RME96_WCR_EMP) {
  1589. snd_iprintf(buffer, " emphasis: on\n");
  1590. } else {
  1591. snd_iprintf(buffer, " emphasis: off\n");
  1592. }
  1593. if (rme96->wcreg & RME96_WCR_DOLBY) {
  1594. snd_iprintf(buffer, " non-audio (dolby): on\n");
  1595. } else {
  1596. snd_iprintf(buffer, " non-audio (dolby): off\n");
  1597. }
  1598. if (RME96_HAS_ANALOG_IN(rme96)) {
  1599. snd_iprintf(buffer, "\nAnalog output settings\n");
  1600. switch (snd_rme96_getmontracks(rme96)) {
  1601. case RME96_MONITOR_TRACKS_1_2:
  1602. snd_iprintf(buffer, " monitored ADAT tracks: 1+2\n");
  1603. break;
  1604. case RME96_MONITOR_TRACKS_3_4:
  1605. snd_iprintf(buffer, " monitored ADAT tracks: 3+4\n");
  1606. break;
  1607. case RME96_MONITOR_TRACKS_5_6:
  1608. snd_iprintf(buffer, " monitored ADAT tracks: 5+6\n");
  1609. break;
  1610. case RME96_MONITOR_TRACKS_7_8:
  1611. snd_iprintf(buffer, " monitored ADAT tracks: 7+8\n");
  1612. break;
  1613. }
  1614. switch (snd_rme96_getattenuation(rme96)) {
  1615. case RME96_ATTENUATION_0:
  1616. snd_iprintf(buffer, " attenuation: 0 dB\n");
  1617. break;
  1618. case RME96_ATTENUATION_6:
  1619. snd_iprintf(buffer, " attenuation: -6 dB\n");
  1620. break;
  1621. case RME96_ATTENUATION_12:
  1622. snd_iprintf(buffer, " attenuation: -12 dB\n");
  1623. break;
  1624. case RME96_ATTENUATION_18:
  1625. snd_iprintf(buffer, " attenuation: -18 dB\n");
  1626. break;
  1627. }
  1628. snd_iprintf(buffer, " volume left: %u\n", rme96->vol[0]);
  1629. snd_iprintf(buffer, " volume right: %u\n", rme96->vol[1]);
  1630. }
  1631. }
  1632. static void __devinit
  1633. snd_rme96_proc_init(struct rme96 *rme96)
  1634. {
  1635. struct snd_info_entry *entry;
  1636. if (! snd_card_proc_new(rme96->card, "rme96", &entry))
  1637. snd_info_set_text_ops(entry, rme96, snd_rme96_proc_read);
  1638. }
  1639. /*
  1640. * control interface
  1641. */
  1642. static int
  1643. snd_rme96_info_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1644. {
  1645. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1646. uinfo->count = 1;
  1647. uinfo->value.integer.min = 0;
  1648. uinfo->value.integer.max = 1;
  1649. return 0;
  1650. }
  1651. static int
  1652. snd_rme96_get_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1653. {
  1654. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1655. spin_lock_irq(&rme96->lock);
  1656. ucontrol->value.integer.value[0] = rme96->wcreg & RME96_WCR_SEL ? 0 : 1;
  1657. spin_unlock_irq(&rme96->lock);
  1658. return 0;
  1659. }
  1660. static int
  1661. snd_rme96_put_loopback_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1662. {
  1663. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1664. unsigned int val;
  1665. int change;
  1666. val = ucontrol->value.integer.value[0] ? 0 : RME96_WCR_SEL;
  1667. spin_lock_irq(&rme96->lock);
  1668. val = (rme96->wcreg & ~RME96_WCR_SEL) | val;
  1669. change = val != rme96->wcreg;
  1670. rme96->wcreg = val;
  1671. writel(val, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1672. spin_unlock_irq(&rme96->lock);
  1673. return change;
  1674. }
  1675. static int
  1676. snd_rme96_info_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1677. {
  1678. static char *_texts[5] = { "Optical", "Coaxial", "Internal", "XLR", "Analog" };
  1679. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1680. char *texts[5] = { _texts[0], _texts[1], _texts[2], _texts[3], _texts[4] };
  1681. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1682. uinfo->count = 1;
  1683. switch (rme96->pci->device) {
  1684. case PCI_DEVICE_ID_RME_DIGI96:
  1685. case PCI_DEVICE_ID_RME_DIGI96_8:
  1686. uinfo->value.enumerated.items = 3;
  1687. break;
  1688. case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
  1689. uinfo->value.enumerated.items = 4;
  1690. break;
  1691. case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
  1692. if (rme96->rev > 4) {
  1693. /* PST */
  1694. uinfo->value.enumerated.items = 4;
  1695. texts[3] = _texts[4]; /* Analog instead of XLR */
  1696. } else {
  1697. /* PAD */
  1698. uinfo->value.enumerated.items = 5;
  1699. }
  1700. break;
  1701. default:
  1702. snd_BUG();
  1703. break;
  1704. }
  1705. if (uinfo->value.enumerated.item > uinfo->value.enumerated.items - 1) {
  1706. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1707. }
  1708. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1709. return 0;
  1710. }
  1711. static int
  1712. snd_rme96_get_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1713. {
  1714. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1715. unsigned int items = 3;
  1716. spin_lock_irq(&rme96->lock);
  1717. ucontrol->value.enumerated.item[0] = snd_rme96_getinputtype(rme96);
  1718. switch (rme96->pci->device) {
  1719. case PCI_DEVICE_ID_RME_DIGI96:
  1720. case PCI_DEVICE_ID_RME_DIGI96_8:
  1721. items = 3;
  1722. break;
  1723. case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
  1724. items = 4;
  1725. break;
  1726. case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
  1727. if (rme96->rev > 4) {
  1728. /* for handling PST case, (INPUT_ANALOG is moved to INPUT_XLR */
  1729. if (ucontrol->value.enumerated.item[0] == RME96_INPUT_ANALOG) {
  1730. ucontrol->value.enumerated.item[0] = RME96_INPUT_XLR;
  1731. }
  1732. items = 4;
  1733. } else {
  1734. items = 5;
  1735. }
  1736. break;
  1737. default:
  1738. snd_BUG();
  1739. break;
  1740. }
  1741. if (ucontrol->value.enumerated.item[0] >= items) {
  1742. ucontrol->value.enumerated.item[0] = items - 1;
  1743. }
  1744. spin_unlock_irq(&rme96->lock);
  1745. return 0;
  1746. }
  1747. static int
  1748. snd_rme96_put_inputtype_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1749. {
  1750. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1751. unsigned int val;
  1752. int change, items = 3;
  1753. switch (rme96->pci->device) {
  1754. case PCI_DEVICE_ID_RME_DIGI96:
  1755. case PCI_DEVICE_ID_RME_DIGI96_8:
  1756. items = 3;
  1757. break;
  1758. case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
  1759. items = 4;
  1760. break;
  1761. case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
  1762. if (rme96->rev > 4) {
  1763. items = 4;
  1764. } else {
  1765. items = 5;
  1766. }
  1767. break;
  1768. default:
  1769. snd_BUG();
  1770. break;
  1771. }
  1772. val = ucontrol->value.enumerated.item[0] % items;
  1773. /* special case for PST */
  1774. if (rme96->pci->device == PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST && rme96->rev > 4) {
  1775. if (val == RME96_INPUT_XLR) {
  1776. val = RME96_INPUT_ANALOG;
  1777. }
  1778. }
  1779. spin_lock_irq(&rme96->lock);
  1780. change = (int)val != snd_rme96_getinputtype(rme96);
  1781. snd_rme96_setinputtype(rme96, val);
  1782. spin_unlock_irq(&rme96->lock);
  1783. return change;
  1784. }
  1785. static int
  1786. snd_rme96_info_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1787. {
  1788. static char *texts[3] = { "AutoSync", "Internal", "Word" };
  1789. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1790. uinfo->count = 1;
  1791. uinfo->value.enumerated.items = 3;
  1792. if (uinfo->value.enumerated.item > 2) {
  1793. uinfo->value.enumerated.item = 2;
  1794. }
  1795. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1796. return 0;
  1797. }
  1798. static int
  1799. snd_rme96_get_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1800. {
  1801. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1802. spin_lock_irq(&rme96->lock);
  1803. ucontrol->value.enumerated.item[0] = snd_rme96_getclockmode(rme96);
  1804. spin_unlock_irq(&rme96->lock);
  1805. return 0;
  1806. }
  1807. static int
  1808. snd_rme96_put_clockmode_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1809. {
  1810. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1811. unsigned int val;
  1812. int change;
  1813. val = ucontrol->value.enumerated.item[0] % 3;
  1814. spin_lock_irq(&rme96->lock);
  1815. change = (int)val != snd_rme96_getclockmode(rme96);
  1816. snd_rme96_setclockmode(rme96, val);
  1817. spin_unlock_irq(&rme96->lock);
  1818. return change;
  1819. }
  1820. static int
  1821. snd_rme96_info_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1822. {
  1823. static char *texts[4] = { "0 dB", "-6 dB", "-12 dB", "-18 dB" };
  1824. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1825. uinfo->count = 1;
  1826. uinfo->value.enumerated.items = 4;
  1827. if (uinfo->value.enumerated.item > 3) {
  1828. uinfo->value.enumerated.item = 3;
  1829. }
  1830. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1831. return 0;
  1832. }
  1833. static int
  1834. snd_rme96_get_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1835. {
  1836. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1837. spin_lock_irq(&rme96->lock);
  1838. ucontrol->value.enumerated.item[0] = snd_rme96_getattenuation(rme96);
  1839. spin_unlock_irq(&rme96->lock);
  1840. return 0;
  1841. }
  1842. static int
  1843. snd_rme96_put_attenuation_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1844. {
  1845. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1846. unsigned int val;
  1847. int change;
  1848. val = ucontrol->value.enumerated.item[0] % 4;
  1849. spin_lock_irq(&rme96->lock);
  1850. change = (int)val != snd_rme96_getattenuation(rme96);
  1851. snd_rme96_setattenuation(rme96, val);
  1852. spin_unlock_irq(&rme96->lock);
  1853. return change;
  1854. }
  1855. static int
  1856. snd_rme96_info_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1857. {
  1858. static char *texts[4] = { "1+2", "3+4", "5+6", "7+8" };
  1859. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1860. uinfo->count = 1;
  1861. uinfo->value.enumerated.items = 4;
  1862. if (uinfo->value.enumerated.item > 3) {
  1863. uinfo->value.enumerated.item = 3;
  1864. }
  1865. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1866. return 0;
  1867. }
  1868. static int
  1869. snd_rme96_get_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1870. {
  1871. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1872. spin_lock_irq(&rme96->lock);
  1873. ucontrol->value.enumerated.item[0] = snd_rme96_getmontracks(rme96);
  1874. spin_unlock_irq(&rme96->lock);
  1875. return 0;
  1876. }
  1877. static int
  1878. snd_rme96_put_montracks_control(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1879. {
  1880. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1881. unsigned int val;
  1882. int change;
  1883. val = ucontrol->value.enumerated.item[0] % 4;
  1884. spin_lock_irq(&rme96->lock);
  1885. change = (int)val != snd_rme96_getmontracks(rme96);
  1886. snd_rme96_setmontracks(rme96, val);
  1887. spin_unlock_irq(&rme96->lock);
  1888. return change;
  1889. }
  1890. static u32 snd_rme96_convert_from_aes(struct snd_aes_iec958 *aes)
  1891. {
  1892. u32 val = 0;
  1893. val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME96_WCR_PRO : 0;
  1894. val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? RME96_WCR_DOLBY : 0;
  1895. if (val & RME96_WCR_PRO)
  1896. val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
  1897. else
  1898. val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME96_WCR_EMP : 0;
  1899. return val;
  1900. }
  1901. static void snd_rme96_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
  1902. {
  1903. aes->status[0] = ((val & RME96_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0) |
  1904. ((val & RME96_WCR_DOLBY) ? IEC958_AES0_NONAUDIO : 0);
  1905. if (val & RME96_WCR_PRO)
  1906. aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
  1907. else
  1908. aes->status[0] |= (val & RME96_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
  1909. }
  1910. static int snd_rme96_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1911. {
  1912. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1913. uinfo->count = 1;
  1914. return 0;
  1915. }
  1916. static int snd_rme96_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1917. {
  1918. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1919. snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif);
  1920. return 0;
  1921. }
  1922. static int snd_rme96_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1923. {
  1924. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1925. int change;
  1926. u32 val;
  1927. val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
  1928. spin_lock_irq(&rme96->lock);
  1929. change = val != rme96->wcreg_spdif;
  1930. rme96->wcreg_spdif = val;
  1931. spin_unlock_irq(&rme96->lock);
  1932. return change;
  1933. }
  1934. static int snd_rme96_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1935. {
  1936. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1937. uinfo->count = 1;
  1938. return 0;
  1939. }
  1940. static int snd_rme96_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1941. {
  1942. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1943. snd_rme96_convert_to_aes(&ucontrol->value.iec958, rme96->wcreg_spdif_stream);
  1944. return 0;
  1945. }
  1946. static int snd_rme96_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1947. {
  1948. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1949. int change;
  1950. u32 val;
  1951. val = snd_rme96_convert_from_aes(&ucontrol->value.iec958);
  1952. spin_lock_irq(&rme96->lock);
  1953. change = val != rme96->wcreg_spdif_stream;
  1954. rme96->wcreg_spdif_stream = val;
  1955. rme96->wcreg &= ~(RME96_WCR_PRO | RME96_WCR_DOLBY | RME96_WCR_EMP);
  1956. rme96->wcreg |= val;
  1957. writel(rme96->wcreg, rme96->iobase + RME96_IO_CONTROL_REGISTER);
  1958. spin_unlock_irq(&rme96->lock);
  1959. return change;
  1960. }
  1961. static int snd_rme96_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1962. {
  1963. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1964. uinfo->count = 1;
  1965. return 0;
  1966. }
  1967. static int snd_rme96_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1968. {
  1969. ucontrol->value.iec958.status[0] = kcontrol->private_value;
  1970. return 0;
  1971. }
  1972. static int
  1973. snd_rme96_dac_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1974. {
  1975. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1976. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1977. uinfo->count = 2;
  1978. uinfo->value.integer.min = 0;
  1979. uinfo->value.integer.max = RME96_185X_MAX_OUT(rme96);
  1980. return 0;
  1981. }
  1982. static int
  1983. snd_rme96_dac_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
  1984. {
  1985. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1986. spin_lock_irq(&rme96->lock);
  1987. u->value.integer.value[0] = rme96->vol[0];
  1988. u->value.integer.value[1] = rme96->vol[1];
  1989. spin_unlock_irq(&rme96->lock);
  1990. return 0;
  1991. }
  1992. static int
  1993. snd_rme96_dac_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *u)
  1994. {
  1995. struct rme96 *rme96 = snd_kcontrol_chip(kcontrol);
  1996. int change = 0;
  1997. if (!RME96_HAS_ANALOG_OUT(rme96)) {
  1998. return -EINVAL;
  1999. }
  2000. spin_lock_irq(&rme96->lock);
  2001. if (u->value.integer.value[0] != rme96->vol[0]) {
  2002. rme96->vol[0] = u->value.integer.value[0];
  2003. change = 1;
  2004. }
  2005. if (u->value.integer.value[1] != rme96->vol[1]) {
  2006. rme96->vol[1] = u->value.integer.value[1];
  2007. change = 1;
  2008. }
  2009. if (change) {
  2010. snd_rme96_apply_dac_volume(rme96);
  2011. }
  2012. spin_unlock_irq(&rme96->lock);
  2013. return change;
  2014. }
  2015. static struct snd_kcontrol_new snd_rme96_controls[] = {
  2016. {
  2017. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2018. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  2019. .info = snd_rme96_control_spdif_info,
  2020. .get = snd_rme96_control_spdif_get,
  2021. .put = snd_rme96_control_spdif_put
  2022. },
  2023. {
  2024. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  2025. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2026. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  2027. .info = snd_rme96_control_spdif_stream_info,
  2028. .get = snd_rme96_control_spdif_stream_get,
  2029. .put = snd_rme96_control_spdif_stream_put
  2030. },
  2031. {
  2032. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  2033. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2034. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  2035. .info = snd_rme96_control_spdif_mask_info,
  2036. .get = snd_rme96_control_spdif_mask_get,
  2037. .private_value = IEC958_AES0_NONAUDIO |
  2038. IEC958_AES0_PROFESSIONAL |
  2039. IEC958_AES0_CON_EMPHASIS
  2040. },
  2041. {
  2042. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  2043. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  2044. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
  2045. .info = snd_rme96_control_spdif_mask_info,
  2046. .get = snd_rme96_control_spdif_mask_get,
  2047. .private_value = IEC958_AES0_NONAUDIO |
  2048. IEC958_AES0_PROFESSIONAL |
  2049. IEC958_AES0_PRO_EMPHASIS
  2050. },
  2051. {
  2052. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2053. .name = "Input Connector",
  2054. .info = snd_rme96_info_inputtype_control,
  2055. .get = snd_rme96_get_inputtype_control,
  2056. .put = snd_rme96_put_inputtype_control
  2057. },
  2058. {
  2059. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2060. .name = "Loopback Input",
  2061. .info = snd_rme96_info_loopback_control,
  2062. .get = snd_rme96_get_loopback_control,
  2063. .put = snd_rme96_put_loopback_control
  2064. },
  2065. {
  2066. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2067. .name = "Sample Clock Source",
  2068. .info = snd_rme96_info_clockmode_control,
  2069. .get = snd_rme96_get_clockmode_control,
  2070. .put = snd_rme96_put_clockmode_control
  2071. },
  2072. {
  2073. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2074. .name = "Monitor Tracks",
  2075. .info = snd_rme96_info_montracks_control,
  2076. .get = snd_rme96_get_montracks_control,
  2077. .put = snd_rme96_put_montracks_control
  2078. },
  2079. {
  2080. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2081. .name = "Attenuation",
  2082. .info = snd_rme96_info_attenuation_control,
  2083. .get = snd_rme96_get_attenuation_control,
  2084. .put = snd_rme96_put_attenuation_control
  2085. },
  2086. {
  2087. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2088. .name = "DAC Playback Volume",
  2089. .info = snd_rme96_dac_volume_info,
  2090. .get = snd_rme96_dac_volume_get,
  2091. .put = snd_rme96_dac_volume_put
  2092. }
  2093. };
  2094. static int
  2095. snd_rme96_create_switches(struct snd_card *card,
  2096. struct rme96 *rme96)
  2097. {
  2098. int idx, err;
  2099. struct snd_kcontrol *kctl;
  2100. for (idx = 0; idx < 7; idx++) {
  2101. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
  2102. return err;
  2103. if (idx == 1) /* IEC958 (S/PDIF) Stream */
  2104. rme96->spdif_ctl = kctl;
  2105. }
  2106. if (RME96_HAS_ANALOG_OUT(rme96)) {
  2107. for (idx = 7; idx < 10; idx++)
  2108. if ((err = snd_ctl_add(card, snd_ctl_new1(&snd_rme96_controls[idx], rme96))) < 0)
  2109. return err;
  2110. }
  2111. return 0;
  2112. }
  2113. /*
  2114. * Card initialisation
  2115. */
  2116. static void snd_rme96_card_free(struct snd_card *card)
  2117. {
  2118. snd_rme96_free(card->private_data);
  2119. }
  2120. static int __devinit
  2121. snd_rme96_probe(struct pci_dev *pci,
  2122. const struct pci_device_id *pci_id)
  2123. {
  2124. static int dev;
  2125. struct rme96 *rme96;
  2126. struct snd_card *card;
  2127. int err;
  2128. u8 val;
  2129. if (dev >= SNDRV_CARDS) {
  2130. return -ENODEV;
  2131. }
  2132. if (!enable[dev]) {
  2133. dev++;
  2134. return -ENOENT;
  2135. }
  2136. if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
  2137. sizeof(struct rme96))) == NULL)
  2138. return -ENOMEM;
  2139. card->private_free = snd_rme96_card_free;
  2140. rme96 = (struct rme96 *)card->private_data;
  2141. rme96->card = card;
  2142. rme96->pci = pci;
  2143. snd_card_set_dev(card, &pci->dev);
  2144. if ((err = snd_rme96_create(rme96)) < 0) {
  2145. snd_card_free(card);
  2146. return err;
  2147. }
  2148. strcpy(card->driver, "Digi96");
  2149. switch (rme96->pci->device) {
  2150. case PCI_DEVICE_ID_RME_DIGI96:
  2151. strcpy(card->shortname, "RME Digi96");
  2152. break;
  2153. case PCI_DEVICE_ID_RME_DIGI96_8:
  2154. strcpy(card->shortname, "RME Digi96/8");
  2155. break;
  2156. case PCI_DEVICE_ID_RME_DIGI96_8_PRO:
  2157. strcpy(card->shortname, "RME Digi96/8 PRO");
  2158. break;
  2159. case PCI_DEVICE_ID_RME_DIGI96_8_PAD_OR_PST:
  2160. pci_read_config_byte(rme96->pci, 8, &val);
  2161. if (val < 5) {
  2162. strcpy(card->shortname, "RME Digi96/8 PAD");
  2163. } else {
  2164. strcpy(card->shortname, "RME Digi96/8 PST");
  2165. }
  2166. break;
  2167. }
  2168. sprintf(card->longname, "%s at 0x%lx, irq %d", card->shortname,
  2169. rme96->port, rme96->irq);
  2170. if ((err = snd_card_register(card)) < 0) {
  2171. snd_card_free(card);
  2172. return err;
  2173. }
  2174. pci_set_drvdata(pci, card);
  2175. dev++;
  2176. return 0;
  2177. }
  2178. static void __devexit snd_rme96_remove(struct pci_dev *pci)
  2179. {
  2180. snd_card_free(pci_get_drvdata(pci));
  2181. pci_set_drvdata(pci, NULL);
  2182. }
  2183. static struct pci_driver driver = {
  2184. .name = "RME Digi96",
  2185. .id_table = snd_rme96_ids,
  2186. .probe = snd_rme96_probe,
  2187. .remove = __devexit_p(snd_rme96_remove),
  2188. };
  2189. static int __init alsa_card_rme96_init(void)
  2190. {
  2191. return pci_register_driver(&driver);
  2192. }
  2193. static void __exit alsa_card_rme96_exit(void)
  2194. {
  2195. pci_unregister_driver(&driver);
  2196. }
  2197. module_init(alsa_card_rme96_init)
  2198. module_exit(alsa_card_rme96_exit)