rme32.c 58 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985986987988989990991992993994995996997998999100010011002100310041005100610071008100910101011101210131014101510161017101810191020102110221023102410251026102710281029103010311032103310341035103610371038103910401041104210431044104510461047104810491050105110521053105410551056105710581059106010611062106310641065106610671068106910701071107210731074107510761077107810791080108110821083108410851086108710881089109010911092109310941095109610971098109911001101110211031104110511061107110811091110111111121113111411151116111711181119112011211122112311241125112611271128112911301131113211331134113511361137113811391140114111421143114411451146114711481149115011511152115311541155115611571158115911601161116211631164116511661167116811691170117111721173117411751176117711781179118011811182118311841185118611871188118911901191119211931194119511961197119811991200120112021203120412051206120712081209121012111212121312141215121612171218121912201221122212231224122512261227122812291230123112321233123412351236123712381239124012411242124312441245124612471248124912501251125212531254125512561257125812591260126112621263126412651266126712681269127012711272127312741275127612771278127912801281128212831284128512861287128812891290129112921293129412951296129712981299130013011302130313041305130613071308130913101311131213131314131513161317131813191320132113221323132413251326132713281329133013311332133313341335133613371338133913401341134213431344134513461347134813491350135113521353135413551356135713581359136013611362136313641365136613671368136913701371137213731374137513761377137813791380138113821383138413851386138713881389139013911392139313941395139613971398139914001401140214031404140514061407140814091410141114121413141414151416141714181419142014211422142314241425142614271428142914301431143214331434143514361437143814391440144114421443144414451446144714481449145014511452145314541455145614571458145914601461146214631464146514661467146814691470147114721473147414751476147714781479148014811482148314841485148614871488148914901491149214931494149514961497149814991500150115021503150415051506150715081509151015111512151315141515151615171518151915201521152215231524152515261527152815291530153115321533153415351536153715381539154015411542154315441545154615471548154915501551155215531554155515561557155815591560156115621563156415651566156715681569157015711572157315741575157615771578157915801581158215831584158515861587158815891590159115921593159415951596159715981599160016011602160316041605160616071608160916101611161216131614161516161617161816191620162116221623162416251626162716281629163016311632163316341635163616371638163916401641164216431644164516461647164816491650165116521653165416551656165716581659166016611662166316641665166616671668166916701671167216731674167516761677167816791680168116821683168416851686168716881689169016911692169316941695169616971698169917001701170217031704170517061707170817091710171117121713171417151716171717181719172017211722172317241725172617271728172917301731173217331734173517361737173817391740174117421743174417451746174717481749175017511752175317541755175617571758175917601761176217631764176517661767176817691770177117721773177417751776177717781779178017811782178317841785178617871788178917901791179217931794179517961797179817991800180118021803180418051806180718081809181018111812181318141815181618171818181918201821182218231824182518261827182818291830183118321833183418351836183718381839184018411842184318441845184618471848184918501851185218531854185518561857185818591860186118621863186418651866186718681869187018711872187318741875187618771878187918801881188218831884188518861887188818891890189118921893189418951896189718981899190019011902190319041905190619071908190919101911191219131914191519161917191819191920192119221923192419251926192719281929193019311932193319341935193619371938193919401941194219431944194519461947194819491950195119521953195419551956195719581959196019611962196319641965196619671968196919701971197219731974197519761977197819791980198119821983198419851986198719881989199019911992199319941995199619971998199920002001200220032004200520062007200820092010201120122013201420152016201720182019202020212022202320242025202620272028202920302031
  1. /*
  2. * ALSA driver for RME Digi32, Digi32/8 and Digi32 PRO audio interfaces
  3. *
  4. * Copyright (c) 2002-2004 Martin Langer <martin-langer@gmx.de>,
  5. * Pilo Chambert <pilo.c@wanadoo.fr>
  6. *
  7. * Thanks to : Anders Torger <torger@ludd.luth.se>,
  8. * Henk Hesselink <henk@anda.nl>
  9. * for writing the digi96-driver
  10. * and RME for all informations.
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  25. *
  26. *
  27. * ****************************************************************************
  28. *
  29. * Note #1 "Sek'd models" ................................... martin 2002-12-07
  30. *
  31. * Identical soundcards by Sek'd were labeled:
  32. * RME Digi 32 = Sek'd Prodif 32
  33. * RME Digi 32 Pro = Sek'd Prodif 96
  34. * RME Digi 32/8 = Sek'd Prodif Gold
  35. *
  36. * ****************************************************************************
  37. *
  38. * Note #2 "full duplex mode" ............................... martin 2002-12-07
  39. *
  40. * Full duplex doesn't work. All cards (32, 32/8, 32Pro) are working identical
  41. * in this mode. Rec data and play data are using the same buffer therefore. At
  42. * first you have got the playing bits in the buffer and then (after playing
  43. * them) they were overwitten by the captured sound of the CS8412/14. Both
  44. * modes (play/record) are running harmonically hand in hand in the same buffer
  45. * and you have only one start bit plus one interrupt bit to control this
  46. * paired action.
  47. * This is opposite to the latter rme96 where playing and capturing is totally
  48. * separated and so their full duplex mode is supported by alsa (using two
  49. * start bits and two interrupts for two different buffers).
  50. * But due to the wrong sequence of playing and capturing ALSA shows no solved
  51. * full duplex support for the rme32 at the moment. That's bad, but I'm not
  52. * able to solve it. Are you motivated enough to solve this problem now? Your
  53. * patch would be welcome!
  54. *
  55. * ****************************************************************************
  56. *
  57. * "The story after the long seeking" -- tiwai
  58. *
  59. * Ok, the situation regarding the full duplex is now improved a bit.
  60. * In the fullduplex mode (given by the module parameter), the hardware buffer
  61. * is split to halves for read and write directions at the DMA pointer.
  62. * That is, the half above the current DMA pointer is used for write, and
  63. * the half below is used for read. To mangle this strange behavior, an
  64. * software intermediate buffer is introduced. This is, of course, not good
  65. * from the viewpoint of the data transfer efficiency. However, this allows
  66. * you to use arbitrary buffer sizes, instead of the fixed I/O buffer size.
  67. *
  68. * ****************************************************************************
  69. */
  70. #include <sound/driver.h>
  71. #include <linux/delay.h>
  72. #include <linux/init.h>
  73. #include <linux/interrupt.h>
  74. #include <linux/pci.h>
  75. #include <linux/slab.h>
  76. #include <linux/moduleparam.h>
  77. #include <sound/core.h>
  78. #include <sound/info.h>
  79. #include <sound/control.h>
  80. #include <sound/pcm.h>
  81. #include <sound/pcm_params.h>
  82. #include <sound/pcm-indirect.h>
  83. #include <sound/asoundef.h>
  84. #include <sound/initval.h>
  85. #include <asm/io.h>
  86. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  87. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  88. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  89. static int fullduplex[SNDRV_CARDS]; // = {[0 ... (SNDRV_CARDS - 1)] = 1};
  90. module_param_array(index, int, NULL, 0444);
  91. MODULE_PARM_DESC(index, "Index value for RME Digi32 soundcard.");
  92. module_param_array(id, charp, NULL, 0444);
  93. MODULE_PARM_DESC(id, "ID string for RME Digi32 soundcard.");
  94. module_param_array(enable, bool, NULL, 0444);
  95. MODULE_PARM_DESC(enable, "Enable RME Digi32 soundcard.");
  96. module_param_array(fullduplex, bool, NULL, 0444);
  97. MODULE_PARM_DESC(fullduplex, "Support full-duplex mode.");
  98. MODULE_AUTHOR("Martin Langer <martin-langer@gmx.de>, Pilo Chambert <pilo.c@wanadoo.fr>");
  99. MODULE_DESCRIPTION("RME Digi32, Digi32/8, Digi32 PRO");
  100. MODULE_LICENSE("GPL");
  101. MODULE_SUPPORTED_DEVICE("{{RME,Digi32}," "{RME,Digi32/8}," "{RME,Digi32 PRO}}");
  102. /* Defines for RME Digi32 series */
  103. #define RME32_SPDIF_NCHANNELS 2
  104. /* Playback and capture buffer size */
  105. #define RME32_BUFFER_SIZE 0x20000
  106. /* IO area size */
  107. #define RME32_IO_SIZE 0x30000
  108. /* IO area offsets */
  109. #define RME32_IO_DATA_BUFFER 0x0
  110. #define RME32_IO_CONTROL_REGISTER 0x20000
  111. #define RME32_IO_GET_POS 0x20000
  112. #define RME32_IO_CONFIRM_ACTION_IRQ 0x20004
  113. #define RME32_IO_RESET_POS 0x20100
  114. /* Write control register bits */
  115. #define RME32_WCR_START (1 << 0) /* startbit */
  116. #define RME32_WCR_MONO (1 << 1) /* 0=stereo, 1=mono
  117. Setting the whole card to mono
  118. doesn't seem to be very useful.
  119. A software-solution can handle
  120. full-duplex with one direction in
  121. stereo and the other way in mono.
  122. So, the hardware should work all
  123. the time in stereo! */
  124. #define RME32_WCR_MODE24 (1 << 2) /* 0=16bit, 1=32bit */
  125. #define RME32_WCR_SEL (1 << 3) /* 0=input on output, 1=normal playback/capture */
  126. #define RME32_WCR_FREQ_0 (1 << 4) /* frequency (play) */
  127. #define RME32_WCR_FREQ_1 (1 << 5)
  128. #define RME32_WCR_INP_0 (1 << 6) /* input switch */
  129. #define RME32_WCR_INP_1 (1 << 7)
  130. #define RME32_WCR_RESET (1 << 8) /* Reset address */
  131. #define RME32_WCR_MUTE (1 << 9) /* digital mute for output */
  132. #define RME32_WCR_PRO (1 << 10) /* 1=professional, 0=consumer */
  133. #define RME32_WCR_DS_BM (1 << 11) /* 1=DoubleSpeed (only PRO-Version); 1=BlockMode (only Adat-Version) */
  134. #define RME32_WCR_ADAT (1 << 12) /* Adat Mode (only Adat-Version) */
  135. #define RME32_WCR_AUTOSYNC (1 << 13) /* AutoSync */
  136. #define RME32_WCR_PD (1 << 14) /* DAC Reset (only PRO-Version) */
  137. #define RME32_WCR_EMP (1 << 15) /* 1=Emphasis on (only PRO-Version) */
  138. #define RME32_WCR_BITPOS_FREQ_0 4
  139. #define RME32_WCR_BITPOS_FREQ_1 5
  140. #define RME32_WCR_BITPOS_INP_0 6
  141. #define RME32_WCR_BITPOS_INP_1 7
  142. /* Read control register bits */
  143. #define RME32_RCR_AUDIO_ADDR_MASK 0x1ffff
  144. #define RME32_RCR_LOCK (1 << 23) /* 1=locked, 0=not locked */
  145. #define RME32_RCR_ERF (1 << 26) /* 1=Error, 0=no Error */
  146. #define RME32_RCR_FREQ_0 (1 << 27) /* CS841x frequency (record) */
  147. #define RME32_RCR_FREQ_1 (1 << 28)
  148. #define RME32_RCR_FREQ_2 (1 << 29)
  149. #define RME32_RCR_KMODE (1 << 30) /* card mode: 1=PLL, 0=quartz */
  150. #define RME32_RCR_IRQ (1 << 31) /* interrupt */
  151. #define RME32_RCR_BITPOS_F0 27
  152. #define RME32_RCR_BITPOS_F1 28
  153. #define RME32_RCR_BITPOS_F2 29
  154. /* Input types */
  155. #define RME32_INPUT_OPTICAL 0
  156. #define RME32_INPUT_COAXIAL 1
  157. #define RME32_INPUT_INTERNAL 2
  158. #define RME32_INPUT_XLR 3
  159. /* Clock modes */
  160. #define RME32_CLOCKMODE_SLAVE 0
  161. #define RME32_CLOCKMODE_MASTER_32 1
  162. #define RME32_CLOCKMODE_MASTER_44 2
  163. #define RME32_CLOCKMODE_MASTER_48 3
  164. /* Block sizes in bytes */
  165. #define RME32_BLOCK_SIZE 8192
  166. /* Software intermediate buffer (max) size */
  167. #define RME32_MID_BUFFER_SIZE (1024*1024)
  168. /* Hardware revisions */
  169. #define RME32_32_REVISION 192
  170. #define RME32_328_REVISION_OLD 100
  171. #define RME32_328_REVISION_NEW 101
  172. #define RME32_PRO_REVISION_WITH_8412 192
  173. #define RME32_PRO_REVISION_WITH_8414 150
  174. struct rme32 {
  175. spinlock_t lock;
  176. int irq;
  177. unsigned long port;
  178. void __iomem *iobase;
  179. u32 wcreg; /* cached write control register value */
  180. u32 wcreg_spdif; /* S/PDIF setup */
  181. u32 wcreg_spdif_stream; /* S/PDIF setup (temporary) */
  182. u32 rcreg; /* cached read control register value */
  183. u8 rev; /* card revision number */
  184. struct snd_pcm_substream *playback_substream;
  185. struct snd_pcm_substream *capture_substream;
  186. int playback_frlog; /* log2 of framesize */
  187. int capture_frlog;
  188. size_t playback_periodsize; /* in bytes, zero if not used */
  189. size_t capture_periodsize; /* in bytes, zero if not used */
  190. unsigned int fullduplex_mode;
  191. int running;
  192. struct snd_pcm_indirect playback_pcm;
  193. struct snd_pcm_indirect capture_pcm;
  194. struct snd_card *card;
  195. struct snd_pcm *spdif_pcm;
  196. struct snd_pcm *adat_pcm;
  197. struct pci_dev *pci;
  198. struct snd_kcontrol *spdif_ctl;
  199. };
  200. static struct pci_device_id snd_rme32_ids[] = {
  201. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32,
  202. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  203. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_8,
  204. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  205. {PCI_VENDOR_ID_XILINX_RME, PCI_DEVICE_ID_RME_DIGI32_PRO,
  206. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0,},
  207. {0,}
  208. };
  209. MODULE_DEVICE_TABLE(pci, snd_rme32_ids);
  210. #define RME32_ISWORKING(rme32) ((rme32)->wcreg & RME32_WCR_START)
  211. #define RME32_PRO_WITH_8414(rme32) ((rme32)->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO && (rme32)->rev == RME32_PRO_REVISION_WITH_8414)
  212. static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream);
  213. static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream);
  214. static int snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
  215. static void snd_rme32_proc_init(struct rme32 * rme32);
  216. static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32);
  217. static inline unsigned int snd_rme32_pcm_byteptr(struct rme32 * rme32)
  218. {
  219. return (readl(rme32->iobase + RME32_IO_GET_POS)
  220. & RME32_RCR_AUDIO_ADDR_MASK);
  221. }
  222. static int snd_rme32_ratecode(int rate)
  223. {
  224. switch (rate) {
  225. case 32000: return SNDRV_PCM_RATE_32000;
  226. case 44100: return SNDRV_PCM_RATE_44100;
  227. case 48000: return SNDRV_PCM_RATE_48000;
  228. case 64000: return SNDRV_PCM_RATE_64000;
  229. case 88200: return SNDRV_PCM_RATE_88200;
  230. case 96000: return SNDRV_PCM_RATE_96000;
  231. }
  232. return 0;
  233. }
  234. /* silence callback for halfduplex mode */
  235. static int snd_rme32_playback_silence(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
  236. snd_pcm_uframes_t pos,
  237. snd_pcm_uframes_t count)
  238. {
  239. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  240. count <<= rme32->playback_frlog;
  241. pos <<= rme32->playback_frlog;
  242. memset_io(rme32->iobase + RME32_IO_DATA_BUFFER + pos, 0, count);
  243. return 0;
  244. }
  245. /* copy callback for halfduplex mode */
  246. static int snd_rme32_playback_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
  247. snd_pcm_uframes_t pos,
  248. void __user *src, snd_pcm_uframes_t count)
  249. {
  250. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  251. count <<= rme32->playback_frlog;
  252. pos <<= rme32->playback_frlog;
  253. if (copy_from_user_toio(rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  254. src, count))
  255. return -EFAULT;
  256. return 0;
  257. }
  258. /* copy callback for halfduplex mode */
  259. static int snd_rme32_capture_copy(struct snd_pcm_substream *substream, int channel, /* not used (interleaved data) */
  260. snd_pcm_uframes_t pos,
  261. void __user *dst, snd_pcm_uframes_t count)
  262. {
  263. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  264. count <<= rme32->capture_frlog;
  265. pos <<= rme32->capture_frlog;
  266. if (copy_to_user_fromio(dst,
  267. rme32->iobase + RME32_IO_DATA_BUFFER + pos,
  268. count))
  269. return -EFAULT;
  270. return 0;
  271. }
  272. /*
  273. * SPDIF I/O capabilities (half-duplex mode)
  274. */
  275. static struct snd_pcm_hardware snd_rme32_spdif_info = {
  276. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  277. SNDRV_PCM_INFO_MMAP_VALID |
  278. SNDRV_PCM_INFO_INTERLEAVED |
  279. SNDRV_PCM_INFO_PAUSE |
  280. SNDRV_PCM_INFO_SYNC_START),
  281. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  282. SNDRV_PCM_FMTBIT_S32_LE),
  283. .rates = (SNDRV_PCM_RATE_32000 |
  284. SNDRV_PCM_RATE_44100 |
  285. SNDRV_PCM_RATE_48000),
  286. .rate_min = 32000,
  287. .rate_max = 48000,
  288. .channels_min = 2,
  289. .channels_max = 2,
  290. .buffer_bytes_max = RME32_BUFFER_SIZE,
  291. .period_bytes_min = RME32_BLOCK_SIZE,
  292. .period_bytes_max = RME32_BLOCK_SIZE,
  293. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  294. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  295. .fifo_size = 0,
  296. };
  297. /*
  298. * ADAT I/O capabilities (half-duplex mode)
  299. */
  300. static struct snd_pcm_hardware snd_rme32_adat_info =
  301. {
  302. .info = (SNDRV_PCM_INFO_MMAP_IOMEM |
  303. SNDRV_PCM_INFO_MMAP_VALID |
  304. SNDRV_PCM_INFO_INTERLEAVED |
  305. SNDRV_PCM_INFO_PAUSE |
  306. SNDRV_PCM_INFO_SYNC_START),
  307. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  308. .rates = (SNDRV_PCM_RATE_44100 |
  309. SNDRV_PCM_RATE_48000),
  310. .rate_min = 44100,
  311. .rate_max = 48000,
  312. .channels_min = 8,
  313. .channels_max = 8,
  314. .buffer_bytes_max = RME32_BUFFER_SIZE,
  315. .period_bytes_min = RME32_BLOCK_SIZE,
  316. .period_bytes_max = RME32_BLOCK_SIZE,
  317. .periods_min = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  318. .periods_max = RME32_BUFFER_SIZE / RME32_BLOCK_SIZE,
  319. .fifo_size = 0,
  320. };
  321. /*
  322. * SPDIF I/O capabilities (full-duplex mode)
  323. */
  324. static struct snd_pcm_hardware snd_rme32_spdif_fd_info = {
  325. .info = (SNDRV_PCM_INFO_MMAP |
  326. SNDRV_PCM_INFO_MMAP_VALID |
  327. SNDRV_PCM_INFO_INTERLEAVED |
  328. SNDRV_PCM_INFO_PAUSE |
  329. SNDRV_PCM_INFO_SYNC_START),
  330. .formats = (SNDRV_PCM_FMTBIT_S16_LE |
  331. SNDRV_PCM_FMTBIT_S32_LE),
  332. .rates = (SNDRV_PCM_RATE_32000 |
  333. SNDRV_PCM_RATE_44100 |
  334. SNDRV_PCM_RATE_48000),
  335. .rate_min = 32000,
  336. .rate_max = 48000,
  337. .channels_min = 2,
  338. .channels_max = 2,
  339. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  340. .period_bytes_min = RME32_BLOCK_SIZE,
  341. .period_bytes_max = RME32_BLOCK_SIZE,
  342. .periods_min = 2,
  343. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  344. .fifo_size = 0,
  345. };
  346. /*
  347. * ADAT I/O capabilities (full-duplex mode)
  348. */
  349. static struct snd_pcm_hardware snd_rme32_adat_fd_info =
  350. {
  351. .info = (SNDRV_PCM_INFO_MMAP |
  352. SNDRV_PCM_INFO_MMAP_VALID |
  353. SNDRV_PCM_INFO_INTERLEAVED |
  354. SNDRV_PCM_INFO_PAUSE |
  355. SNDRV_PCM_INFO_SYNC_START),
  356. .formats= SNDRV_PCM_FMTBIT_S16_LE,
  357. .rates = (SNDRV_PCM_RATE_44100 |
  358. SNDRV_PCM_RATE_48000),
  359. .rate_min = 44100,
  360. .rate_max = 48000,
  361. .channels_min = 8,
  362. .channels_max = 8,
  363. .buffer_bytes_max = RME32_MID_BUFFER_SIZE,
  364. .period_bytes_min = RME32_BLOCK_SIZE,
  365. .period_bytes_max = RME32_BLOCK_SIZE,
  366. .periods_min = 2,
  367. .periods_max = RME32_MID_BUFFER_SIZE / RME32_BLOCK_SIZE,
  368. .fifo_size = 0,
  369. };
  370. static void snd_rme32_reset_dac(struct rme32 *rme32)
  371. {
  372. writel(rme32->wcreg | RME32_WCR_PD,
  373. rme32->iobase + RME32_IO_CONTROL_REGISTER);
  374. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  375. }
  376. static int snd_rme32_playback_getrate(struct rme32 * rme32)
  377. {
  378. int rate;
  379. rate = ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  380. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  381. switch (rate) {
  382. case 1:
  383. rate = 32000;
  384. break;
  385. case 2:
  386. rate = 44100;
  387. break;
  388. case 3:
  389. rate = 48000;
  390. break;
  391. default:
  392. return -1;
  393. }
  394. return (rme32->wcreg & RME32_WCR_DS_BM) ? rate << 1 : rate;
  395. }
  396. static int snd_rme32_capture_getrate(struct rme32 * rme32, int *is_adat)
  397. {
  398. int n;
  399. *is_adat = 0;
  400. if (rme32->rcreg & RME32_RCR_LOCK) {
  401. /* ADAT rate */
  402. *is_adat = 1;
  403. }
  404. if (rme32->rcreg & RME32_RCR_ERF) {
  405. return -1;
  406. }
  407. /* S/PDIF rate */
  408. n = ((rme32->rcreg >> RME32_RCR_BITPOS_F0) & 1) +
  409. (((rme32->rcreg >> RME32_RCR_BITPOS_F1) & 1) << 1) +
  410. (((rme32->rcreg >> RME32_RCR_BITPOS_F2) & 1) << 2);
  411. if (RME32_PRO_WITH_8414(rme32))
  412. switch (n) { /* supporting the CS8414 */
  413. case 0:
  414. case 1:
  415. case 2:
  416. return -1;
  417. case 3:
  418. return 96000;
  419. case 4:
  420. return 88200;
  421. case 5:
  422. return 48000;
  423. case 6:
  424. return 44100;
  425. case 7:
  426. return 32000;
  427. default:
  428. return -1;
  429. break;
  430. }
  431. else
  432. switch (n) { /* supporting the CS8412 */
  433. case 0:
  434. return -1;
  435. case 1:
  436. return 48000;
  437. case 2:
  438. return 44100;
  439. case 3:
  440. return 32000;
  441. case 4:
  442. return 48000;
  443. case 5:
  444. return 44100;
  445. case 6:
  446. return 44056;
  447. case 7:
  448. return 32000;
  449. default:
  450. break;
  451. }
  452. return -1;
  453. }
  454. static int snd_rme32_playback_setrate(struct rme32 * rme32, int rate)
  455. {
  456. int ds;
  457. ds = rme32->wcreg & RME32_WCR_DS_BM;
  458. switch (rate) {
  459. case 32000:
  460. rme32->wcreg &= ~RME32_WCR_DS_BM;
  461. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  462. ~RME32_WCR_FREQ_1;
  463. break;
  464. case 44100:
  465. rme32->wcreg &= ~RME32_WCR_DS_BM;
  466. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  467. ~RME32_WCR_FREQ_0;
  468. break;
  469. case 48000:
  470. rme32->wcreg &= ~RME32_WCR_DS_BM;
  471. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  472. RME32_WCR_FREQ_1;
  473. break;
  474. case 64000:
  475. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  476. return -EINVAL;
  477. rme32->wcreg |= RME32_WCR_DS_BM;
  478. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  479. ~RME32_WCR_FREQ_1;
  480. break;
  481. case 88200:
  482. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  483. return -EINVAL;
  484. rme32->wcreg |= RME32_WCR_DS_BM;
  485. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_1) &
  486. ~RME32_WCR_FREQ_0;
  487. break;
  488. case 96000:
  489. if (rme32->pci->device != PCI_DEVICE_ID_RME_DIGI32_PRO)
  490. return -EINVAL;
  491. rme32->wcreg |= RME32_WCR_DS_BM;
  492. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  493. RME32_WCR_FREQ_1;
  494. break;
  495. default:
  496. return -EINVAL;
  497. }
  498. if ((!ds && rme32->wcreg & RME32_WCR_DS_BM) ||
  499. (ds && !(rme32->wcreg & RME32_WCR_DS_BM)))
  500. {
  501. /* change to/from double-speed: reset the DAC (if available) */
  502. snd_rme32_reset_dac(rme32);
  503. } else {
  504. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  505. }
  506. return 0;
  507. }
  508. static int snd_rme32_setclockmode(struct rme32 * rme32, int mode)
  509. {
  510. switch (mode) {
  511. case RME32_CLOCKMODE_SLAVE:
  512. /* AutoSync */
  513. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) &
  514. ~RME32_WCR_FREQ_1;
  515. break;
  516. case RME32_CLOCKMODE_MASTER_32:
  517. /* Internal 32.0kHz */
  518. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) &
  519. ~RME32_WCR_FREQ_1;
  520. break;
  521. case RME32_CLOCKMODE_MASTER_44:
  522. /* Internal 44.1kHz */
  523. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_FREQ_0) |
  524. RME32_WCR_FREQ_1;
  525. break;
  526. case RME32_CLOCKMODE_MASTER_48:
  527. /* Internal 48.0kHz */
  528. rme32->wcreg = (rme32->wcreg | RME32_WCR_FREQ_0) |
  529. RME32_WCR_FREQ_1;
  530. break;
  531. default:
  532. return -EINVAL;
  533. }
  534. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  535. return 0;
  536. }
  537. static int snd_rme32_getclockmode(struct rme32 * rme32)
  538. {
  539. return ((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_0) & 1) +
  540. (((rme32->wcreg >> RME32_WCR_BITPOS_FREQ_1) & 1) << 1);
  541. }
  542. static int snd_rme32_setinputtype(struct rme32 * rme32, int type)
  543. {
  544. switch (type) {
  545. case RME32_INPUT_OPTICAL:
  546. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) &
  547. ~RME32_WCR_INP_1;
  548. break;
  549. case RME32_INPUT_COAXIAL:
  550. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) &
  551. ~RME32_WCR_INP_1;
  552. break;
  553. case RME32_INPUT_INTERNAL:
  554. rme32->wcreg = (rme32->wcreg & ~RME32_WCR_INP_0) |
  555. RME32_WCR_INP_1;
  556. break;
  557. case RME32_INPUT_XLR:
  558. rme32->wcreg = (rme32->wcreg | RME32_WCR_INP_0) |
  559. RME32_WCR_INP_1;
  560. break;
  561. default:
  562. return -EINVAL;
  563. }
  564. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  565. return 0;
  566. }
  567. static int snd_rme32_getinputtype(struct rme32 * rme32)
  568. {
  569. return ((rme32->wcreg >> RME32_WCR_BITPOS_INP_0) & 1) +
  570. (((rme32->wcreg >> RME32_WCR_BITPOS_INP_1) & 1) << 1);
  571. }
  572. static void
  573. snd_rme32_setframelog(struct rme32 * rme32, int n_channels, int is_playback)
  574. {
  575. int frlog;
  576. if (n_channels == 2) {
  577. frlog = 1;
  578. } else {
  579. /* assume 8 channels */
  580. frlog = 3;
  581. }
  582. if (is_playback) {
  583. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  584. rme32->playback_frlog = frlog;
  585. } else {
  586. frlog += (rme32->wcreg & RME32_WCR_MODE24) ? 2 : 1;
  587. rme32->capture_frlog = frlog;
  588. }
  589. }
  590. static int snd_rme32_setformat(struct rme32 * rme32, int format)
  591. {
  592. switch (format) {
  593. case SNDRV_PCM_FORMAT_S16_LE:
  594. rme32->wcreg &= ~RME32_WCR_MODE24;
  595. break;
  596. case SNDRV_PCM_FORMAT_S32_LE:
  597. rme32->wcreg |= RME32_WCR_MODE24;
  598. break;
  599. default:
  600. return -EINVAL;
  601. }
  602. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  603. return 0;
  604. }
  605. static int
  606. snd_rme32_playback_hw_params(struct snd_pcm_substream *substream,
  607. struct snd_pcm_hw_params *params)
  608. {
  609. int err, rate, dummy;
  610. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  611. struct snd_pcm_runtime *runtime = substream->runtime;
  612. if (rme32->fullduplex_mode) {
  613. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  614. if (err < 0)
  615. return err;
  616. } else {
  617. runtime->dma_area = (void __force *)(rme32->iobase +
  618. RME32_IO_DATA_BUFFER);
  619. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  620. runtime->dma_bytes = RME32_BUFFER_SIZE;
  621. }
  622. spin_lock_irq(&rme32->lock);
  623. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  624. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  625. /* AutoSync */
  626. if ((int)params_rate(params) != rate) {
  627. spin_unlock_irq(&rme32->lock);
  628. return -EIO;
  629. }
  630. } else if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  631. spin_unlock_irq(&rme32->lock);
  632. return err;
  633. }
  634. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  635. spin_unlock_irq(&rme32->lock);
  636. return err;
  637. }
  638. snd_rme32_setframelog(rme32, params_channels(params), 1);
  639. if (rme32->capture_periodsize != 0) {
  640. if (params_period_size(params) << rme32->playback_frlog != rme32->capture_periodsize) {
  641. spin_unlock_irq(&rme32->lock);
  642. return -EBUSY;
  643. }
  644. }
  645. rme32->playback_periodsize = params_period_size(params) << rme32->playback_frlog;
  646. /* S/PDIF setup */
  647. if ((rme32->wcreg & RME32_WCR_ADAT) == 0) {
  648. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  649. rme32->wcreg |= rme32->wcreg_spdif_stream;
  650. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  651. }
  652. spin_unlock_irq(&rme32->lock);
  653. return 0;
  654. }
  655. static int
  656. snd_rme32_capture_hw_params(struct snd_pcm_substream *substream,
  657. struct snd_pcm_hw_params *params)
  658. {
  659. int err, isadat, rate;
  660. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  661. struct snd_pcm_runtime *runtime = substream->runtime;
  662. if (rme32->fullduplex_mode) {
  663. err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
  664. if (err < 0)
  665. return err;
  666. } else {
  667. runtime->dma_area = (void __force *)rme32->iobase +
  668. RME32_IO_DATA_BUFFER;
  669. runtime->dma_addr = rme32->port + RME32_IO_DATA_BUFFER;
  670. runtime->dma_bytes = RME32_BUFFER_SIZE;
  671. }
  672. spin_lock_irq(&rme32->lock);
  673. /* enable AutoSync for record-preparing */
  674. rme32->wcreg |= RME32_WCR_AUTOSYNC;
  675. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  676. if ((err = snd_rme32_setformat(rme32, params_format(params))) < 0) {
  677. spin_unlock_irq(&rme32->lock);
  678. return err;
  679. }
  680. if ((err = snd_rme32_playback_setrate(rme32, params_rate(params))) < 0) {
  681. spin_unlock_irq(&rme32->lock);
  682. return err;
  683. }
  684. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  685. if ((int)params_rate(params) != rate) {
  686. spin_unlock_irq(&rme32->lock);
  687. return -EIO;
  688. }
  689. if ((isadat && runtime->hw.channels_min == 2) ||
  690. (!isadat && runtime->hw.channels_min == 8)) {
  691. spin_unlock_irq(&rme32->lock);
  692. return -EIO;
  693. }
  694. }
  695. /* AutoSync off for recording */
  696. rme32->wcreg &= ~RME32_WCR_AUTOSYNC;
  697. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  698. snd_rme32_setframelog(rme32, params_channels(params), 0);
  699. if (rme32->playback_periodsize != 0) {
  700. if (params_period_size(params) << rme32->capture_frlog !=
  701. rme32->playback_periodsize) {
  702. spin_unlock_irq(&rme32->lock);
  703. return -EBUSY;
  704. }
  705. }
  706. rme32->capture_periodsize =
  707. params_period_size(params) << rme32->capture_frlog;
  708. spin_unlock_irq(&rme32->lock);
  709. return 0;
  710. }
  711. static int snd_rme32_pcm_hw_free(struct snd_pcm_substream *substream)
  712. {
  713. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  714. if (! rme32->fullduplex_mode)
  715. return 0;
  716. return snd_pcm_lib_free_pages(substream);
  717. }
  718. static void snd_rme32_pcm_start(struct rme32 * rme32, int from_pause)
  719. {
  720. if (!from_pause) {
  721. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  722. }
  723. rme32->wcreg |= RME32_WCR_START;
  724. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  725. }
  726. static void snd_rme32_pcm_stop(struct rme32 * rme32, int to_pause)
  727. {
  728. /*
  729. * Check if there is an unconfirmed IRQ, if so confirm it, or else
  730. * the hardware will not stop generating interrupts
  731. */
  732. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  733. if (rme32->rcreg & RME32_RCR_IRQ) {
  734. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  735. }
  736. rme32->wcreg &= ~RME32_WCR_START;
  737. if (rme32->wcreg & RME32_WCR_SEL)
  738. rme32->wcreg |= RME32_WCR_MUTE;
  739. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  740. if (! to_pause)
  741. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  742. }
  743. static irqreturn_t snd_rme32_interrupt(int irq, void *dev_id)
  744. {
  745. struct rme32 *rme32 = (struct rme32 *) dev_id;
  746. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  747. if (!(rme32->rcreg & RME32_RCR_IRQ)) {
  748. return IRQ_NONE;
  749. } else {
  750. if (rme32->capture_substream) {
  751. snd_pcm_period_elapsed(rme32->capture_substream);
  752. }
  753. if (rme32->playback_substream) {
  754. snd_pcm_period_elapsed(rme32->playback_substream);
  755. }
  756. writel(0, rme32->iobase + RME32_IO_CONFIRM_ACTION_IRQ);
  757. }
  758. return IRQ_HANDLED;
  759. }
  760. static unsigned int period_bytes[] = { RME32_BLOCK_SIZE };
  761. static struct snd_pcm_hw_constraint_list hw_constraints_period_bytes = {
  762. .count = ARRAY_SIZE(period_bytes),
  763. .list = period_bytes,
  764. .mask = 0
  765. };
  766. static void snd_rme32_set_buffer_constraint(struct rme32 *rme32, struct snd_pcm_runtime *runtime)
  767. {
  768. if (! rme32->fullduplex_mode) {
  769. snd_pcm_hw_constraint_minmax(runtime,
  770. SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  771. RME32_BUFFER_SIZE, RME32_BUFFER_SIZE);
  772. snd_pcm_hw_constraint_list(runtime, 0,
  773. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  774. &hw_constraints_period_bytes);
  775. }
  776. }
  777. static int snd_rme32_playback_spdif_open(struct snd_pcm_substream *substream)
  778. {
  779. int rate, dummy;
  780. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  781. struct snd_pcm_runtime *runtime = substream->runtime;
  782. snd_pcm_set_sync(substream);
  783. spin_lock_irq(&rme32->lock);
  784. if (rme32->playback_substream != NULL) {
  785. spin_unlock_irq(&rme32->lock);
  786. return -EBUSY;
  787. }
  788. rme32->wcreg &= ~RME32_WCR_ADAT;
  789. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  790. rme32->playback_substream = substream;
  791. spin_unlock_irq(&rme32->lock);
  792. if (rme32->fullduplex_mode)
  793. runtime->hw = snd_rme32_spdif_fd_info;
  794. else
  795. runtime->hw = snd_rme32_spdif_info;
  796. if (rme32->pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO) {
  797. runtime->hw.rates |= SNDRV_PCM_RATE_64000 | SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  798. runtime->hw.rate_max = 96000;
  799. }
  800. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  801. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  802. /* AutoSync */
  803. runtime->hw.rates = snd_rme32_ratecode(rate);
  804. runtime->hw.rate_min = rate;
  805. runtime->hw.rate_max = rate;
  806. }
  807. snd_rme32_set_buffer_constraint(rme32, runtime);
  808. rme32->wcreg_spdif_stream = rme32->wcreg_spdif;
  809. rme32->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  810. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  811. SNDRV_CTL_EVENT_MASK_INFO, &rme32->spdif_ctl->id);
  812. return 0;
  813. }
  814. static int snd_rme32_capture_spdif_open(struct snd_pcm_substream *substream)
  815. {
  816. int isadat, rate;
  817. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  818. struct snd_pcm_runtime *runtime = substream->runtime;
  819. snd_pcm_set_sync(substream);
  820. spin_lock_irq(&rme32->lock);
  821. if (rme32->capture_substream != NULL) {
  822. spin_unlock_irq(&rme32->lock);
  823. return -EBUSY;
  824. }
  825. rme32->capture_substream = substream;
  826. spin_unlock_irq(&rme32->lock);
  827. if (rme32->fullduplex_mode)
  828. runtime->hw = snd_rme32_spdif_fd_info;
  829. else
  830. runtime->hw = snd_rme32_spdif_info;
  831. if (RME32_PRO_WITH_8414(rme32)) {
  832. runtime->hw.rates |= SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000;
  833. runtime->hw.rate_max = 96000;
  834. }
  835. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  836. if (isadat) {
  837. return -EIO;
  838. }
  839. runtime->hw.rates = snd_rme32_ratecode(rate);
  840. runtime->hw.rate_min = rate;
  841. runtime->hw.rate_max = rate;
  842. }
  843. snd_rme32_set_buffer_constraint(rme32, runtime);
  844. return 0;
  845. }
  846. static int
  847. snd_rme32_playback_adat_open(struct snd_pcm_substream *substream)
  848. {
  849. int rate, dummy;
  850. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  851. struct snd_pcm_runtime *runtime = substream->runtime;
  852. snd_pcm_set_sync(substream);
  853. spin_lock_irq(&rme32->lock);
  854. if (rme32->playback_substream != NULL) {
  855. spin_unlock_irq(&rme32->lock);
  856. return -EBUSY;
  857. }
  858. rme32->wcreg |= RME32_WCR_ADAT;
  859. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  860. rme32->playback_substream = substream;
  861. spin_unlock_irq(&rme32->lock);
  862. if (rme32->fullduplex_mode)
  863. runtime->hw = snd_rme32_adat_fd_info;
  864. else
  865. runtime->hw = snd_rme32_adat_info;
  866. if ((rme32->rcreg & RME32_RCR_KMODE) &&
  867. (rate = snd_rme32_capture_getrate(rme32, &dummy)) > 0) {
  868. /* AutoSync */
  869. runtime->hw.rates = snd_rme32_ratecode(rate);
  870. runtime->hw.rate_min = rate;
  871. runtime->hw.rate_max = rate;
  872. }
  873. snd_rme32_set_buffer_constraint(rme32, runtime);
  874. return 0;
  875. }
  876. static int
  877. snd_rme32_capture_adat_open(struct snd_pcm_substream *substream)
  878. {
  879. int isadat, rate;
  880. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  881. struct snd_pcm_runtime *runtime = substream->runtime;
  882. if (rme32->fullduplex_mode)
  883. runtime->hw = snd_rme32_adat_fd_info;
  884. else
  885. runtime->hw = snd_rme32_adat_info;
  886. if ((rate = snd_rme32_capture_getrate(rme32, &isadat)) > 0) {
  887. if (!isadat) {
  888. return -EIO;
  889. }
  890. runtime->hw.rates = snd_rme32_ratecode(rate);
  891. runtime->hw.rate_min = rate;
  892. runtime->hw.rate_max = rate;
  893. }
  894. snd_pcm_set_sync(substream);
  895. spin_lock_irq(&rme32->lock);
  896. if (rme32->capture_substream != NULL) {
  897. spin_unlock_irq(&rme32->lock);
  898. return -EBUSY;
  899. }
  900. rme32->capture_substream = substream;
  901. spin_unlock_irq(&rme32->lock);
  902. snd_rme32_set_buffer_constraint(rme32, runtime);
  903. return 0;
  904. }
  905. static int snd_rme32_playback_close(struct snd_pcm_substream *substream)
  906. {
  907. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  908. int spdif = 0;
  909. spin_lock_irq(&rme32->lock);
  910. rme32->playback_substream = NULL;
  911. rme32->playback_periodsize = 0;
  912. spdif = (rme32->wcreg & RME32_WCR_ADAT) == 0;
  913. spin_unlock_irq(&rme32->lock);
  914. if (spdif) {
  915. rme32->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
  916. snd_ctl_notify(rme32->card, SNDRV_CTL_EVENT_MASK_VALUE |
  917. SNDRV_CTL_EVENT_MASK_INFO,
  918. &rme32->spdif_ctl->id);
  919. }
  920. return 0;
  921. }
  922. static int snd_rme32_capture_close(struct snd_pcm_substream *substream)
  923. {
  924. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  925. spin_lock_irq(&rme32->lock);
  926. rme32->capture_substream = NULL;
  927. rme32->capture_periodsize = 0;
  928. spin_unlock(&rme32->lock);
  929. return 0;
  930. }
  931. static int snd_rme32_playback_prepare(struct snd_pcm_substream *substream)
  932. {
  933. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  934. spin_lock_irq(&rme32->lock);
  935. if (rme32->fullduplex_mode) {
  936. memset(&rme32->playback_pcm, 0, sizeof(rme32->playback_pcm));
  937. rme32->playback_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  938. rme32->playback_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  939. } else {
  940. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  941. }
  942. if (rme32->wcreg & RME32_WCR_SEL)
  943. rme32->wcreg &= ~RME32_WCR_MUTE;
  944. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  945. spin_unlock_irq(&rme32->lock);
  946. return 0;
  947. }
  948. static int snd_rme32_capture_prepare(struct snd_pcm_substream *substream)
  949. {
  950. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  951. spin_lock_irq(&rme32->lock);
  952. if (rme32->fullduplex_mode) {
  953. memset(&rme32->capture_pcm, 0, sizeof(rme32->capture_pcm));
  954. rme32->capture_pcm.hw_buffer_size = RME32_BUFFER_SIZE;
  955. rme32->capture_pcm.hw_queue_size = RME32_BUFFER_SIZE / 2;
  956. rme32->capture_pcm.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  957. } else {
  958. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  959. }
  960. spin_unlock_irq(&rme32->lock);
  961. return 0;
  962. }
  963. static int
  964. snd_rme32_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  965. {
  966. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  967. struct list_head *pos;
  968. struct snd_pcm_substream *s;
  969. spin_lock(&rme32->lock);
  970. snd_pcm_group_for_each(pos, substream) {
  971. s = snd_pcm_group_substream_entry(pos);
  972. if (s != rme32->playback_substream &&
  973. s != rme32->capture_substream)
  974. continue;
  975. switch (cmd) {
  976. case SNDRV_PCM_TRIGGER_START:
  977. rme32->running |= (1 << s->stream);
  978. if (rme32->fullduplex_mode) {
  979. /* remember the current DMA position */
  980. if (s == rme32->playback_substream) {
  981. rme32->playback_pcm.hw_io =
  982. rme32->playback_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  983. } else {
  984. rme32->capture_pcm.hw_io =
  985. rme32->capture_pcm.hw_data = snd_rme32_pcm_byteptr(rme32);
  986. }
  987. }
  988. break;
  989. case SNDRV_PCM_TRIGGER_STOP:
  990. rme32->running &= ~(1 << s->stream);
  991. break;
  992. }
  993. snd_pcm_trigger_done(s, substream);
  994. }
  995. /* prefill playback buffer */
  996. if (cmd == SNDRV_PCM_TRIGGER_START && rme32->fullduplex_mode) {
  997. snd_pcm_group_for_each(pos, substream) {
  998. s = snd_pcm_group_substream_entry(pos);
  999. if (s == rme32->playback_substream) {
  1000. s->ops->ack(s);
  1001. break;
  1002. }
  1003. }
  1004. }
  1005. switch (cmd) {
  1006. case SNDRV_PCM_TRIGGER_START:
  1007. if (rme32->running && ! RME32_ISWORKING(rme32))
  1008. snd_rme32_pcm_start(rme32, 0);
  1009. break;
  1010. case SNDRV_PCM_TRIGGER_STOP:
  1011. if (! rme32->running && RME32_ISWORKING(rme32))
  1012. snd_rme32_pcm_stop(rme32, 0);
  1013. break;
  1014. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1015. if (rme32->running && RME32_ISWORKING(rme32))
  1016. snd_rme32_pcm_stop(rme32, 1);
  1017. break;
  1018. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1019. if (rme32->running && ! RME32_ISWORKING(rme32))
  1020. snd_rme32_pcm_start(rme32, 1);
  1021. break;
  1022. }
  1023. spin_unlock(&rme32->lock);
  1024. return 0;
  1025. }
  1026. /* pointer callback for halfduplex mode */
  1027. static snd_pcm_uframes_t
  1028. snd_rme32_playback_pointer(struct snd_pcm_substream *substream)
  1029. {
  1030. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1031. return snd_rme32_pcm_byteptr(rme32) >> rme32->playback_frlog;
  1032. }
  1033. static snd_pcm_uframes_t
  1034. snd_rme32_capture_pointer(struct snd_pcm_substream *substream)
  1035. {
  1036. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1037. return snd_rme32_pcm_byteptr(rme32) >> rme32->capture_frlog;
  1038. }
  1039. /* ack and pointer callbacks for fullduplex mode */
  1040. static void snd_rme32_pb_trans_copy(struct snd_pcm_substream *substream,
  1041. struct snd_pcm_indirect *rec, size_t bytes)
  1042. {
  1043. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1044. memcpy_toio(rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1045. substream->runtime->dma_area + rec->sw_data, bytes);
  1046. }
  1047. static int snd_rme32_playback_fd_ack(struct snd_pcm_substream *substream)
  1048. {
  1049. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1050. struct snd_pcm_indirect *rec, *cprec;
  1051. rec = &rme32->playback_pcm;
  1052. cprec = &rme32->capture_pcm;
  1053. spin_lock(&rme32->lock);
  1054. rec->hw_queue_size = RME32_BUFFER_SIZE;
  1055. if (rme32->running & (1 << SNDRV_PCM_STREAM_CAPTURE))
  1056. rec->hw_queue_size -= cprec->hw_ready;
  1057. spin_unlock(&rme32->lock);
  1058. snd_pcm_indirect_playback_transfer(substream, rec,
  1059. snd_rme32_pb_trans_copy);
  1060. return 0;
  1061. }
  1062. static void snd_rme32_cp_trans_copy(struct snd_pcm_substream *substream,
  1063. struct snd_pcm_indirect *rec, size_t bytes)
  1064. {
  1065. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1066. memcpy_fromio(substream->runtime->dma_area + rec->sw_data,
  1067. rme32->iobase + RME32_IO_DATA_BUFFER + rec->hw_data,
  1068. bytes);
  1069. }
  1070. static int snd_rme32_capture_fd_ack(struct snd_pcm_substream *substream)
  1071. {
  1072. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1073. snd_pcm_indirect_capture_transfer(substream, &rme32->capture_pcm,
  1074. snd_rme32_cp_trans_copy);
  1075. return 0;
  1076. }
  1077. static snd_pcm_uframes_t
  1078. snd_rme32_playback_fd_pointer(struct snd_pcm_substream *substream)
  1079. {
  1080. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1081. return snd_pcm_indirect_playback_pointer(substream, &rme32->playback_pcm,
  1082. snd_rme32_pcm_byteptr(rme32));
  1083. }
  1084. static snd_pcm_uframes_t
  1085. snd_rme32_capture_fd_pointer(struct snd_pcm_substream *substream)
  1086. {
  1087. struct rme32 *rme32 = snd_pcm_substream_chip(substream);
  1088. return snd_pcm_indirect_capture_pointer(substream, &rme32->capture_pcm,
  1089. snd_rme32_pcm_byteptr(rme32));
  1090. }
  1091. /* for halfduplex mode */
  1092. static struct snd_pcm_ops snd_rme32_playback_spdif_ops = {
  1093. .open = snd_rme32_playback_spdif_open,
  1094. .close = snd_rme32_playback_close,
  1095. .ioctl = snd_pcm_lib_ioctl,
  1096. .hw_params = snd_rme32_playback_hw_params,
  1097. .hw_free = snd_rme32_pcm_hw_free,
  1098. .prepare = snd_rme32_playback_prepare,
  1099. .trigger = snd_rme32_pcm_trigger,
  1100. .pointer = snd_rme32_playback_pointer,
  1101. .copy = snd_rme32_playback_copy,
  1102. .silence = snd_rme32_playback_silence,
  1103. .mmap = snd_pcm_lib_mmap_iomem,
  1104. };
  1105. static struct snd_pcm_ops snd_rme32_capture_spdif_ops = {
  1106. .open = snd_rme32_capture_spdif_open,
  1107. .close = snd_rme32_capture_close,
  1108. .ioctl = snd_pcm_lib_ioctl,
  1109. .hw_params = snd_rme32_capture_hw_params,
  1110. .hw_free = snd_rme32_pcm_hw_free,
  1111. .prepare = snd_rme32_capture_prepare,
  1112. .trigger = snd_rme32_pcm_trigger,
  1113. .pointer = snd_rme32_capture_pointer,
  1114. .copy = snd_rme32_capture_copy,
  1115. .mmap = snd_pcm_lib_mmap_iomem,
  1116. };
  1117. static struct snd_pcm_ops snd_rme32_playback_adat_ops = {
  1118. .open = snd_rme32_playback_adat_open,
  1119. .close = snd_rme32_playback_close,
  1120. .ioctl = snd_pcm_lib_ioctl,
  1121. .hw_params = snd_rme32_playback_hw_params,
  1122. .prepare = snd_rme32_playback_prepare,
  1123. .trigger = snd_rme32_pcm_trigger,
  1124. .pointer = snd_rme32_playback_pointer,
  1125. .copy = snd_rme32_playback_copy,
  1126. .silence = snd_rme32_playback_silence,
  1127. .mmap = snd_pcm_lib_mmap_iomem,
  1128. };
  1129. static struct snd_pcm_ops snd_rme32_capture_adat_ops = {
  1130. .open = snd_rme32_capture_adat_open,
  1131. .close = snd_rme32_capture_close,
  1132. .ioctl = snd_pcm_lib_ioctl,
  1133. .hw_params = snd_rme32_capture_hw_params,
  1134. .prepare = snd_rme32_capture_prepare,
  1135. .trigger = snd_rme32_pcm_trigger,
  1136. .pointer = snd_rme32_capture_pointer,
  1137. .copy = snd_rme32_capture_copy,
  1138. .mmap = snd_pcm_lib_mmap_iomem,
  1139. };
  1140. /* for fullduplex mode */
  1141. static struct snd_pcm_ops snd_rme32_playback_spdif_fd_ops = {
  1142. .open = snd_rme32_playback_spdif_open,
  1143. .close = snd_rme32_playback_close,
  1144. .ioctl = snd_pcm_lib_ioctl,
  1145. .hw_params = snd_rme32_playback_hw_params,
  1146. .hw_free = snd_rme32_pcm_hw_free,
  1147. .prepare = snd_rme32_playback_prepare,
  1148. .trigger = snd_rme32_pcm_trigger,
  1149. .pointer = snd_rme32_playback_fd_pointer,
  1150. .ack = snd_rme32_playback_fd_ack,
  1151. };
  1152. static struct snd_pcm_ops snd_rme32_capture_spdif_fd_ops = {
  1153. .open = snd_rme32_capture_spdif_open,
  1154. .close = snd_rme32_capture_close,
  1155. .ioctl = snd_pcm_lib_ioctl,
  1156. .hw_params = snd_rme32_capture_hw_params,
  1157. .hw_free = snd_rme32_pcm_hw_free,
  1158. .prepare = snd_rme32_capture_prepare,
  1159. .trigger = snd_rme32_pcm_trigger,
  1160. .pointer = snd_rme32_capture_fd_pointer,
  1161. .ack = snd_rme32_capture_fd_ack,
  1162. };
  1163. static struct snd_pcm_ops snd_rme32_playback_adat_fd_ops = {
  1164. .open = snd_rme32_playback_adat_open,
  1165. .close = snd_rme32_playback_close,
  1166. .ioctl = snd_pcm_lib_ioctl,
  1167. .hw_params = snd_rme32_playback_hw_params,
  1168. .prepare = snd_rme32_playback_prepare,
  1169. .trigger = snd_rme32_pcm_trigger,
  1170. .pointer = snd_rme32_playback_fd_pointer,
  1171. .ack = snd_rme32_playback_fd_ack,
  1172. };
  1173. static struct snd_pcm_ops snd_rme32_capture_adat_fd_ops = {
  1174. .open = snd_rme32_capture_adat_open,
  1175. .close = snd_rme32_capture_close,
  1176. .ioctl = snd_pcm_lib_ioctl,
  1177. .hw_params = snd_rme32_capture_hw_params,
  1178. .prepare = snd_rme32_capture_prepare,
  1179. .trigger = snd_rme32_pcm_trigger,
  1180. .pointer = snd_rme32_capture_fd_pointer,
  1181. .ack = snd_rme32_capture_fd_ack,
  1182. };
  1183. static void snd_rme32_free(void *private_data)
  1184. {
  1185. struct rme32 *rme32 = (struct rme32 *) private_data;
  1186. if (rme32 == NULL) {
  1187. return;
  1188. }
  1189. if (rme32->irq >= 0) {
  1190. snd_rme32_pcm_stop(rme32, 0);
  1191. free_irq(rme32->irq, (void *) rme32);
  1192. rme32->irq = -1;
  1193. }
  1194. if (rme32->iobase) {
  1195. iounmap(rme32->iobase);
  1196. rme32->iobase = NULL;
  1197. }
  1198. if (rme32->port) {
  1199. pci_release_regions(rme32->pci);
  1200. rme32->port = 0;
  1201. }
  1202. pci_disable_device(rme32->pci);
  1203. }
  1204. static void snd_rme32_free_spdif_pcm(struct snd_pcm *pcm)
  1205. {
  1206. struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
  1207. rme32->spdif_pcm = NULL;
  1208. }
  1209. static void
  1210. snd_rme32_free_adat_pcm(struct snd_pcm *pcm)
  1211. {
  1212. struct rme32 *rme32 = (struct rme32 *) pcm->private_data;
  1213. rme32->adat_pcm = NULL;
  1214. }
  1215. static int __devinit snd_rme32_create(struct rme32 * rme32)
  1216. {
  1217. struct pci_dev *pci = rme32->pci;
  1218. int err;
  1219. rme32->irq = -1;
  1220. spin_lock_init(&rme32->lock);
  1221. if ((err = pci_enable_device(pci)) < 0)
  1222. return err;
  1223. if ((err = pci_request_regions(pci, "RME32")) < 0)
  1224. return err;
  1225. rme32->port = pci_resource_start(rme32->pci, 0);
  1226. if ((rme32->iobase = ioremap_nocache(rme32->port, RME32_IO_SIZE)) == 0) {
  1227. snd_printk(KERN_ERR "unable to remap memory region 0x%lx-0x%lx\n",
  1228. rme32->port, rme32->port + RME32_IO_SIZE - 1);
  1229. return -ENOMEM;
  1230. }
  1231. if (request_irq(pci->irq, snd_rme32_interrupt, IRQF_SHARED,
  1232. "RME32", rme32)) {
  1233. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1234. return -EBUSY;
  1235. }
  1236. rme32->irq = pci->irq;
  1237. /* read the card's revision number */
  1238. pci_read_config_byte(pci, 8, &rme32->rev);
  1239. /* set up ALSA pcm device for S/PDIF */
  1240. if ((err = snd_pcm_new(rme32->card, "Digi32 IEC958", 0, 1, 1, &rme32->spdif_pcm)) < 0) {
  1241. return err;
  1242. }
  1243. rme32->spdif_pcm->private_data = rme32;
  1244. rme32->spdif_pcm->private_free = snd_rme32_free_spdif_pcm;
  1245. strcpy(rme32->spdif_pcm->name, "Digi32 IEC958");
  1246. if (rme32->fullduplex_mode) {
  1247. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1248. &snd_rme32_playback_spdif_fd_ops);
  1249. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1250. &snd_rme32_capture_spdif_fd_ops);
  1251. snd_pcm_lib_preallocate_pages_for_all(rme32->spdif_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1252. snd_dma_continuous_data(GFP_KERNEL),
  1253. 0, RME32_MID_BUFFER_SIZE);
  1254. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1255. } else {
  1256. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1257. &snd_rme32_playback_spdif_ops);
  1258. snd_pcm_set_ops(rme32->spdif_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1259. &snd_rme32_capture_spdif_ops);
  1260. rme32->spdif_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1261. }
  1262. /* set up ALSA pcm device for ADAT */
  1263. if ((pci->device == PCI_DEVICE_ID_RME_DIGI32) ||
  1264. (pci->device == PCI_DEVICE_ID_RME_DIGI32_PRO)) {
  1265. /* ADAT is not available on DIGI32 and DIGI32 Pro */
  1266. rme32->adat_pcm = NULL;
  1267. }
  1268. else {
  1269. if ((err = snd_pcm_new(rme32->card, "Digi32 ADAT", 1,
  1270. 1, 1, &rme32->adat_pcm)) < 0)
  1271. {
  1272. return err;
  1273. }
  1274. rme32->adat_pcm->private_data = rme32;
  1275. rme32->adat_pcm->private_free = snd_rme32_free_adat_pcm;
  1276. strcpy(rme32->adat_pcm->name, "Digi32 ADAT");
  1277. if (rme32->fullduplex_mode) {
  1278. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1279. &snd_rme32_playback_adat_fd_ops);
  1280. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1281. &snd_rme32_capture_adat_fd_ops);
  1282. snd_pcm_lib_preallocate_pages_for_all(rme32->adat_pcm, SNDRV_DMA_TYPE_CONTINUOUS,
  1283. snd_dma_continuous_data(GFP_KERNEL),
  1284. 0, RME32_MID_BUFFER_SIZE);
  1285. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
  1286. } else {
  1287. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_PLAYBACK,
  1288. &snd_rme32_playback_adat_ops);
  1289. snd_pcm_set_ops(rme32->adat_pcm, SNDRV_PCM_STREAM_CAPTURE,
  1290. &snd_rme32_capture_adat_ops);
  1291. rme32->adat_pcm->info_flags = SNDRV_PCM_INFO_HALF_DUPLEX;
  1292. }
  1293. }
  1294. rme32->playback_periodsize = 0;
  1295. rme32->capture_periodsize = 0;
  1296. /* make sure playback/capture is stopped, if by some reason active */
  1297. snd_rme32_pcm_stop(rme32, 0);
  1298. /* reset DAC */
  1299. snd_rme32_reset_dac(rme32);
  1300. /* reset buffer pointer */
  1301. writel(0, rme32->iobase + RME32_IO_RESET_POS);
  1302. /* set default values in registers */
  1303. rme32->wcreg = RME32_WCR_SEL | /* normal playback */
  1304. RME32_WCR_INP_0 | /* input select */
  1305. RME32_WCR_MUTE; /* muting on */
  1306. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1307. /* init switch interface */
  1308. if ((err = snd_rme32_create_switches(rme32->card, rme32)) < 0) {
  1309. return err;
  1310. }
  1311. /* init proc interface */
  1312. snd_rme32_proc_init(rme32);
  1313. rme32->capture_substream = NULL;
  1314. rme32->playback_substream = NULL;
  1315. return 0;
  1316. }
  1317. /*
  1318. * proc interface
  1319. */
  1320. static void
  1321. snd_rme32_proc_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
  1322. {
  1323. int n;
  1324. struct rme32 *rme32 = (struct rme32 *) entry->private_data;
  1325. rme32->rcreg = readl(rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1326. snd_iprintf(buffer, rme32->card->longname);
  1327. snd_iprintf(buffer, " (index #%d)\n", rme32->card->number + 1);
  1328. snd_iprintf(buffer, "\nGeneral settings\n");
  1329. if (rme32->fullduplex_mode)
  1330. snd_iprintf(buffer, " Full-duplex mode\n");
  1331. else
  1332. snd_iprintf(buffer, " Half-duplex mode\n");
  1333. if (RME32_PRO_WITH_8414(rme32)) {
  1334. snd_iprintf(buffer, " receiver: CS8414\n");
  1335. } else {
  1336. snd_iprintf(buffer, " receiver: CS8412\n");
  1337. }
  1338. if (rme32->wcreg & RME32_WCR_MODE24) {
  1339. snd_iprintf(buffer, " format: 24 bit");
  1340. } else {
  1341. snd_iprintf(buffer, " format: 16 bit");
  1342. }
  1343. if (rme32->wcreg & RME32_WCR_MONO) {
  1344. snd_iprintf(buffer, ", Mono\n");
  1345. } else {
  1346. snd_iprintf(buffer, ", Stereo\n");
  1347. }
  1348. snd_iprintf(buffer, "\nInput settings\n");
  1349. switch (snd_rme32_getinputtype(rme32)) {
  1350. case RME32_INPUT_OPTICAL:
  1351. snd_iprintf(buffer, " input: optical");
  1352. break;
  1353. case RME32_INPUT_COAXIAL:
  1354. snd_iprintf(buffer, " input: coaxial");
  1355. break;
  1356. case RME32_INPUT_INTERNAL:
  1357. snd_iprintf(buffer, " input: internal");
  1358. break;
  1359. case RME32_INPUT_XLR:
  1360. snd_iprintf(buffer, " input: XLR");
  1361. break;
  1362. }
  1363. if (snd_rme32_capture_getrate(rme32, &n) < 0) {
  1364. snd_iprintf(buffer, "\n sample rate: no valid signal\n");
  1365. } else {
  1366. if (n) {
  1367. snd_iprintf(buffer, " (8 channels)\n");
  1368. } else {
  1369. snd_iprintf(buffer, " (2 channels)\n");
  1370. }
  1371. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1372. snd_rme32_capture_getrate(rme32, &n));
  1373. }
  1374. snd_iprintf(buffer, "\nOutput settings\n");
  1375. if (rme32->wcreg & RME32_WCR_SEL) {
  1376. snd_iprintf(buffer, " output signal: normal playback");
  1377. } else {
  1378. snd_iprintf(buffer, " output signal: same as input");
  1379. }
  1380. if (rme32->wcreg & RME32_WCR_MUTE) {
  1381. snd_iprintf(buffer, " (muted)\n");
  1382. } else {
  1383. snd_iprintf(buffer, "\n");
  1384. }
  1385. /* master output frequency */
  1386. if (!
  1387. ((!(rme32->wcreg & RME32_WCR_FREQ_0))
  1388. && (!(rme32->wcreg & RME32_WCR_FREQ_1)))) {
  1389. snd_iprintf(buffer, " sample rate: %d Hz\n",
  1390. snd_rme32_playback_getrate(rme32));
  1391. }
  1392. if (rme32->rcreg & RME32_RCR_KMODE) {
  1393. snd_iprintf(buffer, " sample clock source: AutoSync\n");
  1394. } else {
  1395. snd_iprintf(buffer, " sample clock source: Internal\n");
  1396. }
  1397. if (rme32->wcreg & RME32_WCR_PRO) {
  1398. snd_iprintf(buffer, " format: AES/EBU (professional)\n");
  1399. } else {
  1400. snd_iprintf(buffer, " format: IEC958 (consumer)\n");
  1401. }
  1402. if (rme32->wcreg & RME32_WCR_EMP) {
  1403. snd_iprintf(buffer, " emphasis: on\n");
  1404. } else {
  1405. snd_iprintf(buffer, " emphasis: off\n");
  1406. }
  1407. }
  1408. static void __devinit snd_rme32_proc_init(struct rme32 * rme32)
  1409. {
  1410. struct snd_info_entry *entry;
  1411. if (! snd_card_proc_new(rme32->card, "rme32", &entry))
  1412. snd_info_set_text_ops(entry, rme32, snd_rme32_proc_read);
  1413. }
  1414. /*
  1415. * control interface
  1416. */
  1417. static int
  1418. snd_rme32_info_loopback_control(struct snd_kcontrol *kcontrol,
  1419. struct snd_ctl_elem_info *uinfo)
  1420. {
  1421. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1422. uinfo->count = 1;
  1423. uinfo->value.integer.min = 0;
  1424. uinfo->value.integer.max = 1;
  1425. return 0;
  1426. }
  1427. static int
  1428. snd_rme32_get_loopback_control(struct snd_kcontrol *kcontrol,
  1429. struct snd_ctl_elem_value *ucontrol)
  1430. {
  1431. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1432. spin_lock_irq(&rme32->lock);
  1433. ucontrol->value.integer.value[0] =
  1434. rme32->wcreg & RME32_WCR_SEL ? 0 : 1;
  1435. spin_unlock_irq(&rme32->lock);
  1436. return 0;
  1437. }
  1438. static int
  1439. snd_rme32_put_loopback_control(struct snd_kcontrol *kcontrol,
  1440. struct snd_ctl_elem_value *ucontrol)
  1441. {
  1442. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1443. unsigned int val;
  1444. int change;
  1445. val = ucontrol->value.integer.value[0] ? 0 : RME32_WCR_SEL;
  1446. spin_lock_irq(&rme32->lock);
  1447. val = (rme32->wcreg & ~RME32_WCR_SEL) | val;
  1448. change = val != rme32->wcreg;
  1449. if (ucontrol->value.integer.value[0])
  1450. val &= ~RME32_WCR_MUTE;
  1451. else
  1452. val |= RME32_WCR_MUTE;
  1453. rme32->wcreg = val;
  1454. writel(val, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1455. spin_unlock_irq(&rme32->lock);
  1456. return change;
  1457. }
  1458. static int
  1459. snd_rme32_info_inputtype_control(struct snd_kcontrol *kcontrol,
  1460. struct snd_ctl_elem_info *uinfo)
  1461. {
  1462. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1463. static char *texts[4] = { "Optical", "Coaxial", "Internal", "XLR" };
  1464. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1465. uinfo->count = 1;
  1466. switch (rme32->pci->device) {
  1467. case PCI_DEVICE_ID_RME_DIGI32:
  1468. case PCI_DEVICE_ID_RME_DIGI32_8:
  1469. uinfo->value.enumerated.items = 3;
  1470. break;
  1471. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1472. uinfo->value.enumerated.items = 4;
  1473. break;
  1474. default:
  1475. snd_BUG();
  1476. break;
  1477. }
  1478. if (uinfo->value.enumerated.item >
  1479. uinfo->value.enumerated.items - 1) {
  1480. uinfo->value.enumerated.item =
  1481. uinfo->value.enumerated.items - 1;
  1482. }
  1483. strcpy(uinfo->value.enumerated.name,
  1484. texts[uinfo->value.enumerated.item]);
  1485. return 0;
  1486. }
  1487. static int
  1488. snd_rme32_get_inputtype_control(struct snd_kcontrol *kcontrol,
  1489. struct snd_ctl_elem_value *ucontrol)
  1490. {
  1491. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1492. unsigned int items = 3;
  1493. spin_lock_irq(&rme32->lock);
  1494. ucontrol->value.enumerated.item[0] = snd_rme32_getinputtype(rme32);
  1495. switch (rme32->pci->device) {
  1496. case PCI_DEVICE_ID_RME_DIGI32:
  1497. case PCI_DEVICE_ID_RME_DIGI32_8:
  1498. items = 3;
  1499. break;
  1500. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1501. items = 4;
  1502. break;
  1503. default:
  1504. snd_BUG();
  1505. break;
  1506. }
  1507. if (ucontrol->value.enumerated.item[0] >= items) {
  1508. ucontrol->value.enumerated.item[0] = items - 1;
  1509. }
  1510. spin_unlock_irq(&rme32->lock);
  1511. return 0;
  1512. }
  1513. static int
  1514. snd_rme32_put_inputtype_control(struct snd_kcontrol *kcontrol,
  1515. struct snd_ctl_elem_value *ucontrol)
  1516. {
  1517. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1518. unsigned int val;
  1519. int change, items = 3;
  1520. switch (rme32->pci->device) {
  1521. case PCI_DEVICE_ID_RME_DIGI32:
  1522. case PCI_DEVICE_ID_RME_DIGI32_8:
  1523. items = 3;
  1524. break;
  1525. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1526. items = 4;
  1527. break;
  1528. default:
  1529. snd_BUG();
  1530. break;
  1531. }
  1532. val = ucontrol->value.enumerated.item[0] % items;
  1533. spin_lock_irq(&rme32->lock);
  1534. change = val != (unsigned int)snd_rme32_getinputtype(rme32);
  1535. snd_rme32_setinputtype(rme32, val);
  1536. spin_unlock_irq(&rme32->lock);
  1537. return change;
  1538. }
  1539. static int
  1540. snd_rme32_info_clockmode_control(struct snd_kcontrol *kcontrol,
  1541. struct snd_ctl_elem_info *uinfo)
  1542. {
  1543. static char *texts[4] = { "AutoSync",
  1544. "Internal 32.0kHz",
  1545. "Internal 44.1kHz",
  1546. "Internal 48.0kHz" };
  1547. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1548. uinfo->count = 1;
  1549. uinfo->value.enumerated.items = 4;
  1550. if (uinfo->value.enumerated.item > 3) {
  1551. uinfo->value.enumerated.item = 3;
  1552. }
  1553. strcpy(uinfo->value.enumerated.name,
  1554. texts[uinfo->value.enumerated.item]);
  1555. return 0;
  1556. }
  1557. static int
  1558. snd_rme32_get_clockmode_control(struct snd_kcontrol *kcontrol,
  1559. struct snd_ctl_elem_value *ucontrol)
  1560. {
  1561. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1562. spin_lock_irq(&rme32->lock);
  1563. ucontrol->value.enumerated.item[0] = snd_rme32_getclockmode(rme32);
  1564. spin_unlock_irq(&rme32->lock);
  1565. return 0;
  1566. }
  1567. static int
  1568. snd_rme32_put_clockmode_control(struct snd_kcontrol *kcontrol,
  1569. struct snd_ctl_elem_value *ucontrol)
  1570. {
  1571. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1572. unsigned int val;
  1573. int change;
  1574. val = ucontrol->value.enumerated.item[0] % 3;
  1575. spin_lock_irq(&rme32->lock);
  1576. change = val != (unsigned int)snd_rme32_getclockmode(rme32);
  1577. snd_rme32_setclockmode(rme32, val);
  1578. spin_unlock_irq(&rme32->lock);
  1579. return change;
  1580. }
  1581. static u32 snd_rme32_convert_from_aes(struct snd_aes_iec958 * aes)
  1582. {
  1583. u32 val = 0;
  1584. val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? RME32_WCR_PRO : 0;
  1585. if (val & RME32_WCR_PRO)
  1586. val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1587. else
  1588. val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? RME32_WCR_EMP : 0;
  1589. return val;
  1590. }
  1591. static void snd_rme32_convert_to_aes(struct snd_aes_iec958 * aes, u32 val)
  1592. {
  1593. aes->status[0] = ((val & RME32_WCR_PRO) ? IEC958_AES0_PROFESSIONAL : 0);
  1594. if (val & RME32_WCR_PRO)
  1595. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
  1596. else
  1597. aes->status[0] |= (val & RME32_WCR_EMP) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
  1598. }
  1599. static int snd_rme32_control_spdif_info(struct snd_kcontrol *kcontrol,
  1600. struct snd_ctl_elem_info *uinfo)
  1601. {
  1602. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1603. uinfo->count = 1;
  1604. return 0;
  1605. }
  1606. static int snd_rme32_control_spdif_get(struct snd_kcontrol *kcontrol,
  1607. struct snd_ctl_elem_value *ucontrol)
  1608. {
  1609. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1610. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1611. rme32->wcreg_spdif);
  1612. return 0;
  1613. }
  1614. static int snd_rme32_control_spdif_put(struct snd_kcontrol *kcontrol,
  1615. struct snd_ctl_elem_value *ucontrol)
  1616. {
  1617. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1618. int change;
  1619. u32 val;
  1620. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1621. spin_lock_irq(&rme32->lock);
  1622. change = val != rme32->wcreg_spdif;
  1623. rme32->wcreg_spdif = val;
  1624. spin_unlock_irq(&rme32->lock);
  1625. return change;
  1626. }
  1627. static int snd_rme32_control_spdif_stream_info(struct snd_kcontrol *kcontrol,
  1628. struct snd_ctl_elem_info *uinfo)
  1629. {
  1630. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1631. uinfo->count = 1;
  1632. return 0;
  1633. }
  1634. static int snd_rme32_control_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1635. struct snd_ctl_elem_value *
  1636. ucontrol)
  1637. {
  1638. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1639. snd_rme32_convert_to_aes(&ucontrol->value.iec958,
  1640. rme32->wcreg_spdif_stream);
  1641. return 0;
  1642. }
  1643. static int snd_rme32_control_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1644. struct snd_ctl_elem_value *
  1645. ucontrol)
  1646. {
  1647. struct rme32 *rme32 = snd_kcontrol_chip(kcontrol);
  1648. int change;
  1649. u32 val;
  1650. val = snd_rme32_convert_from_aes(&ucontrol->value.iec958);
  1651. spin_lock_irq(&rme32->lock);
  1652. change = val != rme32->wcreg_spdif_stream;
  1653. rme32->wcreg_spdif_stream = val;
  1654. rme32->wcreg &= ~(RME32_WCR_PRO | RME32_WCR_EMP);
  1655. rme32->wcreg |= val;
  1656. writel(rme32->wcreg, rme32->iobase + RME32_IO_CONTROL_REGISTER);
  1657. spin_unlock_irq(&rme32->lock);
  1658. return change;
  1659. }
  1660. static int snd_rme32_control_spdif_mask_info(struct snd_kcontrol *kcontrol,
  1661. struct snd_ctl_elem_info *uinfo)
  1662. {
  1663. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1664. uinfo->count = 1;
  1665. return 0;
  1666. }
  1667. static int snd_rme32_control_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1668. struct snd_ctl_elem_value *
  1669. ucontrol)
  1670. {
  1671. ucontrol->value.iec958.status[0] = kcontrol->private_value;
  1672. return 0;
  1673. }
  1674. static struct snd_kcontrol_new snd_rme32_controls[] = {
  1675. {
  1676. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1677. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
  1678. .info = snd_rme32_control_spdif_info,
  1679. .get = snd_rme32_control_spdif_get,
  1680. .put = snd_rme32_control_spdif_put
  1681. },
  1682. {
  1683. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
  1684. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1685. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PCM_STREAM),
  1686. .info = snd_rme32_control_spdif_stream_info,
  1687. .get = snd_rme32_control_spdif_stream_get,
  1688. .put = snd_rme32_control_spdif_stream_put
  1689. },
  1690. {
  1691. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1692. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1693. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, CON_MASK),
  1694. .info = snd_rme32_control_spdif_mask_info,
  1695. .get = snd_rme32_control_spdif_mask_get,
  1696. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_CON_EMPHASIS
  1697. },
  1698. {
  1699. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1700. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1701. .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, PRO_MASK),
  1702. .info = snd_rme32_control_spdif_mask_info,
  1703. .get = snd_rme32_control_spdif_mask_get,
  1704. .private_value = IEC958_AES0_PROFESSIONAL | IEC958_AES0_PRO_EMPHASIS
  1705. },
  1706. {
  1707. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1708. .name = "Input Connector",
  1709. .info = snd_rme32_info_inputtype_control,
  1710. .get = snd_rme32_get_inputtype_control,
  1711. .put = snd_rme32_put_inputtype_control
  1712. },
  1713. {
  1714. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1715. .name = "Loopback Input",
  1716. .info = snd_rme32_info_loopback_control,
  1717. .get = snd_rme32_get_loopback_control,
  1718. .put = snd_rme32_put_loopback_control
  1719. },
  1720. {
  1721. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1722. .name = "Sample Clock Source",
  1723. .info = snd_rme32_info_clockmode_control,
  1724. .get = snd_rme32_get_clockmode_control,
  1725. .put = snd_rme32_put_clockmode_control
  1726. }
  1727. };
  1728. static int snd_rme32_create_switches(struct snd_card *card, struct rme32 * rme32)
  1729. {
  1730. int idx, err;
  1731. struct snd_kcontrol *kctl;
  1732. for (idx = 0; idx < (int)ARRAY_SIZE(snd_rme32_controls); idx++) {
  1733. if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_rme32_controls[idx], rme32))) < 0)
  1734. return err;
  1735. if (idx == 1) /* IEC958 (S/PDIF) Stream */
  1736. rme32->spdif_ctl = kctl;
  1737. }
  1738. return 0;
  1739. }
  1740. /*
  1741. * Card initialisation
  1742. */
  1743. static void snd_rme32_card_free(struct snd_card *card)
  1744. {
  1745. snd_rme32_free(card->private_data);
  1746. }
  1747. static int __devinit
  1748. snd_rme32_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1749. {
  1750. static int dev;
  1751. struct rme32 *rme32;
  1752. struct snd_card *card;
  1753. int err;
  1754. if (dev >= SNDRV_CARDS) {
  1755. return -ENODEV;
  1756. }
  1757. if (!enable[dev]) {
  1758. dev++;
  1759. return -ENOENT;
  1760. }
  1761. if ((card = snd_card_new(index[dev], id[dev], THIS_MODULE,
  1762. sizeof(struct rme32))) == NULL)
  1763. return -ENOMEM;
  1764. card->private_free = snd_rme32_card_free;
  1765. rme32 = (struct rme32 *) card->private_data;
  1766. rme32->card = card;
  1767. rme32->pci = pci;
  1768. snd_card_set_dev(card, &pci->dev);
  1769. if (fullduplex[dev])
  1770. rme32->fullduplex_mode = 1;
  1771. if ((err = snd_rme32_create(rme32)) < 0) {
  1772. snd_card_free(card);
  1773. return err;
  1774. }
  1775. strcpy(card->driver, "Digi32");
  1776. switch (rme32->pci->device) {
  1777. case PCI_DEVICE_ID_RME_DIGI32:
  1778. strcpy(card->shortname, "RME Digi32");
  1779. break;
  1780. case PCI_DEVICE_ID_RME_DIGI32_8:
  1781. strcpy(card->shortname, "RME Digi32/8");
  1782. break;
  1783. case PCI_DEVICE_ID_RME_DIGI32_PRO:
  1784. strcpy(card->shortname, "RME Digi32 PRO");
  1785. break;
  1786. }
  1787. sprintf(card->longname, "%s (Rev. %d) at 0x%lx, irq %d",
  1788. card->shortname, rme32->rev, rme32->port, rme32->irq);
  1789. if ((err = snd_card_register(card)) < 0) {
  1790. snd_card_free(card);
  1791. return err;
  1792. }
  1793. pci_set_drvdata(pci, card);
  1794. dev++;
  1795. return 0;
  1796. }
  1797. static void __devexit snd_rme32_remove(struct pci_dev *pci)
  1798. {
  1799. snd_card_free(pci_get_drvdata(pci));
  1800. pci_set_drvdata(pci, NULL);
  1801. }
  1802. static struct pci_driver driver = {
  1803. .name = "RME Digi32",
  1804. .id_table = snd_rme32_ids,
  1805. .probe = snd_rme32_probe,
  1806. .remove = __devexit_p(snd_rme32_remove),
  1807. };
  1808. static int __init alsa_card_rme32_init(void)
  1809. {
  1810. return pci_register_driver(&driver);
  1811. }
  1812. static void __exit alsa_card_rme32_exit(void)
  1813. {
  1814. pci_unregister_driver(&driver);
  1815. }
  1816. module_init(alsa_card_rme32_init)
  1817. module_exit(alsa_card_rme32_exit)