pcxhr_core.c 35 KB

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  1. /*
  2. * Driver for Digigram pcxhr compatible soundcards
  3. *
  4. * low level interface with interrupt and message handling implementation
  5. *
  6. * Copyright (c) 2004 by Digigram <alsa@digigram.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/firmware.h>
  25. #include <linux/interrupt.h>
  26. #include <asm/io.h>
  27. #include <sound/core.h>
  28. #include "pcxhr.h"
  29. #include "pcxhr_mixer.h"
  30. #include "pcxhr_hwdep.h"
  31. #include "pcxhr_core.h"
  32. /* registers used on the PLX (port 1) */
  33. #define PCXHR_PLX_OFFSET_MIN 0x40
  34. #define PCXHR_PLX_MBOX0 0x40
  35. #define PCXHR_PLX_MBOX1 0x44
  36. #define PCXHR_PLX_MBOX2 0x48
  37. #define PCXHR_PLX_MBOX3 0x4C
  38. #define PCXHR_PLX_MBOX4 0x50
  39. #define PCXHR_PLX_MBOX5 0x54
  40. #define PCXHR_PLX_MBOX6 0x58
  41. #define PCXHR_PLX_MBOX7 0x5C
  42. #define PCXHR_PLX_L2PCIDB 0x64
  43. #define PCXHR_PLX_IRQCS 0x68
  44. #define PCXHR_PLX_CHIPSC 0x6C
  45. /* registers used on the DSP (port 2) */
  46. #define PCXHR_DSP_ICR 0x00
  47. #define PCXHR_DSP_CVR 0x04
  48. #define PCXHR_DSP_ISR 0x08
  49. #define PCXHR_DSP_IVR 0x0C
  50. #define PCXHR_DSP_RXH 0x14
  51. #define PCXHR_DSP_TXH 0x14
  52. #define PCXHR_DSP_RXM 0x18
  53. #define PCXHR_DSP_TXM 0x18
  54. #define PCXHR_DSP_RXL 0x1C
  55. #define PCXHR_DSP_TXL 0x1C
  56. #define PCXHR_DSP_RESET 0x20
  57. #define PCXHR_DSP_OFFSET_MAX 0x20
  58. /* access to the card */
  59. #define PCXHR_PLX 1
  60. #define PCXHR_DSP 2
  61. #if (PCXHR_DSP_OFFSET_MAX > PCXHR_PLX_OFFSET_MIN)
  62. #undef PCXHR_REG_TO_PORT(x)
  63. #else
  64. #define PCXHR_REG_TO_PORT(x) ((x)>PCXHR_DSP_OFFSET_MAX ? PCXHR_PLX : PCXHR_DSP)
  65. #endif
  66. #define PCXHR_INPB(mgr,x) inb((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
  67. #define PCXHR_INPL(mgr,x) inl((mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
  68. #define PCXHR_OUTPB(mgr,x,data) outb((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
  69. #define PCXHR_OUTPL(mgr,x,data) outl((data), (mgr)->port[PCXHR_REG_TO_PORT(x)] + (x))
  70. /* attention : access the PCXHR_DSP_* registers with inb and outb only ! */
  71. /* params used with PCXHR_PLX_MBOX0 */
  72. #define PCXHR_MBOX0_HF5 (1 << 0)
  73. #define PCXHR_MBOX0_HF4 (1 << 1)
  74. #define PCXHR_MBOX0_BOOT_HERE (1 << 23)
  75. /* params used with PCXHR_PLX_IRQCS */
  76. #define PCXHR_IRQCS_ENABLE_PCIIRQ (1 << 8)
  77. #define PCXHR_IRQCS_ENABLE_PCIDB (1 << 9)
  78. #define PCXHR_IRQCS_ACTIVE_PCIDB (1 << 13)
  79. /* params used with PCXHR_PLX_CHIPSC */
  80. #define PCXHR_CHIPSC_INIT_VALUE 0x100D767E
  81. #define PCXHR_CHIPSC_RESET_XILINX (1 << 16)
  82. #define PCXHR_CHIPSC_GPI_USERI (1 << 17)
  83. #define PCXHR_CHIPSC_DATA_CLK (1 << 24)
  84. #define PCXHR_CHIPSC_DATA_IN (1 << 26)
  85. /* params used with PCXHR_DSP_ICR */
  86. #define PCXHR_ICR_HI08_RREQ 0x01
  87. #define PCXHR_ICR_HI08_TREQ 0x02
  88. #define PCXHR_ICR_HI08_HDRQ 0x04
  89. #define PCXHR_ICR_HI08_HF0 0x08
  90. #define PCXHR_ICR_HI08_HF1 0x10
  91. #define PCXHR_ICR_HI08_HLEND 0x20
  92. #define PCXHR_ICR_HI08_INIT 0x80
  93. /* params used with PCXHR_DSP_CVR */
  94. #define PCXHR_CVR_HI08_HC 0x80
  95. /* params used with PCXHR_DSP_ISR */
  96. #define PCXHR_ISR_HI08_RXDF 0x01
  97. #define PCXHR_ISR_HI08_TXDE 0x02
  98. #define PCXHR_ISR_HI08_TRDY 0x04
  99. #define PCXHR_ISR_HI08_ERR 0x08
  100. #define PCXHR_ISR_HI08_CHK 0x10
  101. #define PCXHR_ISR_HI08_HREQ 0x80
  102. /* constants used for delay in msec */
  103. #define PCXHR_WAIT_DEFAULT 2
  104. #define PCXHR_WAIT_IT 25
  105. #define PCXHR_WAIT_IT_EXTRA 65
  106. /*
  107. * pcxhr_check_reg_bit - wait for the specified bit is set/reset on a register
  108. * @reg: register to check
  109. * @mask: bit mask
  110. * @bit: resultant bit to be checked
  111. * @time: time-out of loop in msec
  112. *
  113. * returns zero if a bit matches, or a negative error code.
  114. */
  115. static int pcxhr_check_reg_bit(struct pcxhr_mgr *mgr, unsigned int reg,
  116. unsigned char mask, unsigned char bit, int time,
  117. unsigned char* read)
  118. {
  119. int i = 0;
  120. unsigned long end_time = jiffies + (time * HZ + 999) / 1000;
  121. do {
  122. *read = PCXHR_INPB(mgr, reg);
  123. if ((*read & mask) == bit) {
  124. if (i > 100)
  125. snd_printdd("ATTENTION! check_reg(%x) loopcount=%d\n",
  126. reg, i);
  127. return 0;
  128. }
  129. i++;
  130. } while (time_after_eq(end_time, jiffies));
  131. snd_printk(KERN_ERR "pcxhr_check_reg_bit: timeout, reg=%x, mask=0x%x, val=0x%x\n",
  132. reg, mask, *read);
  133. return -EIO;
  134. }
  135. /* constants used with pcxhr_check_reg_bit() */
  136. #define PCXHR_TIMEOUT_DSP 200
  137. #define PCXHR_MASK_EXTRA_INFO 0x0000FE
  138. #define PCXHR_MASK_IT_HF0 0x000100
  139. #define PCXHR_MASK_IT_HF1 0x000200
  140. #define PCXHR_MASK_IT_NO_HF0_HF1 0x000400
  141. #define PCXHR_MASK_IT_MANAGE_HF5 0x000800
  142. #define PCXHR_MASK_IT_WAIT 0x010000
  143. #define PCXHR_MASK_IT_WAIT_EXTRA 0x020000
  144. #define PCXHR_IT_SEND_BYTE_XILINX (0x0000003C | PCXHR_MASK_IT_HF0)
  145. #define PCXHR_IT_TEST_XILINX (0x0000003C | PCXHR_MASK_IT_HF1 | \
  146. PCXHR_MASK_IT_MANAGE_HF5)
  147. #define PCXHR_IT_DOWNLOAD_BOOT (0x0000000C | PCXHR_MASK_IT_HF1 | \
  148. PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT)
  149. #define PCXHR_IT_RESET_BOARD_FUNC (0x0000000C | PCXHR_MASK_IT_HF0 | \
  150. PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT_EXTRA)
  151. #define PCXHR_IT_DOWNLOAD_DSP (0x0000000C | \
  152. PCXHR_MASK_IT_MANAGE_HF5 | PCXHR_MASK_IT_WAIT)
  153. #define PCXHR_IT_DEBUG (0x0000005A | PCXHR_MASK_IT_NO_HF0_HF1)
  154. #define PCXHR_IT_RESET_SEMAPHORE (0x0000005C | PCXHR_MASK_IT_NO_HF0_HF1)
  155. #define PCXHR_IT_MESSAGE (0x00000074 | PCXHR_MASK_IT_NO_HF0_HF1)
  156. #define PCXHR_IT_RESET_CHK (0x00000076 | PCXHR_MASK_IT_NO_HF0_HF1)
  157. #define PCXHR_IT_UPDATE_RBUFFER (0x00000078 | PCXHR_MASK_IT_NO_HF0_HF1)
  158. static int pcxhr_send_it_dsp(struct pcxhr_mgr *mgr, unsigned int itdsp, int atomic)
  159. {
  160. int err;
  161. unsigned char reg;
  162. if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
  163. /* clear hf5 bit */
  164. PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0,
  165. PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5);
  166. }
  167. if ((itdsp & PCXHR_MASK_IT_NO_HF0_HF1) == 0) {
  168. reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ;
  169. if (itdsp & PCXHR_MASK_IT_HF0)
  170. reg |= PCXHR_ICR_HI08_HF0;
  171. if (itdsp & PCXHR_MASK_IT_HF1)
  172. reg |= PCXHR_ICR_HI08_HF1;
  173. PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
  174. }
  175. reg = (unsigned char)(((itdsp & PCXHR_MASK_EXTRA_INFO) >> 1) | PCXHR_CVR_HI08_HC);
  176. PCXHR_OUTPB(mgr, PCXHR_DSP_CVR, reg);
  177. if (itdsp & PCXHR_MASK_IT_WAIT) {
  178. if (atomic)
  179. mdelay(PCXHR_WAIT_IT);
  180. else
  181. msleep(PCXHR_WAIT_IT);
  182. }
  183. if (itdsp & PCXHR_MASK_IT_WAIT_EXTRA) {
  184. if (atomic)
  185. mdelay(PCXHR_WAIT_IT_EXTRA);
  186. else
  187. msleep(PCXHR_WAIT_IT);
  188. }
  189. /* wait for CVR_HI08_HC == 0 */
  190. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_CVR, PCXHR_CVR_HI08_HC, 0,
  191. PCXHR_TIMEOUT_DSP, &reg);
  192. if (err) {
  193. snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT CVR\n");
  194. return err;
  195. }
  196. if (itdsp & PCXHR_MASK_IT_MANAGE_HF5) {
  197. /* wait for hf5 bit */
  198. err = pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5,
  199. PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &reg);
  200. if (err) {
  201. snd_printk(KERN_ERR "pcxhr_send_it_dsp : TIMEOUT HF5\n");
  202. return err;
  203. }
  204. }
  205. return 0; /* retry not handled here */
  206. }
  207. void pcxhr_reset_xilinx_com(struct pcxhr_mgr *mgr)
  208. {
  209. /* reset second xilinx */
  210. PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC,
  211. PCXHR_CHIPSC_INIT_VALUE & ~PCXHR_CHIPSC_RESET_XILINX);
  212. }
  213. static void pcxhr_enable_irq(struct pcxhr_mgr *mgr, int enable)
  214. {
  215. unsigned int reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS);
  216. /* enable/disable interrupts */
  217. if (enable)
  218. reg |= (PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB);
  219. else
  220. reg &= ~(PCXHR_IRQCS_ENABLE_PCIIRQ | PCXHR_IRQCS_ENABLE_PCIDB);
  221. PCXHR_OUTPL(mgr, PCXHR_PLX_IRQCS, reg);
  222. }
  223. void pcxhr_reset_dsp(struct pcxhr_mgr *mgr)
  224. {
  225. /* disable interrupts */
  226. pcxhr_enable_irq(mgr, 0);
  227. /* let's reset the DSP */
  228. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 0);
  229. msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
  230. PCXHR_OUTPB(mgr, PCXHR_DSP_RESET, 3);
  231. msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
  232. /* reset mailbox */
  233. PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0, 0);
  234. }
  235. void pcxhr_enable_dsp(struct pcxhr_mgr *mgr)
  236. {
  237. /* enable interrupts */
  238. pcxhr_enable_irq(mgr, 1);
  239. }
  240. /*
  241. * load the xilinx image
  242. */
  243. int pcxhr_load_xilinx_binary(struct pcxhr_mgr *mgr, const struct firmware *xilinx, int second)
  244. {
  245. unsigned int i;
  246. unsigned int chipsc;
  247. unsigned char data;
  248. unsigned char mask;
  249. unsigned char *image;
  250. /* test first xilinx */
  251. chipsc = PCXHR_INPL(mgr, PCXHR_PLX_CHIPSC);
  252. /* REV01 cards do not support the PCXHR_CHIPSC_GPI_USERI bit anymore */
  253. /* this bit will always be 1; no possibility to test presence of first xilinx */
  254. if(second) {
  255. if ((chipsc & PCXHR_CHIPSC_GPI_USERI) == 0) {
  256. snd_printk(KERN_ERR "error loading first xilinx\n");
  257. return -EINVAL;
  258. }
  259. /* activate second xilinx */
  260. chipsc |= PCXHR_CHIPSC_RESET_XILINX;
  261. PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
  262. msleep( PCXHR_WAIT_DEFAULT ); /* wait 2 msec */
  263. }
  264. image = xilinx->data;
  265. for (i = 0; i < xilinx->size; i++, image++) {
  266. data = *image;
  267. mask = 0x80;
  268. while (mask) {
  269. chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN);
  270. if (data & mask)
  271. chipsc |= PCXHR_CHIPSC_DATA_IN;
  272. PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
  273. chipsc |= PCXHR_CHIPSC_DATA_CLK;
  274. PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
  275. mask >>= 1;
  276. }
  277. /* don't take too much time in this loop... */
  278. cond_resched();
  279. }
  280. chipsc &= ~(PCXHR_CHIPSC_DATA_CLK | PCXHR_CHIPSC_DATA_IN);
  281. PCXHR_OUTPL(mgr, PCXHR_PLX_CHIPSC, chipsc);
  282. /* wait 2 msec (time to boot the xilinx before any access) */
  283. msleep( PCXHR_WAIT_DEFAULT );
  284. return 0;
  285. }
  286. /*
  287. * send an executable file to the DSP
  288. */
  289. static int pcxhr_download_dsp(struct pcxhr_mgr *mgr, const struct firmware *dsp)
  290. {
  291. int err;
  292. unsigned int i;
  293. unsigned int len;
  294. unsigned char *data;
  295. unsigned char dummy;
  296. /* check the length of boot image */
  297. snd_assert(dsp->size > 0, return -EINVAL);
  298. snd_assert(dsp->size % 3 == 0, return -EINVAL);
  299. snd_assert(dsp->data, return -EINVAL);
  300. /* transfert data buffer from PC to DSP */
  301. for (i = 0; i < dsp->size; i += 3) {
  302. data = dsp->data + i;
  303. if (i == 0) {
  304. /* test data header consistency */
  305. len = (unsigned int)((data[0]<<16) + (data[1]<<8) + data[2]);
  306. snd_assert((len==0) || (dsp->size == (len+2)*3), return -EINVAL);
  307. }
  308. /* wait DSP ready for new transfer */
  309. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
  310. PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &dummy);
  311. if (err) {
  312. snd_printk(KERN_ERR "dsp loading error at position %d\n", i);
  313. return err;
  314. }
  315. /* send host data */
  316. PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, data[0]);
  317. PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, data[1]);
  318. PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, data[2]);
  319. /* don't take too much time in this loop... */
  320. cond_resched();
  321. }
  322. /* give some time to boot the DSP */
  323. msleep(PCXHR_WAIT_DEFAULT);
  324. return 0;
  325. }
  326. /*
  327. * load the eeprom image
  328. */
  329. int pcxhr_load_eeprom_binary(struct pcxhr_mgr *mgr, const struct firmware *eeprom)
  330. {
  331. int err;
  332. unsigned char reg;
  333. /* init value of the ICR register */
  334. reg = PCXHR_ICR_HI08_RREQ | PCXHR_ICR_HI08_TREQ | PCXHR_ICR_HI08_HDRQ;
  335. if (PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & PCXHR_MBOX0_BOOT_HERE) {
  336. /* no need to load the eeprom binary, but init the HI08 interface */
  337. PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg | PCXHR_ICR_HI08_INIT);
  338. msleep(PCXHR_WAIT_DEFAULT);
  339. PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
  340. msleep(PCXHR_WAIT_DEFAULT);
  341. snd_printdd("no need to load eeprom boot\n");
  342. return 0;
  343. }
  344. PCXHR_OUTPB(mgr, PCXHR_DSP_ICR, reg);
  345. err = pcxhr_download_dsp(mgr, eeprom);
  346. if (err)
  347. return err;
  348. /* wait for chk bit */
  349. return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
  350. PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
  351. }
  352. /*
  353. * load the boot image
  354. */
  355. int pcxhr_load_boot_binary(struct pcxhr_mgr *mgr, const struct firmware *boot)
  356. {
  357. int err;
  358. unsigned int physaddr = mgr->hostport.addr;
  359. unsigned char dummy;
  360. /* send the hostport address to the DSP (only the upper 24 bit !) */
  361. snd_assert((physaddr & 0xff) == 0, return -EINVAL);
  362. PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX1, (physaddr >> 8));
  363. err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_BOOT, 0);
  364. if (err)
  365. return err;
  366. /* clear hf5 bit */
  367. PCXHR_OUTPL(mgr, PCXHR_PLX_MBOX0,
  368. PCXHR_INPL(mgr, PCXHR_PLX_MBOX0) & ~PCXHR_MBOX0_HF5);
  369. err = pcxhr_download_dsp(mgr, boot);
  370. if (err)
  371. return err;
  372. /* wait for hf5 bit */
  373. return pcxhr_check_reg_bit(mgr, PCXHR_PLX_MBOX0, PCXHR_MBOX0_HF5,
  374. PCXHR_MBOX0_HF5, PCXHR_TIMEOUT_DSP, &dummy);
  375. }
  376. /*
  377. * load the final dsp image
  378. */
  379. int pcxhr_load_dsp_binary(struct pcxhr_mgr *mgr, const struct firmware *dsp)
  380. {
  381. int err;
  382. unsigned char dummy;
  383. err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_BOARD_FUNC, 0);
  384. if (err)
  385. return err;
  386. err = pcxhr_send_it_dsp(mgr, PCXHR_IT_DOWNLOAD_DSP, 0);
  387. if (err)
  388. return err;
  389. err = pcxhr_download_dsp(mgr, dsp);
  390. if (err)
  391. return err;
  392. /* wait for chk bit */
  393. return pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
  394. PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &dummy);
  395. }
  396. struct pcxhr_cmd_info {
  397. u32 opcode; /* command word */
  398. u16 st_length; /* status length */
  399. u16 st_type; /* status type (RMH_SSIZE_XXX) */
  400. };
  401. /* RMH status type */
  402. enum {
  403. RMH_SSIZE_FIXED = 0, /* status size fix (st_length = 0..x) */
  404. RMH_SSIZE_ARG = 1, /* status size given in the LSB byte (used with st_length = 1) */
  405. RMH_SSIZE_MASK = 2, /* status size given in bitmask (used with st_length = 1) */
  406. };
  407. /*
  408. * Array of DSP commands
  409. */
  410. static struct pcxhr_cmd_info pcxhr_dsp_cmds[] = {
  411. [CMD_VERSION] = { 0x010000, 1, RMH_SSIZE_FIXED },
  412. [CMD_SUPPORTED] = { 0x020000, 4, RMH_SSIZE_FIXED },
  413. [CMD_TEST_IT] = { 0x040000, 1, RMH_SSIZE_FIXED },
  414. [CMD_SEND_IRQA] = { 0x070001, 0, RMH_SSIZE_FIXED },
  415. [CMD_ACCESS_IO_WRITE] = { 0x090000, 1, RMH_SSIZE_ARG },
  416. [CMD_ACCESS_IO_READ] = { 0x094000, 1, RMH_SSIZE_ARG },
  417. [CMD_ASYNC] = { 0x0a0000, 1, RMH_SSIZE_ARG },
  418. [CMD_MODIFY_CLOCK] = { 0x0d0000, 0, RMH_SSIZE_FIXED },
  419. [CMD_RESYNC_AUDIO_INPUTS] = { 0x0e0000, 0, RMH_SSIZE_FIXED },
  420. [CMD_GET_DSP_RESOURCES] = { 0x100000, 4, RMH_SSIZE_FIXED },
  421. [CMD_SET_TIMER_INTERRUPT] = { 0x110000, 0, RMH_SSIZE_FIXED },
  422. [CMD_RES_PIPE] = { 0x400000, 0, RMH_SSIZE_FIXED },
  423. [CMD_FREE_PIPE] = { 0x410000, 0, RMH_SSIZE_FIXED },
  424. [CMD_CONF_PIPE] = { 0x422101, 0, RMH_SSIZE_FIXED },
  425. [CMD_STOP_PIPE] = { 0x470004, 0, RMH_SSIZE_FIXED },
  426. [CMD_PIPE_SAMPLE_COUNT] = { 0x49a000, 2, RMH_SSIZE_FIXED },
  427. [CMD_CAN_START_PIPE] = { 0x4b0000, 1, RMH_SSIZE_FIXED },
  428. [CMD_START_STREAM] = { 0x802000, 0, RMH_SSIZE_FIXED },
  429. [CMD_STREAM_OUT_LEVEL_ADJUST] = { 0x822000, 0, RMH_SSIZE_FIXED },
  430. [CMD_STOP_STREAM] = { 0x832000, 0, RMH_SSIZE_FIXED },
  431. [CMD_UPDATE_R_BUFFERS] = { 0x840000, 0, RMH_SSIZE_FIXED },
  432. [CMD_FORMAT_STREAM_OUT] = { 0x860000, 0, RMH_SSIZE_FIXED },
  433. [CMD_FORMAT_STREAM_IN] = { 0x870000, 0, RMH_SSIZE_FIXED },
  434. [CMD_STREAM_SAMPLE_COUNT] = { 0x902000, 2, RMH_SSIZE_FIXED }, /* stat_len = nb_streams * 2 */
  435. [CMD_AUDIO_LEVEL_ADJUST] = { 0xc22000, 0, RMH_SSIZE_FIXED },
  436. };
  437. #ifdef CONFIG_SND_DEBUG_DETECT
  438. static char* cmd_names[] = {
  439. [CMD_VERSION] = "CMD_VERSION",
  440. [CMD_SUPPORTED] = "CMD_SUPPORTED",
  441. [CMD_TEST_IT] = "CMD_TEST_IT",
  442. [CMD_SEND_IRQA] = "CMD_SEND_IRQA",
  443. [CMD_ACCESS_IO_WRITE] = "CMD_ACCESS_IO_WRITE",
  444. [CMD_ACCESS_IO_READ] = "CMD_ACCESS_IO_READ",
  445. [CMD_ASYNC] = "CMD_ASYNC",
  446. [CMD_MODIFY_CLOCK] = "CMD_MODIFY_CLOCK",
  447. [CMD_RESYNC_AUDIO_INPUTS] = "CMD_RESYNC_AUDIO_INPUTS",
  448. [CMD_GET_DSP_RESOURCES] = "CMD_GET_DSP_RESOURCES",
  449. [CMD_SET_TIMER_INTERRUPT] = "CMD_SET_TIMER_INTERRUPT",
  450. [CMD_RES_PIPE] = "CMD_RES_PIPE",
  451. [CMD_FREE_PIPE] = "CMD_FREE_PIPE",
  452. [CMD_CONF_PIPE] = "CMD_CONF_PIPE",
  453. [CMD_STOP_PIPE] = "CMD_STOP_PIPE",
  454. [CMD_PIPE_SAMPLE_COUNT] = "CMD_PIPE_SAMPLE_COUNT",
  455. [CMD_CAN_START_PIPE] = "CMD_CAN_START_PIPE",
  456. [CMD_START_STREAM] = "CMD_START_STREAM",
  457. [CMD_STREAM_OUT_LEVEL_ADJUST] = "CMD_STREAM_OUT_LEVEL_ADJUST",
  458. [CMD_STOP_STREAM] = "CMD_STOP_STREAM",
  459. [CMD_UPDATE_R_BUFFERS] = "CMD_UPDATE_R_BUFFERS",
  460. [CMD_FORMAT_STREAM_OUT] = "CMD_FORMAT_STREAM_OUT",
  461. [CMD_FORMAT_STREAM_IN] = "CMD_FORMAT_STREAM_IN",
  462. [CMD_STREAM_SAMPLE_COUNT] = "CMD_STREAM_SAMPLE_COUNT",
  463. [CMD_AUDIO_LEVEL_ADJUST] = "CMD_AUDIO_LEVEL_ADJUST",
  464. };
  465. #endif
  466. static int pcxhr_read_rmh_status(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
  467. {
  468. int err;
  469. int i;
  470. u32 data;
  471. u32 size_mask;
  472. unsigned char reg;
  473. int max_stat_len;
  474. if (rmh->stat_len < PCXHR_SIZE_MAX_STATUS)
  475. max_stat_len = PCXHR_SIZE_MAX_STATUS;
  476. else max_stat_len = rmh->stat_len;
  477. for (i = 0; i < rmh->stat_len; i++) {
  478. /* wait for receiver full */
  479. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF,
  480. PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg);
  481. if (err) {
  482. snd_printk(KERN_ERR "ERROR RMH stat: ISR:RXDF=1 (ISR = %x; i=%d )\n",
  483. reg, i);
  484. return err;
  485. }
  486. /* read data */
  487. data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16;
  488. data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8;
  489. data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
  490. /* need to update rmh->stat_len on the fly ?? */
  491. if (i==0) {
  492. if (rmh->dsp_stat != RMH_SSIZE_FIXED) {
  493. if (rmh->dsp_stat == RMH_SSIZE_ARG) {
  494. rmh->stat_len = (u16)(data & 0x0000ff) + 1;
  495. data &= 0xffff00;
  496. } else {
  497. /* rmh->dsp_stat == RMH_SSIZE_MASK */
  498. rmh->stat_len = 1;
  499. size_mask = data;
  500. while (size_mask) {
  501. if (size_mask & 1)
  502. rmh->stat_len++;
  503. size_mask >>= 1;
  504. }
  505. }
  506. }
  507. }
  508. #ifdef CONFIG_SND_DEBUG_DETECT
  509. if (rmh->cmd_idx < CMD_LAST_INDEX)
  510. snd_printdd(" stat[%d]=%x\n", i, data);
  511. #endif
  512. if (i < max_stat_len)
  513. rmh->stat[i] = data;
  514. }
  515. if (rmh->stat_len > max_stat_len) {
  516. snd_printdd("PCXHR : rmh->stat_len=%x too big\n", rmh->stat_len);
  517. rmh->stat_len = max_stat_len;
  518. }
  519. return 0;
  520. }
  521. static int pcxhr_send_msg_nolock(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
  522. {
  523. int err;
  524. int i;
  525. u32 data;
  526. unsigned char reg;
  527. snd_assert(rmh->cmd_len<PCXHR_SIZE_MAX_CMD, return -EINVAL);
  528. err = pcxhr_send_it_dsp(mgr, PCXHR_IT_MESSAGE, 1);
  529. if (err) {
  530. snd_printk(KERN_ERR "pcxhr_send_message : ED_DSP_CRASHED\n");
  531. return err;
  532. }
  533. /* wait for chk bit */
  534. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
  535. PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
  536. if (err)
  537. return err;
  538. /* reset irq chk */
  539. err = pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_CHK, 1);
  540. if (err)
  541. return err;
  542. /* wait for chk bit == 0*/
  543. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK, 0,
  544. PCXHR_TIMEOUT_DSP, &reg);
  545. if (err)
  546. return err;
  547. data = rmh->cmd[0];
  548. if (rmh->cmd_len > 1)
  549. data |= 0x008000; /* MASK_MORE_THAN_1_WORD_COMMAND */
  550. else
  551. data &= 0xff7fff; /* MASK_1_WORD_COMMAND */
  552. #ifdef CONFIG_SND_DEBUG_DETECT
  553. if (rmh->cmd_idx < CMD_LAST_INDEX)
  554. snd_printdd("MSG cmd[0]=%x (%s)\n", data, cmd_names[rmh->cmd_idx]);
  555. #endif
  556. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
  557. PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg);
  558. if (err)
  559. return err;
  560. PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
  561. PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
  562. PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
  563. if (rmh->cmd_len > 1) {
  564. /* send length */
  565. data = rmh->cmd_len - 1;
  566. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_TRDY,
  567. PCXHR_ISR_HI08_TRDY, PCXHR_TIMEOUT_DSP, &reg);
  568. if (err)
  569. return err;
  570. PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
  571. PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
  572. PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
  573. for (i=1; i < rmh->cmd_len; i++) {
  574. /* send other words */
  575. data = rmh->cmd[i];
  576. #ifdef CONFIG_SND_DEBUG_DETECT
  577. if (rmh->cmd_idx < CMD_LAST_INDEX)
  578. snd_printdd(" cmd[%d]=%x\n", i, data);
  579. #endif
  580. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR,
  581. PCXHR_ISR_HI08_TRDY,
  582. PCXHR_ISR_HI08_TRDY,
  583. PCXHR_TIMEOUT_DSP, &reg);
  584. if (err)
  585. return err;
  586. PCXHR_OUTPB(mgr, PCXHR_DSP_TXH, (data>>16)&0xFF);
  587. PCXHR_OUTPB(mgr, PCXHR_DSP_TXM, (data>>8)&0xFF);
  588. PCXHR_OUTPB(mgr, PCXHR_DSP_TXL, (data&0xFF));
  589. }
  590. }
  591. /* wait for chk bit */
  592. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_CHK,
  593. PCXHR_ISR_HI08_CHK, PCXHR_TIMEOUT_DSP, &reg);
  594. if (err)
  595. return err;
  596. /* test status ISR */
  597. if (reg & PCXHR_ISR_HI08_ERR) {
  598. /* ERROR, wait for receiver full */
  599. err = pcxhr_check_reg_bit(mgr, PCXHR_DSP_ISR, PCXHR_ISR_HI08_RXDF,
  600. PCXHR_ISR_HI08_RXDF, PCXHR_TIMEOUT_DSP, &reg);
  601. if (err) {
  602. snd_printk(KERN_ERR "ERROR RMH: ISR:RXDF=1 (ISR = %x)\n", reg);
  603. return err;
  604. }
  605. /* read error code */
  606. data = PCXHR_INPB(mgr, PCXHR_DSP_TXH) << 16;
  607. data |= PCXHR_INPB(mgr, PCXHR_DSP_TXM) << 8;
  608. data |= PCXHR_INPB(mgr, PCXHR_DSP_TXL);
  609. snd_printk(KERN_ERR "ERROR RMH(%d): 0x%x\n", rmh->cmd_idx, data);
  610. err = -EINVAL;
  611. } else {
  612. /* read the response data */
  613. err = pcxhr_read_rmh_status(mgr, rmh);
  614. }
  615. /* reset semaphore */
  616. if (pcxhr_send_it_dsp(mgr, PCXHR_IT_RESET_SEMAPHORE, 1) < 0)
  617. return -EIO;
  618. return err;
  619. }
  620. /**
  621. * pcxhr_init_rmh - initialize the RMH instance
  622. * @rmh: the rmh pointer to be initialized
  623. * @cmd: the rmh command to be set
  624. */
  625. void pcxhr_init_rmh(struct pcxhr_rmh *rmh, int cmd)
  626. {
  627. snd_assert(cmd < CMD_LAST_INDEX, return);
  628. rmh->cmd[0] = pcxhr_dsp_cmds[cmd].opcode;
  629. rmh->cmd_len = 1;
  630. rmh->stat_len = pcxhr_dsp_cmds[cmd].st_length;
  631. rmh->dsp_stat = pcxhr_dsp_cmds[cmd].st_type;
  632. rmh->cmd_idx = cmd;
  633. }
  634. void pcxhr_set_pipe_cmd_params(struct pcxhr_rmh *rmh, int capture,
  635. unsigned int param1, unsigned int param2,
  636. unsigned int param3)
  637. {
  638. snd_assert(param1 <= MASK_FIRST_FIELD);
  639. if (capture)
  640. rmh->cmd[0] |= 0x800; /* COMMAND_RECORD_MASK */
  641. if (param1)
  642. rmh->cmd[0] |= (param1 << FIELD_SIZE);
  643. if (param2) {
  644. snd_assert(param2 <= MASK_FIRST_FIELD);
  645. rmh->cmd[0] |= param2;
  646. }
  647. if(param3) {
  648. snd_assert(param3 <= MASK_DSP_WORD);
  649. rmh->cmd[1] = param3;
  650. rmh->cmd_len = 2;
  651. }
  652. }
  653. /*
  654. * pcxhr_send_msg - send a DSP message with spinlock
  655. * @rmh: the rmh record to send and receive
  656. *
  657. * returns 0 if successful, or a negative error code.
  658. */
  659. int pcxhr_send_msg(struct pcxhr_mgr *mgr, struct pcxhr_rmh *rmh)
  660. {
  661. unsigned long flags;
  662. int err;
  663. spin_lock_irqsave(&mgr->msg_lock, flags);
  664. err = pcxhr_send_msg_nolock(mgr, rmh);
  665. spin_unlock_irqrestore(&mgr->msg_lock, flags);
  666. return err;
  667. }
  668. static inline int pcxhr_pipes_running(struct pcxhr_mgr *mgr)
  669. {
  670. int start_mask = PCXHR_INPL(mgr, PCXHR_PLX_MBOX2);
  671. /* least segnificant 12 bits are the pipe states for the playback audios */
  672. /* next 12 bits are the pipe states for the capture audios
  673. * (PCXHR_PIPE_STATE_CAPTURE_OFFSET)
  674. */
  675. start_mask &= 0xffffff;
  676. snd_printdd("CMD_PIPE_STATE MBOX2=0x%06x\n", start_mask);
  677. return start_mask;
  678. }
  679. #define PCXHR_PIPE_STATE_CAPTURE_OFFSET 12
  680. #define MAX_WAIT_FOR_DSP 20
  681. static int pcxhr_prepair_pipe_start(struct pcxhr_mgr *mgr, int audio_mask, int *retry)
  682. {
  683. struct pcxhr_rmh rmh;
  684. int err;
  685. int audio = 0;
  686. *retry = 0;
  687. while (audio_mask) {
  688. if (audio_mask & 1) {
  689. pcxhr_init_rmh(&rmh, CMD_CAN_START_PIPE);
  690. if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) {
  691. /* can start playback pipe */
  692. pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);
  693. } else {
  694. /* can start capture pipe */
  695. pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
  696. PCXHR_PIPE_STATE_CAPTURE_OFFSET,
  697. 0, 0);
  698. }
  699. err = pcxhr_send_msg(mgr, &rmh);
  700. if (err) {
  701. snd_printk(KERN_ERR
  702. "error pipe start (CMD_CAN_START_PIPE) err=%x!\n",
  703. err);
  704. return err;
  705. }
  706. /* if the pipe couldn't be prepaired for start, retry it later */
  707. if (rmh.stat[0] == 0)
  708. *retry |= (1<<audio);
  709. }
  710. audio_mask>>=1;
  711. audio++;
  712. }
  713. return 0;
  714. }
  715. static int pcxhr_stop_pipes(struct pcxhr_mgr *mgr, int audio_mask)
  716. {
  717. struct pcxhr_rmh rmh;
  718. int err;
  719. int audio = 0;
  720. while (audio_mask) {
  721. if (audio_mask & 1) {
  722. pcxhr_init_rmh(&rmh, CMD_STOP_PIPE);
  723. if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET) {
  724. /* stop playback pipe */
  725. pcxhr_set_pipe_cmd_params(&rmh, 0, audio, 0, 0);
  726. } else {
  727. /* stop capture pipe */
  728. pcxhr_set_pipe_cmd_params(&rmh, 1, audio -
  729. PCXHR_PIPE_STATE_CAPTURE_OFFSET,
  730. 0, 0);
  731. }
  732. err = pcxhr_send_msg(mgr, &rmh);
  733. if (err) {
  734. snd_printk(KERN_ERR
  735. "error pipe stop (CMD_STOP_PIPE) err=%x!\n",
  736. err);
  737. return err;
  738. }
  739. }
  740. audio_mask>>=1;
  741. audio++;
  742. }
  743. return 0;
  744. }
  745. static int pcxhr_toggle_pipes(struct pcxhr_mgr *mgr, int audio_mask)
  746. {
  747. struct pcxhr_rmh rmh;
  748. int err;
  749. int audio = 0;
  750. while (audio_mask) {
  751. if (audio_mask & 1) {
  752. pcxhr_init_rmh(&rmh, CMD_CONF_PIPE);
  753. if (audio < PCXHR_PIPE_STATE_CAPTURE_OFFSET)
  754. pcxhr_set_pipe_cmd_params(&rmh, 0, 0, 0, 1 << audio);
  755. else
  756. pcxhr_set_pipe_cmd_params(&rmh, 1, 0, 0,
  757. 1 << (audio - PCXHR_PIPE_STATE_CAPTURE_OFFSET));
  758. err = pcxhr_send_msg(mgr, &rmh);
  759. if (err) {
  760. snd_printk(KERN_ERR
  761. "error pipe start (CMD_CONF_PIPE) err=%x!\n",
  762. err);
  763. return err;
  764. }
  765. }
  766. audio_mask>>=1;
  767. audio++;
  768. }
  769. /* now fire the interrupt on the card */
  770. pcxhr_init_rmh(&rmh, CMD_SEND_IRQA);
  771. err = pcxhr_send_msg(mgr, &rmh);
  772. if (err) {
  773. snd_printk(KERN_ERR "error pipe start (CMD_SEND_IRQA) err=%x!\n", err );
  774. return err;
  775. }
  776. return 0;
  777. }
  778. int pcxhr_set_pipe_state(struct pcxhr_mgr *mgr, int playback_mask, int capture_mask, int start)
  779. {
  780. int state, i, err;
  781. int audio_mask;
  782. #ifdef CONFIG_SND_DEBUG_DETECT
  783. struct timeval my_tv1, my_tv2;
  784. do_gettimeofday(&my_tv1);
  785. #endif
  786. audio_mask = (playback_mask | (capture_mask << PCXHR_PIPE_STATE_CAPTURE_OFFSET));
  787. /* current pipe state (playback + record) */
  788. state = pcxhr_pipes_running(mgr);
  789. snd_printdd("pcxhr_set_pipe_state %s (mask %x current %x)\n",
  790. start ? "START" : "STOP", audio_mask, state);
  791. if (start) {
  792. audio_mask &= ~state; /* start only pipes that are not yet started */
  793. state = audio_mask;
  794. for (i = 0; i < MAX_WAIT_FOR_DSP; i++) {
  795. err = pcxhr_prepair_pipe_start(mgr, state, &state);
  796. if (err)
  797. return err;
  798. if (state == 0)
  799. break; /* success, all pipes prepaired for start */
  800. mdelay(1); /* otherwise wait 1 millisecond and retry */
  801. }
  802. } else {
  803. audio_mask &= state; /* stop only pipes that are started */
  804. }
  805. if (audio_mask == 0)
  806. return 0;
  807. err = pcxhr_toggle_pipes(mgr, audio_mask);
  808. if (err)
  809. return err;
  810. i = 0;
  811. while (1) {
  812. state = pcxhr_pipes_running(mgr);
  813. /* have all pipes the new state ? */
  814. if ((state & audio_mask) == (start ? audio_mask : 0))
  815. break;
  816. if (++i >= MAX_WAIT_FOR_DSP * 100) {
  817. snd_printk(KERN_ERR "error pipe start/stop (ED_NO_RESPONSE_AT_IRQA)\n");
  818. return -EBUSY;
  819. }
  820. udelay(10); /* wait 10 microseconds */
  821. }
  822. if (!start) {
  823. err = pcxhr_stop_pipes(mgr, audio_mask);
  824. if (err)
  825. return err;
  826. }
  827. #ifdef CONFIG_SND_DEBUG_DETECT
  828. do_gettimeofday(&my_tv2);
  829. snd_printdd("***SET PIPE STATE*** TIME = %ld (err = %x)\n",
  830. my_tv2.tv_usec - my_tv1.tv_usec, err);
  831. #endif
  832. return 0;
  833. }
  834. int pcxhr_write_io_num_reg_cont(struct pcxhr_mgr *mgr, unsigned int mask,
  835. unsigned int value, int *changed)
  836. {
  837. struct pcxhr_rmh rmh;
  838. unsigned long flags;
  839. int err;
  840. spin_lock_irqsave(&mgr->msg_lock, flags);
  841. if ((mgr->io_num_reg_cont & mask) == value) {
  842. snd_printdd("IO_NUM_REG_CONT mask %x already is set to %x\n", mask, value);
  843. if (changed)
  844. *changed = 0;
  845. spin_unlock_irqrestore(&mgr->msg_lock, flags);
  846. return 0; /* already programmed */
  847. }
  848. pcxhr_init_rmh(&rmh, CMD_ACCESS_IO_WRITE);
  849. rmh.cmd[0] |= IO_NUM_REG_CONT;
  850. rmh.cmd[1] = mask;
  851. rmh.cmd[2] = value;
  852. rmh.cmd_len = 3;
  853. err = pcxhr_send_msg_nolock(mgr, &rmh);
  854. if (err == 0) {
  855. mgr->io_num_reg_cont &= ~mask;
  856. mgr->io_num_reg_cont |= value;
  857. if (changed)
  858. *changed = 1;
  859. }
  860. spin_unlock_irqrestore(&mgr->msg_lock, flags);
  861. return err;
  862. }
  863. #define PCXHR_IRQ_TIMER 0x000300
  864. #define PCXHR_IRQ_FREQ_CHANGE 0x000800
  865. #define PCXHR_IRQ_TIME_CODE 0x001000
  866. #define PCXHR_IRQ_NOTIFY 0x002000
  867. #define PCXHR_IRQ_ASYNC 0x008000
  868. #define PCXHR_IRQ_MASK 0x00bb00
  869. #define PCXHR_FATAL_DSP_ERR 0xff0000
  870. enum pcxhr_async_err_src {
  871. PCXHR_ERR_PIPE,
  872. PCXHR_ERR_STREAM,
  873. PCXHR_ERR_AUDIO
  874. };
  875. static int pcxhr_handle_async_err(struct pcxhr_mgr *mgr, u32 err,
  876. enum pcxhr_async_err_src err_src, int pipe,
  877. int is_capture)
  878. {
  879. #ifdef CONFIG_SND_DEBUG_DETECT
  880. static char* err_src_name[] = {
  881. [PCXHR_ERR_PIPE] = "Pipe",
  882. [PCXHR_ERR_STREAM] = "Stream",
  883. [PCXHR_ERR_AUDIO] = "Audio"
  884. };
  885. #endif
  886. if (err & 0xfff)
  887. err &= 0xfff;
  888. else
  889. err = ((err >> 12) & 0xfff);
  890. if (!err)
  891. return 0;
  892. snd_printdd("CMD_ASYNC : Error %s %s Pipe %d err=%x\n", err_src_name[err_src],
  893. is_capture ? "Record" : "Play", pipe, err);
  894. if (err == 0xe01)
  895. mgr->async_err_stream_xrun++;
  896. else if (err == 0xe10)
  897. mgr->async_err_pipe_xrun++;
  898. else
  899. mgr->async_err_other_last = (int)err;
  900. return 1;
  901. }
  902. void pcxhr_msg_tasklet(unsigned long arg)
  903. {
  904. struct pcxhr_mgr *mgr = (struct pcxhr_mgr *)(arg);
  905. struct pcxhr_rmh *prmh = mgr->prmh;
  906. int err;
  907. int i, j;
  908. if (mgr->src_it_dsp & PCXHR_IRQ_FREQ_CHANGE)
  909. snd_printdd("TASKLET : PCXHR_IRQ_FREQ_CHANGE event occured\n");
  910. if (mgr->src_it_dsp & PCXHR_IRQ_TIME_CODE)
  911. snd_printdd("TASKLET : PCXHR_IRQ_TIME_CODE event occured\n");
  912. if (mgr->src_it_dsp & PCXHR_IRQ_NOTIFY)
  913. snd_printdd("TASKLET : PCXHR_IRQ_NOTIFY event occured\n");
  914. if (mgr->src_it_dsp & PCXHR_IRQ_ASYNC) {
  915. snd_printdd("TASKLET : PCXHR_IRQ_ASYNC event occured\n");
  916. pcxhr_init_rmh(prmh, CMD_ASYNC);
  917. prmh->cmd[0] |= 1; /* add SEL_ASYNC_EVENTS */
  918. /* this is the only one extra long response command */
  919. prmh->stat_len = PCXHR_SIZE_MAX_LONG_STATUS;
  920. err = pcxhr_send_msg(mgr, prmh);
  921. if (err)
  922. snd_printk(KERN_ERR "ERROR pcxhr_msg_tasklet=%x;\n", err);
  923. i = 1;
  924. while (i < prmh->stat_len) {
  925. int nb_audio = (prmh->stat[i] >> FIELD_SIZE) & MASK_FIRST_FIELD;
  926. int nb_stream = (prmh->stat[i] >> (2*FIELD_SIZE)) & MASK_FIRST_FIELD;
  927. int pipe = prmh->stat[i] & MASK_FIRST_FIELD;
  928. int is_capture = prmh->stat[i] & 0x400000;
  929. u32 err;
  930. if (prmh->stat[i] & 0x800000) { /* if BIT_END */
  931. snd_printdd("TASKLET : End%sPipe %d\n",
  932. is_capture ? "Record" : "Play", pipe);
  933. }
  934. i++;
  935. err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
  936. if (err)
  937. pcxhr_handle_async_err(mgr, err, PCXHR_ERR_PIPE,
  938. pipe, is_capture);
  939. i += 2;
  940. for (j = 0; j < nb_stream; j++) {
  941. err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
  942. if (err)
  943. pcxhr_handle_async_err(mgr, err, PCXHR_ERR_STREAM,
  944. pipe, is_capture);
  945. i += 2;
  946. }
  947. for (j = 0; j < nb_audio; j++) {
  948. err = prmh->stat[i] ? prmh->stat[i] : prmh->stat[i+1];
  949. if (err)
  950. pcxhr_handle_async_err(mgr, err, PCXHR_ERR_AUDIO,
  951. pipe, is_capture);
  952. i += 2;
  953. }
  954. }
  955. }
  956. }
  957. static u_int64_t pcxhr_stream_read_position(struct pcxhr_mgr *mgr,
  958. struct pcxhr_stream *stream)
  959. {
  960. u_int64_t hw_sample_count;
  961. struct pcxhr_rmh rmh;
  962. int err, stream_mask;
  963. stream_mask = stream->pipe->is_capture ? 1 : 1<<stream->substream->number;
  964. /* get sample count for one stream */
  965. pcxhr_init_rmh(&rmh, CMD_STREAM_SAMPLE_COUNT);
  966. pcxhr_set_pipe_cmd_params(&rmh, stream->pipe->is_capture,
  967. stream->pipe->first_audio, 0, stream_mask);
  968. /* rmh.stat_len = 2; */ /* 2 resp data for each stream of the pipe */
  969. err = pcxhr_send_msg(mgr, &rmh);
  970. if (err)
  971. return 0;
  972. hw_sample_count = ((u_int64_t)rmh.stat[0]) << 24;
  973. hw_sample_count += (u_int64_t)rmh.stat[1];
  974. snd_printdd("stream %c%d : abs samples real(%ld) timer(%ld)\n",
  975. stream->pipe->is_capture ? 'C':'P', stream->substream->number,
  976. (long unsigned int)hw_sample_count,
  977. (long unsigned int)(stream->timer_abs_periods +
  978. stream->timer_period_frag + PCXHR_GRANULARITY));
  979. return hw_sample_count;
  980. }
  981. static void pcxhr_update_timer_pos(struct pcxhr_mgr *mgr,
  982. struct pcxhr_stream *stream, int samples_to_add)
  983. {
  984. if (stream->substream && (stream->status == PCXHR_STREAM_STATUS_RUNNING)) {
  985. u_int64_t new_sample_count;
  986. int elapsed = 0;
  987. int hardware_read = 0;
  988. struct snd_pcm_runtime *runtime = stream->substream->runtime;
  989. if (samples_to_add < 0) {
  990. stream->timer_is_synced = 0;
  991. /* add default if no hardware_read possible */
  992. samples_to_add = PCXHR_GRANULARITY;
  993. }
  994. if (!stream->timer_is_synced) {
  995. if (stream->timer_abs_periods != 0 ||
  996. stream->timer_period_frag + PCXHR_GRANULARITY >=
  997. runtime->period_size) {
  998. new_sample_count = pcxhr_stream_read_position(mgr, stream);
  999. hardware_read = 1;
  1000. if (new_sample_count >= PCXHR_GRANULARITY_MIN) {
  1001. /* sub security offset because of jitter and
  1002. * finer granularity of dsp time (MBOX4)
  1003. */
  1004. new_sample_count -= PCXHR_GRANULARITY_MIN;
  1005. stream->timer_is_synced = 1;
  1006. }
  1007. }
  1008. }
  1009. if (!hardware_read) {
  1010. /* if we didn't try to sync the position, increment it
  1011. * by PCXHR_GRANULARITY every timer interrupt
  1012. */
  1013. new_sample_count = stream->timer_abs_periods +
  1014. stream->timer_period_frag + samples_to_add;
  1015. }
  1016. while (1) {
  1017. u_int64_t new_elapse_pos = stream->timer_abs_periods +
  1018. runtime->period_size;
  1019. if (new_elapse_pos > new_sample_count)
  1020. break;
  1021. elapsed = 1;
  1022. stream->timer_buf_periods++;
  1023. if (stream->timer_buf_periods >= runtime->periods)
  1024. stream->timer_buf_periods = 0;
  1025. stream->timer_abs_periods = new_elapse_pos;
  1026. }
  1027. if (new_sample_count >= stream->timer_abs_periods)
  1028. stream->timer_period_frag = (u_int32_t)(new_sample_count -
  1029. stream->timer_abs_periods);
  1030. else
  1031. snd_printk(KERN_ERR "ERROR new_sample_count too small ??? %lx\n",
  1032. (long unsigned int)new_sample_count);
  1033. if (elapsed) {
  1034. spin_unlock(&mgr->lock);
  1035. snd_pcm_period_elapsed(stream->substream);
  1036. spin_lock(&mgr->lock);
  1037. }
  1038. }
  1039. }
  1040. irqreturn_t pcxhr_interrupt(int irq, void *dev_id)
  1041. {
  1042. struct pcxhr_mgr *mgr = dev_id;
  1043. unsigned int reg;
  1044. int i, j;
  1045. struct snd_pcxhr *chip;
  1046. spin_lock(&mgr->lock);
  1047. reg = PCXHR_INPL(mgr, PCXHR_PLX_IRQCS);
  1048. if (! (reg & PCXHR_IRQCS_ACTIVE_PCIDB)) {
  1049. spin_unlock(&mgr->lock);
  1050. return IRQ_NONE; /* this device did not cause the interrupt */
  1051. }
  1052. /* clear interrupt */
  1053. reg = PCXHR_INPL(mgr, PCXHR_PLX_L2PCIDB);
  1054. PCXHR_OUTPL(mgr, PCXHR_PLX_L2PCIDB, reg);
  1055. /* timer irq occured */
  1056. if (reg & PCXHR_IRQ_TIMER) {
  1057. int timer_toggle = reg & PCXHR_IRQ_TIMER;
  1058. /* is a 24 bit counter */
  1059. int dsp_time_new = PCXHR_INPL(mgr, PCXHR_PLX_MBOX4) & PCXHR_DSP_TIME_MASK;
  1060. int dsp_time_diff = dsp_time_new - mgr->dsp_time_last;
  1061. if (dsp_time_diff < 0 && mgr->dsp_time_last != PCXHR_DSP_TIME_INVALID) {
  1062. snd_printdd("ERROR DSP TIME old(%d) new(%d) -> "
  1063. "resynchronize all streams\n",
  1064. mgr->dsp_time_last, dsp_time_new);
  1065. mgr->dsp_time_err++;
  1066. }
  1067. #ifdef CONFIG_SND_DEBUG_DETECT
  1068. if (dsp_time_diff == 0)
  1069. snd_printdd("ERROR DSP TIME NO DIFF time(%d)\n", dsp_time_new);
  1070. else if (dsp_time_diff >= (2*PCXHR_GRANULARITY))
  1071. snd_printdd("ERROR DSP TIME TOO BIG old(%d) add(%d)\n",
  1072. mgr->dsp_time_last, dsp_time_new - mgr->dsp_time_last);
  1073. #endif
  1074. mgr->dsp_time_last = dsp_time_new;
  1075. if (timer_toggle == mgr->timer_toggle)
  1076. snd_printdd("ERROR TIMER TOGGLE\n");
  1077. mgr->timer_toggle = timer_toggle;
  1078. reg &= ~PCXHR_IRQ_TIMER;
  1079. for (i = 0; i < mgr->num_cards; i++) {
  1080. chip = mgr->chip[i];
  1081. for (j = 0; j < chip->nb_streams_capt; j++)
  1082. pcxhr_update_timer_pos(mgr, &chip->capture_stream[j],
  1083. dsp_time_diff);
  1084. }
  1085. for (i = 0; i < mgr->num_cards; i++) {
  1086. chip = mgr->chip[i];
  1087. for (j = 0; j < chip->nb_streams_play; j++)
  1088. pcxhr_update_timer_pos(mgr, &chip->playback_stream[j],
  1089. dsp_time_diff);
  1090. }
  1091. }
  1092. /* other irq's handled in the tasklet */
  1093. if (reg & PCXHR_IRQ_MASK) {
  1094. /* as we didn't request any notifications, some kind of xrun error
  1095. * will probably occured
  1096. */
  1097. /* better resynchronize all streams next interrupt : */
  1098. mgr->dsp_time_last = PCXHR_DSP_TIME_INVALID;
  1099. mgr->src_it_dsp = reg;
  1100. tasklet_hi_schedule(&mgr->msg_taskq);
  1101. }
  1102. #ifdef CONFIG_SND_DEBUG_DETECT
  1103. if (reg & PCXHR_FATAL_DSP_ERR)
  1104. snd_printdd("FATAL DSP ERROR : %x\n", reg);
  1105. #endif
  1106. spin_unlock(&mgr->lock);
  1107. return IRQ_HANDLED; /* this device caused the interrupt */
  1108. }