pontis.c 23 KB

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  1. /*
  2. * ALSA driver for ICEnsemble VT1724 (Envy24HT)
  3. *
  4. * Lowlevel functions for Pontis MS300
  5. *
  6. * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include <sound/driver.h>
  24. #include <asm/io.h>
  25. #include <linux/delay.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/init.h>
  28. #include <linux/slab.h>
  29. #include <linux/mutex.h>
  30. #include <sound/core.h>
  31. #include <sound/info.h>
  32. #include <sound/tlv.h>
  33. #include "ice1712.h"
  34. #include "envy24ht.h"
  35. #include "pontis.h"
  36. /* I2C addresses */
  37. #define WM_DEV 0x34
  38. #define CS_DEV 0x20
  39. /* WM8776 registers */
  40. #define WM_HP_ATTEN_L 0x00 /* headphone left attenuation */
  41. #define WM_HP_ATTEN_R 0x01 /* headphone left attenuation */
  42. #define WM_HP_MASTER 0x02 /* headphone master (both channels), override LLR */
  43. #define WM_DAC_ATTEN_L 0x03 /* digital left attenuation */
  44. #define WM_DAC_ATTEN_R 0x04
  45. #define WM_DAC_MASTER 0x05
  46. #define WM_PHASE_SWAP 0x06 /* DAC phase swap */
  47. #define WM_DAC_CTRL1 0x07
  48. #define WM_DAC_MUTE 0x08
  49. #define WM_DAC_CTRL2 0x09
  50. #define WM_DAC_INT 0x0a
  51. #define WM_ADC_INT 0x0b
  52. #define WM_MASTER_CTRL 0x0c
  53. #define WM_POWERDOWN 0x0d
  54. #define WM_ADC_ATTEN_L 0x0e
  55. #define WM_ADC_ATTEN_R 0x0f
  56. #define WM_ALC_CTRL1 0x10
  57. #define WM_ALC_CTRL2 0x11
  58. #define WM_ALC_CTRL3 0x12
  59. #define WM_NOISE_GATE 0x13
  60. #define WM_LIMITER 0x14
  61. #define WM_ADC_MUX 0x15
  62. #define WM_OUT_MUX 0x16
  63. #define WM_RESET 0x17
  64. /*
  65. * GPIO
  66. */
  67. #define PONTIS_CS_CS (1<<4) /* CS */
  68. #define PONTIS_CS_CLK (1<<5) /* CLK */
  69. #define PONTIS_CS_RDATA (1<<6) /* CS8416 -> VT1720 */
  70. #define PONTIS_CS_WDATA (1<<7) /* VT1720 -> CS8416 */
  71. /*
  72. * get the current register value of WM codec
  73. */
  74. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  75. {
  76. reg <<= 1;
  77. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  78. ice->akm[0].images[reg + 1];
  79. }
  80. /*
  81. * set the register value of WM codec and remember it
  82. */
  83. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  84. {
  85. unsigned short cval;
  86. cval = (reg << 9) | val;
  87. snd_vt1724_write_i2c(ice, WM_DEV, cval >> 8, cval & 0xff);
  88. }
  89. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  90. {
  91. wm_put_nocache(ice, reg, val);
  92. reg <<= 1;
  93. ice->akm[0].images[reg] = val >> 8;
  94. ice->akm[0].images[reg + 1] = val;
  95. }
  96. /*
  97. * DAC volume attenuation mixer control (-64dB to 0dB)
  98. */
  99. #define DAC_0dB 0xff
  100. #define DAC_RES 128
  101. #define DAC_MIN (DAC_0dB - DAC_RES)
  102. static int wm_dac_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  103. {
  104. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  105. uinfo->count = 2;
  106. uinfo->value.integer.min = 0; /* mute */
  107. uinfo->value.integer.max = DAC_RES; /* 0dB, 0.5dB step */
  108. return 0;
  109. }
  110. static int wm_dac_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  111. {
  112. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  113. unsigned short val;
  114. int i;
  115. mutex_lock(&ice->gpio_mutex);
  116. for (i = 0; i < 2; i++) {
  117. val = wm_get(ice, WM_DAC_ATTEN_L + i) & 0xff;
  118. val = val > DAC_MIN ? (val - DAC_MIN) : 0;
  119. ucontrol->value.integer.value[i] = val;
  120. }
  121. mutex_unlock(&ice->gpio_mutex);
  122. return 0;
  123. }
  124. static int wm_dac_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  125. {
  126. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  127. unsigned short oval, nval;
  128. int i, idx, change = 0;
  129. mutex_lock(&ice->gpio_mutex);
  130. for (i = 0; i < 2; i++) {
  131. nval = ucontrol->value.integer.value[i];
  132. nval = (nval ? (nval + DAC_MIN) : 0) & 0xff;
  133. idx = WM_DAC_ATTEN_L + i;
  134. oval = wm_get(ice, idx) & 0xff;
  135. if (oval != nval) {
  136. wm_put(ice, idx, nval);
  137. wm_put_nocache(ice, idx, nval | 0x100);
  138. change = 1;
  139. }
  140. }
  141. mutex_unlock(&ice->gpio_mutex);
  142. return change;
  143. }
  144. /*
  145. * ADC gain mixer control (-64dB to 0dB)
  146. */
  147. #define ADC_0dB 0xcf
  148. #define ADC_RES 128
  149. #define ADC_MIN (ADC_0dB - ADC_RES)
  150. static int wm_adc_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  151. {
  152. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  153. uinfo->count = 2;
  154. uinfo->value.integer.min = 0; /* mute (-64dB) */
  155. uinfo->value.integer.max = ADC_RES; /* 0dB, 0.5dB step */
  156. return 0;
  157. }
  158. static int wm_adc_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  159. {
  160. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  161. unsigned short val;
  162. int i;
  163. mutex_lock(&ice->gpio_mutex);
  164. for (i = 0; i < 2; i++) {
  165. val = wm_get(ice, WM_ADC_ATTEN_L + i) & 0xff;
  166. val = val > ADC_MIN ? (val - ADC_MIN) : 0;
  167. ucontrol->value.integer.value[i] = val;
  168. }
  169. mutex_unlock(&ice->gpio_mutex);
  170. return 0;
  171. }
  172. static int wm_adc_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  173. {
  174. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  175. unsigned short ovol, nvol;
  176. int i, idx, change = 0;
  177. mutex_lock(&ice->gpio_mutex);
  178. for (i = 0; i < 2; i++) {
  179. nvol = ucontrol->value.integer.value[i];
  180. nvol = nvol ? (nvol + ADC_MIN) : 0;
  181. idx = WM_ADC_ATTEN_L + i;
  182. ovol = wm_get(ice, idx) & 0xff;
  183. if (ovol != nvol) {
  184. wm_put(ice, idx, nvol);
  185. change = 1;
  186. }
  187. }
  188. mutex_unlock(&ice->gpio_mutex);
  189. return change;
  190. }
  191. /*
  192. * ADC input mux mixer control
  193. */
  194. static int wm_adc_mux_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  195. {
  196. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  197. uinfo->count = 1;
  198. uinfo->value.integer.min = 0;
  199. uinfo->value.integer.max = 1;
  200. return 0;
  201. }
  202. static int wm_adc_mux_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  203. {
  204. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  205. int bit = kcontrol->private_value;
  206. mutex_lock(&ice->gpio_mutex);
  207. ucontrol->value.integer.value[0] = (wm_get(ice, WM_ADC_MUX) & (1 << bit)) ? 1 : 0;
  208. mutex_unlock(&ice->gpio_mutex);
  209. return 0;
  210. }
  211. static int wm_adc_mux_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  212. {
  213. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  214. int bit = kcontrol->private_value;
  215. unsigned short oval, nval;
  216. int change;
  217. mutex_lock(&ice->gpio_mutex);
  218. nval = oval = wm_get(ice, WM_ADC_MUX);
  219. if (ucontrol->value.integer.value[0])
  220. nval |= (1 << bit);
  221. else
  222. nval &= ~(1 << bit);
  223. change = nval != oval;
  224. if (change) {
  225. wm_put(ice, WM_ADC_MUX, nval);
  226. }
  227. mutex_unlock(&ice->gpio_mutex);
  228. return 0;
  229. }
  230. /*
  231. * Analog bypass (In -> Out)
  232. */
  233. static int wm_bypass_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  234. {
  235. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  236. uinfo->count = 1;
  237. uinfo->value.integer.min = 0;
  238. uinfo->value.integer.max = 1;
  239. return 0;
  240. }
  241. static int wm_bypass_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  242. {
  243. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  244. mutex_lock(&ice->gpio_mutex);
  245. ucontrol->value.integer.value[0] = (wm_get(ice, WM_OUT_MUX) & 0x04) ? 1 : 0;
  246. mutex_unlock(&ice->gpio_mutex);
  247. return 0;
  248. }
  249. static int wm_bypass_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  250. {
  251. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  252. unsigned short val, oval;
  253. int change = 0;
  254. mutex_lock(&ice->gpio_mutex);
  255. val = oval = wm_get(ice, WM_OUT_MUX);
  256. if (ucontrol->value.integer.value[0])
  257. val |= 0x04;
  258. else
  259. val &= ~0x04;
  260. if (val != oval) {
  261. wm_put(ice, WM_OUT_MUX, val);
  262. change = 1;
  263. }
  264. mutex_unlock(&ice->gpio_mutex);
  265. return change;
  266. }
  267. /*
  268. * Left/Right swap
  269. */
  270. static int wm_chswap_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  271. {
  272. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  273. uinfo->count = 1;
  274. uinfo->value.integer.min = 0;
  275. uinfo->value.integer.max = 1;
  276. return 0;
  277. }
  278. static int wm_chswap_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  279. {
  280. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  281. mutex_lock(&ice->gpio_mutex);
  282. ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL1) & 0xf0) != 0x90;
  283. mutex_unlock(&ice->gpio_mutex);
  284. return 0;
  285. }
  286. static int wm_chswap_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  287. {
  288. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  289. unsigned short val, oval;
  290. int change = 0;
  291. mutex_lock(&ice->gpio_mutex);
  292. oval = wm_get(ice, WM_DAC_CTRL1);
  293. val = oval & 0x0f;
  294. if (ucontrol->value.integer.value[0])
  295. val |= 0x60;
  296. else
  297. val |= 0x90;
  298. if (val != oval) {
  299. wm_put(ice, WM_DAC_CTRL1, val);
  300. wm_put_nocache(ice, WM_DAC_CTRL1, val);
  301. change = 1;
  302. }
  303. mutex_unlock(&ice->gpio_mutex);
  304. return change;
  305. }
  306. /*
  307. * write data in the SPI mode
  308. */
  309. static void set_gpio_bit(struct snd_ice1712 *ice, unsigned int bit, int val)
  310. {
  311. unsigned int tmp = snd_ice1712_gpio_read(ice);
  312. if (val)
  313. tmp |= bit;
  314. else
  315. tmp &= ~bit;
  316. snd_ice1712_gpio_write(ice, tmp);
  317. }
  318. static void spi_send_byte(struct snd_ice1712 *ice, unsigned char data)
  319. {
  320. int i;
  321. for (i = 0; i < 8; i++) {
  322. set_gpio_bit(ice, PONTIS_CS_CLK, 0);
  323. udelay(1);
  324. set_gpio_bit(ice, PONTIS_CS_WDATA, data & 0x80);
  325. udelay(1);
  326. set_gpio_bit(ice, PONTIS_CS_CLK, 1);
  327. udelay(1);
  328. data <<= 1;
  329. }
  330. }
  331. static unsigned int spi_read_byte(struct snd_ice1712 *ice)
  332. {
  333. int i;
  334. unsigned int val = 0;
  335. for (i = 0; i < 8; i++) {
  336. val <<= 1;
  337. set_gpio_bit(ice, PONTIS_CS_CLK, 0);
  338. udelay(1);
  339. if (snd_ice1712_gpio_read(ice) & PONTIS_CS_RDATA)
  340. val |= 1;
  341. udelay(1);
  342. set_gpio_bit(ice, PONTIS_CS_CLK, 1);
  343. udelay(1);
  344. }
  345. return val;
  346. }
  347. static void spi_write(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg, unsigned int data)
  348. {
  349. snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
  350. snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
  351. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  352. spi_send_byte(ice, dev & ~1); /* WRITE */
  353. spi_send_byte(ice, reg); /* MAP */
  354. spi_send_byte(ice, data); /* DATA */
  355. /* trigger */
  356. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  357. udelay(1);
  358. /* restore */
  359. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  360. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  361. }
  362. static unsigned int spi_read(struct snd_ice1712 *ice, unsigned int dev, unsigned int reg)
  363. {
  364. unsigned int val;
  365. snd_ice1712_gpio_set_dir(ice, PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK);
  366. snd_ice1712_gpio_set_mask(ice, ~(PONTIS_CS_CS|PONTIS_CS_WDATA|PONTIS_CS_CLK));
  367. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  368. spi_send_byte(ice, dev & ~1); /* WRITE */
  369. spi_send_byte(ice, reg); /* MAP */
  370. /* trigger */
  371. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  372. udelay(1);
  373. set_gpio_bit(ice, PONTIS_CS_CS, 0);
  374. spi_send_byte(ice, dev | 1); /* READ */
  375. val = spi_read_byte(ice);
  376. /* trigger */
  377. set_gpio_bit(ice, PONTIS_CS_CS, 1);
  378. udelay(1);
  379. /* restore */
  380. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  381. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  382. return val;
  383. }
  384. /*
  385. * SPDIF input source
  386. */
  387. static int cs_source_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  388. {
  389. static const char * const texts[] = {
  390. "Coax", /* RXP0 */
  391. "Optical", /* RXP1 */
  392. "CD", /* RXP2 */
  393. };
  394. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  395. uinfo->count = 1;
  396. uinfo->value.enumerated.items = 3;
  397. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  398. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  399. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  400. return 0;
  401. }
  402. static int cs_source_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  403. {
  404. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  405. mutex_lock(&ice->gpio_mutex);
  406. ucontrol->value.enumerated.item[0] = ice->gpio.saved[0];
  407. mutex_unlock(&ice->gpio_mutex);
  408. return 0;
  409. }
  410. static int cs_source_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  411. {
  412. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  413. unsigned char val;
  414. int change = 0;
  415. mutex_lock(&ice->gpio_mutex);
  416. if (ucontrol->value.enumerated.item[0] != ice->gpio.saved[0]) {
  417. ice->gpio.saved[0] = ucontrol->value.enumerated.item[0] & 3;
  418. val = 0x80 | (ice->gpio.saved[0] << 3);
  419. spi_write(ice, CS_DEV, 0x04, val);
  420. change = 1;
  421. }
  422. mutex_unlock(&ice->gpio_mutex);
  423. return 0;
  424. }
  425. /*
  426. * GPIO controls
  427. */
  428. static int pontis_gpio_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  429. {
  430. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  431. uinfo->count = 1;
  432. uinfo->value.integer.min = 0;
  433. uinfo->value.integer.max = 0xffff; /* 16bit */
  434. return 0;
  435. }
  436. static int pontis_gpio_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  437. {
  438. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  439. mutex_lock(&ice->gpio_mutex);
  440. /* 4-7 reserved */
  441. ucontrol->value.integer.value[0] = (~ice->gpio.write_mask & 0xffff) | 0x00f0;
  442. mutex_unlock(&ice->gpio_mutex);
  443. return 0;
  444. }
  445. static int pontis_gpio_mask_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  446. {
  447. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  448. unsigned int val;
  449. int changed;
  450. mutex_lock(&ice->gpio_mutex);
  451. /* 4-7 reserved */
  452. val = (~ucontrol->value.integer.value[0] & 0xffff) | 0x00f0;
  453. changed = val != ice->gpio.write_mask;
  454. ice->gpio.write_mask = val;
  455. mutex_unlock(&ice->gpio_mutex);
  456. return changed;
  457. }
  458. static int pontis_gpio_dir_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  459. {
  460. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  461. mutex_lock(&ice->gpio_mutex);
  462. /* 4-7 reserved */
  463. ucontrol->value.integer.value[0] = ice->gpio.direction & 0xff0f;
  464. mutex_unlock(&ice->gpio_mutex);
  465. return 0;
  466. }
  467. static int pontis_gpio_dir_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  468. {
  469. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  470. unsigned int val;
  471. int changed;
  472. mutex_lock(&ice->gpio_mutex);
  473. /* 4-7 reserved */
  474. val = ucontrol->value.integer.value[0] & 0xff0f;
  475. changed = (val != ice->gpio.direction);
  476. ice->gpio.direction = val;
  477. mutex_unlock(&ice->gpio_mutex);
  478. return changed;
  479. }
  480. static int pontis_gpio_data_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  481. {
  482. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  483. mutex_lock(&ice->gpio_mutex);
  484. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  485. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  486. ucontrol->value.integer.value[0] = snd_ice1712_gpio_read(ice) & 0xffff;
  487. mutex_unlock(&ice->gpio_mutex);
  488. return 0;
  489. }
  490. static int pontis_gpio_data_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  491. {
  492. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  493. unsigned int val, nval;
  494. int changed = 0;
  495. mutex_lock(&ice->gpio_mutex);
  496. snd_ice1712_gpio_set_dir(ice, ice->gpio.direction);
  497. snd_ice1712_gpio_set_mask(ice, ice->gpio.write_mask);
  498. val = snd_ice1712_gpio_read(ice) & 0xffff;
  499. nval = ucontrol->value.integer.value[0] & 0xffff;
  500. if (val != nval) {
  501. snd_ice1712_gpio_write(ice, nval);
  502. changed = 1;
  503. }
  504. mutex_unlock(&ice->gpio_mutex);
  505. return changed;
  506. }
  507. static const DECLARE_TLV_DB_SCALE(db_scale_volume, -6400, 50, 1);
  508. /*
  509. * mixers
  510. */
  511. static const struct snd_kcontrol_new pontis_controls[] __devinitdata = {
  512. {
  513. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  514. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  515. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  516. .name = "PCM Playback Volume",
  517. .info = wm_dac_vol_info,
  518. .get = wm_dac_vol_get,
  519. .put = wm_dac_vol_put,
  520. .tlv = { .p = db_scale_volume },
  521. },
  522. {
  523. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  524. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  525. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  526. .name = "Capture Volume",
  527. .info = wm_adc_vol_info,
  528. .get = wm_adc_vol_get,
  529. .put = wm_adc_vol_put,
  530. .tlv = { .p = db_scale_volume },
  531. },
  532. {
  533. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  534. .name = "CD Capture Switch",
  535. .info = wm_adc_mux_info,
  536. .get = wm_adc_mux_get,
  537. .put = wm_adc_mux_put,
  538. .private_value = 0,
  539. },
  540. {
  541. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  542. .name = "Line Capture Switch",
  543. .info = wm_adc_mux_info,
  544. .get = wm_adc_mux_get,
  545. .put = wm_adc_mux_put,
  546. .private_value = 1,
  547. },
  548. {
  549. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  550. .name = "Analog Bypass Switch",
  551. .info = wm_bypass_info,
  552. .get = wm_bypass_get,
  553. .put = wm_bypass_put,
  554. },
  555. {
  556. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  557. .name = "Swap Output Channels",
  558. .info = wm_chswap_info,
  559. .get = wm_chswap_get,
  560. .put = wm_chswap_put,
  561. },
  562. {
  563. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  564. .name = "IEC958 Input Source",
  565. .info = cs_source_info,
  566. .get = cs_source_get,
  567. .put = cs_source_put,
  568. },
  569. /* FIXME: which interface? */
  570. {
  571. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  572. .name = "GPIO Mask",
  573. .info = pontis_gpio_mask_info,
  574. .get = pontis_gpio_mask_get,
  575. .put = pontis_gpio_mask_put,
  576. },
  577. {
  578. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  579. .name = "GPIO Direction",
  580. .info = pontis_gpio_mask_info,
  581. .get = pontis_gpio_dir_get,
  582. .put = pontis_gpio_dir_put,
  583. },
  584. {
  585. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  586. .name = "GPIO Data",
  587. .info = pontis_gpio_mask_info,
  588. .get = pontis_gpio_data_get,
  589. .put = pontis_gpio_data_put,
  590. },
  591. };
  592. /*
  593. * WM codec registers
  594. */
  595. static void wm_proc_regs_write(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  596. {
  597. struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
  598. char line[64];
  599. unsigned int reg, val;
  600. mutex_lock(&ice->gpio_mutex);
  601. while (!snd_info_get_line(buffer, line, sizeof(line))) {
  602. if (sscanf(line, "%x %x", &reg, &val) != 2)
  603. continue;
  604. if (reg <= 0x17 && val <= 0xffff)
  605. wm_put(ice, reg, val);
  606. }
  607. mutex_unlock(&ice->gpio_mutex);
  608. }
  609. static void wm_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  610. {
  611. struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
  612. int reg, val;
  613. mutex_lock(&ice->gpio_mutex);
  614. for (reg = 0; reg <= 0x17; reg++) {
  615. val = wm_get(ice, reg);
  616. snd_iprintf(buffer, "%02x = %04x\n", reg, val);
  617. }
  618. mutex_unlock(&ice->gpio_mutex);
  619. }
  620. static void wm_proc_init(struct snd_ice1712 *ice)
  621. {
  622. struct snd_info_entry *entry;
  623. if (! snd_card_proc_new(ice->card, "wm_codec", &entry)) {
  624. snd_info_set_text_ops(entry, ice, wm_proc_regs_read);
  625. entry->mode |= S_IWUSR;
  626. entry->c.text.write = wm_proc_regs_write;
  627. }
  628. }
  629. static void cs_proc_regs_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
  630. {
  631. struct snd_ice1712 *ice = (struct snd_ice1712 *)entry->private_data;
  632. int reg, val;
  633. mutex_lock(&ice->gpio_mutex);
  634. for (reg = 0; reg <= 0x26; reg++) {
  635. val = spi_read(ice, CS_DEV, reg);
  636. snd_iprintf(buffer, "%02x = %02x\n", reg, val);
  637. }
  638. val = spi_read(ice, CS_DEV, 0x7f);
  639. snd_iprintf(buffer, "%02x = %02x\n", 0x7f, val);
  640. mutex_unlock(&ice->gpio_mutex);
  641. }
  642. static void cs_proc_init(struct snd_ice1712 *ice)
  643. {
  644. struct snd_info_entry *entry;
  645. if (! snd_card_proc_new(ice->card, "cs_codec", &entry))
  646. snd_info_set_text_ops(entry, ice, cs_proc_regs_read);
  647. }
  648. static int __devinit pontis_add_controls(struct snd_ice1712 *ice)
  649. {
  650. unsigned int i;
  651. int err;
  652. for (i = 0; i < ARRAY_SIZE(pontis_controls); i++) {
  653. err = snd_ctl_add(ice->card, snd_ctl_new1(&pontis_controls[i], ice));
  654. if (err < 0)
  655. return err;
  656. }
  657. wm_proc_init(ice);
  658. cs_proc_init(ice);
  659. return 0;
  660. }
  661. /*
  662. * initialize the chip
  663. */
  664. static int __devinit pontis_init(struct snd_ice1712 *ice)
  665. {
  666. static const unsigned short wm_inits[] = {
  667. /* These come first to reduce init pop noise */
  668. WM_ADC_MUX, 0x00c0, /* ADC mute */
  669. WM_DAC_MUTE, 0x0001, /* DAC softmute */
  670. WM_DAC_CTRL1, 0x0000, /* DAC mute */
  671. WM_POWERDOWN, 0x0008, /* All power-up except HP */
  672. WM_RESET, 0x0000, /* reset */
  673. };
  674. static const unsigned short wm_inits2[] = {
  675. WM_MASTER_CTRL, 0x0022, /* 256fs, slave mode */
  676. WM_DAC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  677. WM_ADC_INT, 0x0022, /* I2S, normal polarity, 24bit */
  678. WM_DAC_CTRL1, 0x0090, /* DAC L/R */
  679. WM_OUT_MUX, 0x0001, /* OUT DAC */
  680. WM_HP_ATTEN_L, 0x0179, /* HP 0dB */
  681. WM_HP_ATTEN_R, 0x0179, /* HP 0dB */
  682. WM_DAC_ATTEN_L, 0x0000, /* DAC 0dB */
  683. WM_DAC_ATTEN_L, 0x0100, /* DAC 0dB */
  684. WM_DAC_ATTEN_R, 0x0000, /* DAC 0dB */
  685. WM_DAC_ATTEN_R, 0x0100, /* DAC 0dB */
  686. // WM_DAC_MASTER, 0x0100, /* DAC master muted */
  687. WM_PHASE_SWAP, 0x0000, /* phase normal */
  688. WM_DAC_CTRL2, 0x0000, /* no deemphasis, no ZFLG */
  689. WM_ADC_ATTEN_L, 0x0000, /* ADC muted */
  690. WM_ADC_ATTEN_R, 0x0000, /* ADC muted */
  691. #if 0
  692. WM_ALC_CTRL1, 0x007b, /* */
  693. WM_ALC_CTRL2, 0x0000, /* */
  694. WM_ALC_CTRL3, 0x0000, /* */
  695. WM_NOISE_GATE, 0x0000, /* */
  696. #endif
  697. WM_DAC_MUTE, 0x0000, /* DAC unmute */
  698. WM_ADC_MUX, 0x0003, /* ADC unmute, both CD/Line On */
  699. };
  700. static const unsigned char cs_inits[] = {
  701. 0x04, 0x80, /* RUN, RXP0 */
  702. 0x05, 0x05, /* slave, 24bit */
  703. 0x01, 0x00,
  704. 0x02, 0x00,
  705. 0x03, 0x00,
  706. };
  707. unsigned int i;
  708. ice->vt1720 = 1;
  709. ice->num_total_dacs = 2;
  710. ice->num_total_adcs = 2;
  711. /* to remeber the register values */
  712. ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  713. if (! ice->akm)
  714. return -ENOMEM;
  715. ice->akm_codecs = 1;
  716. /* HACK - use this as the SPDIF source.
  717. * don't call snd_ice1712_gpio_get/put(), otherwise it's overwritten
  718. */
  719. ice->gpio.saved[0] = 0;
  720. /* initialize WM8776 codec */
  721. for (i = 0; i < ARRAY_SIZE(wm_inits); i += 2)
  722. wm_put(ice, wm_inits[i], wm_inits[i+1]);
  723. schedule_timeout_uninterruptible(1);
  724. for (i = 0; i < ARRAY_SIZE(wm_inits2); i += 2)
  725. wm_put(ice, wm_inits2[i], wm_inits2[i+1]);
  726. /* initialize CS8416 codec */
  727. /* assert PRST#; MT05 bit 7 */
  728. outb(inb(ICEMT1724(ice, AC97_CMD)) | 0x80, ICEMT1724(ice, AC97_CMD));
  729. mdelay(5);
  730. /* deassert PRST# */
  731. outb(inb(ICEMT1724(ice, AC97_CMD)) & ~0x80, ICEMT1724(ice, AC97_CMD));
  732. for (i = 0; i < ARRAY_SIZE(cs_inits); i += 2)
  733. spi_write(ice, CS_DEV, cs_inits[i], cs_inits[i+1]);
  734. return 0;
  735. }
  736. /*
  737. * Pontis boards don't provide the EEPROM data at all.
  738. * hence the driver needs to sets up it properly.
  739. */
  740. static const unsigned char pontis_eeprom[] __devinitdata = {
  741. [ICE_EEP2_SYSCONF] = 0x08, /* clock 256, mpu401, spdif-in/ADC, 1DAC */
  742. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  743. [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit, 192k */
  744. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  745. [ICE_EEP2_GPIO_DIR] = 0x07,
  746. [ICE_EEP2_GPIO_DIR1] = 0x00,
  747. [ICE_EEP2_GPIO_DIR2] = 0x00, /* ignored */
  748. [ICE_EEP2_GPIO_MASK] = 0x0f, /* 4-7 reserved for CS8416 */
  749. [ICE_EEP2_GPIO_MASK1] = 0xff,
  750. [ICE_EEP2_GPIO_MASK2] = 0x00, /* ignored */
  751. [ICE_EEP2_GPIO_STATE] = 0x06, /* 0-low, 1-high, 2-high */
  752. [ICE_EEP2_GPIO_STATE1] = 0x00,
  753. [ICE_EEP2_GPIO_STATE2] = 0x00, /* ignored */
  754. };
  755. /* entry point */
  756. const struct snd_ice1712_card_info snd_vt1720_pontis_cards[] __devinitdata = {
  757. {
  758. .subvendor = VT1720_SUBDEVICE_PONTIS_MS300,
  759. .name = "Pontis MS300",
  760. .model = "ms300",
  761. .chip_init = pontis_init,
  762. .build_controls = pontis_add_controls,
  763. .eeprom_size = sizeof(pontis_eeprom),
  764. .eeprom_data = pontis_eeprom,
  765. },
  766. { } /* terminator */
  767. };