phase.c 25 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1724 (Envy24)
  3. *
  4. * Lowlevel functions for Terratec PHASE 22
  5. *
  6. * Copyright (c) 2005 Misha Zhilin <misha@epiphan.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. /* PHASE 22 overview:
  24. * Audio controller: VIA Envy24HT-S (slightly trimmed down version of Envy24HT)
  25. * Analog chip: AK4524 (partially via Philip's 74HCT125)
  26. * Digital receiver: CS8414-CS (not supported in this release)
  27. *
  28. * Envy connects to AK4524
  29. * - CS directly from GPIO 10
  30. * - CCLK via 74HCT125's gate #4 from GPIO 4
  31. * - CDTI via 74HCT125's gate #2 from GPIO 5
  32. * CDTI may be completely blocked by 74HCT125's gate #1 controlled by GPIO 3
  33. */
  34. #include <sound/driver.h>
  35. #include <asm/io.h>
  36. #include <linux/delay.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/init.h>
  39. #include <linux/slab.h>
  40. #include <linux/mutex.h>
  41. #include <sound/core.h>
  42. #include "ice1712.h"
  43. #include "envy24ht.h"
  44. #include "phase.h"
  45. #include <sound/tlv.h>
  46. /* WM8770 registers */
  47. #define WM_DAC_ATTEN 0x00 /* DAC1-8 analog attenuation */
  48. #define WM_DAC_MASTER_ATTEN 0x08 /* DAC master analog attenuation */
  49. #define WM_DAC_DIG_ATTEN 0x09 /* DAC1-8 digital attenuation */
  50. #define WM_DAC_DIG_MASTER_ATTEN 0x11 /* DAC master digital attenuation */
  51. #define WM_PHASE_SWAP 0x12 /* DAC phase */
  52. #define WM_DAC_CTRL1 0x13 /* DAC control bits */
  53. #define WM_MUTE 0x14 /* mute controls */
  54. #define WM_DAC_CTRL2 0x15 /* de-emphasis and zefo-flag */
  55. #define WM_INT_CTRL 0x16 /* interface control */
  56. #define WM_MASTER 0x17 /* master clock and mode */
  57. #define WM_POWERDOWN 0x18 /* power-down controls */
  58. #define WM_ADC_GAIN 0x19 /* ADC gain L(19)/R(1a) */
  59. #define WM_ADC_MUX 0x1b /* input MUX */
  60. #define WM_OUT_MUX1 0x1c /* output MUX */
  61. #define WM_OUT_MUX2 0x1e /* output MUX */
  62. #define WM_RESET 0x1f /* software reset */
  63. /*
  64. * Logarithmic volume values for WM8770
  65. * Computed as 20 * Log10(255 / x)
  66. */
  67. static const unsigned char wm_vol[256] = {
  68. 127, 48, 42, 39, 36, 34, 33, 31, 30, 29, 28, 27, 27, 26, 25, 25, 24, 24, 23,
  69. 23, 22, 22, 21, 21, 21, 20, 20, 20, 19, 19, 19, 18, 18, 18, 18, 17, 17, 17,
  70. 17, 16, 16, 16, 16, 15, 15, 15, 15, 15, 15, 14, 14, 14, 14, 14, 13, 13, 13,
  71. 13, 13, 13, 13, 12, 12, 12, 12, 12, 12, 12, 11, 11, 11, 11, 11, 11, 11, 11,
  72. 11, 10, 10, 10, 10, 10, 10, 10, 10, 10, 9, 9, 9, 9, 9, 9, 9, 9, 9, 9, 8, 8,
  73. 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 6, 6, 6,
  74. 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
  75. 5, 5, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 3,
  76. 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
  77. 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
  78. 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  79. 0, 0
  80. };
  81. #define WM_VOL_MAX (sizeof(wm_vol) - 1)
  82. #define WM_VOL_MUTE 0x8000
  83. static const struct snd_akm4xxx akm_phase22 __devinitdata = {
  84. .type = SND_AK4524,
  85. .num_dacs = 2,
  86. .num_adcs = 2,
  87. };
  88. static const struct snd_ak4xxx_private akm_phase22_priv __devinitdata = {
  89. .caddr = 2,
  90. .cif = 1,
  91. .data_mask = 1 << 4,
  92. .clk_mask = 1 << 5,
  93. .cs_mask = 1 << 10,
  94. .cs_addr = 1 << 10,
  95. .cs_none = 0,
  96. .add_flags = 1 << 3,
  97. .mask_flags = 0,
  98. };
  99. static int __devinit phase22_init(struct snd_ice1712 *ice)
  100. {
  101. struct snd_akm4xxx *ak;
  102. int err;
  103. // Configure DAC/ADC description for generic part of ice1724
  104. switch (ice->eeprom.subvendor) {
  105. case VT1724_SUBDEVICE_PHASE22:
  106. ice->num_total_dacs = 2;
  107. ice->num_total_adcs = 2;
  108. ice->vt1720 = 1; // Envy24HT-S have 16 bit wide GPIO
  109. break;
  110. default:
  111. snd_BUG();
  112. return -EINVAL;
  113. }
  114. // Initialize analog chips
  115. ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  116. if (! ak)
  117. return -ENOMEM;
  118. ice->akm_codecs = 1;
  119. switch (ice->eeprom.subvendor) {
  120. case VT1724_SUBDEVICE_PHASE22:
  121. if ((err = snd_ice1712_akm4xxx_init(ak, &akm_phase22, &akm_phase22_priv, ice)) < 0)
  122. return err;
  123. break;
  124. }
  125. return 0;
  126. }
  127. static int __devinit phase22_add_controls(struct snd_ice1712 *ice)
  128. {
  129. int err = 0;
  130. switch (ice->eeprom.subvendor) {
  131. case VT1724_SUBDEVICE_PHASE22:
  132. err = snd_ice1712_akm4xxx_build_controls(ice);
  133. if (err < 0)
  134. return err;
  135. }
  136. return 0;
  137. }
  138. static const unsigned char phase22_eeprom[] __devinitdata = {
  139. [ICE_EEP2_SYSCONF] = 0x00, /* 1xADC, 1xDACs */
  140. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  141. [ICE_EEP2_I2S] = 0xf8, /* vol, 96k, 24bit */
  142. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  143. [ICE_EEP2_GPIO_DIR] = 0xff,
  144. [ICE_EEP2_GPIO_DIR1] = 0xff,
  145. [ICE_EEP2_GPIO_DIR2] = 0xff,
  146. [ICE_EEP2_GPIO_MASK] = 0x00,
  147. [ICE_EEP2_GPIO_MASK1] = 0x00,
  148. [ICE_EEP2_GPIO_MASK2] = 0x00,
  149. [ICE_EEP2_GPIO_STATE] = 0x00,
  150. [ICE_EEP2_GPIO_STATE1] = 0x00,
  151. [ICE_EEP2_GPIO_STATE2] = 0x00,
  152. };
  153. static const unsigned char phase28_eeprom[] __devinitdata = {
  154. [ICE_EEP2_SYSCONF] = 0x0b, /* clock 512, spdif-in/ADC, 4DACs */
  155. [ICE_EEP2_ACLINK] = 0x80, /* I2S */
  156. [ICE_EEP2_I2S] = 0xfc, /* vol, 96k, 24bit, 192k */
  157. [ICE_EEP2_SPDIF] = 0xc3, /* out-en, out-int, spdif-in */
  158. [ICE_EEP2_GPIO_DIR] = 0xff,
  159. [ICE_EEP2_GPIO_DIR1] = 0xff,
  160. [ICE_EEP2_GPIO_DIR2] = 0x5f,
  161. [ICE_EEP2_GPIO_MASK] = 0x00,
  162. [ICE_EEP2_GPIO_MASK1] = 0x00,
  163. [ICE_EEP2_GPIO_MASK2] = 0x00,
  164. [ICE_EEP2_GPIO_STATE] = 0x00,
  165. [ICE_EEP2_GPIO_STATE1] = 0x00,
  166. [ICE_EEP2_GPIO_STATE2] = 0x00,
  167. };
  168. /*
  169. * write data in the SPI mode
  170. */
  171. static void phase28_spi_write(struct snd_ice1712 *ice, unsigned int cs, unsigned int data, int bits)
  172. {
  173. unsigned int tmp;
  174. int i;
  175. tmp = snd_ice1712_gpio_read(ice);
  176. snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RW|PHASE28_SPI_MOSI|PHASE28_SPI_CLK|
  177. PHASE28_WM_CS));
  178. tmp |= PHASE28_WM_RW;
  179. tmp &= ~cs;
  180. snd_ice1712_gpio_write(ice, tmp);
  181. udelay(1);
  182. for (i = bits - 1; i >= 0; i--) {
  183. tmp &= ~PHASE28_SPI_CLK;
  184. snd_ice1712_gpio_write(ice, tmp);
  185. udelay(1);
  186. if (data & (1 << i))
  187. tmp |= PHASE28_SPI_MOSI;
  188. else
  189. tmp &= ~PHASE28_SPI_MOSI;
  190. snd_ice1712_gpio_write(ice, tmp);
  191. udelay(1);
  192. tmp |= PHASE28_SPI_CLK;
  193. snd_ice1712_gpio_write(ice, tmp);
  194. udelay(1);
  195. }
  196. tmp &= ~PHASE28_SPI_CLK;
  197. tmp |= cs;
  198. snd_ice1712_gpio_write(ice, tmp);
  199. udelay(1);
  200. tmp |= PHASE28_SPI_CLK;
  201. snd_ice1712_gpio_write(ice, tmp);
  202. udelay(1);
  203. }
  204. /*
  205. * get the current register value of WM codec
  206. */
  207. static unsigned short wm_get(struct snd_ice1712 *ice, int reg)
  208. {
  209. reg <<= 1;
  210. return ((unsigned short)ice->akm[0].images[reg] << 8) |
  211. ice->akm[0].images[reg + 1];
  212. }
  213. /*
  214. * set the register value of WM codec
  215. */
  216. static void wm_put_nocache(struct snd_ice1712 *ice, int reg, unsigned short val)
  217. {
  218. phase28_spi_write(ice, PHASE28_WM_CS, (reg << 9) | (val & 0x1ff), 16);
  219. }
  220. /*
  221. * set the register value of WM codec and remember it
  222. */
  223. static void wm_put(struct snd_ice1712 *ice, int reg, unsigned short val)
  224. {
  225. wm_put_nocache(ice, reg, val);
  226. reg <<= 1;
  227. ice->akm[0].images[reg] = val >> 8;
  228. ice->akm[0].images[reg + 1] = val;
  229. }
  230. static void wm_set_vol(struct snd_ice1712 *ice, unsigned int index, unsigned short vol, unsigned short master)
  231. {
  232. unsigned char nvol;
  233. if ((master & WM_VOL_MUTE) || (vol & WM_VOL_MUTE))
  234. nvol = 0;
  235. else
  236. nvol = 127 - wm_vol[(((vol & ~WM_VOL_MUTE) * (master & ~WM_VOL_MUTE)) / 127) & WM_VOL_MAX];
  237. wm_put(ice, index, nvol);
  238. wm_put_nocache(ice, index, 0x180 | nvol);
  239. }
  240. /*
  241. * DAC mute control
  242. */
  243. #define wm_pcm_mute_info phase28_mono_bool_info
  244. static int wm_pcm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  245. {
  246. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  247. mutex_lock(&ice->gpio_mutex);
  248. ucontrol->value.integer.value[0] = (wm_get(ice, WM_MUTE) & 0x10) ? 0 : 1;
  249. mutex_unlock(&ice->gpio_mutex);
  250. return 0;
  251. }
  252. static int wm_pcm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  253. {
  254. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  255. unsigned short nval, oval;
  256. int change;
  257. snd_ice1712_save_gpio_status(ice);
  258. oval = wm_get(ice, WM_MUTE);
  259. nval = (oval & ~0x10) | (ucontrol->value.integer.value[0] ? 0 : 0x10);
  260. if ((change = (nval != oval)))
  261. wm_put(ice, WM_MUTE, nval);
  262. snd_ice1712_restore_gpio_status(ice);
  263. return change;
  264. }
  265. /*
  266. * Master volume attenuation mixer control
  267. */
  268. static int wm_master_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  269. {
  270. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  271. uinfo->count = 2;
  272. uinfo->value.integer.min = 0;
  273. uinfo->value.integer.max = WM_VOL_MAX;
  274. return 0;
  275. }
  276. static int wm_master_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  277. {
  278. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  279. int i;
  280. for (i=0; i<2; i++)
  281. ucontrol->value.integer.value[i] = ice->spec.phase28.master[i] & ~WM_VOL_MUTE;
  282. return 0;
  283. }
  284. static int wm_master_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  285. {
  286. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  287. int ch, change = 0;
  288. snd_ice1712_save_gpio_status(ice);
  289. for (ch = 0; ch < 2; ch++) {
  290. if (ucontrol->value.integer.value[ch] != ice->spec.phase28.master[ch]) {
  291. int dac;
  292. ice->spec.phase28.master[ch] &= WM_VOL_MUTE;
  293. ice->spec.phase28.master[ch] |= ucontrol->value.integer.value[ch];
  294. for (dac = 0; dac < ice->num_total_dacs; dac += 2)
  295. wm_set_vol(ice, WM_DAC_ATTEN + dac + ch,
  296. ice->spec.phase28.vol[dac + ch],
  297. ice->spec.phase28.master[ch]);
  298. change = 1;
  299. }
  300. }
  301. snd_ice1712_restore_gpio_status(ice);
  302. return change;
  303. }
  304. static int __devinit phase28_init(struct snd_ice1712 *ice)
  305. {
  306. static const unsigned short wm_inits_phase28[] = {
  307. /* These come first to reduce init pop noise */
  308. 0x1b, 0x044, /* ADC Mux (AC'97 source) */
  309. 0x1c, 0x00B, /* Out Mux1 (VOUT1 = DAC+AUX, VOUT2 = DAC) */
  310. 0x1d, 0x009, /* Out Mux2 (VOUT2 = DAC, VOUT3 = DAC) */
  311. 0x18, 0x000, /* All power-up */
  312. 0x16, 0x122, /* I2S, normal polarity, 24bit */
  313. 0x17, 0x022, /* 256fs, slave mode */
  314. 0x00, 0, /* DAC1 analog mute */
  315. 0x01, 0, /* DAC2 analog mute */
  316. 0x02, 0, /* DAC3 analog mute */
  317. 0x03, 0, /* DAC4 analog mute */
  318. 0x04, 0, /* DAC5 analog mute */
  319. 0x05, 0, /* DAC6 analog mute */
  320. 0x06, 0, /* DAC7 analog mute */
  321. 0x07, 0, /* DAC8 analog mute */
  322. 0x08, 0x100, /* master analog mute */
  323. 0x09, 0xff, /* DAC1 digital full */
  324. 0x0a, 0xff, /* DAC2 digital full */
  325. 0x0b, 0xff, /* DAC3 digital full */
  326. 0x0c, 0xff, /* DAC4 digital full */
  327. 0x0d, 0xff, /* DAC5 digital full */
  328. 0x0e, 0xff, /* DAC6 digital full */
  329. 0x0f, 0xff, /* DAC7 digital full */
  330. 0x10, 0xff, /* DAC8 digital full */
  331. 0x11, 0x1ff, /* master digital full */
  332. 0x12, 0x000, /* phase normal */
  333. 0x13, 0x090, /* unmute DAC L/R */
  334. 0x14, 0x000, /* all unmute */
  335. 0x15, 0x000, /* no deemphasis, no ZFLG */
  336. 0x19, 0x000, /* -12dB ADC/L */
  337. 0x1a, 0x000, /* -12dB ADC/R */
  338. (unsigned short)-1
  339. };
  340. unsigned int tmp;
  341. struct snd_akm4xxx *ak;
  342. const unsigned short *p;
  343. int i;
  344. ice->num_total_dacs = 8;
  345. ice->num_total_adcs = 2;
  346. // Initialize analog chips
  347. ak = ice->akm = kzalloc(sizeof(struct snd_akm4xxx), GFP_KERNEL);
  348. if (!ak)
  349. return -ENOMEM;
  350. ice->akm_codecs = 1;
  351. snd_ice1712_gpio_set_dir(ice, 0x5fffff); /* fix this for the time being */
  352. /* reset the wm codec as the SPI mode */
  353. snd_ice1712_save_gpio_status(ice);
  354. snd_ice1712_gpio_set_mask(ice, ~(PHASE28_WM_RESET|PHASE28_WM_CS|PHASE28_HP_SEL));
  355. tmp = snd_ice1712_gpio_read(ice);
  356. tmp &= ~PHASE28_WM_RESET;
  357. snd_ice1712_gpio_write(ice, tmp);
  358. udelay(1);
  359. tmp |= PHASE28_WM_CS;
  360. snd_ice1712_gpio_write(ice, tmp);
  361. udelay(1);
  362. tmp |= PHASE28_WM_RESET;
  363. snd_ice1712_gpio_write(ice, tmp);
  364. udelay(1);
  365. p = wm_inits_phase28;
  366. for (; *p != (unsigned short)-1; p += 2)
  367. wm_put(ice, p[0], p[1]);
  368. snd_ice1712_restore_gpio_status(ice);
  369. ice->spec.phase28.master[0] = WM_VOL_MUTE;
  370. ice->spec.phase28.master[1] = WM_VOL_MUTE;
  371. for (i = 0; i < ice->num_total_dacs; i++) {
  372. ice->spec.phase28.vol[i] = WM_VOL_MUTE;
  373. wm_set_vol(ice, i, ice->spec.phase28.vol[i], ice->spec.phase28.master[i % 2]);
  374. }
  375. return 0;
  376. }
  377. /*
  378. * DAC volume attenuation mixer control
  379. */
  380. static int wm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  381. {
  382. int voices = kcontrol->private_value >> 8;
  383. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  384. uinfo->count = voices;
  385. uinfo->value.integer.min = 0; /* mute (-101dB) */
  386. uinfo->value.integer.max = 0x7F; /* 0dB */
  387. return 0;
  388. }
  389. static int wm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  390. {
  391. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  392. int i, ofs, voices;
  393. voices = kcontrol->private_value >> 8;
  394. ofs = kcontrol->private_value & 0xff;
  395. for (i = 0; i < voices; i++)
  396. ucontrol->value.integer.value[i] = ice->spec.phase28.vol[ofs+i] & ~WM_VOL_MUTE;
  397. return 0;
  398. }
  399. static int wm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  400. {
  401. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  402. int i, idx, ofs, voices;
  403. int change = 0;
  404. voices = kcontrol->private_value >> 8;
  405. ofs = kcontrol->private_value & 0xff;
  406. snd_ice1712_save_gpio_status(ice);
  407. for (i = 0; i < voices; i++) {
  408. idx = WM_DAC_ATTEN + ofs + i;
  409. if (ucontrol->value.integer.value[i] != ice->spec.phase28.vol[ofs+i]) {
  410. ice->spec.phase28.vol[ofs+i] &= WM_VOL_MUTE;
  411. ice->spec.phase28.vol[ofs+i] |= ucontrol->value.integer.value[i];
  412. wm_set_vol(ice, idx, ice->spec.phase28.vol[ofs+i],
  413. ice->spec.phase28.master[i]);
  414. change = 1;
  415. }
  416. }
  417. snd_ice1712_restore_gpio_status(ice);
  418. return change;
  419. }
  420. /*
  421. * WM8770 mute control
  422. */
  423. static int wm_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
  424. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  425. uinfo->count = kcontrol->private_value >> 8;
  426. uinfo->value.integer.min = 0;
  427. uinfo->value.integer.max = 1;
  428. return 0;
  429. }
  430. static int wm_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  431. {
  432. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  433. int voices, ofs, i;
  434. voices = kcontrol->private_value >> 8;
  435. ofs = kcontrol->private_value & 0xFF;
  436. for (i = 0; i < voices; i++)
  437. ucontrol->value.integer.value[i] = (ice->spec.phase28.vol[ofs+i] & WM_VOL_MUTE) ? 0 : 1;
  438. return 0;
  439. }
  440. static int wm_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  441. {
  442. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  443. int change = 0, voices, ofs, i;
  444. voices = kcontrol->private_value >> 8;
  445. ofs = kcontrol->private_value & 0xFF;
  446. snd_ice1712_save_gpio_status(ice);
  447. for (i = 0; i < voices; i++) {
  448. int val = (ice->spec.phase28.vol[ofs + i] & WM_VOL_MUTE) ? 0 : 1;
  449. if (ucontrol->value.integer.value[i] != val) {
  450. ice->spec.phase28.vol[ofs + i] &= ~WM_VOL_MUTE;
  451. ice->spec.phase28.vol[ofs + i] |=
  452. ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
  453. wm_set_vol(ice, ofs + i, ice->spec.phase28.vol[ofs + i],
  454. ice->spec.phase28.master[i]);
  455. change = 1;
  456. }
  457. }
  458. snd_ice1712_restore_gpio_status(ice);
  459. return change;
  460. }
  461. /*
  462. * WM8770 master mute control
  463. */
  464. static int wm_master_mute_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo) {
  465. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  466. uinfo->count = 2;
  467. uinfo->value.integer.min = 0;
  468. uinfo->value.integer.max = 1;
  469. return 0;
  470. }
  471. static int wm_master_mute_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  472. {
  473. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  474. ucontrol->value.integer.value[0] = (ice->spec.phase28.master[0] & WM_VOL_MUTE) ? 0 : 1;
  475. ucontrol->value.integer.value[1] = (ice->spec.phase28.master[1] & WM_VOL_MUTE) ? 0 : 1;
  476. return 0;
  477. }
  478. static int wm_master_mute_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  479. {
  480. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  481. int change = 0, i;
  482. snd_ice1712_save_gpio_status(ice);
  483. for (i = 0; i < 2; i++) {
  484. int val = (ice->spec.phase28.master[i] & WM_VOL_MUTE) ? 0 : 1;
  485. if (ucontrol->value.integer.value[i] != val) {
  486. int dac;
  487. ice->spec.phase28.master[i] &= ~WM_VOL_MUTE;
  488. ice->spec.phase28.master[i] |=
  489. ucontrol->value.integer.value[i] ? 0 : WM_VOL_MUTE;
  490. for (dac = 0; dac < ice->num_total_dacs; dac += 2)
  491. wm_set_vol(ice, WM_DAC_ATTEN + dac + i,
  492. ice->spec.phase28.vol[dac + i],
  493. ice->spec.phase28.master[i]);
  494. change = 1;
  495. }
  496. }
  497. snd_ice1712_restore_gpio_status(ice);
  498. return change;
  499. }
  500. /* digital master volume */
  501. #define PCM_0dB 0xff
  502. #define PCM_RES 128 /* -64dB */
  503. #define PCM_MIN (PCM_0dB - PCM_RES)
  504. static int wm_pcm_vol_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  505. {
  506. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  507. uinfo->count = 1;
  508. uinfo->value.integer.min = 0; /* mute (-64dB) */
  509. uinfo->value.integer.max = PCM_RES; /* 0dB */
  510. return 0;
  511. }
  512. static int wm_pcm_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  513. {
  514. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  515. unsigned short val;
  516. mutex_lock(&ice->gpio_mutex);
  517. val = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
  518. val = val > PCM_MIN ? (val - PCM_MIN) : 0;
  519. ucontrol->value.integer.value[0] = val;
  520. mutex_unlock(&ice->gpio_mutex);
  521. return 0;
  522. }
  523. static int wm_pcm_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  524. {
  525. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  526. unsigned short ovol, nvol;
  527. int change = 0;
  528. snd_ice1712_save_gpio_status(ice);
  529. nvol = ucontrol->value.integer.value[0];
  530. nvol = (nvol ? (nvol + PCM_MIN) : 0) & 0xff;
  531. ovol = wm_get(ice, WM_DAC_DIG_MASTER_ATTEN) & 0xff;
  532. if (ovol != nvol) {
  533. wm_put(ice, WM_DAC_DIG_MASTER_ATTEN, nvol); /* prelatch */
  534. wm_put_nocache(ice, WM_DAC_DIG_MASTER_ATTEN, nvol | 0x100); /* update */
  535. change = 1;
  536. }
  537. snd_ice1712_restore_gpio_status(ice);
  538. return change;
  539. }
  540. /*
  541. */
  542. static int phase28_mono_bool_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
  543. {
  544. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  545. uinfo->count = 1;
  546. uinfo->value.integer.min = 0;
  547. uinfo->value.integer.max = 1;
  548. return 0;
  549. }
  550. /*
  551. * Deemphasis
  552. */
  553. #define phase28_deemp_info phase28_mono_bool_info
  554. static int phase28_deemp_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  555. {
  556. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  557. ucontrol->value.integer.value[0] = (wm_get(ice, WM_DAC_CTRL2) & 0xf) == 0xf;
  558. return 0;
  559. }
  560. static int phase28_deemp_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  561. {
  562. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  563. int temp, temp2;
  564. temp2 = temp = wm_get(ice, WM_DAC_CTRL2);
  565. if (ucontrol->value.integer.value[0])
  566. temp |= 0xf;
  567. else
  568. temp &= ~0xf;
  569. if (temp != temp2) {
  570. wm_put(ice, WM_DAC_CTRL2, temp);
  571. return 1;
  572. }
  573. return 0;
  574. }
  575. /*
  576. * ADC Oversampling
  577. */
  578. static int phase28_oversampling_info(struct snd_kcontrol *k, struct snd_ctl_elem_info *uinfo)
  579. {
  580. static char *texts[2] = { "128x", "64x" };
  581. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  582. uinfo->count = 1;
  583. uinfo->value.enumerated.items = 2;
  584. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  585. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  586. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  587. return 0;
  588. }
  589. static int phase28_oversampling_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  590. {
  591. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  592. ucontrol->value.enumerated.item[0] = (wm_get(ice, WM_MASTER) & 0x8) == 0x8;
  593. return 0;
  594. }
  595. static int phase28_oversampling_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  596. {
  597. int temp, temp2;
  598. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  599. temp2 = temp = wm_get(ice, WM_MASTER);
  600. if (ucontrol->value.enumerated.item[0])
  601. temp |= 0x8;
  602. else
  603. temp &= ~0x8;
  604. if (temp != temp2) {
  605. wm_put(ice, WM_MASTER, temp);
  606. return 1;
  607. }
  608. return 0;
  609. }
  610. static const DECLARE_TLV_DB_SCALE(db_scale_wm_dac, -12700, 100, 1);
  611. static const DECLARE_TLV_DB_SCALE(db_scale_wm_pcm, -6400, 50, 1);
  612. static const struct snd_kcontrol_new phase28_dac_controls[] __devinitdata = {
  613. {
  614. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  615. .name = "Master Playback Switch",
  616. .info = wm_master_mute_info,
  617. .get = wm_master_mute_get,
  618. .put = wm_master_mute_put
  619. },
  620. {
  621. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  622. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  623. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  624. .name = "Master Playback Volume",
  625. .info = wm_master_vol_info,
  626. .get = wm_master_vol_get,
  627. .put = wm_master_vol_put,
  628. .tlv = { .p = db_scale_wm_dac }
  629. },
  630. {
  631. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  632. .name = "Front Playback Switch",
  633. .info = wm_mute_info,
  634. .get = wm_mute_get,
  635. .put = wm_mute_put,
  636. .private_value = (2 << 8) | 0
  637. },
  638. {
  639. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  640. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  641. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  642. .name = "Front Playback Volume",
  643. .info = wm_vol_info,
  644. .get = wm_vol_get,
  645. .put = wm_vol_put,
  646. .private_value = (2 << 8) | 0,
  647. .tlv = { .p = db_scale_wm_dac }
  648. },
  649. {
  650. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  651. .name = "Rear Playback Switch",
  652. .info = wm_mute_info,
  653. .get = wm_mute_get,
  654. .put = wm_mute_put,
  655. .private_value = (2 << 8) | 2
  656. },
  657. {
  658. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  659. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  660. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  661. .name = "Rear Playback Volume",
  662. .info = wm_vol_info,
  663. .get = wm_vol_get,
  664. .put = wm_vol_put,
  665. .private_value = (2 << 8) | 2,
  666. .tlv = { .p = db_scale_wm_dac }
  667. },
  668. {
  669. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  670. .name = "Center Playback Switch",
  671. .info = wm_mute_info,
  672. .get = wm_mute_get,
  673. .put = wm_mute_put,
  674. .private_value = (1 << 8) | 4
  675. },
  676. {
  677. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  678. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  679. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  680. .name = "Center Playback Volume",
  681. .info = wm_vol_info,
  682. .get = wm_vol_get,
  683. .put = wm_vol_put,
  684. .private_value = (1 << 8) | 4,
  685. .tlv = { .p = db_scale_wm_dac }
  686. },
  687. {
  688. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  689. .name = "LFE Playback Switch",
  690. .info = wm_mute_info,
  691. .get = wm_mute_get,
  692. .put = wm_mute_put,
  693. .private_value = (1 << 8) | 5
  694. },
  695. {
  696. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  697. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  698. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  699. .name = "LFE Playback Volume",
  700. .info = wm_vol_info,
  701. .get = wm_vol_get,
  702. .put = wm_vol_put,
  703. .private_value = (1 << 8) | 5,
  704. .tlv = { .p = db_scale_wm_dac }
  705. },
  706. {
  707. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  708. .name = "Side Playback Switch",
  709. .info = wm_mute_info,
  710. .get = wm_mute_get,
  711. .put = wm_mute_put,
  712. .private_value = (2 << 8) | 6
  713. },
  714. {
  715. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  716. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  717. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  718. .name = "Side Playback Volume",
  719. .info = wm_vol_info,
  720. .get = wm_vol_get,
  721. .put = wm_vol_put,
  722. .private_value = (2 << 8) | 6,
  723. .tlv = { .p = db_scale_wm_dac }
  724. }
  725. };
  726. static const struct snd_kcontrol_new wm_controls[] __devinitdata = {
  727. {
  728. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  729. .name = "PCM Playback Switch",
  730. .info = wm_pcm_mute_info,
  731. .get = wm_pcm_mute_get,
  732. .put = wm_pcm_mute_put
  733. },
  734. {
  735. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  736. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  737. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  738. .name = "PCM Playback Volume",
  739. .info = wm_pcm_vol_info,
  740. .get = wm_pcm_vol_get,
  741. .put = wm_pcm_vol_put,
  742. .tlv = { .p = db_scale_wm_pcm }
  743. },
  744. {
  745. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  746. .name = "DAC Deemphasis Switch",
  747. .info = phase28_deemp_info,
  748. .get = phase28_deemp_get,
  749. .put = phase28_deemp_put
  750. },
  751. {
  752. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  753. .name = "ADC Oversampling",
  754. .info = phase28_oversampling_info,
  755. .get = phase28_oversampling_get,
  756. .put = phase28_oversampling_put
  757. }
  758. };
  759. static int __devinit phase28_add_controls(struct snd_ice1712 *ice)
  760. {
  761. unsigned int i, counts;
  762. int err;
  763. counts = ARRAY_SIZE(phase28_dac_controls);
  764. for (i = 0; i < counts; i++) {
  765. err = snd_ctl_add(ice->card, snd_ctl_new1(&phase28_dac_controls[i], ice));
  766. if (err < 0)
  767. return err;
  768. }
  769. for (i = 0; i < ARRAY_SIZE(wm_controls); i++) {
  770. err = snd_ctl_add(ice->card, snd_ctl_new1(&wm_controls[i], ice));
  771. if (err < 0)
  772. return err;
  773. }
  774. return 0;
  775. }
  776. const struct snd_ice1712_card_info snd_vt1724_phase_cards[] __devinitdata = {
  777. {
  778. .subvendor = VT1724_SUBDEVICE_PHASE22,
  779. .name = "Terratec PHASE 22",
  780. .model = "phase22",
  781. .chip_init = phase22_init,
  782. .build_controls = phase22_add_controls,
  783. .eeprom_size = sizeof(phase22_eeprom),
  784. .eeprom_data = phase22_eeprom,
  785. },
  786. {
  787. .subvendor = VT1724_SUBDEVICE_PHASE28,
  788. .name = "Terratec PHASE 28",
  789. .model = "phase28",
  790. .chip_init = phase28_init,
  791. .build_controls = phase28_add_controls,
  792. .eeprom_size = sizeof(phase28_eeprom),
  793. .eeprom_data = phase28_eeprom,
  794. },
  795. { } /* terminator */
  796. };