ice1712.c 83 KB

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  1. /*
  2. * ALSA driver for ICEnsemble ICE1712 (Envy24)
  3. *
  4. * Copyright (c) 2000 Jaroslav Kysela <perex@suse.cz>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. NOTES:
  23. - spdif nonaudio consumer mode does not work (at least with my
  24. Sony STR-DB830)
  25. */
  26. /*
  27. * Changes:
  28. *
  29. * 2002.09.09 Takashi Iwai <tiwai@suse.de>
  30. * split the code to several files. each low-level routine
  31. * is stored in the local file and called from registration
  32. * function from card_info struct.
  33. *
  34. * 2002.11.26 James Stafford <jstafford@ampltd.com>
  35. * Added support for VT1724 (Envy24HT)
  36. * I have left out support for 176.4 and 192 KHz for the moment.
  37. * I also haven't done anything with the internal S/PDIF transmitter or the MPU-401
  38. *
  39. * 2003.02.20 Taksahi Iwai <tiwai@suse.de>
  40. * Split vt1724 part to an independent driver.
  41. * The GPIO is accessed through the callback functions now.
  42. *
  43. * 2004.03.31 Doug McLain <nostar@comcast.net>
  44. * Added support for Event Electronics EZ8 card to hoontech.c.
  45. */
  46. #include <sound/driver.h>
  47. #include <asm/io.h>
  48. #include <linux/delay.h>
  49. #include <linux/interrupt.h>
  50. #include <linux/init.h>
  51. #include <linux/pci.h>
  52. #include <linux/dma-mapping.h>
  53. #include <linux/slab.h>
  54. #include <linux/moduleparam.h>
  55. #include <linux/mutex.h>
  56. #include <sound/core.h>
  57. #include <sound/cs8427.h>
  58. #include <sound/info.h>
  59. #include <sound/initval.h>
  60. #include <sound/tlv.h>
  61. #include <sound/asoundef.h>
  62. #include "ice1712.h"
  63. /* lowlevel routines */
  64. #include "delta.h"
  65. #include "ews.h"
  66. #include "hoontech.h"
  67. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  68. MODULE_DESCRIPTION("ICEnsemble ICE1712 (Envy24)");
  69. MODULE_LICENSE("GPL");
  70. MODULE_SUPPORTED_DEVICE("{"
  71. HOONTECH_DEVICE_DESC
  72. DELTA_DEVICE_DESC
  73. EWS_DEVICE_DESC
  74. "{ICEnsemble,Generic ICE1712},"
  75. "{ICEnsemble,Generic Envy24}}");
  76. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  77. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  78. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
  79. static char *model[SNDRV_CARDS];
  80. static int omni[SNDRV_CARDS]; /* Delta44 & 66 Omni I/O support */
  81. static int cs8427_timeout[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = 500}; /* CS8427 S/PDIF transciever reset timeout value in msec */
  82. static int dxr_enable[SNDRV_CARDS]; /* DXR enable for DMX6FIRE */
  83. module_param_array(index, int, NULL, 0444);
  84. MODULE_PARM_DESC(index, "Index value for ICE1712 soundcard.");
  85. module_param_array(id, charp, NULL, 0444);
  86. MODULE_PARM_DESC(id, "ID string for ICE1712 soundcard.");
  87. module_param_array(enable, bool, NULL, 0444);
  88. MODULE_PARM_DESC(enable, "Enable ICE1712 soundcard.");
  89. module_param_array(omni, bool, NULL, 0444);
  90. MODULE_PARM_DESC(omni, "Enable Midiman M-Audio Delta Omni I/O support.");
  91. module_param_array(cs8427_timeout, int, NULL, 0444);
  92. MODULE_PARM_DESC(cs8427_timeout, "Define reset timeout for cs8427 chip in msec resolution.");
  93. module_param_array(model, charp, NULL, 0444);
  94. MODULE_PARM_DESC(model, "Use the given board model.");
  95. module_param_array(dxr_enable, int, NULL, 0444);
  96. MODULE_PARM_DESC(dxr_enable, "Enable DXR support for Terratec DMX6FIRE.");
  97. static const struct pci_device_id snd_ice1712_ids[] = {
  98. { PCI_VENDOR_ID_ICE, PCI_DEVICE_ID_ICE_1712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ICE1712 */
  99. { 0, }
  100. };
  101. MODULE_DEVICE_TABLE(pci, snd_ice1712_ids);
  102. static int snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice);
  103. static int snd_ice1712_build_controls(struct snd_ice1712 *ice);
  104. static int PRO_RATE_LOCKED;
  105. static int PRO_RATE_RESET = 1;
  106. static unsigned int PRO_RATE_DEFAULT = 44100;
  107. /*
  108. * Basic I/O
  109. */
  110. /* check whether the clock mode is spdif-in */
  111. static inline int is_spdif_master(struct snd_ice1712 *ice)
  112. {
  113. return (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER) ? 1 : 0;
  114. }
  115. static inline int is_pro_rate_locked(struct snd_ice1712 *ice)
  116. {
  117. return is_spdif_master(ice) || PRO_RATE_LOCKED;
  118. }
  119. static inline void snd_ice1712_ds_write(struct snd_ice1712 * ice, u8 channel, u8 addr, u32 data)
  120. {
  121. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  122. outl(data, ICEDS(ice, DATA));
  123. }
  124. static inline u32 snd_ice1712_ds_read(struct snd_ice1712 * ice, u8 channel, u8 addr)
  125. {
  126. outb((channel << 4) | addr, ICEDS(ice, INDEX));
  127. return inl(ICEDS(ice, DATA));
  128. }
  129. static void snd_ice1712_ac97_write(struct snd_ac97 *ac97,
  130. unsigned short reg,
  131. unsigned short val)
  132. {
  133. struct snd_ice1712 *ice = ac97->private_data;
  134. int tm;
  135. unsigned char old_cmd = 0;
  136. for (tm = 0; tm < 0x10000; tm++) {
  137. old_cmd = inb(ICEREG(ice, AC97_CMD));
  138. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  139. continue;
  140. if (!(old_cmd & ICE1712_AC97_READY))
  141. continue;
  142. break;
  143. }
  144. outb(reg, ICEREG(ice, AC97_INDEX));
  145. outw(val, ICEREG(ice, AC97_DATA));
  146. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  147. outb(old_cmd | ICE1712_AC97_WRITE, ICEREG(ice, AC97_CMD));
  148. for (tm = 0; tm < 0x10000; tm++)
  149. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  150. break;
  151. }
  152. static unsigned short snd_ice1712_ac97_read(struct snd_ac97 *ac97,
  153. unsigned short reg)
  154. {
  155. struct snd_ice1712 *ice = ac97->private_data;
  156. int tm;
  157. unsigned char old_cmd = 0;
  158. for (tm = 0; tm < 0x10000; tm++) {
  159. old_cmd = inb(ICEREG(ice, AC97_CMD));
  160. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  161. continue;
  162. if (!(old_cmd & ICE1712_AC97_READY))
  163. continue;
  164. break;
  165. }
  166. outb(reg, ICEREG(ice, AC97_INDEX));
  167. outb(old_cmd | ICE1712_AC97_READ, ICEREG(ice, AC97_CMD));
  168. for (tm = 0; tm < 0x10000; tm++)
  169. if ((inb(ICEREG(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  170. break;
  171. if (tm >= 0x10000) /* timeout */
  172. return ~0;
  173. return inw(ICEREG(ice, AC97_DATA));
  174. }
  175. /*
  176. * pro ac97 section
  177. */
  178. static void snd_ice1712_pro_ac97_write(struct snd_ac97 *ac97,
  179. unsigned short reg,
  180. unsigned short val)
  181. {
  182. struct snd_ice1712 *ice = ac97->private_data;
  183. int tm;
  184. unsigned char old_cmd = 0;
  185. for (tm = 0; tm < 0x10000; tm++) {
  186. old_cmd = inb(ICEMT(ice, AC97_CMD));
  187. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  188. continue;
  189. if (!(old_cmd & ICE1712_AC97_READY))
  190. continue;
  191. break;
  192. }
  193. outb(reg, ICEMT(ice, AC97_INDEX));
  194. outw(val, ICEMT(ice, AC97_DATA));
  195. old_cmd &= ~(ICE1712_AC97_PBK_VSR | ICE1712_AC97_CAP_VSR);
  196. outb(old_cmd | ICE1712_AC97_WRITE, ICEMT(ice, AC97_CMD));
  197. for (tm = 0; tm < 0x10000; tm++)
  198. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_WRITE) == 0)
  199. break;
  200. }
  201. static unsigned short snd_ice1712_pro_ac97_read(struct snd_ac97 *ac97,
  202. unsigned short reg)
  203. {
  204. struct snd_ice1712 *ice = ac97->private_data;
  205. int tm;
  206. unsigned char old_cmd = 0;
  207. for (tm = 0; tm < 0x10000; tm++) {
  208. old_cmd = inb(ICEMT(ice, AC97_CMD));
  209. if (old_cmd & (ICE1712_AC97_WRITE | ICE1712_AC97_READ))
  210. continue;
  211. if (!(old_cmd & ICE1712_AC97_READY))
  212. continue;
  213. break;
  214. }
  215. outb(reg, ICEMT(ice, AC97_INDEX));
  216. outb(old_cmd | ICE1712_AC97_READ, ICEMT(ice, AC97_CMD));
  217. for (tm = 0; tm < 0x10000; tm++)
  218. if ((inb(ICEMT(ice, AC97_CMD)) & ICE1712_AC97_READ) == 0)
  219. break;
  220. if (tm >= 0x10000) /* timeout */
  221. return ~0;
  222. return inw(ICEMT(ice, AC97_DATA));
  223. }
  224. /*
  225. * consumer ac97 digital mix
  226. */
  227. static int snd_ice1712_digmix_route_ac97_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  228. {
  229. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  230. uinfo->count = 1;
  231. uinfo->value.integer.min = 0;
  232. uinfo->value.integer.max = 1;
  233. return 0;
  234. }
  235. static int snd_ice1712_digmix_route_ac97_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  236. {
  237. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  238. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_ROUTECTRL)) & ICE1712_ROUTE_AC97 ? 1 : 0;
  239. return 0;
  240. }
  241. static int snd_ice1712_digmix_route_ac97_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  242. {
  243. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  244. unsigned char val, nval;
  245. spin_lock_irq(&ice->reg_lock);
  246. val = inb(ICEMT(ice, MONITOR_ROUTECTRL));
  247. nval = val & ~ICE1712_ROUTE_AC97;
  248. if (ucontrol->value.integer.value[0]) nval |= ICE1712_ROUTE_AC97;
  249. outb(nval, ICEMT(ice, MONITOR_ROUTECTRL));
  250. spin_unlock_irq(&ice->reg_lock);
  251. return val != nval;
  252. }
  253. static const struct snd_kcontrol_new snd_ice1712_mixer_digmix_route_ac97 __devinitdata = {
  254. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  255. .name = "Digital Mixer To AC97",
  256. .info = snd_ice1712_digmix_route_ac97_info,
  257. .get = snd_ice1712_digmix_route_ac97_get,
  258. .put = snd_ice1712_digmix_route_ac97_put,
  259. };
  260. /*
  261. * gpio operations
  262. */
  263. static void snd_ice1712_set_gpio_dir(struct snd_ice1712 *ice, unsigned int data)
  264. {
  265. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, data);
  266. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  267. }
  268. static void snd_ice1712_set_gpio_mask(struct snd_ice1712 *ice, unsigned int data)
  269. {
  270. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, data);
  271. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  272. }
  273. static unsigned int snd_ice1712_get_gpio_data(struct snd_ice1712 *ice)
  274. {
  275. return snd_ice1712_read(ice, ICE1712_IREG_GPIO_DATA);
  276. }
  277. static void snd_ice1712_set_gpio_data(struct snd_ice1712 *ice, unsigned int val)
  278. {
  279. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA, val);
  280. inb(ICEREG(ice, DATA)); /* dummy read for pci-posting */
  281. }
  282. /*
  283. *
  284. * CS8427 interface
  285. *
  286. */
  287. /*
  288. * change the input clock selection
  289. * spdif_clock = 1 - IEC958 input, 0 - Envy24
  290. */
  291. static int snd_ice1712_cs8427_set_input_clock(struct snd_ice1712 *ice, int spdif_clock)
  292. {
  293. unsigned char reg[2] = { 0x80 | 4, 0 }; /* CS8427 auto increment | register number 4 + data */
  294. unsigned char val, nval;
  295. int res = 0;
  296. snd_i2c_lock(ice->i2c);
  297. if (snd_i2c_sendbytes(ice->cs8427, reg, 1) != 1) {
  298. snd_i2c_unlock(ice->i2c);
  299. return -EIO;
  300. }
  301. if (snd_i2c_readbytes(ice->cs8427, &val, 1) != 1) {
  302. snd_i2c_unlock(ice->i2c);
  303. return -EIO;
  304. }
  305. nval = val & 0xf0;
  306. if (spdif_clock)
  307. nval |= 0x01;
  308. else
  309. nval |= 0x04;
  310. if (val != nval) {
  311. reg[1] = nval;
  312. if (snd_i2c_sendbytes(ice->cs8427, reg, 2) != 2) {
  313. res = -EIO;
  314. } else {
  315. res++;
  316. }
  317. }
  318. snd_i2c_unlock(ice->i2c);
  319. return res;
  320. }
  321. /*
  322. * spdif callbacks
  323. */
  324. static void open_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  325. {
  326. snd_cs8427_iec958_active(ice->cs8427, 1);
  327. }
  328. static void close_cs8427(struct snd_ice1712 *ice, struct snd_pcm_substream *substream)
  329. {
  330. snd_cs8427_iec958_active(ice->cs8427, 0);
  331. }
  332. static void setup_cs8427(struct snd_ice1712 *ice, int rate)
  333. {
  334. snd_cs8427_iec958_pcm(ice->cs8427, rate);
  335. }
  336. /*
  337. * create and initialize callbacks for cs8427 interface
  338. */
  339. int __devinit snd_ice1712_init_cs8427(struct snd_ice1712 *ice, int addr)
  340. {
  341. int err;
  342. if ((err = snd_cs8427_create(ice->i2c, addr,
  343. (ice->cs8427_timeout * HZ) / 1000,
  344. &ice->cs8427)) < 0) {
  345. snd_printk(KERN_ERR "CS8427 initialization failed\n");
  346. return err;
  347. }
  348. ice->spdif.ops.open = open_cs8427;
  349. ice->spdif.ops.close = close_cs8427;
  350. ice->spdif.ops.setup_rate = setup_cs8427;
  351. return 0;
  352. }
  353. static void snd_ice1712_set_input_clock_source(struct snd_ice1712 *ice, int spdif_is_master)
  354. {
  355. /* change CS8427 clock source too */
  356. if (ice->cs8427)
  357. snd_ice1712_cs8427_set_input_clock(ice, spdif_is_master);
  358. /* notify ak4524 chip as well */
  359. if (spdif_is_master) {
  360. unsigned int i;
  361. for (i = 0; i < ice->akm_codecs; i++) {
  362. if (ice->akm[i].ops.set_rate_val)
  363. ice->akm[i].ops.set_rate_val(&ice->akm[i], 0);
  364. }
  365. }
  366. }
  367. /*
  368. * Interrupt handler
  369. */
  370. static irqreturn_t snd_ice1712_interrupt(int irq, void *dev_id)
  371. {
  372. struct snd_ice1712 *ice = dev_id;
  373. unsigned char status;
  374. int handled = 0;
  375. while (1) {
  376. status = inb(ICEREG(ice, IRQSTAT));
  377. if (status == 0)
  378. break;
  379. handled = 1;
  380. if (status & ICE1712_IRQ_MPU1) {
  381. if (ice->rmidi[0])
  382. snd_mpu401_uart_interrupt(irq, ice->rmidi[0]->private_data);
  383. outb(ICE1712_IRQ_MPU1, ICEREG(ice, IRQSTAT));
  384. status &= ~ICE1712_IRQ_MPU1;
  385. }
  386. if (status & ICE1712_IRQ_TIMER)
  387. outb(ICE1712_IRQ_TIMER, ICEREG(ice, IRQSTAT));
  388. if (status & ICE1712_IRQ_MPU2) {
  389. if (ice->rmidi[1])
  390. snd_mpu401_uart_interrupt(irq, ice->rmidi[1]->private_data);
  391. outb(ICE1712_IRQ_MPU2, ICEREG(ice, IRQSTAT));
  392. status &= ~ICE1712_IRQ_MPU2;
  393. }
  394. if (status & ICE1712_IRQ_PROPCM) {
  395. unsigned char mtstat = inb(ICEMT(ice, IRQ));
  396. if (mtstat & ICE1712_MULTI_PBKSTATUS) {
  397. if (ice->playback_pro_substream)
  398. snd_pcm_period_elapsed(ice->playback_pro_substream);
  399. outb(ICE1712_MULTI_PBKSTATUS, ICEMT(ice, IRQ));
  400. }
  401. if (mtstat & ICE1712_MULTI_CAPSTATUS) {
  402. if (ice->capture_pro_substream)
  403. snd_pcm_period_elapsed(ice->capture_pro_substream);
  404. outb(ICE1712_MULTI_CAPSTATUS, ICEMT(ice, IRQ));
  405. }
  406. }
  407. if (status & ICE1712_IRQ_FM)
  408. outb(ICE1712_IRQ_FM, ICEREG(ice, IRQSTAT));
  409. if (status & ICE1712_IRQ_PBKDS) {
  410. u32 idx;
  411. u16 pbkstatus;
  412. struct snd_pcm_substream *substream;
  413. pbkstatus = inw(ICEDS(ice, INTSTAT));
  414. //printk("pbkstatus = 0x%x\n", pbkstatus);
  415. for (idx = 0; idx < 6; idx++) {
  416. if ((pbkstatus & (3 << (idx * 2))) == 0)
  417. continue;
  418. if ((substream = ice->playback_con_substream_ds[idx]) != NULL)
  419. snd_pcm_period_elapsed(substream);
  420. outw(3 << (idx * 2), ICEDS(ice, INTSTAT));
  421. }
  422. outb(ICE1712_IRQ_PBKDS, ICEREG(ice, IRQSTAT));
  423. }
  424. if (status & ICE1712_IRQ_CONCAP) {
  425. if (ice->capture_con_substream)
  426. snd_pcm_period_elapsed(ice->capture_con_substream);
  427. outb(ICE1712_IRQ_CONCAP, ICEREG(ice, IRQSTAT));
  428. }
  429. if (status & ICE1712_IRQ_CONPBK) {
  430. if (ice->playback_con_substream)
  431. snd_pcm_period_elapsed(ice->playback_con_substream);
  432. outb(ICE1712_IRQ_CONPBK, ICEREG(ice, IRQSTAT));
  433. }
  434. }
  435. return IRQ_RETVAL(handled);
  436. }
  437. /*
  438. * PCM part - misc
  439. */
  440. static int snd_ice1712_hw_params(struct snd_pcm_substream *substream,
  441. struct snd_pcm_hw_params *hw_params)
  442. {
  443. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  444. }
  445. static int snd_ice1712_hw_free(struct snd_pcm_substream *substream)
  446. {
  447. return snd_pcm_lib_free_pages(substream);
  448. }
  449. /*
  450. * PCM part - consumer I/O
  451. */
  452. static int snd_ice1712_playback_trigger(struct snd_pcm_substream *substream,
  453. int cmd)
  454. {
  455. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  456. int result = 0;
  457. u32 tmp;
  458. spin_lock(&ice->reg_lock);
  459. tmp = snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL);
  460. if (cmd == SNDRV_PCM_TRIGGER_START) {
  461. tmp |= 1;
  462. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  463. tmp &= ~1;
  464. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  465. tmp |= 2;
  466. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  467. tmp &= ~2;
  468. } else {
  469. result = -EINVAL;
  470. }
  471. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  472. spin_unlock(&ice->reg_lock);
  473. return result;
  474. }
  475. static int snd_ice1712_playback_ds_trigger(struct snd_pcm_substream *substream,
  476. int cmd)
  477. {
  478. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  479. int result = 0;
  480. u32 tmp;
  481. spin_lock(&ice->reg_lock);
  482. tmp = snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL);
  483. if (cmd == SNDRV_PCM_TRIGGER_START) {
  484. tmp |= 1;
  485. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  486. tmp &= ~1;
  487. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH) {
  488. tmp |= 2;
  489. } else if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE) {
  490. tmp &= ~2;
  491. } else {
  492. result = -EINVAL;
  493. }
  494. snd_ice1712_ds_write(ice, substream->number * 2, ICE1712_DSC_CONTROL, tmp);
  495. spin_unlock(&ice->reg_lock);
  496. return result;
  497. }
  498. static int snd_ice1712_capture_trigger(struct snd_pcm_substream *substream,
  499. int cmd)
  500. {
  501. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  502. int result = 0;
  503. u8 tmp;
  504. spin_lock(&ice->reg_lock);
  505. tmp = snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL);
  506. if (cmd == SNDRV_PCM_TRIGGER_START) {
  507. tmp |= 1;
  508. } else if (cmd == SNDRV_PCM_TRIGGER_STOP) {
  509. tmp &= ~1;
  510. } else {
  511. result = -EINVAL;
  512. }
  513. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  514. spin_unlock(&ice->reg_lock);
  515. return result;
  516. }
  517. static int snd_ice1712_playback_prepare(struct snd_pcm_substream *substream)
  518. {
  519. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  520. struct snd_pcm_runtime *runtime = substream->runtime;
  521. u32 period_size, buf_size, rate, tmp;
  522. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  523. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  524. tmp = 0x0000;
  525. if (snd_pcm_format_width(runtime->format) == 16)
  526. tmp |= 0x10;
  527. if (runtime->channels == 2)
  528. tmp |= 0x08;
  529. rate = (runtime->rate * 8192) / 375;
  530. if (rate > 0x000fffff)
  531. rate = 0x000fffff;
  532. spin_lock_irq(&ice->reg_lock);
  533. outb(0, ice->ddma_port + 15);
  534. outb(ICE1712_DMA_MODE_WRITE | ICE1712_DMA_AUTOINIT, ice->ddma_port + 0x0b);
  535. outl(runtime->dma_addr, ice->ddma_port + 0);
  536. outw(buf_size, ice->ddma_port + 4);
  537. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_LO, rate & 0xff);
  538. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_MID, (rate >> 8) & 0xff);
  539. snd_ice1712_write(ice, ICE1712_IREG_PBK_RATE_HI, (rate >> 16) & 0xff);
  540. snd_ice1712_write(ice, ICE1712_IREG_PBK_CTRL, tmp);
  541. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_LO, period_size & 0xff);
  542. snd_ice1712_write(ice, ICE1712_IREG_PBK_COUNT_HI, period_size >> 8);
  543. snd_ice1712_write(ice, ICE1712_IREG_PBK_LEFT, 0);
  544. snd_ice1712_write(ice, ICE1712_IREG_PBK_RIGHT, 0);
  545. spin_unlock_irq(&ice->reg_lock);
  546. return 0;
  547. }
  548. static int snd_ice1712_playback_ds_prepare(struct snd_pcm_substream *substream)
  549. {
  550. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  551. struct snd_pcm_runtime *runtime = substream->runtime;
  552. u32 period_size, buf_size, rate, tmp, chn;
  553. period_size = snd_pcm_lib_period_bytes(substream) - 1;
  554. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  555. tmp = 0x0064;
  556. if (snd_pcm_format_width(runtime->format) == 16)
  557. tmp &= ~0x04;
  558. if (runtime->channels == 2)
  559. tmp |= 0x08;
  560. rate = (runtime->rate * 8192) / 375;
  561. if (rate > 0x000fffff)
  562. rate = 0x000fffff;
  563. ice->playback_con_active_buf[substream->number] = 0;
  564. ice->playback_con_virt_addr[substream->number] = runtime->dma_addr;
  565. chn = substream->number * 2;
  566. spin_lock_irq(&ice->reg_lock);
  567. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR0, runtime->dma_addr);
  568. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT0, period_size);
  569. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_ADDR1, runtime->dma_addr + (runtime->periods > 1 ? period_size + 1 : 0));
  570. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_COUNT1, period_size);
  571. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_RATE, rate);
  572. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_VOLUME, 0);
  573. snd_ice1712_ds_write(ice, chn, ICE1712_DSC_CONTROL, tmp);
  574. if (runtime->channels == 2) {
  575. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_RATE, rate);
  576. snd_ice1712_ds_write(ice, chn + 1, ICE1712_DSC_VOLUME, 0);
  577. }
  578. spin_unlock_irq(&ice->reg_lock);
  579. return 0;
  580. }
  581. static int snd_ice1712_capture_prepare(struct snd_pcm_substream *substream)
  582. {
  583. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  584. struct snd_pcm_runtime *runtime = substream->runtime;
  585. u32 period_size, buf_size;
  586. u8 tmp;
  587. period_size = (snd_pcm_lib_period_bytes(substream) >> 2) - 1;
  588. buf_size = snd_pcm_lib_buffer_bytes(substream) - 1;
  589. tmp = 0x06;
  590. if (snd_pcm_format_width(runtime->format) == 16)
  591. tmp &= ~0x04;
  592. if (runtime->channels == 2)
  593. tmp &= ~0x02;
  594. spin_lock_irq(&ice->reg_lock);
  595. outl(ice->capture_con_virt_addr = runtime->dma_addr, ICEREG(ice, CONCAP_ADDR));
  596. outw(buf_size, ICEREG(ice, CONCAP_COUNT));
  597. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_HI, period_size >> 8);
  598. snd_ice1712_write(ice, ICE1712_IREG_CAP_COUNT_LO, period_size & 0xff);
  599. snd_ice1712_write(ice, ICE1712_IREG_CAP_CTRL, tmp);
  600. spin_unlock_irq(&ice->reg_lock);
  601. snd_ac97_set_rate(ice->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  602. return 0;
  603. }
  604. static snd_pcm_uframes_t snd_ice1712_playback_pointer(struct snd_pcm_substream *substream)
  605. {
  606. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  607. struct snd_pcm_runtime *runtime = substream->runtime;
  608. size_t ptr;
  609. if (!(snd_ice1712_read(ice, ICE1712_IREG_PBK_CTRL) & 1))
  610. return 0;
  611. ptr = runtime->buffer_size - inw(ice->ddma_port + 4);
  612. if (ptr == runtime->buffer_size)
  613. ptr = 0;
  614. return bytes_to_frames(substream->runtime, ptr);
  615. }
  616. static snd_pcm_uframes_t snd_ice1712_playback_ds_pointer(struct snd_pcm_substream *substream)
  617. {
  618. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  619. u8 addr;
  620. size_t ptr;
  621. if (!(snd_ice1712_ds_read(ice, substream->number * 2, ICE1712_DSC_CONTROL) & 1))
  622. return 0;
  623. if (ice->playback_con_active_buf[substream->number])
  624. addr = ICE1712_DSC_ADDR1;
  625. else
  626. addr = ICE1712_DSC_ADDR0;
  627. ptr = snd_ice1712_ds_read(ice, substream->number * 2, addr) -
  628. ice->playback_con_virt_addr[substream->number];
  629. if (ptr == substream->runtime->buffer_size)
  630. ptr = 0;
  631. return bytes_to_frames(substream->runtime, ptr);
  632. }
  633. static snd_pcm_uframes_t snd_ice1712_capture_pointer(struct snd_pcm_substream *substream)
  634. {
  635. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  636. size_t ptr;
  637. if (!(snd_ice1712_read(ice, ICE1712_IREG_CAP_CTRL) & 1))
  638. return 0;
  639. ptr = inl(ICEREG(ice, CONCAP_ADDR)) - ice->capture_con_virt_addr;
  640. if (ptr == substream->runtime->buffer_size)
  641. ptr = 0;
  642. return bytes_to_frames(substream->runtime, ptr);
  643. }
  644. static const struct snd_pcm_hardware snd_ice1712_playback =
  645. {
  646. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  647. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  648. SNDRV_PCM_INFO_MMAP_VALID |
  649. SNDRV_PCM_INFO_PAUSE),
  650. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  651. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  652. .rate_min = 4000,
  653. .rate_max = 48000,
  654. .channels_min = 1,
  655. .channels_max = 2,
  656. .buffer_bytes_max = (64*1024),
  657. .period_bytes_min = 64,
  658. .period_bytes_max = (64*1024),
  659. .periods_min = 1,
  660. .periods_max = 1024,
  661. .fifo_size = 0,
  662. };
  663. static const struct snd_pcm_hardware snd_ice1712_playback_ds =
  664. {
  665. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  666. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  667. SNDRV_PCM_INFO_MMAP_VALID |
  668. SNDRV_PCM_INFO_PAUSE),
  669. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  670. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  671. .rate_min = 4000,
  672. .rate_max = 48000,
  673. .channels_min = 1,
  674. .channels_max = 2,
  675. .buffer_bytes_max = (128*1024),
  676. .period_bytes_min = 64,
  677. .period_bytes_max = (128*1024),
  678. .periods_min = 2,
  679. .periods_max = 2,
  680. .fifo_size = 0,
  681. };
  682. static const struct snd_pcm_hardware snd_ice1712_capture =
  683. {
  684. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  685. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  686. SNDRV_PCM_INFO_MMAP_VALID),
  687. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  688. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  689. .rate_min = 4000,
  690. .rate_max = 48000,
  691. .channels_min = 1,
  692. .channels_max = 2,
  693. .buffer_bytes_max = (64*1024),
  694. .period_bytes_min = 64,
  695. .period_bytes_max = (64*1024),
  696. .periods_min = 1,
  697. .periods_max = 1024,
  698. .fifo_size = 0,
  699. };
  700. static int snd_ice1712_playback_open(struct snd_pcm_substream *substream)
  701. {
  702. struct snd_pcm_runtime *runtime = substream->runtime;
  703. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  704. ice->playback_con_substream = substream;
  705. runtime->hw = snd_ice1712_playback;
  706. return 0;
  707. }
  708. static int snd_ice1712_playback_ds_open(struct snd_pcm_substream *substream)
  709. {
  710. struct snd_pcm_runtime *runtime = substream->runtime;
  711. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  712. u32 tmp;
  713. ice->playback_con_substream_ds[substream->number] = substream;
  714. runtime->hw = snd_ice1712_playback_ds;
  715. spin_lock_irq(&ice->reg_lock);
  716. tmp = inw(ICEDS(ice, INTMASK)) & ~(1 << (substream->number * 2));
  717. outw(tmp, ICEDS(ice, INTMASK));
  718. spin_unlock_irq(&ice->reg_lock);
  719. return 0;
  720. }
  721. static int snd_ice1712_capture_open(struct snd_pcm_substream *substream)
  722. {
  723. struct snd_pcm_runtime *runtime = substream->runtime;
  724. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  725. ice->capture_con_substream = substream;
  726. runtime->hw = snd_ice1712_capture;
  727. runtime->hw.rates = ice->ac97->rates[AC97_RATES_ADC];
  728. if (!(runtime->hw.rates & SNDRV_PCM_RATE_8000))
  729. runtime->hw.rate_min = 48000;
  730. return 0;
  731. }
  732. static int snd_ice1712_playback_close(struct snd_pcm_substream *substream)
  733. {
  734. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  735. ice->playback_con_substream = NULL;
  736. return 0;
  737. }
  738. static int snd_ice1712_playback_ds_close(struct snd_pcm_substream *substream)
  739. {
  740. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  741. u32 tmp;
  742. spin_lock_irq(&ice->reg_lock);
  743. tmp = inw(ICEDS(ice, INTMASK)) | (3 << (substream->number * 2));
  744. outw(tmp, ICEDS(ice, INTMASK));
  745. spin_unlock_irq(&ice->reg_lock);
  746. ice->playback_con_substream_ds[substream->number] = NULL;
  747. return 0;
  748. }
  749. static int snd_ice1712_capture_close(struct snd_pcm_substream *substream)
  750. {
  751. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  752. ice->capture_con_substream = NULL;
  753. return 0;
  754. }
  755. static struct snd_pcm_ops snd_ice1712_playback_ops = {
  756. .open = snd_ice1712_playback_open,
  757. .close = snd_ice1712_playback_close,
  758. .ioctl = snd_pcm_lib_ioctl,
  759. .hw_params = snd_ice1712_hw_params,
  760. .hw_free = snd_ice1712_hw_free,
  761. .prepare = snd_ice1712_playback_prepare,
  762. .trigger = snd_ice1712_playback_trigger,
  763. .pointer = snd_ice1712_playback_pointer,
  764. };
  765. static struct snd_pcm_ops snd_ice1712_playback_ds_ops = {
  766. .open = snd_ice1712_playback_ds_open,
  767. .close = snd_ice1712_playback_ds_close,
  768. .ioctl = snd_pcm_lib_ioctl,
  769. .hw_params = snd_ice1712_hw_params,
  770. .hw_free = snd_ice1712_hw_free,
  771. .prepare = snd_ice1712_playback_ds_prepare,
  772. .trigger = snd_ice1712_playback_ds_trigger,
  773. .pointer = snd_ice1712_playback_ds_pointer,
  774. };
  775. static struct snd_pcm_ops snd_ice1712_capture_ops = {
  776. .open = snd_ice1712_capture_open,
  777. .close = snd_ice1712_capture_close,
  778. .ioctl = snd_pcm_lib_ioctl,
  779. .hw_params = snd_ice1712_hw_params,
  780. .hw_free = snd_ice1712_hw_free,
  781. .prepare = snd_ice1712_capture_prepare,
  782. .trigger = snd_ice1712_capture_trigger,
  783. .pointer = snd_ice1712_capture_pointer,
  784. };
  785. static int __devinit snd_ice1712_pcm(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  786. {
  787. struct snd_pcm *pcm;
  788. int err;
  789. if (rpcm)
  790. *rpcm = NULL;
  791. err = snd_pcm_new(ice->card, "ICE1712 consumer", device, 1, 1, &pcm);
  792. if (err < 0)
  793. return err;
  794. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ops);
  795. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_ops);
  796. pcm->private_data = ice;
  797. pcm->info_flags = 0;
  798. strcpy(pcm->name, "ICE1712 consumer");
  799. ice->pcm = pcm;
  800. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  801. snd_dma_pci_data(ice->pci), 64*1024, 64*1024);
  802. if (rpcm)
  803. *rpcm = pcm;
  804. printk(KERN_WARNING "Consumer PCM code does not work well at the moment --jk\n");
  805. return 0;
  806. }
  807. static int __devinit snd_ice1712_pcm_ds(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  808. {
  809. struct snd_pcm *pcm;
  810. int err;
  811. if (rpcm)
  812. *rpcm = NULL;
  813. err = snd_pcm_new(ice->card, "ICE1712 consumer (DS)", device, 6, 0, &pcm);
  814. if (err < 0)
  815. return err;
  816. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_ds_ops);
  817. pcm->private_data = ice;
  818. pcm->info_flags = 0;
  819. strcpy(pcm->name, "ICE1712 consumer (DS)");
  820. ice->pcm_ds = pcm;
  821. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  822. snd_dma_pci_data(ice->pci), 64*1024, 128*1024);
  823. if (rpcm)
  824. *rpcm = pcm;
  825. return 0;
  826. }
  827. /*
  828. * PCM code - professional part (multitrack)
  829. */
  830. static unsigned int rates[] = { 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  831. 32000, 44100, 48000, 64000, 88200, 96000 };
  832. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  833. .count = ARRAY_SIZE(rates),
  834. .list = rates,
  835. .mask = 0,
  836. };
  837. static int snd_ice1712_pro_trigger(struct snd_pcm_substream *substream,
  838. int cmd)
  839. {
  840. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  841. switch (cmd) {
  842. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  843. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  844. {
  845. unsigned int what;
  846. unsigned int old;
  847. if (substream->stream != SNDRV_PCM_STREAM_PLAYBACK)
  848. return -EINVAL;
  849. what = ICE1712_PLAYBACK_PAUSE;
  850. snd_pcm_trigger_done(substream, substream);
  851. spin_lock(&ice->reg_lock);
  852. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  853. if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH)
  854. old |= what;
  855. else
  856. old &= ~what;
  857. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  858. spin_unlock(&ice->reg_lock);
  859. break;
  860. }
  861. case SNDRV_PCM_TRIGGER_START:
  862. case SNDRV_PCM_TRIGGER_STOP:
  863. {
  864. unsigned int what = 0;
  865. unsigned int old;
  866. struct list_head *pos;
  867. struct snd_pcm_substream *s;
  868. snd_pcm_group_for_each(pos, substream) {
  869. s = snd_pcm_group_substream_entry(pos);
  870. if (s == ice->playback_pro_substream) {
  871. what |= ICE1712_PLAYBACK_START;
  872. snd_pcm_trigger_done(s, substream);
  873. } else if (s == ice->capture_pro_substream) {
  874. what |= ICE1712_CAPTURE_START_SHADOW;
  875. snd_pcm_trigger_done(s, substream);
  876. }
  877. }
  878. spin_lock(&ice->reg_lock);
  879. old = inl(ICEMT(ice, PLAYBACK_CONTROL));
  880. if (cmd == SNDRV_PCM_TRIGGER_START)
  881. old |= what;
  882. else
  883. old &= ~what;
  884. outl(old, ICEMT(ice, PLAYBACK_CONTROL));
  885. spin_unlock(&ice->reg_lock);
  886. break;
  887. }
  888. default:
  889. return -EINVAL;
  890. }
  891. return 0;
  892. }
  893. /*
  894. */
  895. static void snd_ice1712_set_pro_rate(struct snd_ice1712 *ice, unsigned int rate, int force)
  896. {
  897. unsigned long flags;
  898. unsigned char val, old;
  899. unsigned int i;
  900. switch (rate) {
  901. case 8000: val = 6; break;
  902. case 9600: val = 3; break;
  903. case 11025: val = 10; break;
  904. case 12000: val = 2; break;
  905. case 16000: val = 5; break;
  906. case 22050: val = 9; break;
  907. case 24000: val = 1; break;
  908. case 32000: val = 4; break;
  909. case 44100: val = 8; break;
  910. case 48000: val = 0; break;
  911. case 64000: val = 15; break;
  912. case 88200: val = 11; break;
  913. case 96000: val = 7; break;
  914. default:
  915. snd_BUG();
  916. val = 0;
  917. rate = 48000;
  918. break;
  919. }
  920. spin_lock_irqsave(&ice->reg_lock, flags);
  921. if (inb(ICEMT(ice, PLAYBACK_CONTROL)) & (ICE1712_CAPTURE_START_SHADOW|
  922. ICE1712_PLAYBACK_PAUSE|
  923. ICE1712_PLAYBACK_START)) {
  924. __out:
  925. spin_unlock_irqrestore(&ice->reg_lock, flags);
  926. return;
  927. }
  928. if (!force && is_pro_rate_locked(ice))
  929. goto __out;
  930. old = inb(ICEMT(ice, RATE));
  931. if (!force && old == val)
  932. goto __out;
  933. outb(val, ICEMT(ice, RATE));
  934. spin_unlock_irqrestore(&ice->reg_lock, flags);
  935. if (ice->gpio.set_pro_rate)
  936. ice->gpio.set_pro_rate(ice, rate);
  937. for (i = 0; i < ice->akm_codecs; i++) {
  938. if (ice->akm[i].ops.set_rate_val)
  939. ice->akm[i].ops.set_rate_val(&ice->akm[i], rate);
  940. }
  941. if (ice->spdif.ops.setup_rate)
  942. ice->spdif.ops.setup_rate(ice, rate);
  943. }
  944. static int snd_ice1712_playback_pro_prepare(struct snd_pcm_substream *substream)
  945. {
  946. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  947. ice->playback_pro_size = snd_pcm_lib_buffer_bytes(substream);
  948. spin_lock_irq(&ice->reg_lock);
  949. outl(substream->runtime->dma_addr, ICEMT(ice, PLAYBACK_ADDR));
  950. outw((ice->playback_pro_size >> 2) - 1, ICEMT(ice, PLAYBACK_SIZE));
  951. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, PLAYBACK_COUNT));
  952. spin_unlock_irq(&ice->reg_lock);
  953. return 0;
  954. }
  955. static int snd_ice1712_playback_pro_hw_params(struct snd_pcm_substream *substream,
  956. struct snd_pcm_hw_params *hw_params)
  957. {
  958. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  959. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  960. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  961. }
  962. static int snd_ice1712_capture_pro_prepare(struct snd_pcm_substream *substream)
  963. {
  964. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  965. ice->capture_pro_size = snd_pcm_lib_buffer_bytes(substream);
  966. spin_lock_irq(&ice->reg_lock);
  967. outl(substream->runtime->dma_addr, ICEMT(ice, CAPTURE_ADDR));
  968. outw((ice->capture_pro_size >> 2) - 1, ICEMT(ice, CAPTURE_SIZE));
  969. outw((snd_pcm_lib_period_bytes(substream) >> 2) - 1, ICEMT(ice, CAPTURE_COUNT));
  970. spin_unlock_irq(&ice->reg_lock);
  971. return 0;
  972. }
  973. static int snd_ice1712_capture_pro_hw_params(struct snd_pcm_substream *substream,
  974. struct snd_pcm_hw_params *hw_params)
  975. {
  976. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  977. snd_ice1712_set_pro_rate(ice, params_rate(hw_params), 0);
  978. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  979. }
  980. static snd_pcm_uframes_t snd_ice1712_playback_pro_pointer(struct snd_pcm_substream *substream)
  981. {
  982. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  983. size_t ptr;
  984. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_PLAYBACK_START))
  985. return 0;
  986. ptr = ice->playback_pro_size - (inw(ICEMT(ice, PLAYBACK_SIZE)) << 2);
  987. if (ptr == substream->runtime->buffer_size)
  988. ptr = 0;
  989. return bytes_to_frames(substream->runtime, ptr);
  990. }
  991. static snd_pcm_uframes_t snd_ice1712_capture_pro_pointer(struct snd_pcm_substream *substream)
  992. {
  993. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  994. size_t ptr;
  995. if (!(inl(ICEMT(ice, PLAYBACK_CONTROL)) & ICE1712_CAPTURE_START_SHADOW))
  996. return 0;
  997. ptr = ice->capture_pro_size - (inw(ICEMT(ice, CAPTURE_SIZE)) << 2);
  998. if (ptr == substream->runtime->buffer_size)
  999. ptr = 0;
  1000. return bytes_to_frames(substream->runtime, ptr);
  1001. }
  1002. static const struct snd_pcm_hardware snd_ice1712_playback_pro =
  1003. {
  1004. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1005. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1006. SNDRV_PCM_INFO_MMAP_VALID |
  1007. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1008. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1009. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1010. .rate_min = 4000,
  1011. .rate_max = 96000,
  1012. .channels_min = 10,
  1013. .channels_max = 10,
  1014. .buffer_bytes_max = (256*1024),
  1015. .period_bytes_min = 10 * 4 * 2,
  1016. .period_bytes_max = 131040,
  1017. .periods_min = 1,
  1018. .periods_max = 1024,
  1019. .fifo_size = 0,
  1020. };
  1021. static const struct snd_pcm_hardware snd_ice1712_capture_pro =
  1022. {
  1023. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  1024. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1025. SNDRV_PCM_INFO_MMAP_VALID |
  1026. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_SYNC_START),
  1027. .formats = SNDRV_PCM_FMTBIT_S32_LE,
  1028. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_96000,
  1029. .rate_min = 4000,
  1030. .rate_max = 96000,
  1031. .channels_min = 12,
  1032. .channels_max = 12,
  1033. .buffer_bytes_max = (256*1024),
  1034. .period_bytes_min = 12 * 4 * 2,
  1035. .period_bytes_max = 131040,
  1036. .periods_min = 1,
  1037. .periods_max = 1024,
  1038. .fifo_size = 0,
  1039. };
  1040. static int snd_ice1712_playback_pro_open(struct snd_pcm_substream *substream)
  1041. {
  1042. struct snd_pcm_runtime *runtime = substream->runtime;
  1043. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1044. ice->playback_pro_substream = substream;
  1045. runtime->hw = snd_ice1712_playback_pro;
  1046. snd_pcm_set_sync(substream);
  1047. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1048. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1049. if (ice->spdif.ops.open)
  1050. ice->spdif.ops.open(ice, substream);
  1051. return 0;
  1052. }
  1053. static int snd_ice1712_capture_pro_open(struct snd_pcm_substream *substream)
  1054. {
  1055. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1056. struct snd_pcm_runtime *runtime = substream->runtime;
  1057. ice->capture_pro_substream = substream;
  1058. runtime->hw = snd_ice1712_capture_pro;
  1059. snd_pcm_set_sync(substream);
  1060. snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
  1061. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  1062. return 0;
  1063. }
  1064. static int snd_ice1712_playback_pro_close(struct snd_pcm_substream *substream)
  1065. {
  1066. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1067. if (PRO_RATE_RESET)
  1068. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1069. ice->playback_pro_substream = NULL;
  1070. if (ice->spdif.ops.close)
  1071. ice->spdif.ops.close(ice, substream);
  1072. return 0;
  1073. }
  1074. static int snd_ice1712_capture_pro_close(struct snd_pcm_substream *substream)
  1075. {
  1076. struct snd_ice1712 *ice = snd_pcm_substream_chip(substream);
  1077. if (PRO_RATE_RESET)
  1078. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 0);
  1079. ice->capture_pro_substream = NULL;
  1080. return 0;
  1081. }
  1082. static struct snd_pcm_ops snd_ice1712_playback_pro_ops = {
  1083. .open = snd_ice1712_playback_pro_open,
  1084. .close = snd_ice1712_playback_pro_close,
  1085. .ioctl = snd_pcm_lib_ioctl,
  1086. .hw_params = snd_ice1712_playback_pro_hw_params,
  1087. .hw_free = snd_ice1712_hw_free,
  1088. .prepare = snd_ice1712_playback_pro_prepare,
  1089. .trigger = snd_ice1712_pro_trigger,
  1090. .pointer = snd_ice1712_playback_pro_pointer,
  1091. };
  1092. static struct snd_pcm_ops snd_ice1712_capture_pro_ops = {
  1093. .open = snd_ice1712_capture_pro_open,
  1094. .close = snd_ice1712_capture_pro_close,
  1095. .ioctl = snd_pcm_lib_ioctl,
  1096. .hw_params = snd_ice1712_capture_pro_hw_params,
  1097. .hw_free = snd_ice1712_hw_free,
  1098. .prepare = snd_ice1712_capture_pro_prepare,
  1099. .trigger = snd_ice1712_pro_trigger,
  1100. .pointer = snd_ice1712_capture_pro_pointer,
  1101. };
  1102. static int __devinit snd_ice1712_pcm_profi(struct snd_ice1712 * ice, int device, struct snd_pcm ** rpcm)
  1103. {
  1104. struct snd_pcm *pcm;
  1105. int err;
  1106. if (rpcm)
  1107. *rpcm = NULL;
  1108. err = snd_pcm_new(ice->card, "ICE1712 multi", device, 1, 1, &pcm);
  1109. if (err < 0)
  1110. return err;
  1111. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_ice1712_playback_pro_ops);
  1112. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_ice1712_capture_pro_ops);
  1113. pcm->private_data = ice;
  1114. pcm->info_flags = 0;
  1115. strcpy(pcm->name, "ICE1712 multi");
  1116. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1117. snd_dma_pci_data(ice->pci), 256*1024, 256*1024);
  1118. ice->pcm_pro = pcm;
  1119. if (rpcm)
  1120. *rpcm = pcm;
  1121. if (ice->cs8427) {
  1122. /* assign channels to iec958 */
  1123. err = snd_cs8427_iec958_build(ice->cs8427,
  1124. pcm->streams[0].substream,
  1125. pcm->streams[1].substream);
  1126. if (err < 0)
  1127. return err;
  1128. }
  1129. if ((err = snd_ice1712_build_pro_mixer(ice)) < 0)
  1130. return err;
  1131. return 0;
  1132. }
  1133. /*
  1134. * Mixer section
  1135. */
  1136. static void snd_ice1712_update_volume(struct snd_ice1712 *ice, int index)
  1137. {
  1138. unsigned int vol = ice->pro_volumes[index];
  1139. unsigned short val = 0;
  1140. val |= (vol & 0x8000) == 0 ? (96 - (vol & 0x7f)) : 0x7f;
  1141. val |= ((vol & 0x80000000) == 0 ? (96 - ((vol >> 16) & 0x7f)) : 0x7f) << 8;
  1142. outb(index, ICEMT(ice, MONITOR_INDEX));
  1143. outw(val, ICEMT(ice, MONITOR_VOLUME));
  1144. }
  1145. static int snd_ice1712_pro_mixer_switch_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1146. {
  1147. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1148. uinfo->count = 2;
  1149. uinfo->value.integer.min = 0;
  1150. uinfo->value.integer.max = 1;
  1151. return 0;
  1152. }
  1153. static int snd_ice1712_pro_mixer_switch_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1154. {
  1155. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1156. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1157. spin_lock_irq(&ice->reg_lock);
  1158. ucontrol->value.integer.value[0] = !((ice->pro_volumes[index] >> 15) & 1);
  1159. ucontrol->value.integer.value[1] = !((ice->pro_volumes[index] >> 31) & 1);
  1160. spin_unlock_irq(&ice->reg_lock);
  1161. return 0;
  1162. }
  1163. static int snd_ice1712_pro_mixer_switch_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1164. {
  1165. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1166. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1167. unsigned int nval, change;
  1168. nval = (ucontrol->value.integer.value[0] ? 0 : 0x00008000) |
  1169. (ucontrol->value.integer.value[1] ? 0 : 0x80000000);
  1170. spin_lock_irq(&ice->reg_lock);
  1171. nval |= ice->pro_volumes[index] & ~0x80008000;
  1172. change = nval != ice->pro_volumes[index];
  1173. ice->pro_volumes[index] = nval;
  1174. snd_ice1712_update_volume(ice, index);
  1175. spin_unlock_irq(&ice->reg_lock);
  1176. return change;
  1177. }
  1178. static int snd_ice1712_pro_mixer_volume_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1179. {
  1180. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1181. uinfo->count = 2;
  1182. uinfo->value.integer.min = 0;
  1183. uinfo->value.integer.max = 96;
  1184. return 0;
  1185. }
  1186. static int snd_ice1712_pro_mixer_volume_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1187. {
  1188. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1189. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1190. spin_lock_irq(&ice->reg_lock);
  1191. ucontrol->value.integer.value[0] = (ice->pro_volumes[index] >> 0) & 127;
  1192. ucontrol->value.integer.value[1] = (ice->pro_volumes[index] >> 16) & 127;
  1193. spin_unlock_irq(&ice->reg_lock);
  1194. return 0;
  1195. }
  1196. static int snd_ice1712_pro_mixer_volume_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1197. {
  1198. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1199. int index = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id) + kcontrol->private_value;
  1200. unsigned int nval, change;
  1201. nval = (ucontrol->value.integer.value[0] & 127) |
  1202. ((ucontrol->value.integer.value[1] & 127) << 16);
  1203. spin_lock_irq(&ice->reg_lock);
  1204. nval |= ice->pro_volumes[index] & ~0x007f007f;
  1205. change = nval != ice->pro_volumes[index];
  1206. ice->pro_volumes[index] = nval;
  1207. snd_ice1712_update_volume(ice, index);
  1208. spin_unlock_irq(&ice->reg_lock);
  1209. return change;
  1210. }
  1211. static const DECLARE_TLV_DB_SCALE(db_scale_playback, -14400, 150, 0);
  1212. static const struct snd_kcontrol_new snd_ice1712_multi_playback_ctrls[] __devinitdata = {
  1213. {
  1214. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1215. .name = "Multi Playback Switch",
  1216. .info = snd_ice1712_pro_mixer_switch_info,
  1217. .get = snd_ice1712_pro_mixer_switch_get,
  1218. .put = snd_ice1712_pro_mixer_switch_put,
  1219. .private_value = 0,
  1220. .count = 10,
  1221. },
  1222. {
  1223. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1224. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1225. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1226. .name = "Multi Playback Volume",
  1227. .info = snd_ice1712_pro_mixer_volume_info,
  1228. .get = snd_ice1712_pro_mixer_volume_get,
  1229. .put = snd_ice1712_pro_mixer_volume_put,
  1230. .private_value = 0,
  1231. .count = 10,
  1232. .tlv = { .p = db_scale_playback }
  1233. },
  1234. };
  1235. static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_switch __devinitdata = {
  1236. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1237. .name = "H/W Multi Capture Switch",
  1238. .info = snd_ice1712_pro_mixer_switch_info,
  1239. .get = snd_ice1712_pro_mixer_switch_get,
  1240. .put = snd_ice1712_pro_mixer_switch_put,
  1241. .private_value = 10,
  1242. };
  1243. static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_switch __devinitdata = {
  1244. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1245. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,SWITCH),
  1246. .info = snd_ice1712_pro_mixer_switch_info,
  1247. .get = snd_ice1712_pro_mixer_switch_get,
  1248. .put = snd_ice1712_pro_mixer_switch_put,
  1249. .private_value = 18,
  1250. .count = 2,
  1251. };
  1252. static const struct snd_kcontrol_new snd_ice1712_multi_capture_analog_volume __devinitdata = {
  1253. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1254. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1255. SNDRV_CTL_ELEM_ACCESS_TLV_READ),
  1256. .name = "H/W Multi Capture Volume",
  1257. .info = snd_ice1712_pro_mixer_volume_info,
  1258. .get = snd_ice1712_pro_mixer_volume_get,
  1259. .put = snd_ice1712_pro_mixer_volume_put,
  1260. .private_value = 10,
  1261. .tlv = { .p = db_scale_playback }
  1262. };
  1263. static const struct snd_kcontrol_new snd_ice1712_multi_capture_spdif_volume __devinitdata = {
  1264. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1265. .name = SNDRV_CTL_NAME_IEC958("Multi ",CAPTURE,VOLUME),
  1266. .info = snd_ice1712_pro_mixer_volume_info,
  1267. .get = snd_ice1712_pro_mixer_volume_get,
  1268. .put = snd_ice1712_pro_mixer_volume_put,
  1269. .private_value = 18,
  1270. .count = 2,
  1271. };
  1272. static int __devinit snd_ice1712_build_pro_mixer(struct snd_ice1712 *ice)
  1273. {
  1274. struct snd_card *card = ice->card;
  1275. unsigned int idx;
  1276. int err;
  1277. /* multi-channel mixer */
  1278. for (idx = 0; idx < ARRAY_SIZE(snd_ice1712_multi_playback_ctrls); idx++) {
  1279. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_playback_ctrls[idx], ice));
  1280. if (err < 0)
  1281. return err;
  1282. }
  1283. if (ice->num_total_adcs > 0) {
  1284. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_switch;
  1285. tmp.count = ice->num_total_adcs;
  1286. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1287. if (err < 0)
  1288. return err;
  1289. }
  1290. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_switch, ice));
  1291. if (err < 0)
  1292. return err;
  1293. if (ice->num_total_adcs > 0) {
  1294. struct snd_kcontrol_new tmp = snd_ice1712_multi_capture_analog_volume;
  1295. tmp.count = ice->num_total_adcs;
  1296. err = snd_ctl_add(card, snd_ctl_new1(&tmp, ice));
  1297. if (err < 0)
  1298. return err;
  1299. }
  1300. err = snd_ctl_add(card, snd_ctl_new1(&snd_ice1712_multi_capture_spdif_volume, ice));
  1301. if (err < 0)
  1302. return err;
  1303. /* initialize volumes */
  1304. for (idx = 0; idx < 10; idx++) {
  1305. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1306. snd_ice1712_update_volume(ice, idx);
  1307. }
  1308. for (idx = 10; idx < 10 + ice->num_total_adcs; idx++) {
  1309. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1310. snd_ice1712_update_volume(ice, idx);
  1311. }
  1312. for (idx = 18; idx < 20; idx++) {
  1313. ice->pro_volumes[idx] = 0x80008000; /* mute */
  1314. snd_ice1712_update_volume(ice, idx);
  1315. }
  1316. return 0;
  1317. }
  1318. static void snd_ice1712_mixer_free_ac97(struct snd_ac97 *ac97)
  1319. {
  1320. struct snd_ice1712 *ice = ac97->private_data;
  1321. ice->ac97 = NULL;
  1322. }
  1323. static int __devinit snd_ice1712_ac97_mixer(struct snd_ice1712 * ice)
  1324. {
  1325. int err, bus_num = 0;
  1326. struct snd_ac97_template ac97;
  1327. struct snd_ac97_bus *pbus;
  1328. static struct snd_ac97_bus_ops con_ops = {
  1329. .write = snd_ice1712_ac97_write,
  1330. .read = snd_ice1712_ac97_read,
  1331. };
  1332. static struct snd_ac97_bus_ops pro_ops = {
  1333. .write = snd_ice1712_pro_ac97_write,
  1334. .read = snd_ice1712_pro_ac97_read,
  1335. };
  1336. if (ice_has_con_ac97(ice)) {
  1337. if ((err = snd_ac97_bus(ice->card, bus_num++, &con_ops, NULL, &pbus)) < 0)
  1338. return err;
  1339. memset(&ac97, 0, sizeof(ac97));
  1340. ac97.private_data = ice;
  1341. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1342. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1343. printk(KERN_WARNING "ice1712: cannot initialize ac97 for consumer, skipped\n");
  1344. else {
  1345. if ((err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_digmix_route_ac97, ice))) < 0)
  1346. return err;
  1347. return 0;
  1348. }
  1349. }
  1350. if (! (ice->eeprom.data[ICE_EEP1_ACLINK] & ICE1712_CFG_PRO_I2S)) {
  1351. if ((err = snd_ac97_bus(ice->card, bus_num, &pro_ops, NULL, &pbus)) < 0)
  1352. return err;
  1353. memset(&ac97, 0, sizeof(ac97));
  1354. ac97.private_data = ice;
  1355. ac97.private_free = snd_ice1712_mixer_free_ac97;
  1356. if ((err = snd_ac97_mixer(pbus, &ac97, &ice->ac97)) < 0)
  1357. printk(KERN_WARNING "ice1712: cannot initialize pro ac97, skipped\n");
  1358. else
  1359. return 0;
  1360. }
  1361. /* I2S mixer only */
  1362. strcat(ice->card->mixername, "ICE1712 - multitrack");
  1363. return 0;
  1364. }
  1365. /*
  1366. *
  1367. */
  1368. static inline unsigned int eeprom_double(struct snd_ice1712 *ice, int idx)
  1369. {
  1370. return (unsigned int)ice->eeprom.data[idx] | ((unsigned int)ice->eeprom.data[idx + 1] << 8);
  1371. }
  1372. static void snd_ice1712_proc_read(struct snd_info_entry *entry,
  1373. struct snd_info_buffer *buffer)
  1374. {
  1375. struct snd_ice1712 *ice = entry->private_data;
  1376. unsigned int idx;
  1377. snd_iprintf(buffer, "%s\n\n", ice->card->longname);
  1378. snd_iprintf(buffer, "EEPROM:\n");
  1379. snd_iprintf(buffer, " Subvendor : 0x%x\n", ice->eeprom.subvendor);
  1380. snd_iprintf(buffer, " Size : %i bytes\n", ice->eeprom.size);
  1381. snd_iprintf(buffer, " Version : %i\n", ice->eeprom.version);
  1382. snd_iprintf(buffer, " Codec : 0x%x\n", ice->eeprom.data[ICE_EEP1_CODEC]);
  1383. snd_iprintf(buffer, " ACLink : 0x%x\n", ice->eeprom.data[ICE_EEP1_ACLINK]);
  1384. snd_iprintf(buffer, " I2S ID : 0x%x\n", ice->eeprom.data[ICE_EEP1_I2SID]);
  1385. snd_iprintf(buffer, " S/PDIF : 0x%x\n", ice->eeprom.data[ICE_EEP1_SPDIF]);
  1386. snd_iprintf(buffer, " GPIO mask : 0x%x\n", ice->eeprom.gpiomask);
  1387. snd_iprintf(buffer, " GPIO state : 0x%x\n", ice->eeprom.gpiostate);
  1388. snd_iprintf(buffer, " GPIO direction : 0x%x\n", ice->eeprom.gpiodir);
  1389. snd_iprintf(buffer, " AC'97 main : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_MAIN_LO));
  1390. snd_iprintf(buffer, " AC'97 pcm : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_PCM_LO));
  1391. snd_iprintf(buffer, " AC'97 record : 0x%x\n", eeprom_double(ice, ICE_EEP1_AC97_REC_LO));
  1392. snd_iprintf(buffer, " AC'97 record src : 0x%x\n", ice->eeprom.data[ICE_EEP1_AC97_RECSRC]);
  1393. for (idx = 0; idx < 4; idx++)
  1394. snd_iprintf(buffer, " DAC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_DAC_ID + idx]);
  1395. for (idx = 0; idx < 4; idx++)
  1396. snd_iprintf(buffer, " ADC ID #%i : 0x%x\n", idx, ice->eeprom.data[ICE_EEP1_ADC_ID + idx]);
  1397. for (idx = 0x1c; idx < ice->eeprom.size; idx++)
  1398. snd_iprintf(buffer, " Extra #%02i : 0x%x\n", idx, ice->eeprom.data[idx]);
  1399. snd_iprintf(buffer, "\nRegisters:\n");
  1400. snd_iprintf(buffer, " PSDOUT03 : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_PSDOUT03)));
  1401. snd_iprintf(buffer, " CAPTURE : 0x%08x\n", inl(ICEMT(ice, ROUTE_CAPTURE)));
  1402. snd_iprintf(buffer, " SPDOUT : 0x%04x\n", (unsigned)inw(ICEMT(ice, ROUTE_SPDOUT)));
  1403. snd_iprintf(buffer, " RATE : 0x%02x\n", (unsigned)inb(ICEMT(ice, RATE)));
  1404. snd_iprintf(buffer, " GPIO_DATA : 0x%02x\n", (unsigned)snd_ice1712_get_gpio_data(ice));
  1405. snd_iprintf(buffer, " GPIO_WRITE_MASK : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_WRITE_MASK));
  1406. snd_iprintf(buffer, " GPIO_DIRECTION : 0x%02x\n", (unsigned)snd_ice1712_read(ice, ICE1712_IREG_GPIO_DIRECTION));
  1407. }
  1408. static void __devinit snd_ice1712_proc_init(struct snd_ice1712 * ice)
  1409. {
  1410. struct snd_info_entry *entry;
  1411. if (! snd_card_proc_new(ice->card, "ice1712", &entry))
  1412. snd_info_set_text_ops(entry, ice, snd_ice1712_proc_read);
  1413. }
  1414. /*
  1415. *
  1416. */
  1417. static int snd_ice1712_eeprom_info(struct snd_kcontrol *kcontrol,
  1418. struct snd_ctl_elem_info *uinfo)
  1419. {
  1420. uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
  1421. uinfo->count = sizeof(struct snd_ice1712_eeprom);
  1422. return 0;
  1423. }
  1424. static int snd_ice1712_eeprom_get(struct snd_kcontrol *kcontrol,
  1425. struct snd_ctl_elem_value *ucontrol)
  1426. {
  1427. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1428. memcpy(ucontrol->value.bytes.data, &ice->eeprom, sizeof(ice->eeprom));
  1429. return 0;
  1430. }
  1431. static const struct snd_kcontrol_new snd_ice1712_eeprom __devinitdata = {
  1432. .iface = SNDRV_CTL_ELEM_IFACE_CARD,
  1433. .name = "ICE1712 EEPROM",
  1434. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1435. .info = snd_ice1712_eeprom_info,
  1436. .get = snd_ice1712_eeprom_get
  1437. };
  1438. /*
  1439. */
  1440. static int snd_ice1712_spdif_info(struct snd_kcontrol *kcontrol,
  1441. struct snd_ctl_elem_info *uinfo)
  1442. {
  1443. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1444. uinfo->count = 1;
  1445. return 0;
  1446. }
  1447. static int snd_ice1712_spdif_default_get(struct snd_kcontrol *kcontrol,
  1448. struct snd_ctl_elem_value *ucontrol)
  1449. {
  1450. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1451. if (ice->spdif.ops.default_get)
  1452. ice->spdif.ops.default_get(ice, ucontrol);
  1453. return 0;
  1454. }
  1455. static int snd_ice1712_spdif_default_put(struct snd_kcontrol *kcontrol,
  1456. struct snd_ctl_elem_value *ucontrol)
  1457. {
  1458. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1459. if (ice->spdif.ops.default_put)
  1460. return ice->spdif.ops.default_put(ice, ucontrol);
  1461. return 0;
  1462. }
  1463. static const struct snd_kcontrol_new snd_ice1712_spdif_default __devinitdata =
  1464. {
  1465. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1466. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1467. .info = snd_ice1712_spdif_info,
  1468. .get = snd_ice1712_spdif_default_get,
  1469. .put = snd_ice1712_spdif_default_put
  1470. };
  1471. static int snd_ice1712_spdif_maskc_get(struct snd_kcontrol *kcontrol,
  1472. struct snd_ctl_elem_value *ucontrol)
  1473. {
  1474. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1475. if (ice->spdif.ops.default_get) {
  1476. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1477. IEC958_AES0_PROFESSIONAL |
  1478. IEC958_AES0_CON_NOT_COPYRIGHT |
  1479. IEC958_AES0_CON_EMPHASIS;
  1480. ucontrol->value.iec958.status[1] = IEC958_AES1_CON_ORIGINAL |
  1481. IEC958_AES1_CON_CATEGORY;
  1482. ucontrol->value.iec958.status[3] = IEC958_AES3_CON_FS;
  1483. } else {
  1484. ucontrol->value.iec958.status[0] = 0xff;
  1485. ucontrol->value.iec958.status[1] = 0xff;
  1486. ucontrol->value.iec958.status[2] = 0xff;
  1487. ucontrol->value.iec958.status[3] = 0xff;
  1488. ucontrol->value.iec958.status[4] = 0xff;
  1489. }
  1490. return 0;
  1491. }
  1492. static int snd_ice1712_spdif_maskp_get(struct snd_kcontrol *kcontrol,
  1493. struct snd_ctl_elem_value *ucontrol)
  1494. {
  1495. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1496. if (ice->spdif.ops.default_get) {
  1497. ucontrol->value.iec958.status[0] = IEC958_AES0_NONAUDIO |
  1498. IEC958_AES0_PROFESSIONAL |
  1499. IEC958_AES0_PRO_FS |
  1500. IEC958_AES0_PRO_EMPHASIS;
  1501. ucontrol->value.iec958.status[1] = IEC958_AES1_PRO_MODE;
  1502. } else {
  1503. ucontrol->value.iec958.status[0] = 0xff;
  1504. ucontrol->value.iec958.status[1] = 0xff;
  1505. ucontrol->value.iec958.status[2] = 0xff;
  1506. ucontrol->value.iec958.status[3] = 0xff;
  1507. ucontrol->value.iec958.status[4] = 0xff;
  1508. }
  1509. return 0;
  1510. }
  1511. static const struct snd_kcontrol_new snd_ice1712_spdif_maskc __devinitdata =
  1512. {
  1513. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1514. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1515. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
  1516. .info = snd_ice1712_spdif_info,
  1517. .get = snd_ice1712_spdif_maskc_get,
  1518. };
  1519. static const struct snd_kcontrol_new snd_ice1712_spdif_maskp __devinitdata =
  1520. {
  1521. .access = SNDRV_CTL_ELEM_ACCESS_READ,
  1522. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1523. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
  1524. .info = snd_ice1712_spdif_info,
  1525. .get = snd_ice1712_spdif_maskp_get,
  1526. };
  1527. static int snd_ice1712_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1528. struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1531. if (ice->spdif.ops.stream_get)
  1532. ice->spdif.ops.stream_get(ice, ucontrol);
  1533. return 0;
  1534. }
  1535. static int snd_ice1712_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1536. struct snd_ctl_elem_value *ucontrol)
  1537. {
  1538. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1539. if (ice->spdif.ops.stream_put)
  1540. return ice->spdif.ops.stream_put(ice, ucontrol);
  1541. return 0;
  1542. }
  1543. static const struct snd_kcontrol_new snd_ice1712_spdif_stream __devinitdata =
  1544. {
  1545. .access = (SNDRV_CTL_ELEM_ACCESS_READWRITE |
  1546. SNDRV_CTL_ELEM_ACCESS_INACTIVE),
  1547. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1548. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1549. .info = snd_ice1712_spdif_info,
  1550. .get = snd_ice1712_spdif_stream_get,
  1551. .put = snd_ice1712_spdif_stream_put
  1552. };
  1553. int snd_ice1712_gpio_info(struct snd_kcontrol *kcontrol,
  1554. struct snd_ctl_elem_info *uinfo)
  1555. {
  1556. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1557. uinfo->count = 1;
  1558. uinfo->value.integer.min = 0;
  1559. uinfo->value.integer.max = 1;
  1560. return 0;
  1561. }
  1562. int snd_ice1712_gpio_get(struct snd_kcontrol *kcontrol,
  1563. struct snd_ctl_elem_value *ucontrol)
  1564. {
  1565. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1566. unsigned char mask = kcontrol->private_value & 0xff;
  1567. int invert = (kcontrol->private_value & (1<<24)) ? 1 : 0;
  1568. snd_ice1712_save_gpio_status(ice);
  1569. ucontrol->value.integer.value[0] =
  1570. (snd_ice1712_gpio_read(ice) & mask ? 1 : 0) ^ invert;
  1571. snd_ice1712_restore_gpio_status(ice);
  1572. return 0;
  1573. }
  1574. int snd_ice1712_gpio_put(struct snd_kcontrol *kcontrol,
  1575. struct snd_ctl_elem_value *ucontrol)
  1576. {
  1577. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1578. unsigned char mask = kcontrol->private_value & 0xff;
  1579. int invert = (kcontrol->private_value & (1<<24)) ? mask : 0;
  1580. unsigned int val, nval;
  1581. if (kcontrol->private_value & (1 << 31))
  1582. return -EPERM;
  1583. nval = (ucontrol->value.integer.value[0] ? mask : 0) ^ invert;
  1584. snd_ice1712_save_gpio_status(ice);
  1585. val = snd_ice1712_gpio_read(ice);
  1586. nval |= val & ~mask;
  1587. if (val != nval)
  1588. snd_ice1712_gpio_write(ice, nval);
  1589. snd_ice1712_restore_gpio_status(ice);
  1590. return val != nval;
  1591. }
  1592. /*
  1593. * rate
  1594. */
  1595. static int snd_ice1712_pro_internal_clock_info(struct snd_kcontrol *kcontrol,
  1596. struct snd_ctl_elem_info *uinfo)
  1597. {
  1598. static const char * const texts[] = {
  1599. "8000", /* 0: 6 */
  1600. "9600", /* 1: 3 */
  1601. "11025", /* 2: 10 */
  1602. "12000", /* 3: 2 */
  1603. "16000", /* 4: 5 */
  1604. "22050", /* 5: 9 */
  1605. "24000", /* 6: 1 */
  1606. "32000", /* 7: 4 */
  1607. "44100", /* 8: 8 */
  1608. "48000", /* 9: 0 */
  1609. "64000", /* 10: 15 */
  1610. "88200", /* 11: 11 */
  1611. "96000", /* 12: 7 */
  1612. "IEC958 Input", /* 13: -- */
  1613. };
  1614. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1615. uinfo->count = 1;
  1616. uinfo->value.enumerated.items = 14;
  1617. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1618. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1619. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1620. return 0;
  1621. }
  1622. static int snd_ice1712_pro_internal_clock_get(struct snd_kcontrol *kcontrol,
  1623. struct snd_ctl_elem_value *ucontrol)
  1624. {
  1625. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1626. static const unsigned char xlate[16] = {
  1627. 9, 6, 3, 1, 7, 4, 0, 12, 8, 5, 2, 11, 255, 255, 255, 10
  1628. };
  1629. unsigned char val;
  1630. spin_lock_irq(&ice->reg_lock);
  1631. if (is_spdif_master(ice)) {
  1632. ucontrol->value.enumerated.item[0] = 13;
  1633. } else {
  1634. val = xlate[inb(ICEMT(ice, RATE)) & 15];
  1635. if (val == 255) {
  1636. snd_BUG();
  1637. val = 0;
  1638. }
  1639. ucontrol->value.enumerated.item[0] = val;
  1640. }
  1641. spin_unlock_irq(&ice->reg_lock);
  1642. return 0;
  1643. }
  1644. static int snd_ice1712_pro_internal_clock_put(struct snd_kcontrol *kcontrol,
  1645. struct snd_ctl_elem_value *ucontrol)
  1646. {
  1647. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1648. static const unsigned int xrate[13] = {
  1649. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1650. 32000, 44100, 48000, 64000, 88200, 96000
  1651. };
  1652. unsigned char oval;
  1653. int change = 0;
  1654. spin_lock_irq(&ice->reg_lock);
  1655. oval = inb(ICEMT(ice, RATE));
  1656. if (ucontrol->value.enumerated.item[0] == 13) {
  1657. outb(oval | ICE1712_SPDIF_MASTER, ICEMT(ice, RATE));
  1658. } else {
  1659. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1660. spin_unlock_irq(&ice->reg_lock);
  1661. snd_ice1712_set_pro_rate(ice, PRO_RATE_DEFAULT, 1);
  1662. spin_lock_irq(&ice->reg_lock);
  1663. }
  1664. change = inb(ICEMT(ice, RATE)) != oval;
  1665. spin_unlock_irq(&ice->reg_lock);
  1666. if ((oval & ICE1712_SPDIF_MASTER) !=
  1667. (inb(ICEMT(ice, RATE)) & ICE1712_SPDIF_MASTER))
  1668. snd_ice1712_set_input_clock_source(ice, is_spdif_master(ice));
  1669. return change;
  1670. }
  1671. static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock __devinitdata = {
  1672. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1673. .name = "Multi Track Internal Clock",
  1674. .info = snd_ice1712_pro_internal_clock_info,
  1675. .get = snd_ice1712_pro_internal_clock_get,
  1676. .put = snd_ice1712_pro_internal_clock_put
  1677. };
  1678. static int snd_ice1712_pro_internal_clock_default_info(struct snd_kcontrol *kcontrol,
  1679. struct snd_ctl_elem_info *uinfo)
  1680. {
  1681. static const char * const texts[] = {
  1682. "8000", /* 0: 6 */
  1683. "9600", /* 1: 3 */
  1684. "11025", /* 2: 10 */
  1685. "12000", /* 3: 2 */
  1686. "16000", /* 4: 5 */
  1687. "22050", /* 5: 9 */
  1688. "24000", /* 6: 1 */
  1689. "32000", /* 7: 4 */
  1690. "44100", /* 8: 8 */
  1691. "48000", /* 9: 0 */
  1692. "64000", /* 10: 15 */
  1693. "88200", /* 11: 11 */
  1694. "96000", /* 12: 7 */
  1695. // "IEC958 Input", /* 13: -- */
  1696. };
  1697. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1698. uinfo->count = 1;
  1699. uinfo->value.enumerated.items = 13;
  1700. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1701. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1702. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1703. return 0;
  1704. }
  1705. static int snd_ice1712_pro_internal_clock_default_get(struct snd_kcontrol *kcontrol,
  1706. struct snd_ctl_elem_value *ucontrol)
  1707. {
  1708. int val;
  1709. static const unsigned int xrate[13] = {
  1710. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1711. 32000, 44100, 48000, 64000, 88200, 96000
  1712. };
  1713. for (val = 0; val < 13; val++) {
  1714. if (xrate[val] == PRO_RATE_DEFAULT)
  1715. break;
  1716. }
  1717. ucontrol->value.enumerated.item[0] = val;
  1718. return 0;
  1719. }
  1720. static int snd_ice1712_pro_internal_clock_default_put(struct snd_kcontrol *kcontrol,
  1721. struct snd_ctl_elem_value *ucontrol)
  1722. {
  1723. static const unsigned int xrate[13] = {
  1724. 8000, 9600, 11025, 12000, 16000, 22050, 24000,
  1725. 32000, 44100, 48000, 64000, 88200, 96000
  1726. };
  1727. unsigned char oval;
  1728. int change = 0;
  1729. oval = PRO_RATE_DEFAULT;
  1730. PRO_RATE_DEFAULT = xrate[ucontrol->value.integer.value[0] % 13];
  1731. change = PRO_RATE_DEFAULT != oval;
  1732. return change;
  1733. }
  1734. static const struct snd_kcontrol_new snd_ice1712_pro_internal_clock_default __devinitdata = {
  1735. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1736. .name = "Multi Track Internal Clock Default",
  1737. .info = snd_ice1712_pro_internal_clock_default_info,
  1738. .get = snd_ice1712_pro_internal_clock_default_get,
  1739. .put = snd_ice1712_pro_internal_clock_default_put
  1740. };
  1741. static int snd_ice1712_pro_rate_locking_info(struct snd_kcontrol *kcontrol,
  1742. struct snd_ctl_elem_info *uinfo)
  1743. {
  1744. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1745. uinfo->count = 1;
  1746. uinfo->value.integer.min = 0;
  1747. uinfo->value.integer.max = 1;
  1748. return 0;
  1749. }
  1750. static int snd_ice1712_pro_rate_locking_get(struct snd_kcontrol *kcontrol,
  1751. struct snd_ctl_elem_value *ucontrol)
  1752. {
  1753. ucontrol->value.integer.value[0] = PRO_RATE_LOCKED;
  1754. return 0;
  1755. }
  1756. static int snd_ice1712_pro_rate_locking_put(struct snd_kcontrol *kcontrol,
  1757. struct snd_ctl_elem_value *ucontrol)
  1758. {
  1759. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1760. int change = 0, nval;
  1761. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1762. spin_lock_irq(&ice->reg_lock);
  1763. change = PRO_RATE_LOCKED != nval;
  1764. PRO_RATE_LOCKED = nval;
  1765. spin_unlock_irq(&ice->reg_lock);
  1766. return change;
  1767. }
  1768. static const struct snd_kcontrol_new snd_ice1712_pro_rate_locking __devinitdata = {
  1769. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1770. .name = "Multi Track Rate Locking",
  1771. .info = snd_ice1712_pro_rate_locking_info,
  1772. .get = snd_ice1712_pro_rate_locking_get,
  1773. .put = snd_ice1712_pro_rate_locking_put
  1774. };
  1775. static int snd_ice1712_pro_rate_reset_info(struct snd_kcontrol *kcontrol,
  1776. struct snd_ctl_elem_info *uinfo)
  1777. {
  1778. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1779. uinfo->count = 1;
  1780. uinfo->value.integer.min = 0;
  1781. uinfo->value.integer.max = 1;
  1782. return 0;
  1783. }
  1784. static int snd_ice1712_pro_rate_reset_get(struct snd_kcontrol *kcontrol,
  1785. struct snd_ctl_elem_value *ucontrol)
  1786. {
  1787. ucontrol->value.integer.value[0] = PRO_RATE_RESET;
  1788. return 0;
  1789. }
  1790. static int snd_ice1712_pro_rate_reset_put(struct snd_kcontrol *kcontrol,
  1791. struct snd_ctl_elem_value *ucontrol)
  1792. {
  1793. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1794. int change = 0, nval;
  1795. nval = ucontrol->value.integer.value[0] ? 1 : 0;
  1796. spin_lock_irq(&ice->reg_lock);
  1797. change = PRO_RATE_RESET != nval;
  1798. PRO_RATE_RESET = nval;
  1799. spin_unlock_irq(&ice->reg_lock);
  1800. return change;
  1801. }
  1802. static const struct snd_kcontrol_new snd_ice1712_pro_rate_reset __devinitdata = {
  1803. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1804. .name = "Multi Track Rate Reset",
  1805. .info = snd_ice1712_pro_rate_reset_info,
  1806. .get = snd_ice1712_pro_rate_reset_get,
  1807. .put = snd_ice1712_pro_rate_reset_put
  1808. };
  1809. /*
  1810. * routing
  1811. */
  1812. static int snd_ice1712_pro_route_info(struct snd_kcontrol *kcontrol,
  1813. struct snd_ctl_elem_info *uinfo)
  1814. {
  1815. static const char * const texts[] = {
  1816. "PCM Out", /* 0 */
  1817. "H/W In 0", "H/W In 1", "H/W In 2", "H/W In 3", /* 1-4 */
  1818. "H/W In 4", "H/W In 5", "H/W In 6", "H/W In 7", /* 5-8 */
  1819. "IEC958 In L", "IEC958 In R", /* 9-10 */
  1820. "Digital Mixer", /* 11 - optional */
  1821. };
  1822. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  1823. uinfo->count = 1;
  1824. uinfo->value.enumerated.items =
  1825. snd_ctl_get_ioffidx(kcontrol, &uinfo->id) < 2 ? 12 : 11;
  1826. if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
  1827. uinfo->value.enumerated.item = uinfo->value.enumerated.items - 1;
  1828. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1829. return 0;
  1830. }
  1831. static int snd_ice1712_pro_route_analog_get(struct snd_kcontrol *kcontrol,
  1832. struct snd_ctl_elem_value *ucontrol)
  1833. {
  1834. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1835. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1836. unsigned int val, cval;
  1837. spin_lock_irq(&ice->reg_lock);
  1838. val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1839. cval = inl(ICEMT(ice, ROUTE_CAPTURE));
  1840. spin_unlock_irq(&ice->reg_lock);
  1841. val >>= ((idx % 2) * 8) + ((idx / 2) * 2);
  1842. val &= 3;
  1843. cval >>= ((idx / 2) * 8) + ((idx % 2) * 4);
  1844. if (val == 1 && idx < 2)
  1845. ucontrol->value.enumerated.item[0] = 11;
  1846. else if (val == 2)
  1847. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1848. else if (val == 3)
  1849. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1850. else
  1851. ucontrol->value.enumerated.item[0] = 0;
  1852. return 0;
  1853. }
  1854. static int snd_ice1712_pro_route_analog_put(struct snd_kcontrol *kcontrol,
  1855. struct snd_ctl_elem_value *ucontrol)
  1856. {
  1857. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1858. int change, shift;
  1859. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1860. unsigned int val, old_val, nval;
  1861. /* update PSDOUT */
  1862. if (ucontrol->value.enumerated.item[0] >= 11)
  1863. nval = idx < 2 ? 1 : 0; /* dig mixer (or pcm) */
  1864. else if (ucontrol->value.enumerated.item[0] >= 9)
  1865. nval = 3; /* spdif in */
  1866. else if (ucontrol->value.enumerated.item[0] >= 1)
  1867. nval = 2; /* analog in */
  1868. else
  1869. nval = 0; /* pcm */
  1870. shift = ((idx % 2) * 8) + ((idx / 2) * 2);
  1871. spin_lock_irq(&ice->reg_lock);
  1872. val = old_val = inw(ICEMT(ice, ROUTE_PSDOUT03));
  1873. val &= ~(0x03 << shift);
  1874. val |= nval << shift;
  1875. change = val != old_val;
  1876. if (change)
  1877. outw(val, ICEMT(ice, ROUTE_PSDOUT03));
  1878. spin_unlock_irq(&ice->reg_lock);
  1879. if (nval < 2) /* dig mixer of pcm */
  1880. return change;
  1881. /* update CAPTURE */
  1882. spin_lock_irq(&ice->reg_lock);
  1883. val = old_val = inl(ICEMT(ice, ROUTE_CAPTURE));
  1884. shift = ((idx / 2) * 8) + ((idx % 2) * 4);
  1885. if (nval == 2) { /* analog in */
  1886. nval = ucontrol->value.enumerated.item[0] - 1;
  1887. val &= ~(0x07 << shift);
  1888. val |= nval << shift;
  1889. } else { /* spdif in */
  1890. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1891. val &= ~(0x08 << shift);
  1892. val |= nval << shift;
  1893. }
  1894. if (val != old_val) {
  1895. change = 1;
  1896. outl(val, ICEMT(ice, ROUTE_CAPTURE));
  1897. }
  1898. spin_unlock_irq(&ice->reg_lock);
  1899. return change;
  1900. }
  1901. static int snd_ice1712_pro_route_spdif_get(struct snd_kcontrol *kcontrol,
  1902. struct snd_ctl_elem_value *ucontrol)
  1903. {
  1904. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1905. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1906. unsigned int val, cval;
  1907. val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1908. cval = (val >> (idx * 4 + 8)) & 0x0f;
  1909. val = (val >> (idx * 2)) & 0x03;
  1910. if (val == 1)
  1911. ucontrol->value.enumerated.item[0] = 11;
  1912. else if (val == 2)
  1913. ucontrol->value.enumerated.item[0] = (cval & 7) + 1;
  1914. else if (val == 3)
  1915. ucontrol->value.enumerated.item[0] = ((cval >> 3) & 1) + 9;
  1916. else
  1917. ucontrol->value.enumerated.item[0] = 0;
  1918. return 0;
  1919. }
  1920. static int snd_ice1712_pro_route_spdif_put(struct snd_kcontrol *kcontrol,
  1921. struct snd_ctl_elem_value *ucontrol)
  1922. {
  1923. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1924. int change, shift;
  1925. int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
  1926. unsigned int val, old_val, nval;
  1927. /* update SPDOUT */
  1928. spin_lock_irq(&ice->reg_lock);
  1929. val = old_val = inw(ICEMT(ice, ROUTE_SPDOUT));
  1930. if (ucontrol->value.enumerated.item[0] >= 11)
  1931. nval = 1;
  1932. else if (ucontrol->value.enumerated.item[0] >= 9)
  1933. nval = 3;
  1934. else if (ucontrol->value.enumerated.item[0] >= 1)
  1935. nval = 2;
  1936. else
  1937. nval = 0;
  1938. shift = idx * 2;
  1939. val &= ~(0x03 << shift);
  1940. val |= nval << shift;
  1941. shift = idx * 4 + 8;
  1942. if (nval == 2) {
  1943. nval = ucontrol->value.enumerated.item[0] - 1;
  1944. val &= ~(0x07 << shift);
  1945. val |= nval << shift;
  1946. } else if (nval == 3) {
  1947. nval = (ucontrol->value.enumerated.item[0] - 9) << 3;
  1948. val &= ~(0x08 << shift);
  1949. val |= nval << shift;
  1950. }
  1951. change = val != old_val;
  1952. if (change)
  1953. outw(val, ICEMT(ice, ROUTE_SPDOUT));
  1954. spin_unlock_irq(&ice->reg_lock);
  1955. return change;
  1956. }
  1957. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_analog_route __devinitdata = {
  1958. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1959. .name = "H/W Playback Route",
  1960. .info = snd_ice1712_pro_route_info,
  1961. .get = snd_ice1712_pro_route_analog_get,
  1962. .put = snd_ice1712_pro_route_analog_put,
  1963. };
  1964. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_spdif_route __devinitdata = {
  1965. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1966. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,NONE) "Route",
  1967. .info = snd_ice1712_pro_route_info,
  1968. .get = snd_ice1712_pro_route_spdif_get,
  1969. .put = snd_ice1712_pro_route_spdif_put,
  1970. .count = 2,
  1971. };
  1972. static int snd_ice1712_pro_volume_rate_info(struct snd_kcontrol *kcontrol,
  1973. struct snd_ctl_elem_info *uinfo)
  1974. {
  1975. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1976. uinfo->count = 1;
  1977. uinfo->value.integer.min = 0;
  1978. uinfo->value.integer.max = 255;
  1979. return 0;
  1980. }
  1981. static int snd_ice1712_pro_volume_rate_get(struct snd_kcontrol *kcontrol,
  1982. struct snd_ctl_elem_value *ucontrol)
  1983. {
  1984. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1985. ucontrol->value.integer.value[0] = inb(ICEMT(ice, MONITOR_RATE));
  1986. return 0;
  1987. }
  1988. static int snd_ice1712_pro_volume_rate_put(struct snd_kcontrol *kcontrol,
  1989. struct snd_ctl_elem_value *ucontrol)
  1990. {
  1991. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  1992. int change;
  1993. spin_lock_irq(&ice->reg_lock);
  1994. change = inb(ICEMT(ice, MONITOR_RATE)) != ucontrol->value.integer.value[0];
  1995. outb(ucontrol->value.integer.value[0], ICEMT(ice, MONITOR_RATE));
  1996. spin_unlock_irq(&ice->reg_lock);
  1997. return change;
  1998. }
  1999. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_volume_rate __devinitdata = {
  2000. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2001. .name = "Multi Track Volume Rate",
  2002. .info = snd_ice1712_pro_volume_rate_info,
  2003. .get = snd_ice1712_pro_volume_rate_get,
  2004. .put = snd_ice1712_pro_volume_rate_put
  2005. };
  2006. static int snd_ice1712_pro_peak_info(struct snd_kcontrol *kcontrol,
  2007. struct snd_ctl_elem_info *uinfo)
  2008. {
  2009. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  2010. uinfo->count = 22;
  2011. uinfo->value.integer.min = 0;
  2012. uinfo->value.integer.max = 255;
  2013. return 0;
  2014. }
  2015. static int snd_ice1712_pro_peak_get(struct snd_kcontrol *kcontrol,
  2016. struct snd_ctl_elem_value *ucontrol)
  2017. {
  2018. struct snd_ice1712 *ice = snd_kcontrol_chip(kcontrol);
  2019. int idx;
  2020. spin_lock_irq(&ice->reg_lock);
  2021. for (idx = 0; idx < 22; idx++) {
  2022. outb(idx, ICEMT(ice, MONITOR_PEAKINDEX));
  2023. ucontrol->value.integer.value[idx] = inb(ICEMT(ice, MONITOR_PEAKDATA));
  2024. }
  2025. spin_unlock_irq(&ice->reg_lock);
  2026. return 0;
  2027. }
  2028. static const struct snd_kcontrol_new snd_ice1712_mixer_pro_peak __devinitdata = {
  2029. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  2030. .name = "Multi Track Peak",
  2031. .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE,
  2032. .info = snd_ice1712_pro_peak_info,
  2033. .get = snd_ice1712_pro_peak_get
  2034. };
  2035. /*
  2036. *
  2037. */
  2038. /*
  2039. * list of available boards
  2040. */
  2041. static const struct snd_ice1712_card_info *card_tables[] __devinitdata = {
  2042. snd_ice1712_hoontech_cards,
  2043. snd_ice1712_delta_cards,
  2044. snd_ice1712_ews_cards,
  2045. NULL,
  2046. };
  2047. static unsigned char __devinit snd_ice1712_read_i2c(struct snd_ice1712 *ice,
  2048. unsigned char dev,
  2049. unsigned char addr)
  2050. {
  2051. long t = 0x10000;
  2052. outb(addr, ICEREG(ice, I2C_BYTE_ADDR));
  2053. outb(dev & ~ICE1712_I2C_WRITE, ICEREG(ice, I2C_DEV_ADDR));
  2054. while (t-- > 0 && (inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_BUSY)) ;
  2055. return inb(ICEREG(ice, I2C_DATA));
  2056. }
  2057. static int __devinit snd_ice1712_read_eeprom(struct snd_ice1712 *ice,
  2058. const char *modelname)
  2059. {
  2060. int dev = 0xa0; /* EEPROM device address */
  2061. unsigned int i, size;
  2062. const struct snd_ice1712_card_info **tbl, *c;
  2063. if (! modelname || ! *modelname) {
  2064. ice->eeprom.subvendor = 0;
  2065. if ((inb(ICEREG(ice, I2C_CTRL)) & ICE1712_I2C_EEPROM) != 0)
  2066. ice->eeprom.subvendor = (snd_ice1712_read_i2c(ice, dev, 0x00) << 0) |
  2067. (snd_ice1712_read_i2c(ice, dev, 0x01) << 8) |
  2068. (snd_ice1712_read_i2c(ice, dev, 0x02) << 16) |
  2069. (snd_ice1712_read_i2c(ice, dev, 0x03) << 24);
  2070. if (ice->eeprom.subvendor == 0 ||
  2071. ice->eeprom.subvendor == (unsigned int)-1) {
  2072. /* invalid subvendor from EEPROM, try the PCI subststem ID instead */
  2073. u16 vendor, device;
  2074. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_VENDOR_ID, &vendor);
  2075. pci_read_config_word(ice->pci, PCI_SUBSYSTEM_ID, &device);
  2076. ice->eeprom.subvendor = ((unsigned int)swab16(vendor) << 16) | swab16(device);
  2077. if (ice->eeprom.subvendor == 0 || ice->eeprom.subvendor == (unsigned int)-1) {
  2078. printk(KERN_ERR "ice1712: No valid ID is found\n");
  2079. return -ENXIO;
  2080. }
  2081. }
  2082. }
  2083. for (tbl = card_tables; *tbl; tbl++) {
  2084. for (c = *tbl; c->subvendor; c++) {
  2085. if (modelname && c->model && ! strcmp(modelname, c->model)) {
  2086. printk(KERN_INFO "ice1712: Using board model %s\n", c->name);
  2087. ice->eeprom.subvendor = c->subvendor;
  2088. } else if (c->subvendor != ice->eeprom.subvendor)
  2089. continue;
  2090. if (! c->eeprom_size || ! c->eeprom_data)
  2091. goto found;
  2092. /* if the EEPROM is given by the driver, use it */
  2093. snd_printdd("using the defined eeprom..\n");
  2094. ice->eeprom.version = 1;
  2095. ice->eeprom.size = c->eeprom_size + 6;
  2096. memcpy(ice->eeprom.data, c->eeprom_data, c->eeprom_size);
  2097. goto read_skipped;
  2098. }
  2099. }
  2100. printk(KERN_WARNING "ice1712: No matching model found for ID 0x%x\n",
  2101. ice->eeprom.subvendor);
  2102. found:
  2103. ice->eeprom.size = snd_ice1712_read_i2c(ice, dev, 0x04);
  2104. if (ice->eeprom.size < 6)
  2105. ice->eeprom.size = 32; /* FIXME: any cards without the correct size? */
  2106. else if (ice->eeprom.size > 32) {
  2107. snd_printk(KERN_ERR "invalid EEPROM (size = %i)\n", ice->eeprom.size);
  2108. return -EIO;
  2109. }
  2110. ice->eeprom.version = snd_ice1712_read_i2c(ice, dev, 0x05);
  2111. if (ice->eeprom.version != 1) {
  2112. snd_printk(KERN_ERR "invalid EEPROM version %i\n",
  2113. ice->eeprom.version);
  2114. /* return -EIO; */
  2115. }
  2116. size = ice->eeprom.size - 6;
  2117. for (i = 0; i < size; i++)
  2118. ice->eeprom.data[i] = snd_ice1712_read_i2c(ice, dev, i + 6);
  2119. read_skipped:
  2120. ice->eeprom.gpiomask = ice->eeprom.data[ICE_EEP1_GPIO_MASK];
  2121. ice->eeprom.gpiostate = ice->eeprom.data[ICE_EEP1_GPIO_STATE];
  2122. ice->eeprom.gpiodir = ice->eeprom.data[ICE_EEP1_GPIO_DIR];
  2123. return 0;
  2124. }
  2125. static int __devinit snd_ice1712_chip_init(struct snd_ice1712 *ice)
  2126. {
  2127. outb(ICE1712_RESET | ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2128. udelay(200);
  2129. outb(ICE1712_NATIVE, ICEREG(ice, CONTROL));
  2130. udelay(200);
  2131. if (ice->eeprom.subvendor == ICE1712_SUBDEVICE_DMX6FIRE &&
  2132. !ice->dxr_enable)
  2133. /* Set eeprom value to limit active ADCs and DACs to 6;
  2134. * Also disable AC97 as no hardware in standard 6fire card/box
  2135. * Note: DXR extensions are not currently supported
  2136. */
  2137. ice->eeprom.data[ICE_EEP1_CODEC] = 0x3a;
  2138. pci_write_config_byte(ice->pci, 0x60, ice->eeprom.data[ICE_EEP1_CODEC]);
  2139. pci_write_config_byte(ice->pci, 0x61, ice->eeprom.data[ICE_EEP1_ACLINK]);
  2140. pci_write_config_byte(ice->pci, 0x62, ice->eeprom.data[ICE_EEP1_I2SID]);
  2141. pci_write_config_byte(ice->pci, 0x63, ice->eeprom.data[ICE_EEP1_SPDIF]);
  2142. if (ice->eeprom.subvendor != ICE1712_SUBDEVICE_STDSP24) {
  2143. ice->gpio.write_mask = ice->eeprom.gpiomask;
  2144. ice->gpio.direction = ice->eeprom.gpiodir;
  2145. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK,
  2146. ice->eeprom.gpiomask);
  2147. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION,
  2148. ice->eeprom.gpiodir);
  2149. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2150. ice->eeprom.gpiostate);
  2151. } else {
  2152. ice->gpio.write_mask = 0xc0;
  2153. ice->gpio.direction = 0xff;
  2154. snd_ice1712_write(ice, ICE1712_IREG_GPIO_WRITE_MASK, 0xc0);
  2155. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DIRECTION, 0xff);
  2156. snd_ice1712_write(ice, ICE1712_IREG_GPIO_DATA,
  2157. ICE1712_STDSP24_CLOCK_BIT);
  2158. }
  2159. snd_ice1712_write(ice, ICE1712_IREG_PRO_POWERDOWN, 0);
  2160. if (!(ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97)) {
  2161. outb(ICE1712_AC97_WARM, ICEREG(ice, AC97_CMD));
  2162. udelay(100);
  2163. outb(0, ICEREG(ice, AC97_CMD));
  2164. udelay(200);
  2165. snd_ice1712_write(ice, ICE1712_IREG_CONSUMER_POWERDOWN, 0);
  2166. }
  2167. snd_ice1712_set_pro_rate(ice, 48000, 1);
  2168. return 0;
  2169. }
  2170. int __devinit snd_ice1712_spdif_build_controls(struct snd_ice1712 *ice)
  2171. {
  2172. int err;
  2173. struct snd_kcontrol *kctl;
  2174. snd_assert(ice->pcm_pro != NULL, return -EIO);
  2175. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_default, ice));
  2176. if (err < 0)
  2177. return err;
  2178. kctl->id.device = ice->pcm_pro->device;
  2179. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskc, ice));
  2180. if (err < 0)
  2181. return err;
  2182. kctl->id.device = ice->pcm_pro->device;
  2183. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_maskp, ice));
  2184. if (err < 0)
  2185. return err;
  2186. kctl->id.device = ice->pcm_pro->device;
  2187. err = snd_ctl_add(ice->card, kctl = snd_ctl_new1(&snd_ice1712_spdif_stream, ice));
  2188. if (err < 0)
  2189. return err;
  2190. kctl->id.device = ice->pcm_pro->device;
  2191. ice->spdif.stream_ctl = kctl;
  2192. return 0;
  2193. }
  2194. static int __devinit snd_ice1712_build_controls(struct snd_ice1712 *ice)
  2195. {
  2196. int err;
  2197. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_eeprom, ice));
  2198. if (err < 0)
  2199. return err;
  2200. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock, ice));
  2201. if (err < 0)
  2202. return err;
  2203. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_internal_clock_default, ice));
  2204. if (err < 0)
  2205. return err;
  2206. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_locking, ice));
  2207. if (err < 0)
  2208. return err;
  2209. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_pro_rate_reset, ice));
  2210. if (err < 0)
  2211. return err;
  2212. if (ice->num_total_dacs > 0) {
  2213. struct snd_kcontrol_new tmp = snd_ice1712_mixer_pro_analog_route;
  2214. tmp.count = ice->num_total_dacs;
  2215. err = snd_ctl_add(ice->card, snd_ctl_new1(&tmp, ice));
  2216. if (err < 0)
  2217. return err;
  2218. }
  2219. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_spdif_route, ice));
  2220. if (err < 0)
  2221. return err;
  2222. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_volume_rate, ice));
  2223. if (err < 0)
  2224. return err;
  2225. err = snd_ctl_add(ice->card, snd_ctl_new1(&snd_ice1712_mixer_pro_peak, ice));
  2226. if (err < 0)
  2227. return err;
  2228. return 0;
  2229. }
  2230. static int snd_ice1712_free(struct snd_ice1712 *ice)
  2231. {
  2232. if (! ice->port)
  2233. goto __hw_end;
  2234. /* mask all interrupts */
  2235. outb(0xc0, ICEMT(ice, IRQ));
  2236. outb(0xff, ICEREG(ice, IRQMASK));
  2237. /* --- */
  2238. __hw_end:
  2239. if (ice->irq >= 0) {
  2240. synchronize_irq(ice->irq);
  2241. free_irq(ice->irq, ice);
  2242. }
  2243. if (ice->port)
  2244. pci_release_regions(ice->pci);
  2245. snd_ice1712_akm4xxx_free(ice);
  2246. pci_disable_device(ice->pci);
  2247. kfree(ice);
  2248. return 0;
  2249. }
  2250. static int snd_ice1712_dev_free(struct snd_device *device)
  2251. {
  2252. struct snd_ice1712 *ice = device->device_data;
  2253. return snd_ice1712_free(ice);
  2254. }
  2255. static int __devinit snd_ice1712_create(struct snd_card *card,
  2256. struct pci_dev *pci,
  2257. const char *modelname,
  2258. int omni,
  2259. int cs8427_timeout,
  2260. int dxr_enable,
  2261. struct snd_ice1712 ** r_ice1712)
  2262. {
  2263. struct snd_ice1712 *ice;
  2264. int err;
  2265. static struct snd_device_ops ops = {
  2266. .dev_free = snd_ice1712_dev_free,
  2267. };
  2268. *r_ice1712 = NULL;
  2269. /* enable PCI device */
  2270. if ((err = pci_enable_device(pci)) < 0)
  2271. return err;
  2272. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2273. if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
  2274. pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
  2275. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2276. pci_disable_device(pci);
  2277. return -ENXIO;
  2278. }
  2279. ice = kzalloc(sizeof(*ice), GFP_KERNEL);
  2280. if (ice == NULL) {
  2281. pci_disable_device(pci);
  2282. return -ENOMEM;
  2283. }
  2284. ice->omni = omni ? 1 : 0;
  2285. if (cs8427_timeout < 1)
  2286. cs8427_timeout = 1;
  2287. else if (cs8427_timeout > 1000)
  2288. cs8427_timeout = 1000;
  2289. ice->cs8427_timeout = cs8427_timeout;
  2290. ice->dxr_enable = dxr_enable;
  2291. spin_lock_init(&ice->reg_lock);
  2292. mutex_init(&ice->gpio_mutex);
  2293. mutex_init(&ice->i2c_mutex);
  2294. mutex_init(&ice->open_mutex);
  2295. ice->gpio.set_mask = snd_ice1712_set_gpio_mask;
  2296. ice->gpio.set_dir = snd_ice1712_set_gpio_dir;
  2297. ice->gpio.set_data = snd_ice1712_set_gpio_data;
  2298. ice->gpio.get_data = snd_ice1712_get_gpio_data;
  2299. ice->spdif.cs8403_bits =
  2300. ice->spdif.cs8403_stream_bits = (0x01 | /* consumer format */
  2301. 0x10 | /* no emphasis */
  2302. 0x20); /* PCM encoder/decoder */
  2303. ice->card = card;
  2304. ice->pci = pci;
  2305. ice->irq = -1;
  2306. pci_set_master(pci);
  2307. pci_write_config_word(ice->pci, 0x40, 0x807f);
  2308. pci_write_config_word(ice->pci, 0x42, 0x0006);
  2309. snd_ice1712_proc_init(ice);
  2310. synchronize_irq(pci->irq);
  2311. if ((err = pci_request_regions(pci, "ICE1712")) < 0) {
  2312. kfree(ice);
  2313. pci_disable_device(pci);
  2314. return err;
  2315. }
  2316. ice->port = pci_resource_start(pci, 0);
  2317. ice->ddma_port = pci_resource_start(pci, 1);
  2318. ice->dmapath_port = pci_resource_start(pci, 2);
  2319. ice->profi_port = pci_resource_start(pci, 3);
  2320. if (request_irq(pci->irq, snd_ice1712_interrupt, IRQF_SHARED,
  2321. "ICE1712", ice)) {
  2322. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2323. snd_ice1712_free(ice);
  2324. return -EIO;
  2325. }
  2326. ice->irq = pci->irq;
  2327. if (snd_ice1712_read_eeprom(ice, modelname) < 0) {
  2328. snd_ice1712_free(ice);
  2329. return -EIO;
  2330. }
  2331. if (snd_ice1712_chip_init(ice) < 0) {
  2332. snd_ice1712_free(ice);
  2333. return -EIO;
  2334. }
  2335. /* unmask used interrupts */
  2336. outb(((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) == 0 ?
  2337. ICE1712_IRQ_MPU2 : 0) |
  2338. ((ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_NO_CON_AC97) ?
  2339. ICE1712_IRQ_PBKDS | ICE1712_IRQ_CONCAP | ICE1712_IRQ_CONPBK : 0),
  2340. ICEREG(ice, IRQMASK));
  2341. outb(0x00, ICEMT(ice, IRQ));
  2342. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, ice, &ops)) < 0) {
  2343. snd_ice1712_free(ice);
  2344. return err;
  2345. }
  2346. snd_card_set_dev(card, &pci->dev);
  2347. *r_ice1712 = ice;
  2348. return 0;
  2349. }
  2350. /*
  2351. *
  2352. * Registration
  2353. *
  2354. */
  2355. static const struct snd_ice1712_card_info no_matched __devinitdata;
  2356. static int __devinit snd_ice1712_probe(struct pci_dev *pci,
  2357. const struct pci_device_id *pci_id)
  2358. {
  2359. static int dev;
  2360. struct snd_card *card;
  2361. struct snd_ice1712 *ice;
  2362. int pcm_dev = 0, err;
  2363. const struct snd_ice1712_card_info **tbl, *c;
  2364. if (dev >= SNDRV_CARDS)
  2365. return -ENODEV;
  2366. if (!enable[dev]) {
  2367. dev++;
  2368. return -ENOENT;
  2369. }
  2370. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  2371. if (card == NULL)
  2372. return -ENOMEM;
  2373. strcpy(card->driver, "ICE1712");
  2374. strcpy(card->shortname, "ICEnsemble ICE1712");
  2375. if ((err = snd_ice1712_create(card, pci, model[dev], omni[dev],
  2376. cs8427_timeout[dev], dxr_enable[dev],
  2377. &ice)) < 0) {
  2378. snd_card_free(card);
  2379. return err;
  2380. }
  2381. for (tbl = card_tables; *tbl; tbl++) {
  2382. for (c = *tbl; c->subvendor; c++) {
  2383. if (c->subvendor == ice->eeprom.subvendor) {
  2384. strcpy(card->shortname, c->name);
  2385. if (c->driver) /* specific driver? */
  2386. strcpy(card->driver, c->driver);
  2387. if (c->chip_init) {
  2388. if ((err = c->chip_init(ice)) < 0) {
  2389. snd_card_free(card);
  2390. return err;
  2391. }
  2392. }
  2393. goto __found;
  2394. }
  2395. }
  2396. }
  2397. c = &no_matched;
  2398. __found:
  2399. if ((err = snd_ice1712_pcm_profi(ice, pcm_dev++, NULL)) < 0) {
  2400. snd_card_free(card);
  2401. return err;
  2402. }
  2403. if (ice_has_con_ac97(ice))
  2404. if ((err = snd_ice1712_pcm(ice, pcm_dev++, NULL)) < 0) {
  2405. snd_card_free(card);
  2406. return err;
  2407. }
  2408. if ((err = snd_ice1712_ac97_mixer(ice)) < 0) {
  2409. snd_card_free(card);
  2410. return err;
  2411. }
  2412. if ((err = snd_ice1712_build_controls(ice)) < 0) {
  2413. snd_card_free(card);
  2414. return err;
  2415. }
  2416. if (c->build_controls) {
  2417. if ((err = c->build_controls(ice)) < 0) {
  2418. snd_card_free(card);
  2419. return err;
  2420. }
  2421. }
  2422. if (ice_has_con_ac97(ice))
  2423. if ((err = snd_ice1712_pcm_ds(ice, pcm_dev++, NULL)) < 0) {
  2424. snd_card_free(card);
  2425. return err;
  2426. }
  2427. if (! c->no_mpu401) {
  2428. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_ICE1712,
  2429. ICEREG(ice, MPU1_CTRL),
  2430. (c->mpu401_1_info_flags |
  2431. MPU401_INFO_INTEGRATED),
  2432. ice->irq, 0,
  2433. &ice->rmidi[0])) < 0) {
  2434. snd_card_free(card);
  2435. return err;
  2436. }
  2437. if (c->mpu401_1_name)
  2438. /* Prefered name available in card_info */
  2439. snprintf(ice->rmidi[0]->name,
  2440. sizeof(ice->rmidi[0]->name),
  2441. "%s %d", c->mpu401_1_name, card->number);
  2442. if (ice->eeprom.data[ICE_EEP1_CODEC] & ICE1712_CFG_2xMPU401) {
  2443. /* 2nd port used */
  2444. if ((err = snd_mpu401_uart_new(card, 1, MPU401_HW_ICE1712,
  2445. ICEREG(ice, MPU2_CTRL),
  2446. (c->mpu401_2_info_flags |
  2447. MPU401_INFO_INTEGRATED),
  2448. ice->irq, 0,
  2449. &ice->rmidi[1])) < 0) {
  2450. snd_card_free(card);
  2451. return err;
  2452. }
  2453. if (c->mpu401_2_name)
  2454. /* Prefered name available in card_info */
  2455. snprintf(ice->rmidi[1]->name,
  2456. sizeof(ice->rmidi[1]->name),
  2457. "%s %d", c->mpu401_2_name,
  2458. card->number);
  2459. }
  2460. }
  2461. snd_ice1712_set_input_clock_source(ice, 0);
  2462. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2463. card->shortname, ice->port, ice->irq);
  2464. if ((err = snd_card_register(card)) < 0) {
  2465. snd_card_free(card);
  2466. return err;
  2467. }
  2468. pci_set_drvdata(pci, card);
  2469. dev++;
  2470. return 0;
  2471. }
  2472. static void __devexit snd_ice1712_remove(struct pci_dev *pci)
  2473. {
  2474. snd_card_free(pci_get_drvdata(pci));
  2475. pci_set_drvdata(pci, NULL);
  2476. }
  2477. static struct pci_driver driver = {
  2478. .name = "ICE1712",
  2479. .id_table = snd_ice1712_ids,
  2480. .probe = snd_ice1712_probe,
  2481. .remove = __devexit_p(snd_ice1712_remove),
  2482. };
  2483. static int __init alsa_card_ice1712_init(void)
  2484. {
  2485. return pci_register_driver(&driver);
  2486. }
  2487. static void __exit alsa_card_ice1712_exit(void)
  2488. {
  2489. pci_unregister_driver(&driver);
  2490. }
  2491. module_init(alsa_card_ice1712_init)
  2492. module_exit(alsa_card_ice1712_exit)