patch_si3054.c 8.6 KB

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  1. /*
  2. * Universal Interface for Intel High Definition Audio Codec
  3. *
  4. * HD audio interface patch for Silicon Labs 3054/5 modem codec
  5. *
  6. * Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
  7. * Takashi Iwai <tiwai@suse.de>
  8. *
  9. *
  10. * This driver is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This driver is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <sound/driver.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/slab.h>
  28. #include <linux/pci.h>
  29. #include <sound/core.h>
  30. #include "hda_codec.h"
  31. #include "hda_local.h"
  32. /* si3054 verbs */
  33. #define SI3054_VERB_READ_NODE 0x900
  34. #define SI3054_VERB_WRITE_NODE 0x100
  35. /* si3054 nodes (registers) */
  36. #define SI3054_EXTENDED_MID 2
  37. #define SI3054_LINE_RATE 3
  38. #define SI3054_LINE_LEVEL 4
  39. #define SI3054_GPIO_CFG 5
  40. #define SI3054_GPIO_POLARITY 6
  41. #define SI3054_GPIO_STICKY 7
  42. #define SI3054_GPIO_WAKEUP 8
  43. #define SI3054_GPIO_STATUS 9
  44. #define SI3054_GPIO_CONTROL 10
  45. #define SI3054_MISC_AFE 11
  46. #define SI3054_CHIPID 12
  47. #define SI3054_LINE_CFG1 13
  48. #define SI3054_LINE_STATUS 14
  49. #define SI3054_DC_TERMINATION 15
  50. #define SI3054_LINE_CONFIG 16
  51. #define SI3054_CALLPROG_ATT 17
  52. #define SI3054_SQ_CONTROL 18
  53. #define SI3054_MISC_CONTROL 19
  54. #define SI3054_RING_CTRL1 20
  55. #define SI3054_RING_CTRL2 21
  56. /* extended MID */
  57. #define SI3054_MEI_READY 0xf
  58. /* line level */
  59. #define SI3054_ATAG_MASK 0x00f0
  60. #define SI3054_DTAG_MASK 0xf000
  61. /* GPIO bits */
  62. #define SI3054_GPIO_OH 0x0001
  63. #define SI3054_GPIO_CID 0x0002
  64. /* chipid and revisions */
  65. #define SI3054_CHIPID_CODEC_REV_MASK 0x000f
  66. #define SI3054_CHIPID_DAA_REV_MASK 0x00f0
  67. #define SI3054_CHIPID_INTERNATIONAL 0x0100
  68. #define SI3054_CHIPID_DAA_ID 0x0f00
  69. #define SI3054_CHIPID_CODEC_ID (1<<12)
  70. /* si3054 codec registers (nodes) access macros */
  71. #define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
  72. #define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
  73. struct si3054_spec {
  74. unsigned international;
  75. struct hda_pcm pcm;
  76. };
  77. /*
  78. * Modem mixer
  79. */
  80. #define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
  81. #define PRIVATE_REG(val) ((val>>16)&0xffff)
  82. #define PRIVATE_MASK(val) (val&0xffff)
  83. static int si3054_switch_info(struct snd_kcontrol *kcontrol,
  84. struct snd_ctl_elem_info *uinfo)
  85. {
  86. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  87. uinfo->count = 1;
  88. uinfo->value.integer.min = 0;
  89. uinfo->value.integer.max = 1;
  90. return 0;
  91. }
  92. static int si3054_switch_get(struct snd_kcontrol *kcontrol,
  93. struct snd_ctl_elem_value *uvalue)
  94. {
  95. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  96. u16 reg = PRIVATE_REG(kcontrol->private_value);
  97. u16 mask = PRIVATE_MASK(kcontrol->private_value);
  98. uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
  99. return 0;
  100. }
  101. static int si3054_switch_put(struct snd_kcontrol *kcontrol,
  102. struct snd_ctl_elem_value *uvalue)
  103. {
  104. struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
  105. u16 reg = PRIVATE_REG(kcontrol->private_value);
  106. u16 mask = PRIVATE_MASK(kcontrol->private_value);
  107. if (uvalue->value.integer.value[0])
  108. SET_REG(codec, reg, (GET_REG(codec, reg)) | mask);
  109. else
  110. SET_REG(codec, reg, (GET_REG(codec, reg)) & ~mask);
  111. return 0;
  112. }
  113. #define SI3054_KCONTROL(kname,reg,mask) { \
  114. .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  115. .name = kname, \
  116. .info = si3054_switch_info, \
  117. .get = si3054_switch_get, \
  118. .put = si3054_switch_put, \
  119. .private_value = PRIVATE_VALUE(reg,mask), \
  120. }
  121. static struct snd_kcontrol_new si3054_modem_mixer[] = {
  122. SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
  123. SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
  124. {}
  125. };
  126. static int si3054_build_controls(struct hda_codec *codec)
  127. {
  128. return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
  129. }
  130. /*
  131. * PCM callbacks
  132. */
  133. static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
  134. struct hda_codec *codec,
  135. unsigned int stream_tag,
  136. unsigned int format,
  137. struct snd_pcm_substream *substream)
  138. {
  139. u16 val;
  140. SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
  141. val = GET_REG(codec, SI3054_LINE_LEVEL);
  142. val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
  143. val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
  144. SET_REG(codec, SI3054_LINE_LEVEL, val);
  145. snd_hda_codec_setup_stream(codec, hinfo->nid,
  146. stream_tag, 0, format);
  147. return 0;
  148. }
  149. static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
  150. struct hda_codec *codec,
  151. struct snd_pcm_substream *substream)
  152. {
  153. static unsigned int rates[] = { 8000, 9600, 16000 };
  154. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  155. .count = ARRAY_SIZE(rates),
  156. .list = rates,
  157. .mask = 0,
  158. };
  159. substream->runtime->hw.period_bytes_min = 80;
  160. return snd_pcm_hw_constraint_list(substream->runtime, 0,
  161. SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
  162. }
  163. static struct hda_pcm_stream si3054_pcm = {
  164. .substreams = 1,
  165. .channels_min = 1,
  166. .channels_max = 1,
  167. .nid = 0x1,
  168. .rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
  169. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  170. .maxbps = 16,
  171. .ops = {
  172. .open = si3054_pcm_open,
  173. .prepare = si3054_pcm_prepare,
  174. },
  175. };
  176. static int si3054_build_pcms(struct hda_codec *codec)
  177. {
  178. struct si3054_spec *spec = codec->spec;
  179. struct hda_pcm *info = &spec->pcm;
  180. si3054_pcm.nid = codec->mfg;
  181. codec->num_pcms = 1;
  182. codec->pcm_info = info;
  183. info->name = "Si3054 Modem";
  184. info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
  185. info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm;
  186. info->is_modem = 1;
  187. return 0;
  188. }
  189. /*
  190. * Init part
  191. */
  192. static int si3054_init(struct hda_codec *codec)
  193. {
  194. struct si3054_spec *spec = codec->spec;
  195. unsigned wait_count;
  196. u16 val;
  197. snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
  198. snd_hda_codec_write(codec, codec->mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
  199. SET_REG(codec, SI3054_LINE_RATE, 9600);
  200. SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
  201. SET_REG(codec, SI3054_EXTENDED_MID, 0);
  202. wait_count = 10;
  203. do {
  204. msleep(2);
  205. val = GET_REG(codec, SI3054_EXTENDED_MID);
  206. } while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
  207. if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
  208. snd_printk(KERN_ERR "si3054: cannot initialize. EXT MID = %04x\n", val);
  209. /* let's pray that this is no fatal error */
  210. /* return -EACCES; */
  211. }
  212. SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
  213. SET_REG(codec, SI3054_GPIO_CFG, 0x0);
  214. SET_REG(codec, SI3054_MISC_AFE, 0);
  215. SET_REG(codec, SI3054_LINE_CFG1,0x200);
  216. if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
  217. snd_printd("Link Frame Detect(FDT) is not ready (line status: %04x)\n",
  218. GET_REG(codec,SI3054_LINE_STATUS));
  219. }
  220. spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
  221. return 0;
  222. }
  223. static void si3054_free(struct hda_codec *codec)
  224. {
  225. kfree(codec->spec);
  226. }
  227. /*
  228. */
  229. static struct hda_codec_ops si3054_patch_ops = {
  230. .build_controls = si3054_build_controls,
  231. .build_pcms = si3054_build_pcms,
  232. .init = si3054_init,
  233. .free = si3054_free,
  234. #ifdef CONFIG_PM
  235. //.suspend = si3054_suspend,
  236. .resume = si3054_init,
  237. #endif
  238. };
  239. static int patch_si3054(struct hda_codec *codec)
  240. {
  241. struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
  242. if (spec == NULL)
  243. return -ENOMEM;
  244. codec->spec = spec;
  245. codec->patch_ops = si3054_patch_ops;
  246. return 0;
  247. }
  248. /*
  249. * patch entries
  250. */
  251. struct hda_codec_preset snd_hda_preset_si3054[] = {
  252. { .id = 0x163c3055, .name = "Si3054", .patch = patch_si3054 },
  253. { .id = 0x163c3155, .name = "Si3054", .patch = patch_si3054 },
  254. { .id = 0x11c11040, .name = "Si3054", .patch = patch_si3054 },
  255. { .id = 0x11c13026, .name = "Si3054", .patch = patch_si3054 },
  256. { .id = 0x11c13055, .name = "Si3054", .patch = patch_si3054 },
  257. { .id = 0x11c13155, .name = "Si3054", .patch = patch_si3054 },
  258. { .id = 0x10573055, .name = "Si3054", .patch = patch_si3054 },
  259. { .id = 0x10573057, .name = "Si3054", .patch = patch_si3054 },
  260. { .id = 0x10573155, .name = "Si3054", .patch = patch_si3054 },
  261. {}
  262. };