fm801.c 46 KB

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  1. /*
  2. * The driver for the ForteMedia FM801 based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  4. *
  5. * Support FM only card by Andy Shevchenko <andy@smile.org.ua>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. *
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/delay.h>
  24. #include <linux/init.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/moduleparam.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/tlv.h>
  32. #include <sound/ac97_codec.h>
  33. #include <sound/mpu401.h>
  34. #include <sound/opl3.h>
  35. #include <sound/initval.h>
  36. #include <asm/io.h>
  37. #ifdef CONFIG_SND_FM801_TEA575X_BOOL
  38. #include <sound/tea575x-tuner.h>
  39. #define TEA575X_RADIO 1
  40. #endif
  41. MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>");
  42. MODULE_DESCRIPTION("ForteMedia FM801");
  43. MODULE_LICENSE("GPL");
  44. MODULE_SUPPORTED_DEVICE("{{ForteMedia,FM801},"
  45. "{Genius,SoundMaker Live 5.1}}");
  46. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  47. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  48. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  49. /*
  50. * Enable TEA575x tuner
  51. * 1 = MediaForte 256-PCS
  52. * 2 = MediaForte 256-PCPR
  53. * 3 = MediaForte 64-PCR
  54. * 16 = setup tuner only (this is additional bit), i.e. SF-64-PCR FM card
  55. * High 16-bits are video (radio) device number + 1
  56. */
  57. static int tea575x_tuner[SNDRV_CARDS];
  58. module_param_array(index, int, NULL, 0444);
  59. MODULE_PARM_DESC(index, "Index value for the FM801 soundcard.");
  60. module_param_array(id, charp, NULL, 0444);
  61. MODULE_PARM_DESC(id, "ID string for the FM801 soundcard.");
  62. module_param_array(enable, bool, NULL, 0444);
  63. MODULE_PARM_DESC(enable, "Enable FM801 soundcard.");
  64. module_param_array(tea575x_tuner, int, NULL, 0444);
  65. MODULE_PARM_DESC(tea575x_tuner, "Enable TEA575x tuner.");
  66. /*
  67. * Direct registers
  68. */
  69. #define FM801_REG(chip, reg) (chip->port + FM801_##reg)
  70. #define FM801_PCM_VOL 0x00 /* PCM Output Volume */
  71. #define FM801_FM_VOL 0x02 /* FM Output Volume */
  72. #define FM801_I2S_VOL 0x04 /* I2S Volume */
  73. #define FM801_REC_SRC 0x06 /* Record Source */
  74. #define FM801_PLY_CTRL 0x08 /* Playback Control */
  75. #define FM801_PLY_COUNT 0x0a /* Playback Count */
  76. #define FM801_PLY_BUF1 0x0c /* Playback Bufer I */
  77. #define FM801_PLY_BUF2 0x10 /* Playback Buffer II */
  78. #define FM801_CAP_CTRL 0x14 /* Capture Control */
  79. #define FM801_CAP_COUNT 0x16 /* Capture Count */
  80. #define FM801_CAP_BUF1 0x18 /* Capture Buffer I */
  81. #define FM801_CAP_BUF2 0x1c /* Capture Buffer II */
  82. #define FM801_CODEC_CTRL 0x22 /* Codec Control */
  83. #define FM801_I2S_MODE 0x24 /* I2S Mode Control */
  84. #define FM801_VOLUME 0x26 /* Volume Up/Down/Mute Status */
  85. #define FM801_I2C_CTRL 0x29 /* I2C Control */
  86. #define FM801_AC97_CMD 0x2a /* AC'97 Command */
  87. #define FM801_AC97_DATA 0x2c /* AC'97 Data */
  88. #define FM801_MPU401_DATA 0x30 /* MPU401 Data */
  89. #define FM801_MPU401_CMD 0x31 /* MPU401 Command */
  90. #define FM801_GPIO_CTRL 0x52 /* General Purpose I/O Control */
  91. #define FM801_GEN_CTRL 0x54 /* General Control */
  92. #define FM801_IRQ_MASK 0x56 /* Interrupt Mask */
  93. #define FM801_IRQ_STATUS 0x5a /* Interrupt Status */
  94. #define FM801_OPL3_BANK0 0x68 /* OPL3 Status Read / Bank 0 Write */
  95. #define FM801_OPL3_DATA0 0x69 /* OPL3 Data 0 Write */
  96. #define FM801_OPL3_BANK1 0x6a /* OPL3 Bank 1 Write */
  97. #define FM801_OPL3_DATA1 0x6b /* OPL3 Bank 1 Write */
  98. #define FM801_POWERDOWN 0x70 /* Blocks Power Down Control */
  99. /* codec access */
  100. #define FM801_AC97_READ (1<<7) /* read=1, write=0 */
  101. #define FM801_AC97_VALID (1<<8) /* port valid=1 */
  102. #define FM801_AC97_BUSY (1<<9) /* busy=1 */
  103. #define FM801_AC97_ADDR_SHIFT 10 /* codec id (2bit) */
  104. /* playback and record control register bits */
  105. #define FM801_BUF1_LAST (1<<1)
  106. #define FM801_BUF2_LAST (1<<2)
  107. #define FM801_START (1<<5)
  108. #define FM801_PAUSE (1<<6)
  109. #define FM801_IMMED_STOP (1<<7)
  110. #define FM801_RATE_SHIFT 8
  111. #define FM801_RATE_MASK (15 << FM801_RATE_SHIFT)
  112. #define FM801_CHANNELS_4 (1<<12) /* playback only */
  113. #define FM801_CHANNELS_6 (2<<12) /* playback only */
  114. #define FM801_CHANNELS_6MS (3<<12) /* playback only */
  115. #define FM801_CHANNELS_MASK (3<<12)
  116. #define FM801_16BIT (1<<14)
  117. #define FM801_STEREO (1<<15)
  118. /* IRQ status bits */
  119. #define FM801_IRQ_PLAYBACK (1<<8)
  120. #define FM801_IRQ_CAPTURE (1<<9)
  121. #define FM801_IRQ_VOLUME (1<<14)
  122. #define FM801_IRQ_MPU (1<<15)
  123. /* GPIO control register */
  124. #define FM801_GPIO_GP0 (1<<0) /* read/write */
  125. #define FM801_GPIO_GP1 (1<<1)
  126. #define FM801_GPIO_GP2 (1<<2)
  127. #define FM801_GPIO_GP3 (1<<3)
  128. #define FM801_GPIO_GP(x) (1<<(0+(x)))
  129. #define FM801_GPIO_GD0 (1<<8) /* directions: 1 = input, 0 = output*/
  130. #define FM801_GPIO_GD1 (1<<9)
  131. #define FM801_GPIO_GD2 (1<<10)
  132. #define FM801_GPIO_GD3 (1<<11)
  133. #define FM801_GPIO_GD(x) (1<<(8+(x)))
  134. #define FM801_GPIO_GS0 (1<<12) /* function select: */
  135. #define FM801_GPIO_GS1 (1<<13) /* 1 = GPIO */
  136. #define FM801_GPIO_GS2 (1<<14) /* 0 = other (S/PDIF, VOL) */
  137. #define FM801_GPIO_GS3 (1<<15)
  138. #define FM801_GPIO_GS(x) (1<<(12+(x)))
  139. /*
  140. */
  141. struct fm801 {
  142. int irq;
  143. unsigned long port; /* I/O port number */
  144. unsigned int multichannel: 1, /* multichannel support */
  145. secondary: 1; /* secondary codec */
  146. unsigned char secondary_addr; /* address of the secondary codec */
  147. unsigned int tea575x_tuner; /* tuner flags */
  148. unsigned short ply_ctrl; /* playback control */
  149. unsigned short cap_ctrl; /* capture control */
  150. unsigned long ply_buffer;
  151. unsigned int ply_buf;
  152. unsigned int ply_count;
  153. unsigned int ply_size;
  154. unsigned int ply_pos;
  155. unsigned long cap_buffer;
  156. unsigned int cap_buf;
  157. unsigned int cap_count;
  158. unsigned int cap_size;
  159. unsigned int cap_pos;
  160. struct snd_ac97_bus *ac97_bus;
  161. struct snd_ac97 *ac97;
  162. struct snd_ac97 *ac97_sec;
  163. struct pci_dev *pci;
  164. struct snd_card *card;
  165. struct snd_pcm *pcm;
  166. struct snd_rawmidi *rmidi;
  167. struct snd_pcm_substream *playback_substream;
  168. struct snd_pcm_substream *capture_substream;
  169. unsigned int p_dma_size;
  170. unsigned int c_dma_size;
  171. spinlock_t reg_lock;
  172. struct snd_info_entry *proc_entry;
  173. #ifdef TEA575X_RADIO
  174. struct snd_tea575x tea;
  175. #endif
  176. #ifdef CONFIG_PM
  177. u16 saved_regs[0x20];
  178. #endif
  179. };
  180. static struct pci_device_id snd_fm801_ids[] = {
  181. { 0x1319, 0x0801, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* FM801 */
  182. { 0x5213, 0x0510, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, 0, }, /* Gallant Odyssey Sound 4 */
  183. { 0, }
  184. };
  185. MODULE_DEVICE_TABLE(pci, snd_fm801_ids);
  186. /*
  187. * common I/O routines
  188. */
  189. static int snd_fm801_update_bits(struct fm801 *chip, unsigned short reg,
  190. unsigned short mask, unsigned short value)
  191. {
  192. int change;
  193. unsigned long flags;
  194. unsigned short old, new;
  195. spin_lock_irqsave(&chip->reg_lock, flags);
  196. old = inw(chip->port + reg);
  197. new = (old & ~mask) | value;
  198. change = old != new;
  199. if (change)
  200. outw(new, chip->port + reg);
  201. spin_unlock_irqrestore(&chip->reg_lock, flags);
  202. return change;
  203. }
  204. static void snd_fm801_codec_write(struct snd_ac97 *ac97,
  205. unsigned short reg,
  206. unsigned short val)
  207. {
  208. struct fm801 *chip = ac97->private_data;
  209. int idx;
  210. /*
  211. * Wait until the codec interface is not ready..
  212. */
  213. for (idx = 0; idx < 100; idx++) {
  214. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  215. goto ok1;
  216. udelay(10);
  217. }
  218. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  219. return;
  220. ok1:
  221. /* write data and address */
  222. outw(val, FM801_REG(chip, AC97_DATA));
  223. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT), FM801_REG(chip, AC97_CMD));
  224. /*
  225. * Wait until the write command is not completed..
  226. */
  227. for (idx = 0; idx < 1000; idx++) {
  228. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  229. return;
  230. udelay(10);
  231. }
  232. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  233. }
  234. static unsigned short snd_fm801_codec_read(struct snd_ac97 *ac97, unsigned short reg)
  235. {
  236. struct fm801 *chip = ac97->private_data;
  237. int idx;
  238. /*
  239. * Wait until the codec interface is not ready..
  240. */
  241. for (idx = 0; idx < 100; idx++) {
  242. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  243. goto ok1;
  244. udelay(10);
  245. }
  246. snd_printk(KERN_ERR "AC'97 interface is busy (1)\n");
  247. return 0;
  248. ok1:
  249. /* read command */
  250. outw(reg | (ac97->addr << FM801_AC97_ADDR_SHIFT) | FM801_AC97_READ,
  251. FM801_REG(chip, AC97_CMD));
  252. for (idx = 0; idx < 100; idx++) {
  253. if (!(inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_BUSY))
  254. goto ok2;
  255. udelay(10);
  256. }
  257. snd_printk(KERN_ERR "AC'97 interface #%d is busy (2)\n", ac97->num);
  258. return 0;
  259. ok2:
  260. for (idx = 0; idx < 1000; idx++) {
  261. if (inw(FM801_REG(chip, AC97_CMD)) & FM801_AC97_VALID)
  262. goto ok3;
  263. udelay(10);
  264. }
  265. snd_printk(KERN_ERR "AC'97 interface #%d is not valid (2)\n", ac97->num);
  266. return 0;
  267. ok3:
  268. return inw(FM801_REG(chip, AC97_DATA));
  269. }
  270. static unsigned int rates[] = {
  271. 5500, 8000, 9600, 11025,
  272. 16000, 19200, 22050, 32000,
  273. 38400, 44100, 48000
  274. };
  275. static struct snd_pcm_hw_constraint_list hw_constraints_rates = {
  276. .count = ARRAY_SIZE(rates),
  277. .list = rates,
  278. .mask = 0,
  279. };
  280. static unsigned int channels[] = {
  281. 2, 4, 6
  282. };
  283. static struct snd_pcm_hw_constraint_list hw_constraints_channels = {
  284. .count = ARRAY_SIZE(channels),
  285. .list = channels,
  286. .mask = 0,
  287. };
  288. /*
  289. * Sample rate routines
  290. */
  291. static unsigned short snd_fm801_rate_bits(unsigned int rate)
  292. {
  293. unsigned int idx;
  294. for (idx = 0; idx < ARRAY_SIZE(rates); idx++)
  295. if (rates[idx] == rate)
  296. return idx;
  297. snd_BUG();
  298. return ARRAY_SIZE(rates) - 1;
  299. }
  300. /*
  301. * PCM part
  302. */
  303. static int snd_fm801_playback_trigger(struct snd_pcm_substream *substream,
  304. int cmd)
  305. {
  306. struct fm801 *chip = snd_pcm_substream_chip(substream);
  307. spin_lock(&chip->reg_lock);
  308. switch (cmd) {
  309. case SNDRV_PCM_TRIGGER_START:
  310. chip->ply_ctrl &= ~(FM801_BUF1_LAST |
  311. FM801_BUF2_LAST |
  312. FM801_PAUSE);
  313. chip->ply_ctrl |= FM801_START |
  314. FM801_IMMED_STOP;
  315. break;
  316. case SNDRV_PCM_TRIGGER_STOP:
  317. chip->ply_ctrl &= ~(FM801_START | FM801_PAUSE);
  318. break;
  319. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  320. case SNDRV_PCM_TRIGGER_SUSPEND:
  321. chip->ply_ctrl |= FM801_PAUSE;
  322. break;
  323. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  324. case SNDRV_PCM_TRIGGER_RESUME:
  325. chip->ply_ctrl &= ~FM801_PAUSE;
  326. break;
  327. default:
  328. spin_unlock(&chip->reg_lock);
  329. snd_BUG();
  330. return -EINVAL;
  331. }
  332. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  333. spin_unlock(&chip->reg_lock);
  334. return 0;
  335. }
  336. static int snd_fm801_capture_trigger(struct snd_pcm_substream *substream,
  337. int cmd)
  338. {
  339. struct fm801 *chip = snd_pcm_substream_chip(substream);
  340. spin_lock(&chip->reg_lock);
  341. switch (cmd) {
  342. case SNDRV_PCM_TRIGGER_START:
  343. chip->cap_ctrl &= ~(FM801_BUF1_LAST |
  344. FM801_BUF2_LAST |
  345. FM801_PAUSE);
  346. chip->cap_ctrl |= FM801_START |
  347. FM801_IMMED_STOP;
  348. break;
  349. case SNDRV_PCM_TRIGGER_STOP:
  350. chip->cap_ctrl &= ~(FM801_START | FM801_PAUSE);
  351. break;
  352. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  353. case SNDRV_PCM_TRIGGER_SUSPEND:
  354. chip->cap_ctrl |= FM801_PAUSE;
  355. break;
  356. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  357. case SNDRV_PCM_TRIGGER_RESUME:
  358. chip->cap_ctrl &= ~FM801_PAUSE;
  359. break;
  360. default:
  361. spin_unlock(&chip->reg_lock);
  362. snd_BUG();
  363. return -EINVAL;
  364. }
  365. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  366. spin_unlock(&chip->reg_lock);
  367. return 0;
  368. }
  369. static int snd_fm801_hw_params(struct snd_pcm_substream *substream,
  370. struct snd_pcm_hw_params *hw_params)
  371. {
  372. return snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  373. }
  374. static int snd_fm801_hw_free(struct snd_pcm_substream *substream)
  375. {
  376. return snd_pcm_lib_free_pages(substream);
  377. }
  378. static int snd_fm801_playback_prepare(struct snd_pcm_substream *substream)
  379. {
  380. struct fm801 *chip = snd_pcm_substream_chip(substream);
  381. struct snd_pcm_runtime *runtime = substream->runtime;
  382. chip->ply_size = snd_pcm_lib_buffer_bytes(substream);
  383. chip->ply_count = snd_pcm_lib_period_bytes(substream);
  384. spin_lock_irq(&chip->reg_lock);
  385. chip->ply_ctrl &= ~(FM801_START | FM801_16BIT |
  386. FM801_STEREO | FM801_RATE_MASK |
  387. FM801_CHANNELS_MASK);
  388. if (snd_pcm_format_width(runtime->format) == 16)
  389. chip->ply_ctrl |= FM801_16BIT;
  390. if (runtime->channels > 1) {
  391. chip->ply_ctrl |= FM801_STEREO;
  392. if (runtime->channels == 4)
  393. chip->ply_ctrl |= FM801_CHANNELS_4;
  394. else if (runtime->channels == 6)
  395. chip->ply_ctrl |= FM801_CHANNELS_6;
  396. }
  397. chip->ply_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  398. chip->ply_buf = 0;
  399. outw(chip->ply_ctrl, FM801_REG(chip, PLY_CTRL));
  400. outw(chip->ply_count - 1, FM801_REG(chip, PLY_COUNT));
  401. chip->ply_buffer = runtime->dma_addr;
  402. chip->ply_pos = 0;
  403. outl(chip->ply_buffer, FM801_REG(chip, PLY_BUF1));
  404. outl(chip->ply_buffer + (chip->ply_count % chip->ply_size), FM801_REG(chip, PLY_BUF2));
  405. spin_unlock_irq(&chip->reg_lock);
  406. return 0;
  407. }
  408. static int snd_fm801_capture_prepare(struct snd_pcm_substream *substream)
  409. {
  410. struct fm801 *chip = snd_pcm_substream_chip(substream);
  411. struct snd_pcm_runtime *runtime = substream->runtime;
  412. chip->cap_size = snd_pcm_lib_buffer_bytes(substream);
  413. chip->cap_count = snd_pcm_lib_period_bytes(substream);
  414. spin_lock_irq(&chip->reg_lock);
  415. chip->cap_ctrl &= ~(FM801_START | FM801_16BIT |
  416. FM801_STEREO | FM801_RATE_MASK);
  417. if (snd_pcm_format_width(runtime->format) == 16)
  418. chip->cap_ctrl |= FM801_16BIT;
  419. if (runtime->channels > 1)
  420. chip->cap_ctrl |= FM801_STEREO;
  421. chip->cap_ctrl |= snd_fm801_rate_bits(runtime->rate) << FM801_RATE_SHIFT;
  422. chip->cap_buf = 0;
  423. outw(chip->cap_ctrl, FM801_REG(chip, CAP_CTRL));
  424. outw(chip->cap_count - 1, FM801_REG(chip, CAP_COUNT));
  425. chip->cap_buffer = runtime->dma_addr;
  426. chip->cap_pos = 0;
  427. outl(chip->cap_buffer, FM801_REG(chip, CAP_BUF1));
  428. outl(chip->cap_buffer + (chip->cap_count % chip->cap_size), FM801_REG(chip, CAP_BUF2));
  429. spin_unlock_irq(&chip->reg_lock);
  430. return 0;
  431. }
  432. static snd_pcm_uframes_t snd_fm801_playback_pointer(struct snd_pcm_substream *substream)
  433. {
  434. struct fm801 *chip = snd_pcm_substream_chip(substream);
  435. size_t ptr;
  436. if (!(chip->ply_ctrl & FM801_START))
  437. return 0;
  438. spin_lock(&chip->reg_lock);
  439. ptr = chip->ply_pos + (chip->ply_count - 1) - inw(FM801_REG(chip, PLY_COUNT));
  440. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_PLAYBACK) {
  441. ptr += chip->ply_count;
  442. ptr %= chip->ply_size;
  443. }
  444. spin_unlock(&chip->reg_lock);
  445. return bytes_to_frames(substream->runtime, ptr);
  446. }
  447. static snd_pcm_uframes_t snd_fm801_capture_pointer(struct snd_pcm_substream *substream)
  448. {
  449. struct fm801 *chip = snd_pcm_substream_chip(substream);
  450. size_t ptr;
  451. if (!(chip->cap_ctrl & FM801_START))
  452. return 0;
  453. spin_lock(&chip->reg_lock);
  454. ptr = chip->cap_pos + (chip->cap_count - 1) - inw(FM801_REG(chip, CAP_COUNT));
  455. if (inw(FM801_REG(chip, IRQ_STATUS)) & FM801_IRQ_CAPTURE) {
  456. ptr += chip->cap_count;
  457. ptr %= chip->cap_size;
  458. }
  459. spin_unlock(&chip->reg_lock);
  460. return bytes_to_frames(substream->runtime, ptr);
  461. }
  462. static irqreturn_t snd_fm801_interrupt(int irq, void *dev_id)
  463. {
  464. struct fm801 *chip = dev_id;
  465. unsigned short status;
  466. unsigned int tmp;
  467. status = inw(FM801_REG(chip, IRQ_STATUS));
  468. status &= FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU|FM801_IRQ_VOLUME;
  469. if (! status)
  470. return IRQ_NONE;
  471. /* ack first */
  472. outw(status, FM801_REG(chip, IRQ_STATUS));
  473. if (chip->pcm && (status & FM801_IRQ_PLAYBACK) && chip->playback_substream) {
  474. spin_lock(&chip->reg_lock);
  475. chip->ply_buf++;
  476. chip->ply_pos += chip->ply_count;
  477. chip->ply_pos %= chip->ply_size;
  478. tmp = chip->ply_pos + chip->ply_count;
  479. tmp %= chip->ply_size;
  480. outl(chip->ply_buffer + tmp,
  481. (chip->ply_buf & 1) ?
  482. FM801_REG(chip, PLY_BUF1) :
  483. FM801_REG(chip, PLY_BUF2));
  484. spin_unlock(&chip->reg_lock);
  485. snd_pcm_period_elapsed(chip->playback_substream);
  486. }
  487. if (chip->pcm && (status & FM801_IRQ_CAPTURE) && chip->capture_substream) {
  488. spin_lock(&chip->reg_lock);
  489. chip->cap_buf++;
  490. chip->cap_pos += chip->cap_count;
  491. chip->cap_pos %= chip->cap_size;
  492. tmp = chip->cap_pos + chip->cap_count;
  493. tmp %= chip->cap_size;
  494. outl(chip->cap_buffer + tmp,
  495. (chip->cap_buf & 1) ?
  496. FM801_REG(chip, CAP_BUF1) :
  497. FM801_REG(chip, CAP_BUF2));
  498. spin_unlock(&chip->reg_lock);
  499. snd_pcm_period_elapsed(chip->capture_substream);
  500. }
  501. if (chip->rmidi && (status & FM801_IRQ_MPU))
  502. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  503. if (status & FM801_IRQ_VOLUME)
  504. ;/* TODO */
  505. return IRQ_HANDLED;
  506. }
  507. static struct snd_pcm_hardware snd_fm801_playback =
  508. {
  509. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  510. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  511. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  512. SNDRV_PCM_INFO_MMAP_VALID),
  513. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  514. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  515. .rate_min = 5500,
  516. .rate_max = 48000,
  517. .channels_min = 1,
  518. .channels_max = 2,
  519. .buffer_bytes_max = (128*1024),
  520. .period_bytes_min = 64,
  521. .period_bytes_max = (128*1024),
  522. .periods_min = 1,
  523. .periods_max = 1024,
  524. .fifo_size = 0,
  525. };
  526. static struct snd_pcm_hardware snd_fm801_capture =
  527. {
  528. .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
  529. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  530. SNDRV_PCM_INFO_PAUSE | SNDRV_PCM_INFO_RESUME |
  531. SNDRV_PCM_INFO_MMAP_VALID),
  532. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  533. .rates = SNDRV_PCM_RATE_KNOT | SNDRV_PCM_RATE_8000_48000,
  534. .rate_min = 5500,
  535. .rate_max = 48000,
  536. .channels_min = 1,
  537. .channels_max = 2,
  538. .buffer_bytes_max = (128*1024),
  539. .period_bytes_min = 64,
  540. .period_bytes_max = (128*1024),
  541. .periods_min = 1,
  542. .periods_max = 1024,
  543. .fifo_size = 0,
  544. };
  545. static int snd_fm801_playback_open(struct snd_pcm_substream *substream)
  546. {
  547. struct fm801 *chip = snd_pcm_substream_chip(substream);
  548. struct snd_pcm_runtime *runtime = substream->runtime;
  549. int err;
  550. chip->playback_substream = substream;
  551. runtime->hw = snd_fm801_playback;
  552. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  553. &hw_constraints_rates);
  554. if (chip->multichannel) {
  555. runtime->hw.channels_max = 6;
  556. snd_pcm_hw_constraint_list(runtime, 0,
  557. SNDRV_PCM_HW_PARAM_CHANNELS,
  558. &hw_constraints_channels);
  559. }
  560. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  561. return err;
  562. return 0;
  563. }
  564. static int snd_fm801_capture_open(struct snd_pcm_substream *substream)
  565. {
  566. struct fm801 *chip = snd_pcm_substream_chip(substream);
  567. struct snd_pcm_runtime *runtime = substream->runtime;
  568. int err;
  569. chip->capture_substream = substream;
  570. runtime->hw = snd_fm801_capture;
  571. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  572. &hw_constraints_rates);
  573. if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
  574. return err;
  575. return 0;
  576. }
  577. static int snd_fm801_playback_close(struct snd_pcm_substream *substream)
  578. {
  579. struct fm801 *chip = snd_pcm_substream_chip(substream);
  580. chip->playback_substream = NULL;
  581. return 0;
  582. }
  583. static int snd_fm801_capture_close(struct snd_pcm_substream *substream)
  584. {
  585. struct fm801 *chip = snd_pcm_substream_chip(substream);
  586. chip->capture_substream = NULL;
  587. return 0;
  588. }
  589. static struct snd_pcm_ops snd_fm801_playback_ops = {
  590. .open = snd_fm801_playback_open,
  591. .close = snd_fm801_playback_close,
  592. .ioctl = snd_pcm_lib_ioctl,
  593. .hw_params = snd_fm801_hw_params,
  594. .hw_free = snd_fm801_hw_free,
  595. .prepare = snd_fm801_playback_prepare,
  596. .trigger = snd_fm801_playback_trigger,
  597. .pointer = snd_fm801_playback_pointer,
  598. };
  599. static struct snd_pcm_ops snd_fm801_capture_ops = {
  600. .open = snd_fm801_capture_open,
  601. .close = snd_fm801_capture_close,
  602. .ioctl = snd_pcm_lib_ioctl,
  603. .hw_params = snd_fm801_hw_params,
  604. .hw_free = snd_fm801_hw_free,
  605. .prepare = snd_fm801_capture_prepare,
  606. .trigger = snd_fm801_capture_trigger,
  607. .pointer = snd_fm801_capture_pointer,
  608. };
  609. static int __devinit snd_fm801_pcm(struct fm801 *chip, int device, struct snd_pcm ** rpcm)
  610. {
  611. struct snd_pcm *pcm;
  612. int err;
  613. if (rpcm)
  614. *rpcm = NULL;
  615. if ((err = snd_pcm_new(chip->card, "FM801", device, 1, 1, &pcm)) < 0)
  616. return err;
  617. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_fm801_playback_ops);
  618. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_fm801_capture_ops);
  619. pcm->private_data = chip;
  620. pcm->info_flags = 0;
  621. strcpy(pcm->name, "FM801");
  622. chip->pcm = pcm;
  623. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  624. snd_dma_pci_data(chip->pci),
  625. chip->multichannel ? 128*1024 : 64*1024, 128*1024);
  626. if (rpcm)
  627. *rpcm = pcm;
  628. return 0;
  629. }
  630. /*
  631. * TEA5757 radio
  632. */
  633. #ifdef TEA575X_RADIO
  634. /* 256PCS GPIO numbers */
  635. #define TEA_256PCS_DATA 1
  636. #define TEA_256PCS_WRITE_ENABLE 2 /* inverted */
  637. #define TEA_256PCS_BUS_CLOCK 3
  638. static void snd_fm801_tea575x_256pcs_write(struct snd_tea575x *tea, unsigned int val)
  639. {
  640. struct fm801 *chip = tea->private_data;
  641. unsigned short reg;
  642. int i = 25;
  643. spin_lock_irq(&chip->reg_lock);
  644. reg = inw(FM801_REG(chip, GPIO_CTRL));
  645. /* use GPIO lines and set write enable bit */
  646. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  647. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  648. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK);
  649. /* all of lines are in the write direction */
  650. /* clear data and clock lines */
  651. reg &= ~(FM801_GPIO_GD(TEA_256PCS_DATA) |
  652. FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  653. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  654. FM801_GPIO_GP(TEA_256PCS_DATA) |
  655. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK) |
  656. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE));
  657. outw(reg, FM801_REG(chip, GPIO_CTRL));
  658. udelay(1);
  659. while (i--) {
  660. if (val & (1 << i))
  661. reg |= FM801_GPIO_GP(TEA_256PCS_DATA);
  662. else
  663. reg &= ~FM801_GPIO_GP(TEA_256PCS_DATA);
  664. outw(reg, FM801_REG(chip, GPIO_CTRL));
  665. udelay(1);
  666. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  667. outw(reg, FM801_REG(chip, GPIO_CTRL));
  668. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  669. outw(reg, FM801_REG(chip, GPIO_CTRL));
  670. udelay(1);
  671. }
  672. /* and reset the write enable bit */
  673. reg |= FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE) |
  674. FM801_GPIO_GP(TEA_256PCS_DATA);
  675. outw(reg, FM801_REG(chip, GPIO_CTRL));
  676. spin_unlock_irq(&chip->reg_lock);
  677. }
  678. static unsigned int snd_fm801_tea575x_256pcs_read(struct snd_tea575x *tea)
  679. {
  680. struct fm801 *chip = tea->private_data;
  681. unsigned short reg;
  682. unsigned int val = 0;
  683. int i;
  684. spin_lock_irq(&chip->reg_lock);
  685. reg = inw(FM801_REG(chip, GPIO_CTRL));
  686. /* use GPIO lines, set data direction to input */
  687. reg |= FM801_GPIO_GS(TEA_256PCS_DATA) |
  688. FM801_GPIO_GS(TEA_256PCS_WRITE_ENABLE) |
  689. FM801_GPIO_GS(TEA_256PCS_BUS_CLOCK) |
  690. FM801_GPIO_GD(TEA_256PCS_DATA) |
  691. FM801_GPIO_GP(TEA_256PCS_DATA) |
  692. FM801_GPIO_GP(TEA_256PCS_WRITE_ENABLE);
  693. /* all of lines are in the write direction, except data */
  694. /* clear data, write enable and clock lines */
  695. reg &= ~(FM801_GPIO_GD(TEA_256PCS_WRITE_ENABLE) |
  696. FM801_GPIO_GD(TEA_256PCS_BUS_CLOCK) |
  697. FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK));
  698. for (i = 0; i < 24; i++) {
  699. reg &= ~FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  700. outw(reg, FM801_REG(chip, GPIO_CTRL));
  701. udelay(1);
  702. reg |= FM801_GPIO_GP(TEA_256PCS_BUS_CLOCK);
  703. outw(reg, FM801_REG(chip, GPIO_CTRL));
  704. udelay(1);
  705. val <<= 1;
  706. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCS_DATA))
  707. val |= 1;
  708. }
  709. spin_unlock_irq(&chip->reg_lock);
  710. return val;
  711. }
  712. /* 256PCPR GPIO numbers */
  713. #define TEA_256PCPR_BUS_CLOCK 0
  714. #define TEA_256PCPR_DATA 1
  715. #define TEA_256PCPR_WRITE_ENABLE 2 /* inverted */
  716. static void snd_fm801_tea575x_256pcpr_write(struct snd_tea575x *tea, unsigned int val)
  717. {
  718. struct fm801 *chip = tea->private_data;
  719. unsigned short reg;
  720. int i = 25;
  721. spin_lock_irq(&chip->reg_lock);
  722. reg = inw(FM801_REG(chip, GPIO_CTRL));
  723. /* use GPIO lines and set write enable bit */
  724. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  725. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  726. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK);
  727. /* all of lines are in the write direction */
  728. /* clear data and clock lines */
  729. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_DATA) |
  730. FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  731. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  732. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  733. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK) |
  734. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE));
  735. outw(reg, FM801_REG(chip, GPIO_CTRL));
  736. udelay(1);
  737. while (i--) {
  738. if (val & (1 << i))
  739. reg |= FM801_GPIO_GP(TEA_256PCPR_DATA);
  740. else
  741. reg &= ~FM801_GPIO_GP(TEA_256PCPR_DATA);
  742. outw(reg, FM801_REG(chip, GPIO_CTRL));
  743. udelay(1);
  744. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  745. outw(reg, FM801_REG(chip, GPIO_CTRL));
  746. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  747. outw(reg, FM801_REG(chip, GPIO_CTRL));
  748. udelay(1);
  749. }
  750. /* and reset the write enable bit */
  751. reg |= FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE) |
  752. FM801_GPIO_GP(TEA_256PCPR_DATA);
  753. outw(reg, FM801_REG(chip, GPIO_CTRL));
  754. spin_unlock_irq(&chip->reg_lock);
  755. }
  756. static unsigned int snd_fm801_tea575x_256pcpr_read(struct snd_tea575x *tea)
  757. {
  758. struct fm801 *chip = tea->private_data;
  759. unsigned short reg;
  760. unsigned int val = 0;
  761. int i;
  762. spin_lock_irq(&chip->reg_lock);
  763. reg = inw(FM801_REG(chip, GPIO_CTRL));
  764. /* use GPIO lines, set data direction to input */
  765. reg |= FM801_GPIO_GS(TEA_256PCPR_DATA) |
  766. FM801_GPIO_GS(TEA_256PCPR_WRITE_ENABLE) |
  767. FM801_GPIO_GS(TEA_256PCPR_BUS_CLOCK) |
  768. FM801_GPIO_GD(TEA_256PCPR_DATA) |
  769. FM801_GPIO_GP(TEA_256PCPR_DATA) |
  770. FM801_GPIO_GP(TEA_256PCPR_WRITE_ENABLE);
  771. /* all of lines are in the write direction, except data */
  772. /* clear data, write enable and clock lines */
  773. reg &= ~(FM801_GPIO_GD(TEA_256PCPR_WRITE_ENABLE) |
  774. FM801_GPIO_GD(TEA_256PCPR_BUS_CLOCK) |
  775. FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK));
  776. for (i = 0; i < 24; i++) {
  777. reg &= ~FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  778. outw(reg, FM801_REG(chip, GPIO_CTRL));
  779. udelay(1);
  780. reg |= FM801_GPIO_GP(TEA_256PCPR_BUS_CLOCK);
  781. outw(reg, FM801_REG(chip, GPIO_CTRL));
  782. udelay(1);
  783. val <<= 1;
  784. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_256PCPR_DATA))
  785. val |= 1;
  786. }
  787. spin_unlock_irq(&chip->reg_lock);
  788. return val;
  789. }
  790. /* 64PCR GPIO numbers */
  791. #define TEA_64PCR_BUS_CLOCK 0
  792. #define TEA_64PCR_WRITE_ENABLE 1 /* inverted */
  793. #define TEA_64PCR_DATA 2
  794. static void snd_fm801_tea575x_64pcr_write(struct snd_tea575x *tea, unsigned int val)
  795. {
  796. struct fm801 *chip = tea->private_data;
  797. unsigned short reg;
  798. int i = 25;
  799. spin_lock_irq(&chip->reg_lock);
  800. reg = inw(FM801_REG(chip, GPIO_CTRL));
  801. /* use GPIO lines and set write enable bit */
  802. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  803. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  804. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK);
  805. /* all of lines are in the write direction */
  806. /* clear data and clock lines */
  807. reg &= ~(FM801_GPIO_GD(TEA_64PCR_DATA) |
  808. FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  809. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  810. FM801_GPIO_GP(TEA_64PCR_DATA) |
  811. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK) |
  812. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE));
  813. outw(reg, FM801_REG(chip, GPIO_CTRL));
  814. udelay(1);
  815. while (i--) {
  816. if (val & (1 << i))
  817. reg |= FM801_GPIO_GP(TEA_64PCR_DATA);
  818. else
  819. reg &= ~FM801_GPIO_GP(TEA_64PCR_DATA);
  820. outw(reg, FM801_REG(chip, GPIO_CTRL));
  821. udelay(1);
  822. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  823. outw(reg, FM801_REG(chip, GPIO_CTRL));
  824. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  825. outw(reg, FM801_REG(chip, GPIO_CTRL));
  826. udelay(1);
  827. }
  828. /* and reset the write enable bit */
  829. reg |= FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE) |
  830. FM801_GPIO_GP(TEA_64PCR_DATA);
  831. outw(reg, FM801_REG(chip, GPIO_CTRL));
  832. spin_unlock_irq(&chip->reg_lock);
  833. }
  834. static unsigned int snd_fm801_tea575x_64pcr_read(struct snd_tea575x *tea)
  835. {
  836. struct fm801 *chip = tea->private_data;
  837. unsigned short reg;
  838. unsigned int val = 0;
  839. int i;
  840. spin_lock_irq(&chip->reg_lock);
  841. reg = inw(FM801_REG(chip, GPIO_CTRL));
  842. /* use GPIO lines, set data direction to input */
  843. reg |= FM801_GPIO_GS(TEA_64PCR_DATA) |
  844. FM801_GPIO_GS(TEA_64PCR_WRITE_ENABLE) |
  845. FM801_GPIO_GS(TEA_64PCR_BUS_CLOCK) |
  846. FM801_GPIO_GD(TEA_64PCR_DATA) |
  847. FM801_GPIO_GP(TEA_64PCR_DATA) |
  848. FM801_GPIO_GP(TEA_64PCR_WRITE_ENABLE);
  849. /* all of lines are in the write direction, except data */
  850. /* clear data, write enable and clock lines */
  851. reg &= ~(FM801_GPIO_GD(TEA_64PCR_WRITE_ENABLE) |
  852. FM801_GPIO_GD(TEA_64PCR_BUS_CLOCK) |
  853. FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK));
  854. for (i = 0; i < 24; i++) {
  855. reg &= ~FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  856. outw(reg, FM801_REG(chip, GPIO_CTRL));
  857. udelay(1);
  858. reg |= FM801_GPIO_GP(TEA_64PCR_BUS_CLOCK);
  859. outw(reg, FM801_REG(chip, GPIO_CTRL));
  860. udelay(1);
  861. val <<= 1;
  862. if (inw(FM801_REG(chip, GPIO_CTRL)) & FM801_GPIO_GP(TEA_64PCR_DATA))
  863. val |= 1;
  864. }
  865. spin_unlock_irq(&chip->reg_lock);
  866. return val;
  867. }
  868. static struct snd_tea575x_ops snd_fm801_tea_ops[3] = {
  869. {
  870. /* 1 = MediaForte 256-PCS */
  871. .write = snd_fm801_tea575x_256pcs_write,
  872. .read = snd_fm801_tea575x_256pcs_read,
  873. },
  874. {
  875. /* 2 = MediaForte 256-PCPR */
  876. .write = snd_fm801_tea575x_256pcpr_write,
  877. .read = snd_fm801_tea575x_256pcpr_read,
  878. },
  879. {
  880. /* 3 = MediaForte 64-PCR */
  881. .write = snd_fm801_tea575x_64pcr_write,
  882. .read = snd_fm801_tea575x_64pcr_read,
  883. }
  884. };
  885. #endif
  886. /*
  887. * Mixer routines
  888. */
  889. #define FM801_SINGLE(xname, reg, shift, mask, invert) \
  890. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_single, \
  891. .get = snd_fm801_get_single, .put = snd_fm801_put_single, \
  892. .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
  893. static int snd_fm801_info_single(struct snd_kcontrol *kcontrol,
  894. struct snd_ctl_elem_info *uinfo)
  895. {
  896. int mask = (kcontrol->private_value >> 16) & 0xff;
  897. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  898. uinfo->count = 1;
  899. uinfo->value.integer.min = 0;
  900. uinfo->value.integer.max = mask;
  901. return 0;
  902. }
  903. static int snd_fm801_get_single(struct snd_kcontrol *kcontrol,
  904. struct snd_ctl_elem_value *ucontrol)
  905. {
  906. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  907. int reg = kcontrol->private_value & 0xff;
  908. int shift = (kcontrol->private_value >> 8) & 0xff;
  909. int mask = (kcontrol->private_value >> 16) & 0xff;
  910. int invert = (kcontrol->private_value >> 24) & 0xff;
  911. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift) & mask;
  912. if (invert)
  913. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  914. return 0;
  915. }
  916. static int snd_fm801_put_single(struct snd_kcontrol *kcontrol,
  917. struct snd_ctl_elem_value *ucontrol)
  918. {
  919. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  920. int reg = kcontrol->private_value & 0xff;
  921. int shift = (kcontrol->private_value >> 8) & 0xff;
  922. int mask = (kcontrol->private_value >> 16) & 0xff;
  923. int invert = (kcontrol->private_value >> 24) & 0xff;
  924. unsigned short val;
  925. val = (ucontrol->value.integer.value[0] & mask);
  926. if (invert)
  927. val = mask - val;
  928. return snd_fm801_update_bits(chip, reg, mask << shift, val << shift);
  929. }
  930. #define FM801_DOUBLE(xname, reg, shift_left, shift_right, mask, invert) \
  931. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .info = snd_fm801_info_double, \
  932. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  933. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24) }
  934. #define FM801_DOUBLE_TLV(xname, reg, shift_left, shift_right, mask, invert, xtlv) \
  935. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  936. .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
  937. .name = xname, .info = snd_fm801_info_double, \
  938. .get = snd_fm801_get_double, .put = snd_fm801_put_double, \
  939. .private_value = reg | (shift_left << 8) | (shift_right << 12) | (mask << 16) | (invert << 24), \
  940. .tlv = { .p = (xtlv) } }
  941. static int snd_fm801_info_double(struct snd_kcontrol *kcontrol,
  942. struct snd_ctl_elem_info *uinfo)
  943. {
  944. int mask = (kcontrol->private_value >> 16) & 0xff;
  945. uinfo->type = mask == 1 ? SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  946. uinfo->count = 2;
  947. uinfo->value.integer.min = 0;
  948. uinfo->value.integer.max = mask;
  949. return 0;
  950. }
  951. static int snd_fm801_get_double(struct snd_kcontrol *kcontrol,
  952. struct snd_ctl_elem_value *ucontrol)
  953. {
  954. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  955. int reg = kcontrol->private_value & 0xff;
  956. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  957. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  958. int mask = (kcontrol->private_value >> 16) & 0xff;
  959. int invert = (kcontrol->private_value >> 24) & 0xff;
  960. spin_lock_irq(&chip->reg_lock);
  961. ucontrol->value.integer.value[0] = (inw(chip->port + reg) >> shift_left) & mask;
  962. ucontrol->value.integer.value[1] = (inw(chip->port + reg) >> shift_right) & mask;
  963. spin_unlock_irq(&chip->reg_lock);
  964. if (invert) {
  965. ucontrol->value.integer.value[0] = mask - ucontrol->value.integer.value[0];
  966. ucontrol->value.integer.value[1] = mask - ucontrol->value.integer.value[1];
  967. }
  968. return 0;
  969. }
  970. static int snd_fm801_put_double(struct snd_kcontrol *kcontrol,
  971. struct snd_ctl_elem_value *ucontrol)
  972. {
  973. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  974. int reg = kcontrol->private_value & 0xff;
  975. int shift_left = (kcontrol->private_value >> 8) & 0x0f;
  976. int shift_right = (kcontrol->private_value >> 12) & 0x0f;
  977. int mask = (kcontrol->private_value >> 16) & 0xff;
  978. int invert = (kcontrol->private_value >> 24) & 0xff;
  979. unsigned short val1, val2;
  980. val1 = ucontrol->value.integer.value[0] & mask;
  981. val2 = ucontrol->value.integer.value[1] & mask;
  982. if (invert) {
  983. val1 = mask - val1;
  984. val2 = mask - val2;
  985. }
  986. return snd_fm801_update_bits(chip, reg,
  987. (mask << shift_left) | (mask << shift_right),
  988. (val1 << shift_left ) | (val2 << shift_right));
  989. }
  990. static int snd_fm801_info_mux(struct snd_kcontrol *kcontrol,
  991. struct snd_ctl_elem_info *uinfo)
  992. {
  993. static char *texts[5] = {
  994. "AC97 Primary", "FM", "I2S", "PCM", "AC97 Secondary"
  995. };
  996. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  997. uinfo->count = 1;
  998. uinfo->value.enumerated.items = 5;
  999. if (uinfo->value.enumerated.item > 4)
  1000. uinfo->value.enumerated.item = 4;
  1001. strcpy(uinfo->value.enumerated.name, texts[uinfo->value.enumerated.item]);
  1002. return 0;
  1003. }
  1004. static int snd_fm801_get_mux(struct snd_kcontrol *kcontrol,
  1005. struct snd_ctl_elem_value *ucontrol)
  1006. {
  1007. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1008. unsigned short val;
  1009. val = inw(FM801_REG(chip, REC_SRC)) & 7;
  1010. if (val > 4)
  1011. val = 4;
  1012. ucontrol->value.enumerated.item[0] = val;
  1013. return 0;
  1014. }
  1015. static int snd_fm801_put_mux(struct snd_kcontrol *kcontrol,
  1016. struct snd_ctl_elem_value *ucontrol)
  1017. {
  1018. struct fm801 *chip = snd_kcontrol_chip(kcontrol);
  1019. unsigned short val;
  1020. if ((val = ucontrol->value.enumerated.item[0]) > 4)
  1021. return -EINVAL;
  1022. return snd_fm801_update_bits(chip, FM801_REC_SRC, 7, val);
  1023. }
  1024. static const DECLARE_TLV_DB_SCALE(db_scale_dsp, -3450, 150, 0);
  1025. #define FM801_CONTROLS ARRAY_SIZE(snd_fm801_controls)
  1026. static struct snd_kcontrol_new snd_fm801_controls[] __devinitdata = {
  1027. FM801_DOUBLE_TLV("Wave Playback Volume", FM801_PCM_VOL, 0, 8, 31, 1,
  1028. db_scale_dsp),
  1029. FM801_SINGLE("Wave Playback Switch", FM801_PCM_VOL, 15, 1, 1),
  1030. FM801_DOUBLE_TLV("I2S Playback Volume", FM801_I2S_VOL, 0, 8, 31, 1,
  1031. db_scale_dsp),
  1032. FM801_SINGLE("I2S Playback Switch", FM801_I2S_VOL, 15, 1, 1),
  1033. FM801_DOUBLE_TLV("FM Playback Volume", FM801_FM_VOL, 0, 8, 31, 1,
  1034. db_scale_dsp),
  1035. FM801_SINGLE("FM Playback Switch", FM801_FM_VOL, 15, 1, 1),
  1036. {
  1037. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1038. .name = "Digital Capture Source",
  1039. .info = snd_fm801_info_mux,
  1040. .get = snd_fm801_get_mux,
  1041. .put = snd_fm801_put_mux,
  1042. }
  1043. };
  1044. #define FM801_CONTROLS_MULTI ARRAY_SIZE(snd_fm801_controls_multi)
  1045. static struct snd_kcontrol_new snd_fm801_controls_multi[] __devinitdata = {
  1046. FM801_SINGLE("AC97 2ch->4ch Copy Switch", FM801_CODEC_CTRL, 7, 1, 0),
  1047. FM801_SINGLE("AC97 18-bit Switch", FM801_CODEC_CTRL, 10, 1, 0),
  1048. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",CAPTURE,SWITCH), FM801_I2S_MODE, 8, 1, 0),
  1049. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",PLAYBACK,SWITCH), FM801_I2S_MODE, 9, 1, 0),
  1050. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("Raw Data ",CAPTURE,SWITCH), FM801_I2S_MODE, 10, 1, 0),
  1051. FM801_SINGLE(SNDRV_CTL_NAME_IEC958("",PLAYBACK,SWITCH), FM801_GEN_CTRL, 2, 1, 0),
  1052. };
  1053. static void snd_fm801_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1054. {
  1055. struct fm801 *chip = bus->private_data;
  1056. chip->ac97_bus = NULL;
  1057. }
  1058. static void snd_fm801_mixer_free_ac97(struct snd_ac97 *ac97)
  1059. {
  1060. struct fm801 *chip = ac97->private_data;
  1061. if (ac97->num == 0) {
  1062. chip->ac97 = NULL;
  1063. } else {
  1064. chip->ac97_sec = NULL;
  1065. }
  1066. }
  1067. static int __devinit snd_fm801_mixer(struct fm801 *chip)
  1068. {
  1069. struct snd_ac97_template ac97;
  1070. unsigned int i;
  1071. int err;
  1072. static struct snd_ac97_bus_ops ops = {
  1073. .write = snd_fm801_codec_write,
  1074. .read = snd_fm801_codec_read,
  1075. };
  1076. if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  1077. return err;
  1078. chip->ac97_bus->private_free = snd_fm801_mixer_free_ac97_bus;
  1079. memset(&ac97, 0, sizeof(ac97));
  1080. ac97.private_data = chip;
  1081. ac97.private_free = snd_fm801_mixer_free_ac97;
  1082. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97)) < 0)
  1083. return err;
  1084. if (chip->secondary) {
  1085. ac97.num = 1;
  1086. ac97.addr = chip->secondary_addr;
  1087. if ((err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97_sec)) < 0)
  1088. return err;
  1089. }
  1090. for (i = 0; i < FM801_CONTROLS; i++)
  1091. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls[i], chip));
  1092. if (chip->multichannel) {
  1093. for (i = 0; i < FM801_CONTROLS_MULTI; i++)
  1094. snd_ctl_add(chip->card, snd_ctl_new1(&snd_fm801_controls_multi[i], chip));
  1095. }
  1096. return 0;
  1097. }
  1098. /*
  1099. * initialization routines
  1100. */
  1101. static int wait_for_codec(struct fm801 *chip, unsigned int codec_id,
  1102. unsigned short reg, unsigned long waits)
  1103. {
  1104. unsigned long timeout = jiffies + waits;
  1105. outw(FM801_AC97_READ | (codec_id << FM801_AC97_ADDR_SHIFT) | reg,
  1106. FM801_REG(chip, AC97_CMD));
  1107. udelay(5);
  1108. do {
  1109. if ((inw(FM801_REG(chip, AC97_CMD)) & (FM801_AC97_VALID|FM801_AC97_BUSY))
  1110. == FM801_AC97_VALID)
  1111. return 0;
  1112. schedule_timeout_uninterruptible(1);
  1113. } while (time_after(timeout, jiffies));
  1114. return -EIO;
  1115. }
  1116. static int snd_fm801_chip_init(struct fm801 *chip, int resume)
  1117. {
  1118. int id;
  1119. unsigned short cmdw;
  1120. if (chip->tea575x_tuner & 0x0010)
  1121. goto __ac97_ok;
  1122. /* codec cold reset + AC'97 warm reset */
  1123. outw((1<<5) | (1<<6), FM801_REG(chip, CODEC_CTRL));
  1124. inw(FM801_REG(chip, CODEC_CTRL)); /* flush posting data */
  1125. udelay(100);
  1126. outw(0, FM801_REG(chip, CODEC_CTRL));
  1127. if (wait_for_codec(chip, 0, AC97_RESET, msecs_to_jiffies(750)) < 0) {
  1128. snd_printk(KERN_ERR "Primary AC'97 codec not found\n");
  1129. if (! resume)
  1130. return -EIO;
  1131. }
  1132. if (chip->multichannel) {
  1133. if (chip->secondary_addr) {
  1134. wait_for_codec(chip, chip->secondary_addr,
  1135. AC97_VENDOR_ID1, msecs_to_jiffies(50));
  1136. } else {
  1137. /* my card has the secondary codec */
  1138. /* at address #3, so the loop is inverted */
  1139. for (id = 3; id > 0; id--) {
  1140. if (! wait_for_codec(chip, id, AC97_VENDOR_ID1,
  1141. msecs_to_jiffies(50))) {
  1142. cmdw = inw(FM801_REG(chip, AC97_DATA));
  1143. if (cmdw != 0xffff && cmdw != 0) {
  1144. chip->secondary = 1;
  1145. chip->secondary_addr = id;
  1146. break;
  1147. }
  1148. }
  1149. }
  1150. }
  1151. /* the recovery phase, it seems that probing for non-existing codec might */
  1152. /* cause timeout problems */
  1153. wait_for_codec(chip, 0, AC97_VENDOR_ID1, msecs_to_jiffies(750));
  1154. }
  1155. __ac97_ok:
  1156. /* init volume */
  1157. outw(0x0808, FM801_REG(chip, PCM_VOL));
  1158. outw(0x9f1f, FM801_REG(chip, FM_VOL));
  1159. outw(0x8808, FM801_REG(chip, I2S_VOL));
  1160. /* I2S control - I2S mode */
  1161. outw(0x0003, FM801_REG(chip, I2S_MODE));
  1162. /* interrupt setup */
  1163. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1164. if (chip->irq < 0)
  1165. cmdw |= 0x00c3; /* mask everything, no PCM nor MPU */
  1166. else
  1167. cmdw &= ~0x0083; /* unmask MPU, PLAYBACK & CAPTURE */
  1168. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1169. /* interrupt clear */
  1170. outw(FM801_IRQ_PLAYBACK|FM801_IRQ_CAPTURE|FM801_IRQ_MPU, FM801_REG(chip, IRQ_STATUS));
  1171. return 0;
  1172. }
  1173. static int snd_fm801_free(struct fm801 *chip)
  1174. {
  1175. unsigned short cmdw;
  1176. if (chip->irq < 0)
  1177. goto __end_hw;
  1178. /* interrupt setup - mask everything */
  1179. cmdw = inw(FM801_REG(chip, IRQ_MASK));
  1180. cmdw |= 0x00c3;
  1181. outw(cmdw, FM801_REG(chip, IRQ_MASK));
  1182. __end_hw:
  1183. #ifdef TEA575X_RADIO
  1184. snd_tea575x_exit(&chip->tea);
  1185. #endif
  1186. if (chip->irq >= 0)
  1187. free_irq(chip->irq, chip);
  1188. pci_release_regions(chip->pci);
  1189. pci_disable_device(chip->pci);
  1190. kfree(chip);
  1191. return 0;
  1192. }
  1193. static int snd_fm801_dev_free(struct snd_device *device)
  1194. {
  1195. struct fm801 *chip = device->device_data;
  1196. return snd_fm801_free(chip);
  1197. }
  1198. static int __devinit snd_fm801_create(struct snd_card *card,
  1199. struct pci_dev * pci,
  1200. int tea575x_tuner,
  1201. struct fm801 ** rchip)
  1202. {
  1203. struct fm801 *chip;
  1204. unsigned char rev;
  1205. int err;
  1206. static struct snd_device_ops ops = {
  1207. .dev_free = snd_fm801_dev_free,
  1208. };
  1209. *rchip = NULL;
  1210. if ((err = pci_enable_device(pci)) < 0)
  1211. return err;
  1212. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1213. if (chip == NULL) {
  1214. pci_disable_device(pci);
  1215. return -ENOMEM;
  1216. }
  1217. spin_lock_init(&chip->reg_lock);
  1218. chip->card = card;
  1219. chip->pci = pci;
  1220. chip->irq = -1;
  1221. chip->tea575x_tuner = tea575x_tuner;
  1222. if ((err = pci_request_regions(pci, "FM801")) < 0) {
  1223. kfree(chip);
  1224. pci_disable_device(pci);
  1225. return err;
  1226. }
  1227. chip->port = pci_resource_start(pci, 0);
  1228. if ((tea575x_tuner & 0x0010) == 0) {
  1229. if (request_irq(pci->irq, snd_fm801_interrupt, IRQF_SHARED,
  1230. "FM801", chip)) {
  1231. snd_printk(KERN_ERR "unable to grab IRQ %d\n", chip->irq);
  1232. snd_fm801_free(chip);
  1233. return -EBUSY;
  1234. }
  1235. chip->irq = pci->irq;
  1236. pci_set_master(pci);
  1237. }
  1238. pci_read_config_byte(pci, PCI_REVISION_ID, &rev);
  1239. if (rev >= 0xb1) /* FM801-AU */
  1240. chip->multichannel = 1;
  1241. snd_fm801_chip_init(chip, 0);
  1242. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1243. snd_fm801_free(chip);
  1244. return err;
  1245. }
  1246. snd_card_set_dev(card, &pci->dev);
  1247. #ifdef TEA575X_RADIO
  1248. if (tea575x_tuner > 0 && (tea575x_tuner & 0x000f) < 4) {
  1249. chip->tea.dev_nr = tea575x_tuner >> 16;
  1250. chip->tea.card = card;
  1251. chip->tea.freq_fixup = 10700;
  1252. chip->tea.private_data = chip;
  1253. chip->tea.ops = &snd_fm801_tea_ops[(tea575x_tuner & 0x000f) - 1];
  1254. snd_tea575x_init(&chip->tea);
  1255. }
  1256. #endif
  1257. *rchip = chip;
  1258. return 0;
  1259. }
  1260. static int __devinit snd_card_fm801_probe(struct pci_dev *pci,
  1261. const struct pci_device_id *pci_id)
  1262. {
  1263. static int dev;
  1264. struct snd_card *card;
  1265. struct fm801 *chip;
  1266. struct snd_opl3 *opl3;
  1267. int err;
  1268. if (dev >= SNDRV_CARDS)
  1269. return -ENODEV;
  1270. if (!enable[dev]) {
  1271. dev++;
  1272. return -ENOENT;
  1273. }
  1274. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  1275. if (card == NULL)
  1276. return -ENOMEM;
  1277. if ((err = snd_fm801_create(card, pci, tea575x_tuner[dev], &chip)) < 0) {
  1278. snd_card_free(card);
  1279. return err;
  1280. }
  1281. card->private_data = chip;
  1282. strcpy(card->driver, "FM801");
  1283. strcpy(card->shortname, "ForteMedia FM801-");
  1284. strcat(card->shortname, chip->multichannel ? "AU" : "AS");
  1285. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1286. card->shortname, chip->port, chip->irq);
  1287. if (tea575x_tuner[dev] & 0x0010)
  1288. goto __fm801_tuner_only;
  1289. if ((err = snd_fm801_pcm(chip, 0, NULL)) < 0) {
  1290. snd_card_free(card);
  1291. return err;
  1292. }
  1293. if ((err = snd_fm801_mixer(chip)) < 0) {
  1294. snd_card_free(card);
  1295. return err;
  1296. }
  1297. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_FM801,
  1298. FM801_REG(chip, MPU401_DATA),
  1299. MPU401_INFO_INTEGRATED,
  1300. chip->irq, 0, &chip->rmidi)) < 0) {
  1301. snd_card_free(card);
  1302. return err;
  1303. }
  1304. if ((err = snd_opl3_create(card, FM801_REG(chip, OPL3_BANK0),
  1305. FM801_REG(chip, OPL3_BANK1),
  1306. OPL3_HW_OPL3_FM801, 1, &opl3)) < 0) {
  1307. snd_card_free(card);
  1308. return err;
  1309. }
  1310. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1311. snd_card_free(card);
  1312. return err;
  1313. }
  1314. __fm801_tuner_only:
  1315. if ((err = snd_card_register(card)) < 0) {
  1316. snd_card_free(card);
  1317. return err;
  1318. }
  1319. pci_set_drvdata(pci, card);
  1320. dev++;
  1321. return 0;
  1322. }
  1323. static void __devexit snd_card_fm801_remove(struct pci_dev *pci)
  1324. {
  1325. snd_card_free(pci_get_drvdata(pci));
  1326. pci_set_drvdata(pci, NULL);
  1327. }
  1328. #ifdef CONFIG_PM
  1329. static unsigned char saved_regs[] = {
  1330. FM801_PCM_VOL, FM801_I2S_VOL, FM801_FM_VOL, FM801_REC_SRC,
  1331. FM801_PLY_CTRL, FM801_PLY_COUNT, FM801_PLY_BUF1, FM801_PLY_BUF2,
  1332. FM801_CAP_CTRL, FM801_CAP_COUNT, FM801_CAP_BUF1, FM801_CAP_BUF2,
  1333. FM801_CODEC_CTRL, FM801_I2S_MODE, FM801_VOLUME, FM801_GEN_CTRL,
  1334. };
  1335. static int snd_fm801_suspend(struct pci_dev *pci, pm_message_t state)
  1336. {
  1337. struct snd_card *card = pci_get_drvdata(pci);
  1338. struct fm801 *chip = card->private_data;
  1339. int i;
  1340. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1341. snd_pcm_suspend_all(chip->pcm);
  1342. snd_ac97_suspend(chip->ac97);
  1343. snd_ac97_suspend(chip->ac97_sec);
  1344. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1345. chip->saved_regs[i] = inw(chip->port + saved_regs[i]);
  1346. /* FIXME: tea575x suspend */
  1347. pci_disable_device(pci);
  1348. pci_save_state(pci);
  1349. pci_set_power_state(pci, pci_choose_state(pci, state));
  1350. return 0;
  1351. }
  1352. static int snd_fm801_resume(struct pci_dev *pci)
  1353. {
  1354. struct snd_card *card = pci_get_drvdata(pci);
  1355. struct fm801 *chip = card->private_data;
  1356. int i;
  1357. pci_set_power_state(pci, PCI_D0);
  1358. pci_restore_state(pci);
  1359. if (pci_enable_device(pci) < 0) {
  1360. printk(KERN_ERR "fm801: pci_enable_device failed, "
  1361. "disabling device\n");
  1362. snd_card_disconnect(card);
  1363. return -EIO;
  1364. }
  1365. pci_set_master(pci);
  1366. snd_fm801_chip_init(chip, 1);
  1367. snd_ac97_resume(chip->ac97);
  1368. snd_ac97_resume(chip->ac97_sec);
  1369. for (i = 0; i < ARRAY_SIZE(saved_regs); i++)
  1370. outw(chip->saved_regs[i], chip->port + saved_regs[i]);
  1371. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1372. return 0;
  1373. }
  1374. #endif
  1375. static struct pci_driver driver = {
  1376. .name = "FM801",
  1377. .id_table = snd_fm801_ids,
  1378. .probe = snd_card_fm801_probe,
  1379. .remove = __devexit_p(snd_card_fm801_remove),
  1380. #ifdef CONFIG_PM
  1381. .suspend = snd_fm801_suspend,
  1382. .resume = snd_fm801_resume,
  1383. #endif
  1384. };
  1385. static int __init alsa_card_fm801_init(void)
  1386. {
  1387. return pci_register_driver(&driver);
  1388. }
  1389. static void __exit alsa_card_fm801_exit(void)
  1390. {
  1391. pci_unregister_driver(&driver);
  1392. }
  1393. module_init(alsa_card_fm801_init)
  1394. module_exit(alsa_card_fm801_exit)