es1968.c 74 KB

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  1. /*
  2. * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
  3. * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
  4. * Takashi Iwai <tiwai@suse.de>
  5. *
  6. * Most of the driver code comes from Zach Brown(zab@redhat.com)
  7. * Alan Cox OSS Driver
  8. * Rewritted from card-es1938.c source.
  9. *
  10. * TODO:
  11. * Perhaps Synth
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License as published by
  15. * the Free Software Foundation; either version 2 of the License, or
  16. * (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. *
  28. * Notes from Zach Brown about the driver code
  29. *
  30. * Hardware Description
  31. *
  32. * A working Maestro setup contains the Maestro chip wired to a
  33. * codec or 2. In the Maestro we have the APUs, the ASSP, and the
  34. * Wavecache. The APUs can be though of as virtual audio routing
  35. * channels. They can take data from a number of sources and perform
  36. * basic encodings of the data. The wavecache is a storehouse for
  37. * PCM data. Typically it deals with PCI and interracts with the
  38. * APUs. The ASSP is a wacky DSP like device that ESS is loth
  39. * to release docs on. Thankfully it isn't required on the Maestro
  40. * until you start doing insane things like FM emulation and surround
  41. * encoding. The codecs are almost always AC-97 compliant codecs,
  42. * but it appears that early Maestros may have had PT101 (an ESS
  43. * part?) wired to them. The only real difference in the Maestro
  44. * families is external goop like docking capability, memory for
  45. * the ASSP, and initialization differences.
  46. *
  47. * Driver Operation
  48. *
  49. * We only drive the APU/Wavecache as typical DACs and drive the
  50. * mixers in the codecs. There are 64 APUs. We assign 6 to each
  51. * /dev/dsp? device. 2 channels for output, and 4 channels for
  52. * input.
  53. *
  54. * Each APU can do a number of things, but we only really use
  55. * 3 basic functions. For playback we use them to convert PCM
  56. * data fetched over PCI by the wavecahche into analog data that
  57. * is handed to the codec. One APU for mono, and a pair for stereo.
  58. * When in stereo, the combination of smarts in the APU and Wavecache
  59. * decide which wavecache gets the left or right channel.
  60. *
  61. * For record we still use the old overly mono system. For each in
  62. * coming channel the data comes in from the codec, through a 'input'
  63. * APU, through another rate converter APU, and then into memory via
  64. * the wavecache and PCI. If its stereo, we mash it back into LRLR in
  65. * software. The pass between the 2 APUs is supposedly what requires us
  66. * to have a 512 byte buffer sitting around in wavecache/memory.
  67. *
  68. * The wavecache makes our life even more fun. First off, it can
  69. * only address the first 28 bits of PCI address space, making it
  70. * useless on quite a few architectures. Secondly, its insane.
  71. * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
  72. * But that doesn't really work. You can only use 1 region. So all our
  73. * allocations have to be in 4meg of each other. Booo. Hiss.
  74. * So we have a module parameter, dsps_order, that is the order of
  75. * the number of dsps to provide. All their buffer space is allocated
  76. * on open time. The sonicvibes OSS routines we inherited really want
  77. * power of 2 buffers, so we have all those next to each other, then
  78. * 512 byte regions for the recording wavecaches. This ends up
  79. * wasting quite a bit of memory. The only fixes I can see would be
  80. * getting a kernel allocator that could work in zones, or figuring out
  81. * just how to coerce the WP into doing what we want.
  82. *
  83. * The indirection of the various registers means we have to spinlock
  84. * nearly all register accesses. We have the main register indirection
  85. * like the wave cache, maestro registers, etc. Then we have beasts
  86. * like the APU interface that is indirect registers gotten at through
  87. * the main maestro indirection. Ouch. We spinlock around the actual
  88. * ports on a per card basis. This means spinlock activity at each IO
  89. * operation, but the only IO operation clusters are in non critical
  90. * paths and it makes the code far easier to follow. Interrupts are
  91. * blocked while holding the locks because the int handler has to
  92. * get at some of them :(. The mixer interface doesn't, however.
  93. * We also have an OSS state lock that is thrown around in a few
  94. * places.
  95. */
  96. #include <sound/driver.h>
  97. #include <asm/io.h>
  98. #include <linux/delay.h>
  99. #include <linux/interrupt.h>
  100. #include <linux/init.h>
  101. #include <linux/pci.h>
  102. #include <linux/dma-mapping.h>
  103. #include <linux/slab.h>
  104. #include <linux/gameport.h>
  105. #include <linux/moduleparam.h>
  106. #include <linux/mutex.h>
  107. #include <sound/core.h>
  108. #include <sound/pcm.h>
  109. #include <sound/mpu401.h>
  110. #include <sound/ac97_codec.h>
  111. #include <sound/initval.h>
  112. #define CARD_NAME "ESS Maestro1/2"
  113. #define DRIVER_NAME "ES1968"
  114. MODULE_DESCRIPTION("ESS Maestro");
  115. MODULE_LICENSE("GPL");
  116. MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
  117. "{ESS,Maestro 2},"
  118. "{ESS,Maestro 1},"
  119. "{TerraTec,DMX}}");
  120. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  121. #define SUPPORT_JOYSTICK 1
  122. #endif
  123. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
  124. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  125. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  126. static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
  127. static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
  128. static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
  129. static int clock[SNDRV_CARDS];
  130. static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
  131. static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
  132. #ifdef SUPPORT_JOYSTICK
  133. static int joystick[SNDRV_CARDS];
  134. #endif
  135. module_param_array(index, int, NULL, 0444);
  136. MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
  137. module_param_array(id, charp, NULL, 0444);
  138. MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
  139. module_param_array(enable, bool, NULL, 0444);
  140. MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
  141. module_param_array(total_bufsize, int, NULL, 0444);
  142. MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
  143. module_param_array(pcm_substreams_p, int, NULL, 0444);
  144. MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
  145. module_param_array(pcm_substreams_c, int, NULL, 0444);
  146. MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
  147. module_param_array(clock, int, NULL, 0444);
  148. MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
  149. module_param_array(use_pm, int, NULL, 0444);
  150. MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
  151. module_param_array(enable_mpu, int, NULL, 0444);
  152. MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
  153. #ifdef SUPPORT_JOYSTICK
  154. module_param_array(joystick, bool, NULL, 0444);
  155. MODULE_PARM_DESC(joystick, "Enable joystick.");
  156. #endif
  157. #define NR_APUS 64
  158. #define NR_APU_REGS 16
  159. /* NEC Versas ? */
  160. #define NEC_VERSA_SUBID1 0x80581033
  161. #define NEC_VERSA_SUBID2 0x803c1033
  162. /* Mode Flags */
  163. #define ESS_FMT_STEREO 0x01
  164. #define ESS_FMT_16BIT 0x02
  165. #define DAC_RUNNING 1
  166. #define ADC_RUNNING 2
  167. /* Values for the ESM_LEGACY_AUDIO_CONTROL */
  168. #define ESS_DISABLE_AUDIO 0x8000
  169. #define ESS_ENABLE_SERIAL_IRQ 0x4000
  170. #define IO_ADRESS_ALIAS 0x0020
  171. #define MPU401_IRQ_ENABLE 0x0010
  172. #define MPU401_IO_ENABLE 0x0008
  173. #define GAME_IO_ENABLE 0x0004
  174. #define FM_IO_ENABLE 0x0002
  175. #define SB_IO_ENABLE 0x0001
  176. /* Values for the ESM_CONFIG_A */
  177. #define PIC_SNOOP1 0x4000
  178. #define PIC_SNOOP2 0x2000
  179. #define SAFEGUARD 0x0800
  180. #define DMA_CLEAR 0x0700
  181. #define DMA_DDMA 0x0000
  182. #define DMA_TDMA 0x0100
  183. #define DMA_PCPCI 0x0200
  184. #define POST_WRITE 0x0080
  185. #define PCI_TIMING 0x0040
  186. #define SWAP_LR 0x0020
  187. #define SUBTR_DECODE 0x0002
  188. /* Values for the ESM_CONFIG_B */
  189. #define SPDIF_CONFB 0x0100
  190. #define HWV_CONFB 0x0080
  191. #define DEBOUNCE 0x0040
  192. #define GPIO_CONFB 0x0020
  193. #define CHI_CONFB 0x0010
  194. #define IDMA_CONFB 0x0008 /*undoc */
  195. #define MIDI_FIX 0x0004 /*undoc */
  196. #define IRQ_TO_ISA 0x0001 /*undoc */
  197. /* Values for Ring Bus Control B */
  198. #define RINGB_2CODEC_ID_MASK 0x0003
  199. #define RINGB_DIS_VALIDATION 0x0008
  200. #define RINGB_EN_SPDIF 0x0010
  201. #define RINGB_EN_2CODEC 0x0020
  202. #define RINGB_SING_BIT_DUAL 0x0040
  203. /* ****Port Adresses**** */
  204. /* Write & Read */
  205. #define ESM_INDEX 0x02
  206. #define ESM_DATA 0x00
  207. /* AC97 + RingBus */
  208. #define ESM_AC97_INDEX 0x30
  209. #define ESM_AC97_DATA 0x32
  210. #define ESM_RING_BUS_DEST 0x34
  211. #define ESM_RING_BUS_CONTR_A 0x36
  212. #define ESM_RING_BUS_CONTR_B 0x38
  213. #define ESM_RING_BUS_SDO 0x3A
  214. /* WaveCache*/
  215. #define WC_INDEX 0x10
  216. #define WC_DATA 0x12
  217. #define WC_CONTROL 0x14
  218. /* ASSP*/
  219. #define ASSP_INDEX 0x80
  220. #define ASSP_MEMORY 0x82
  221. #define ASSP_DATA 0x84
  222. #define ASSP_CONTROL_A 0xA2
  223. #define ASSP_CONTROL_B 0xA4
  224. #define ASSP_CONTROL_C 0xA6
  225. #define ASSP_HOSTW_INDEX 0xA8
  226. #define ASSP_HOSTW_DATA 0xAA
  227. #define ASSP_HOSTW_IRQ 0xAC
  228. /* Midi */
  229. #define ESM_MPU401_PORT 0x98
  230. /* Others */
  231. #define ESM_PORT_HOST_IRQ 0x18
  232. #define IDR0_DATA_PORT 0x00
  233. #define IDR1_CRAM_POINTER 0x01
  234. #define IDR2_CRAM_DATA 0x02
  235. #define IDR3_WAVE_DATA 0x03
  236. #define IDR4_WAVE_PTR_LOW 0x04
  237. #define IDR5_WAVE_PTR_HI 0x05
  238. #define IDR6_TIMER_CTRL 0x06
  239. #define IDR7_WAVE_ROMRAM 0x07
  240. #define WRITEABLE_MAP 0xEFFFFF
  241. #define READABLE_MAP 0x64003F
  242. /* PCI Register */
  243. #define ESM_LEGACY_AUDIO_CONTROL 0x40
  244. #define ESM_ACPI_COMMAND 0x54
  245. #define ESM_CONFIG_A 0x50
  246. #define ESM_CONFIG_B 0x52
  247. #define ESM_DDMA 0x60
  248. /* Bob Bits */
  249. #define ESM_BOB_ENABLE 0x0001
  250. #define ESM_BOB_START 0x0001
  251. /* Host IRQ Control Bits */
  252. #define ESM_RESET_MAESTRO 0x8000
  253. #define ESM_RESET_DIRECTSOUND 0x4000
  254. #define ESM_HIRQ_ClkRun 0x0100
  255. #define ESM_HIRQ_HW_VOLUME 0x0040
  256. #define ESM_HIRQ_HARPO 0x0030 /* What's that? */
  257. #define ESM_HIRQ_ASSP 0x0010
  258. #define ESM_HIRQ_DSIE 0x0004
  259. #define ESM_HIRQ_MPU401 0x0002
  260. #define ESM_HIRQ_SB 0x0001
  261. /* Host IRQ Status Bits */
  262. #define ESM_MPU401_IRQ 0x02
  263. #define ESM_SB_IRQ 0x01
  264. #define ESM_SOUND_IRQ 0x04
  265. #define ESM_ASSP_IRQ 0x10
  266. #define ESM_HWVOL_IRQ 0x40
  267. #define ESS_SYSCLK 50000000
  268. #define ESM_BOB_FREQ 200
  269. #define ESM_BOB_FREQ_MAX 800
  270. #define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
  271. #define ESM_FREQ_ESM2 (50000000L / 1024L)
  272. /* APU Modes: reg 0x00, bit 4-7 */
  273. #define ESM_APU_MODE_SHIFT 4
  274. #define ESM_APU_MODE_MASK (0xf << 4)
  275. #define ESM_APU_OFF 0x00
  276. #define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
  277. #define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
  278. #define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
  279. #define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
  280. #define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
  281. #define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
  282. #define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
  283. #define ESM_APU_CORRELATOR 0x08 /* Correlator */
  284. #define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
  285. #define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
  286. #define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
  287. #define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
  288. #define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
  289. #define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
  290. #define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
  291. /* reg 0x00 */
  292. #define ESM_APU_FILTER_Q_SHIFT 0
  293. #define ESM_APU_FILTER_Q_MASK (3 << 0)
  294. /* APU Filtey Q Control */
  295. #define ESM_APU_FILTER_LESSQ 0x00
  296. #define ESM_APU_FILTER_MOREQ 0x03
  297. #define ESM_APU_FILTER_TYPE_SHIFT 2
  298. #define ESM_APU_FILTER_TYPE_MASK (3 << 2)
  299. #define ESM_APU_ENV_TYPE_SHIFT 8
  300. #define ESM_APU_ENV_TYPE_MASK (3 << 8)
  301. #define ESM_APU_ENV_STATE_SHIFT 10
  302. #define ESM_APU_ENV_STATE_MASK (3 << 10)
  303. #define ESM_APU_END_CURVE (1 << 12)
  304. #define ESM_APU_INT_ON_LOOP (1 << 13)
  305. #define ESM_APU_DMA_ENABLE (1 << 14)
  306. /* reg 0x02 */
  307. #define ESM_APU_SUBMIX_GROUP_SHIRT 0
  308. #define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
  309. #define ESM_APU_SUBMIX_MODE (1 << 3)
  310. #define ESM_APU_6dB (1 << 4)
  311. #define ESM_APU_DUAL_EFFECT (1 << 5)
  312. #define ESM_APU_EFFECT_CHANNELS_SHIFT 6
  313. #define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
  314. /* reg 0x03 */
  315. #define ESM_APU_STEP_SIZE_MASK 0x0fff
  316. /* reg 0x04 */
  317. #define ESM_APU_PHASE_SHIFT 0
  318. #define ESM_APU_PHASE_MASK (0xff << 0)
  319. #define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
  320. #define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
  321. /* reg 0x05 - wave start offset */
  322. /* reg 0x06 - wave end offset */
  323. /* reg 0x07 - wave loop length */
  324. /* reg 0x08 */
  325. #define ESM_APU_EFFECT_GAIN_SHIFT 0
  326. #define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
  327. #define ESM_APU_TREMOLO_DEPTH_SHIFT 8
  328. #define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
  329. #define ESM_APU_TREMOLO_RATE_SHIFT 12
  330. #define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
  331. /* reg 0x09 */
  332. /* bit 0-7 amplitude dest? */
  333. #define ESM_APU_AMPLITUDE_NOW_SHIFT 8
  334. #define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
  335. /* reg 0x0a */
  336. #define ESM_APU_POLAR_PAN_SHIFT 0
  337. #define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
  338. /* Polar Pan Control */
  339. #define ESM_APU_PAN_CENTER_CIRCLE 0x00
  340. #define ESM_APU_PAN_MIDDLE_RADIUS 0x01
  341. #define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
  342. #define ESM_APU_FILTER_TUNING_SHIFT 8
  343. #define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
  344. /* reg 0x0b */
  345. #define ESM_APU_DATA_SRC_A_SHIFT 0
  346. #define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
  347. #define ESM_APU_INV_POL_A (1 << 7)
  348. #define ESM_APU_DATA_SRC_B_SHIFT 8
  349. #define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
  350. #define ESM_APU_INV_POL_B (1 << 15)
  351. #define ESM_APU_VIBRATO_RATE_SHIFT 0
  352. #define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
  353. #define ESM_APU_VIBRATO_DEPTH_SHIFT 4
  354. #define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
  355. #define ESM_APU_VIBRATO_PHASE_SHIFT 8
  356. #define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
  357. /* reg 0x0c */
  358. #define ESM_APU_RADIUS_SELECT (1 << 6)
  359. /* APU Filter Control */
  360. #define ESM_APU_FILTER_2POLE_LOPASS 0x00
  361. #define ESM_APU_FILTER_2POLE_BANDPASS 0x01
  362. #define ESM_APU_FILTER_2POLE_HIPASS 0x02
  363. #define ESM_APU_FILTER_1POLE_LOPASS 0x03
  364. #define ESM_APU_FILTER_1POLE_HIPASS 0x04
  365. #define ESM_APU_FILTER_OFF 0x05
  366. /* APU ATFP Type */
  367. #define ESM_APU_ATFP_AMPLITUDE 0x00
  368. #define ESM_APU_ATFP_TREMELO 0x01
  369. #define ESM_APU_ATFP_FILTER 0x02
  370. #define ESM_APU_ATFP_PAN 0x03
  371. /* APU ATFP Flags */
  372. #define ESM_APU_ATFP_FLG_OFF 0x00
  373. #define ESM_APU_ATFP_FLG_WAIT 0x01
  374. #define ESM_APU_ATFP_FLG_DONE 0x02
  375. #define ESM_APU_ATFP_FLG_INPROCESS 0x03
  376. /* capture mixing buffer size */
  377. #define ESM_MEM_ALIGN 0x1000
  378. #define ESM_MIXBUF_SIZE 0x400
  379. #define ESM_MODE_PLAY 0
  380. #define ESM_MODE_CAPTURE 1
  381. /* APU use in the driver */
  382. enum snd_enum_apu_type {
  383. ESM_APU_PCM_PLAY,
  384. ESM_APU_PCM_CAPTURE,
  385. ESM_APU_PCM_RATECONV,
  386. ESM_APU_FREE
  387. };
  388. /* chip type */
  389. enum {
  390. TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
  391. };
  392. /* DMA Hack! */
  393. struct esm_memory {
  394. struct snd_dma_buffer buf;
  395. int empty; /* status */
  396. struct list_head list;
  397. };
  398. /* Playback Channel */
  399. struct esschan {
  400. int running;
  401. u8 apu[4];
  402. u8 apu_mode[4];
  403. /* playback/capture pcm buffer */
  404. struct esm_memory *memory;
  405. /* capture mixer buffer */
  406. struct esm_memory *mixbuf;
  407. unsigned int hwptr; /* current hw pointer in bytes */
  408. unsigned int count; /* sample counter in bytes */
  409. unsigned int dma_size; /* total buffer size in bytes */
  410. unsigned int frag_size; /* period size in bytes */
  411. unsigned int wav_shift;
  412. u16 base[4]; /* offset for ptr */
  413. /* stereo/16bit flag */
  414. unsigned char fmt;
  415. int mode; /* playback / capture */
  416. int bob_freq; /* required timer frequency */
  417. struct snd_pcm_substream *substream;
  418. /* linked list */
  419. struct list_head list;
  420. #ifdef CONFIG_PM
  421. u16 wc_map[4];
  422. #endif
  423. };
  424. struct es1968 {
  425. /* Module Config */
  426. int total_bufsize; /* in bytes */
  427. int playback_streams, capture_streams;
  428. unsigned int clock; /* clock */
  429. /* for clock measurement */
  430. unsigned int in_measurement: 1;
  431. unsigned int measure_apu;
  432. unsigned int measure_lastpos;
  433. unsigned int measure_count;
  434. /* buffer */
  435. struct snd_dma_buffer dma;
  436. /* Resources... */
  437. int irq;
  438. unsigned long io_port;
  439. int type;
  440. struct pci_dev *pci;
  441. struct snd_card *card;
  442. struct snd_pcm *pcm;
  443. int do_pm; /* power-management enabled */
  444. /* DMA memory block */
  445. struct list_head buf_list;
  446. /* ALSA Stuff */
  447. struct snd_ac97 *ac97;
  448. struct snd_kcontrol *master_switch; /* for h/w volume control */
  449. struct snd_kcontrol *master_volume;
  450. struct snd_rawmidi *rmidi;
  451. spinlock_t reg_lock;
  452. spinlock_t ac97_lock;
  453. struct tasklet_struct hwvol_tq;
  454. unsigned int in_suspend;
  455. /* Maestro Stuff */
  456. u16 maestro_map[32];
  457. int bobclient; /* active timer instancs */
  458. int bob_freq; /* timer frequency */
  459. struct mutex memory_mutex; /* memory lock */
  460. /* APU states */
  461. unsigned char apu[NR_APUS];
  462. /* active substreams */
  463. struct list_head substream_list;
  464. spinlock_t substream_lock;
  465. #ifdef CONFIG_PM
  466. u16 apu_map[NR_APUS][NR_APU_REGS];
  467. #endif
  468. #ifdef SUPPORT_JOYSTICK
  469. struct gameport *gameport;
  470. #endif
  471. };
  472. static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
  473. static struct pci_device_id snd_es1968_ids[] = {
  474. /* Maestro 1 */
  475. { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
  476. /* Maestro 2 */
  477. { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
  478. /* Maestro 2E */
  479. { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
  480. { 0, }
  481. };
  482. MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
  483. /* *********************
  484. * Low Level Funcs! *
  485. *********************/
  486. /* no spinlock */
  487. static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
  488. {
  489. outw(reg, chip->io_port + ESM_INDEX);
  490. outw(data, chip->io_port + ESM_DATA);
  491. chip->maestro_map[reg] = data;
  492. }
  493. static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
  494. {
  495. unsigned long flags;
  496. spin_lock_irqsave(&chip->reg_lock, flags);
  497. __maestro_write(chip, reg, data);
  498. spin_unlock_irqrestore(&chip->reg_lock, flags);
  499. }
  500. /* no spinlock */
  501. static u16 __maestro_read(struct es1968 *chip, u16 reg)
  502. {
  503. if (READABLE_MAP & (1 << reg)) {
  504. outw(reg, chip->io_port + ESM_INDEX);
  505. chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
  506. }
  507. return chip->maestro_map[reg];
  508. }
  509. static inline u16 maestro_read(struct es1968 *chip, u16 reg)
  510. {
  511. unsigned long flags;
  512. u16 result;
  513. spin_lock_irqsave(&chip->reg_lock, flags);
  514. result = __maestro_read(chip, reg);
  515. spin_unlock_irqrestore(&chip->reg_lock, flags);
  516. return result;
  517. }
  518. /* Wait for the codec bus to be free */
  519. static int snd_es1968_ac97_wait(struct es1968 *chip)
  520. {
  521. int timeout = 100000;
  522. while (timeout-- > 0) {
  523. if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
  524. return 0;
  525. cond_resched();
  526. }
  527. snd_printd("es1968: ac97 timeout\n");
  528. return 1; /* timeout */
  529. }
  530. static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
  531. {
  532. struct es1968 *chip = ac97->private_data;
  533. unsigned long flags;
  534. snd_es1968_ac97_wait(chip);
  535. /* Write the bus */
  536. spin_lock_irqsave(&chip->ac97_lock, flags);
  537. outw(val, chip->io_port + ESM_AC97_DATA);
  538. /*msleep(1);*/
  539. outb(reg, chip->io_port + ESM_AC97_INDEX);
  540. /*msleep(1);*/
  541. spin_unlock_irqrestore(&chip->ac97_lock, flags);
  542. }
  543. static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  544. {
  545. u16 data = 0;
  546. struct es1968 *chip = ac97->private_data;
  547. unsigned long flags;
  548. snd_es1968_ac97_wait(chip);
  549. spin_lock_irqsave(&chip->ac97_lock, flags);
  550. outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
  551. /*msleep(1);*/
  552. if (! snd_es1968_ac97_wait(chip)) {
  553. data = inw(chip->io_port + ESM_AC97_DATA);
  554. /*msleep(1);*/
  555. }
  556. spin_unlock_irqrestore(&chip->ac97_lock, flags);
  557. return data;
  558. }
  559. /* no spinlock */
  560. static void apu_index_set(struct es1968 *chip, u16 index)
  561. {
  562. int i;
  563. __maestro_write(chip, IDR1_CRAM_POINTER, index);
  564. for (i = 0; i < 1000; i++)
  565. if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
  566. return;
  567. snd_printd("es1968: APU register select failed. (Timeout)\n");
  568. }
  569. /* no spinlock */
  570. static void apu_data_set(struct es1968 *chip, u16 data)
  571. {
  572. int i;
  573. for (i = 0; i < 1000; i++) {
  574. if (__maestro_read(chip, IDR0_DATA_PORT) == data)
  575. return;
  576. __maestro_write(chip, IDR0_DATA_PORT, data);
  577. }
  578. snd_printd("es1968: APU register set probably failed (Timeout)!\n");
  579. }
  580. /* no spinlock */
  581. static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
  582. {
  583. snd_assert(channel < NR_APUS, return);
  584. #ifdef CONFIG_PM
  585. chip->apu_map[channel][reg] = data;
  586. #endif
  587. reg |= (channel << 4);
  588. apu_index_set(chip, reg);
  589. apu_data_set(chip, data);
  590. }
  591. static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
  592. {
  593. unsigned long flags;
  594. spin_lock_irqsave(&chip->reg_lock, flags);
  595. __apu_set_register(chip, channel, reg, data);
  596. spin_unlock_irqrestore(&chip->reg_lock, flags);
  597. }
  598. static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
  599. {
  600. snd_assert(channel < NR_APUS, return 0);
  601. reg |= (channel << 4);
  602. apu_index_set(chip, reg);
  603. return __maestro_read(chip, IDR0_DATA_PORT);
  604. }
  605. static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
  606. {
  607. unsigned long flags;
  608. u16 v;
  609. spin_lock_irqsave(&chip->reg_lock, flags);
  610. v = __apu_get_register(chip, channel, reg);
  611. spin_unlock_irqrestore(&chip->reg_lock, flags);
  612. return v;
  613. }
  614. #if 0 /* ASSP is not supported */
  615. static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
  616. {
  617. unsigned long flags;
  618. spin_lock_irqsave(&chip->reg_lock, flags);
  619. outl(reg, chip->io_port + ASSP_INDEX);
  620. outl(value, chip->io_port + ASSP_DATA);
  621. spin_unlock_irqrestore(&chip->reg_lock, flags);
  622. }
  623. static u32 assp_get_register(struct es1968 *chip, u32 reg)
  624. {
  625. unsigned long flags;
  626. u32 value;
  627. spin_lock_irqsave(&chip->reg_lock, flags);
  628. outl(reg, chip->io_port + ASSP_INDEX);
  629. value = inl(chip->io_port + ASSP_DATA);
  630. spin_unlock_irqrestore(&chip->reg_lock, flags);
  631. return value;
  632. }
  633. #endif
  634. static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
  635. {
  636. unsigned long flags;
  637. spin_lock_irqsave(&chip->reg_lock, flags);
  638. outw(reg, chip->io_port + WC_INDEX);
  639. outw(value, chip->io_port + WC_DATA);
  640. spin_unlock_irqrestore(&chip->reg_lock, flags);
  641. }
  642. static u16 wave_get_register(struct es1968 *chip, u16 reg)
  643. {
  644. unsigned long flags;
  645. u16 value;
  646. spin_lock_irqsave(&chip->reg_lock, flags);
  647. outw(reg, chip->io_port + WC_INDEX);
  648. value = inw(chip->io_port + WC_DATA);
  649. spin_unlock_irqrestore(&chip->reg_lock, flags);
  650. return value;
  651. }
  652. /* *******************
  653. * Bob the Timer! *
  654. *******************/
  655. static void snd_es1968_bob_stop(struct es1968 *chip)
  656. {
  657. u16 reg;
  658. reg = __maestro_read(chip, 0x11);
  659. reg &= ~ESM_BOB_ENABLE;
  660. __maestro_write(chip, 0x11, reg);
  661. reg = __maestro_read(chip, 0x17);
  662. reg &= ~ESM_BOB_START;
  663. __maestro_write(chip, 0x17, reg);
  664. }
  665. static void snd_es1968_bob_start(struct es1968 *chip)
  666. {
  667. int prescale;
  668. int divide;
  669. /* compute ideal interrupt frequency for buffer size & play rate */
  670. /* first, find best prescaler value to match freq */
  671. for (prescale = 5; prescale < 12; prescale++)
  672. if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
  673. break;
  674. /* next, back off prescaler whilst getting divider into optimum range */
  675. divide = 1;
  676. while ((prescale > 5) && (divide < 32)) {
  677. prescale--;
  678. divide <<= 1;
  679. }
  680. divide >>= 1;
  681. /* now fine-tune the divider for best match */
  682. for (; divide < 31; divide++)
  683. if (chip->bob_freq >
  684. ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
  685. /* divide = 0 is illegal, but don't let prescale = 4! */
  686. if (divide == 0) {
  687. divide++;
  688. if (prescale > 5)
  689. prescale--;
  690. } else if (divide > 1)
  691. divide--;
  692. __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
  693. /* Now set IDR 11/17 */
  694. __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
  695. __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
  696. }
  697. /* call with substream spinlock */
  698. static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
  699. {
  700. chip->bobclient++;
  701. if (chip->bobclient == 1) {
  702. chip->bob_freq = freq;
  703. snd_es1968_bob_start(chip);
  704. } else if (chip->bob_freq < freq) {
  705. snd_es1968_bob_stop(chip);
  706. chip->bob_freq = freq;
  707. snd_es1968_bob_start(chip);
  708. }
  709. }
  710. /* call with substream spinlock */
  711. static void snd_es1968_bob_dec(struct es1968 *chip)
  712. {
  713. chip->bobclient--;
  714. if (chip->bobclient <= 0)
  715. snd_es1968_bob_stop(chip);
  716. else if (chip->bob_freq > ESM_BOB_FREQ) {
  717. /* check reduction of timer frequency */
  718. struct list_head *p;
  719. int max_freq = ESM_BOB_FREQ;
  720. list_for_each(p, &chip->substream_list) {
  721. struct esschan *es = list_entry(p, struct esschan, list);
  722. if (max_freq < es->bob_freq)
  723. max_freq = es->bob_freq;
  724. }
  725. if (max_freq != chip->bob_freq) {
  726. snd_es1968_bob_stop(chip);
  727. chip->bob_freq = max_freq;
  728. snd_es1968_bob_start(chip);
  729. }
  730. }
  731. }
  732. static int
  733. snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
  734. struct snd_pcm_runtime *runtime)
  735. {
  736. /* we acquire 4 interrupts per period for precise control.. */
  737. int freq = runtime->rate * 4;
  738. if (es->fmt & ESS_FMT_STEREO)
  739. freq <<= 1;
  740. if (es->fmt & ESS_FMT_16BIT)
  741. freq <<= 1;
  742. freq /= es->frag_size;
  743. if (freq < ESM_BOB_FREQ)
  744. freq = ESM_BOB_FREQ;
  745. else if (freq > ESM_BOB_FREQ_MAX)
  746. freq = ESM_BOB_FREQ_MAX;
  747. return freq;
  748. }
  749. /*************
  750. * PCM Part *
  751. *************/
  752. static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
  753. {
  754. u32 rate = (freq << 16) / chip->clock;
  755. #if 0 /* XXX: do we need this? */
  756. if (rate > 0x10000)
  757. rate = 0x10000;
  758. #endif
  759. return rate;
  760. }
  761. /* get current pointer */
  762. static inline unsigned int
  763. snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
  764. {
  765. unsigned int offset;
  766. offset = apu_get_register(chip, es->apu[0], 5);
  767. offset -= es->base[0];
  768. return (offset & 0xFFFE); /* hardware is in words */
  769. }
  770. static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
  771. {
  772. apu_set_register(chip, apu, 2,
  773. (apu_get_register(chip, apu, 2) & 0x00FF) |
  774. ((freq & 0xff) << 8) | 0x10);
  775. apu_set_register(chip, apu, 3, freq >> 8);
  776. }
  777. /* spin lock held */
  778. static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
  779. {
  780. /* set the APU mode */
  781. __apu_set_register(esm, apu, 0,
  782. (__apu_get_register(esm, apu, 0) & 0xff0f) |
  783. (mode << 4));
  784. }
  785. static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
  786. {
  787. spin_lock(&chip->reg_lock);
  788. __apu_set_register(chip, es->apu[0], 5, es->base[0]);
  789. snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
  790. if (es->mode == ESM_MODE_CAPTURE) {
  791. __apu_set_register(chip, es->apu[2], 5, es->base[2]);
  792. snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
  793. }
  794. if (es->fmt & ESS_FMT_STEREO) {
  795. __apu_set_register(chip, es->apu[1], 5, es->base[1]);
  796. snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
  797. if (es->mode == ESM_MODE_CAPTURE) {
  798. __apu_set_register(chip, es->apu[3], 5, es->base[3]);
  799. snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
  800. }
  801. }
  802. spin_unlock(&chip->reg_lock);
  803. }
  804. static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
  805. {
  806. spin_lock(&chip->reg_lock);
  807. snd_es1968_trigger_apu(chip, es->apu[0], 0);
  808. snd_es1968_trigger_apu(chip, es->apu[1], 0);
  809. if (es->mode == ESM_MODE_CAPTURE) {
  810. snd_es1968_trigger_apu(chip, es->apu[2], 0);
  811. snd_es1968_trigger_apu(chip, es->apu[3], 0);
  812. }
  813. spin_unlock(&chip->reg_lock);
  814. }
  815. /* set the wavecache control reg */
  816. static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
  817. int channel, u32 addr, int capture)
  818. {
  819. u32 tmpval = (addr - 0x10) & 0xFFF8;
  820. if (! capture) {
  821. if (!(es->fmt & ESS_FMT_16BIT))
  822. tmpval |= 4; /* 8bit */
  823. if (es->fmt & ESS_FMT_STEREO)
  824. tmpval |= 2; /* stereo */
  825. }
  826. /* set the wavecache control reg */
  827. wave_set_register(chip, es->apu[channel] << 3, tmpval);
  828. #ifdef CONFIG_PM
  829. es->wc_map[channel] = tmpval;
  830. #endif
  831. }
  832. static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
  833. struct snd_pcm_runtime *runtime)
  834. {
  835. u32 pa;
  836. int high_apu = 0;
  837. int channel, apu;
  838. int i, size;
  839. unsigned long flags;
  840. u32 freq;
  841. size = es->dma_size >> es->wav_shift;
  842. if (es->fmt & ESS_FMT_STEREO)
  843. high_apu++;
  844. for (channel = 0; channel <= high_apu; channel++) {
  845. apu = es->apu[channel];
  846. snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
  847. /* Offset to PCMBAR */
  848. pa = es->memory->buf.addr;
  849. pa -= chip->dma.addr;
  850. pa >>= 1; /* words */
  851. pa |= 0x00400000; /* System RAM (Bit 22) */
  852. if (es->fmt & ESS_FMT_STEREO) {
  853. /* Enable stereo */
  854. if (channel)
  855. pa |= 0x00800000; /* (Bit 23) */
  856. if (es->fmt & ESS_FMT_16BIT)
  857. pa >>= 1;
  858. }
  859. /* base offset of dma calcs when reading the pointer
  860. on this left one */
  861. es->base[channel] = pa & 0xFFFF;
  862. for (i = 0; i < 16; i++)
  863. apu_set_register(chip, apu, i, 0x0000);
  864. /* Load the buffer into the wave engine */
  865. apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
  866. apu_set_register(chip, apu, 5, pa & 0xFFFF);
  867. apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
  868. /* setting loop == sample len */
  869. apu_set_register(chip, apu, 7, size);
  870. /* clear effects/env.. */
  871. apu_set_register(chip, apu, 8, 0x0000);
  872. /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
  873. apu_set_register(chip, apu, 9, 0xD000);
  874. /* clear routing stuff */
  875. apu_set_register(chip, apu, 11, 0x0000);
  876. /* dma on, no envelopes, filter to all 1s) */
  877. apu_set_register(chip, apu, 0, 0x400F);
  878. if (es->fmt & ESS_FMT_16BIT)
  879. es->apu_mode[channel] = ESM_APU_16BITLINEAR;
  880. else
  881. es->apu_mode[channel] = ESM_APU_8BITLINEAR;
  882. if (es->fmt & ESS_FMT_STEREO) {
  883. /* set panning: left or right */
  884. /* Check: different panning. On my Canyon 3D Chipset the
  885. Channels are swapped. I don't know, about the output
  886. to the SPDif Link. Perhaps you have to change this
  887. and not the APU Regs 4-5. */
  888. apu_set_register(chip, apu, 10,
  889. 0x8F00 | (channel ? 0 : 0x10));
  890. es->apu_mode[channel] += 1; /* stereo */
  891. } else
  892. apu_set_register(chip, apu, 10, 0x8F08);
  893. }
  894. spin_lock_irqsave(&chip->reg_lock, flags);
  895. /* clear WP interrupts */
  896. outw(1, chip->io_port + 0x04);
  897. /* enable WP ints */
  898. outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
  899. spin_unlock_irqrestore(&chip->reg_lock, flags);
  900. freq = runtime->rate;
  901. /* set frequency */
  902. if (freq > 48000)
  903. freq = 48000;
  904. if (freq < 4000)
  905. freq = 4000;
  906. /* hmmm.. */
  907. if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
  908. freq >>= 1;
  909. freq = snd_es1968_compute_rate(chip, freq);
  910. /* Load the frequency, turn on 6dB */
  911. snd_es1968_apu_set_freq(chip, es->apu[0], freq);
  912. snd_es1968_apu_set_freq(chip, es->apu[1], freq);
  913. }
  914. static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
  915. unsigned int pa, unsigned int bsize,
  916. int mode, int route)
  917. {
  918. int i, apu = es->apu[channel];
  919. es->apu_mode[channel] = mode;
  920. /* set the wavecache control reg */
  921. snd_es1968_program_wavecache(chip, es, channel, pa, 1);
  922. /* Offset to PCMBAR */
  923. pa -= chip->dma.addr;
  924. pa >>= 1; /* words */
  925. /* base offset of dma calcs when reading the pointer
  926. on this left one */
  927. es->base[channel] = pa & 0xFFFF;
  928. pa |= 0x00400000; /* bit 22 -> System RAM */
  929. /* Begin loading the APU */
  930. for (i = 0; i < 16; i++)
  931. apu_set_register(chip, apu, i, 0x0000);
  932. /* need to enable subgroups.. and we should probably
  933. have different groups for different /dev/dsps.. */
  934. apu_set_register(chip, apu, 2, 0x8);
  935. /* Load the buffer into the wave engine */
  936. apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
  937. apu_set_register(chip, apu, 5, pa & 0xFFFF);
  938. apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
  939. apu_set_register(chip, apu, 7, bsize);
  940. /* clear effects/env.. */
  941. apu_set_register(chip, apu, 8, 0x00F0);
  942. /* amplitude now? sure. why not. */
  943. apu_set_register(chip, apu, 9, 0x0000);
  944. /* set filter tune, radius, polar pan */
  945. apu_set_register(chip, apu, 10, 0x8F08);
  946. /* route input */
  947. apu_set_register(chip, apu, 11, route);
  948. /* dma on, no envelopes, filter to all 1s) */
  949. apu_set_register(chip, apu, 0, 0x400F);
  950. }
  951. static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
  952. struct snd_pcm_runtime *runtime)
  953. {
  954. int size;
  955. u32 freq;
  956. unsigned long flags;
  957. size = es->dma_size >> es->wav_shift;
  958. /* APU assignments:
  959. 0 = mono/left SRC
  960. 1 = right SRC
  961. 2 = mono/left Input Mixer
  962. 3 = right Input Mixer
  963. */
  964. /* data seems to flow from the codec, through an apu into
  965. the 'mixbuf' bit of page, then through the SRC apu
  966. and out to the real 'buffer'. ok. sure. */
  967. /* input mixer (left/mono) */
  968. /* parallel in crap, see maestro reg 0xC [8-11] */
  969. init_capture_apu(chip, es, 2,
  970. es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
  971. ESM_APU_INPUTMIXER, 0x14);
  972. /* SRC (left/mono); get input from inputing apu */
  973. init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
  974. ESM_APU_SRCONVERTOR, es->apu[2]);
  975. if (es->fmt & ESS_FMT_STEREO) {
  976. /* input mixer (right) */
  977. init_capture_apu(chip, es, 3,
  978. es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
  979. ESM_MIXBUF_SIZE/4, /* in words */
  980. ESM_APU_INPUTMIXER, 0x15);
  981. /* SRC (right) */
  982. init_capture_apu(chip, es, 1,
  983. es->memory->buf.addr + size*2, size,
  984. ESM_APU_SRCONVERTOR, es->apu[3]);
  985. }
  986. freq = runtime->rate;
  987. /* Sample Rate conversion APUs don't like 0x10000 for their rate */
  988. if (freq > 47999)
  989. freq = 47999;
  990. if (freq < 4000)
  991. freq = 4000;
  992. freq = snd_es1968_compute_rate(chip, freq);
  993. /* Load the frequency, turn on 6dB */
  994. snd_es1968_apu_set_freq(chip, es->apu[0], freq);
  995. snd_es1968_apu_set_freq(chip, es->apu[1], freq);
  996. /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
  997. freq = 0x10000;
  998. snd_es1968_apu_set_freq(chip, es->apu[2], freq);
  999. snd_es1968_apu_set_freq(chip, es->apu[3], freq);
  1000. spin_lock_irqsave(&chip->reg_lock, flags);
  1001. /* clear WP interrupts */
  1002. outw(1, chip->io_port + 0x04);
  1003. /* enable WP ints */
  1004. outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
  1005. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1006. }
  1007. /*******************
  1008. * ALSA Interface *
  1009. *******************/
  1010. static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
  1011. {
  1012. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1013. struct snd_pcm_runtime *runtime = substream->runtime;
  1014. struct esschan *es = runtime->private_data;
  1015. es->dma_size = snd_pcm_lib_buffer_bytes(substream);
  1016. es->frag_size = snd_pcm_lib_period_bytes(substream);
  1017. es->wav_shift = 1; /* maestro handles always 16bit */
  1018. es->fmt = 0;
  1019. if (snd_pcm_format_width(runtime->format) == 16)
  1020. es->fmt |= ESS_FMT_16BIT;
  1021. if (runtime->channels > 1) {
  1022. es->fmt |= ESS_FMT_STEREO;
  1023. if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
  1024. es->wav_shift++;
  1025. }
  1026. es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
  1027. switch (es->mode) {
  1028. case ESM_MODE_PLAY:
  1029. snd_es1968_playback_setup(chip, es, runtime);
  1030. break;
  1031. case ESM_MODE_CAPTURE:
  1032. snd_es1968_capture_setup(chip, es, runtime);
  1033. break;
  1034. }
  1035. return 0;
  1036. }
  1037. static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
  1038. {
  1039. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1040. struct esschan *es = substream->runtime->private_data;
  1041. spin_lock(&chip->substream_lock);
  1042. switch (cmd) {
  1043. case SNDRV_PCM_TRIGGER_START:
  1044. case SNDRV_PCM_TRIGGER_RESUME:
  1045. if (es->running)
  1046. break;
  1047. snd_es1968_bob_inc(chip, es->bob_freq);
  1048. es->count = 0;
  1049. es->hwptr = 0;
  1050. snd_es1968_pcm_start(chip, es);
  1051. es->running = 1;
  1052. break;
  1053. case SNDRV_PCM_TRIGGER_STOP:
  1054. case SNDRV_PCM_TRIGGER_SUSPEND:
  1055. if (! es->running)
  1056. break;
  1057. snd_es1968_pcm_stop(chip, es);
  1058. es->running = 0;
  1059. snd_es1968_bob_dec(chip);
  1060. break;
  1061. }
  1062. spin_unlock(&chip->substream_lock);
  1063. return 0;
  1064. }
  1065. static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
  1066. {
  1067. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1068. struct esschan *es = substream->runtime->private_data;
  1069. unsigned int ptr;
  1070. ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
  1071. return bytes_to_frames(substream->runtime, ptr % es->dma_size);
  1072. }
  1073. static struct snd_pcm_hardware snd_es1968_playback = {
  1074. .info = (SNDRV_PCM_INFO_MMAP |
  1075. SNDRV_PCM_INFO_MMAP_VALID |
  1076. SNDRV_PCM_INFO_INTERLEAVED |
  1077. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1078. /*SNDRV_PCM_INFO_PAUSE |*/
  1079. SNDRV_PCM_INFO_RESUME),
  1080. .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
  1081. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1082. .rate_min = 4000,
  1083. .rate_max = 48000,
  1084. .channels_min = 1,
  1085. .channels_max = 2,
  1086. .buffer_bytes_max = 65536,
  1087. .period_bytes_min = 256,
  1088. .period_bytes_max = 65536,
  1089. .periods_min = 1,
  1090. .periods_max = 1024,
  1091. .fifo_size = 0,
  1092. };
  1093. static struct snd_pcm_hardware snd_es1968_capture = {
  1094. .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
  1095. SNDRV_PCM_INFO_MMAP |
  1096. SNDRV_PCM_INFO_MMAP_VALID |
  1097. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  1098. /*SNDRV_PCM_INFO_PAUSE |*/
  1099. SNDRV_PCM_INFO_RESUME),
  1100. .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
  1101. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1102. .rate_min = 4000,
  1103. .rate_max = 48000,
  1104. .channels_min = 1,
  1105. .channels_max = 2,
  1106. .buffer_bytes_max = 65536,
  1107. .period_bytes_min = 256,
  1108. .period_bytes_max = 65536,
  1109. .periods_min = 1,
  1110. .periods_max = 1024,
  1111. .fifo_size = 0,
  1112. };
  1113. /* *************************
  1114. * DMA memory management *
  1115. *************************/
  1116. /* Because the Maestro can only take addresses relative to the PCM base address
  1117. register :( */
  1118. static int calc_available_memory_size(struct es1968 *chip)
  1119. {
  1120. struct list_head *p;
  1121. int max_size = 0;
  1122. mutex_lock(&chip->memory_mutex);
  1123. list_for_each(p, &chip->buf_list) {
  1124. struct esm_memory *buf = list_entry(p, struct esm_memory, list);
  1125. if (buf->empty && buf->buf.bytes > max_size)
  1126. max_size = buf->buf.bytes;
  1127. }
  1128. mutex_unlock(&chip->memory_mutex);
  1129. if (max_size >= 128*1024)
  1130. max_size = 127*1024;
  1131. return max_size;
  1132. }
  1133. /* allocate a new memory chunk with the specified size */
  1134. static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
  1135. {
  1136. struct esm_memory *buf;
  1137. struct list_head *p;
  1138. size = ALIGN(size, ESM_MEM_ALIGN);
  1139. mutex_lock(&chip->memory_mutex);
  1140. list_for_each(p, &chip->buf_list) {
  1141. buf = list_entry(p, struct esm_memory, list);
  1142. if (buf->empty && buf->buf.bytes >= size)
  1143. goto __found;
  1144. }
  1145. mutex_unlock(&chip->memory_mutex);
  1146. return NULL;
  1147. __found:
  1148. if (buf->buf.bytes > size) {
  1149. struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
  1150. if (chunk == NULL) {
  1151. mutex_unlock(&chip->memory_mutex);
  1152. return NULL;
  1153. }
  1154. chunk->buf = buf->buf;
  1155. chunk->buf.bytes -= size;
  1156. chunk->buf.area += size;
  1157. chunk->buf.addr += size;
  1158. chunk->empty = 1;
  1159. buf->buf.bytes = size;
  1160. list_add(&chunk->list, &buf->list);
  1161. }
  1162. buf->empty = 0;
  1163. mutex_unlock(&chip->memory_mutex);
  1164. return buf;
  1165. }
  1166. /* free a memory chunk */
  1167. static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
  1168. {
  1169. struct esm_memory *chunk;
  1170. mutex_lock(&chip->memory_mutex);
  1171. buf->empty = 1;
  1172. if (buf->list.prev != &chip->buf_list) {
  1173. chunk = list_entry(buf->list.prev, struct esm_memory, list);
  1174. if (chunk->empty) {
  1175. chunk->buf.bytes += buf->buf.bytes;
  1176. list_del(&buf->list);
  1177. kfree(buf);
  1178. buf = chunk;
  1179. }
  1180. }
  1181. if (buf->list.next != &chip->buf_list) {
  1182. chunk = list_entry(buf->list.next, struct esm_memory, list);
  1183. if (chunk->empty) {
  1184. buf->buf.bytes += chunk->buf.bytes;
  1185. list_del(&chunk->list);
  1186. kfree(chunk);
  1187. }
  1188. }
  1189. mutex_unlock(&chip->memory_mutex);
  1190. }
  1191. static void snd_es1968_free_dmabuf(struct es1968 *chip)
  1192. {
  1193. struct list_head *p;
  1194. if (! chip->dma.area)
  1195. return;
  1196. snd_dma_reserve_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci));
  1197. while ((p = chip->buf_list.next) != &chip->buf_list) {
  1198. struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
  1199. list_del(p);
  1200. kfree(chunk);
  1201. }
  1202. }
  1203. static int __devinit
  1204. snd_es1968_init_dmabuf(struct es1968 *chip)
  1205. {
  1206. int err;
  1207. struct esm_memory *chunk;
  1208. chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
  1209. chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
  1210. if (! snd_dma_get_reserved_buf(&chip->dma, snd_dma_pci_buf_id(chip->pci))) {
  1211. err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
  1212. snd_dma_pci_data(chip->pci),
  1213. chip->total_bufsize, &chip->dma);
  1214. if (err < 0 || ! chip->dma.area) {
  1215. snd_printk(KERN_ERR "es1968: can't allocate dma pages for size %d\n",
  1216. chip->total_bufsize);
  1217. return -ENOMEM;
  1218. }
  1219. if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
  1220. snd_dma_free_pages(&chip->dma);
  1221. snd_printk(KERN_ERR "es1968: DMA buffer beyond 256MB.\n");
  1222. return -ENOMEM;
  1223. }
  1224. }
  1225. INIT_LIST_HEAD(&chip->buf_list);
  1226. /* allocate an empty chunk */
  1227. chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
  1228. if (chunk == NULL) {
  1229. snd_es1968_free_dmabuf(chip);
  1230. return -ENOMEM;
  1231. }
  1232. memset(chip->dma.area, 0, ESM_MEM_ALIGN);
  1233. chunk->buf = chip->dma;
  1234. chunk->buf.area += ESM_MEM_ALIGN;
  1235. chunk->buf.addr += ESM_MEM_ALIGN;
  1236. chunk->buf.bytes -= ESM_MEM_ALIGN;
  1237. chunk->empty = 1;
  1238. list_add(&chunk->list, &chip->buf_list);
  1239. return 0;
  1240. }
  1241. /* setup the dma_areas */
  1242. /* buffer is extracted from the pre-allocated memory chunk */
  1243. static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
  1244. struct snd_pcm_hw_params *hw_params)
  1245. {
  1246. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1247. struct snd_pcm_runtime *runtime = substream->runtime;
  1248. struct esschan *chan = runtime->private_data;
  1249. int size = params_buffer_bytes(hw_params);
  1250. if (chan->memory) {
  1251. if (chan->memory->buf.bytes >= size) {
  1252. runtime->dma_bytes = size;
  1253. return 0;
  1254. }
  1255. snd_es1968_free_memory(chip, chan->memory);
  1256. }
  1257. chan->memory = snd_es1968_new_memory(chip, size);
  1258. if (chan->memory == NULL) {
  1259. // snd_printd("cannot allocate dma buffer: size = %d\n", size);
  1260. return -ENOMEM;
  1261. }
  1262. snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
  1263. return 1; /* area was changed */
  1264. }
  1265. /* remove dma areas if allocated */
  1266. static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
  1267. {
  1268. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1269. struct snd_pcm_runtime *runtime = substream->runtime;
  1270. struct esschan *chan;
  1271. if (runtime->private_data == NULL)
  1272. return 0;
  1273. chan = runtime->private_data;
  1274. if (chan->memory) {
  1275. snd_es1968_free_memory(chip, chan->memory);
  1276. chan->memory = NULL;
  1277. }
  1278. return 0;
  1279. }
  1280. /*
  1281. * allocate APU pair
  1282. */
  1283. static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
  1284. {
  1285. int apu;
  1286. for (apu = 0; apu < NR_APUS; apu += 2) {
  1287. if (chip->apu[apu] == ESM_APU_FREE &&
  1288. chip->apu[apu + 1] == ESM_APU_FREE) {
  1289. chip->apu[apu] = chip->apu[apu + 1] = type;
  1290. return apu;
  1291. }
  1292. }
  1293. return -EBUSY;
  1294. }
  1295. /*
  1296. * release APU pair
  1297. */
  1298. static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
  1299. {
  1300. chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
  1301. }
  1302. /******************
  1303. * PCM open/close *
  1304. ******************/
  1305. static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
  1306. {
  1307. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1308. struct snd_pcm_runtime *runtime = substream->runtime;
  1309. struct esschan *es;
  1310. int apu1;
  1311. /* search 2 APUs */
  1312. apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
  1313. if (apu1 < 0)
  1314. return apu1;
  1315. es = kzalloc(sizeof(*es), GFP_KERNEL);
  1316. if (!es) {
  1317. snd_es1968_free_apu_pair(chip, apu1);
  1318. return -ENOMEM;
  1319. }
  1320. es->apu[0] = apu1;
  1321. es->apu[1] = apu1 + 1;
  1322. es->apu_mode[0] = 0;
  1323. es->apu_mode[1] = 0;
  1324. es->running = 0;
  1325. es->substream = substream;
  1326. es->mode = ESM_MODE_PLAY;
  1327. runtime->private_data = es;
  1328. runtime->hw = snd_es1968_playback;
  1329. runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
  1330. calc_available_memory_size(chip);
  1331. #if 0
  1332. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1333. 1024);
  1334. #endif
  1335. spin_lock_irq(&chip->substream_lock);
  1336. list_add(&es->list, &chip->substream_list);
  1337. spin_unlock_irq(&chip->substream_lock);
  1338. return 0;
  1339. }
  1340. static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
  1341. {
  1342. struct snd_pcm_runtime *runtime = substream->runtime;
  1343. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1344. struct esschan *es;
  1345. int apu1, apu2;
  1346. apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
  1347. if (apu1 < 0)
  1348. return apu1;
  1349. apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
  1350. if (apu2 < 0) {
  1351. snd_es1968_free_apu_pair(chip, apu1);
  1352. return apu2;
  1353. }
  1354. es = kzalloc(sizeof(*es), GFP_KERNEL);
  1355. if (!es) {
  1356. snd_es1968_free_apu_pair(chip, apu1);
  1357. snd_es1968_free_apu_pair(chip, apu2);
  1358. return -ENOMEM;
  1359. }
  1360. es->apu[0] = apu1;
  1361. es->apu[1] = apu1 + 1;
  1362. es->apu[2] = apu2;
  1363. es->apu[3] = apu2 + 1;
  1364. es->apu_mode[0] = 0;
  1365. es->apu_mode[1] = 0;
  1366. es->apu_mode[2] = 0;
  1367. es->apu_mode[3] = 0;
  1368. es->running = 0;
  1369. es->substream = substream;
  1370. es->mode = ESM_MODE_CAPTURE;
  1371. /* get mixbuffer */
  1372. if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
  1373. snd_es1968_free_apu_pair(chip, apu1);
  1374. snd_es1968_free_apu_pair(chip, apu2);
  1375. kfree(es);
  1376. return -ENOMEM;
  1377. }
  1378. memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
  1379. runtime->private_data = es;
  1380. runtime->hw = snd_es1968_capture;
  1381. runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
  1382. calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
  1383. #if 0
  1384. snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
  1385. 1024);
  1386. #endif
  1387. spin_lock_irq(&chip->substream_lock);
  1388. list_add(&es->list, &chip->substream_list);
  1389. spin_unlock_irq(&chip->substream_lock);
  1390. return 0;
  1391. }
  1392. static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
  1393. {
  1394. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1395. struct esschan *es;
  1396. if (substream->runtime->private_data == NULL)
  1397. return 0;
  1398. es = substream->runtime->private_data;
  1399. spin_lock_irq(&chip->substream_lock);
  1400. list_del(&es->list);
  1401. spin_unlock_irq(&chip->substream_lock);
  1402. snd_es1968_free_apu_pair(chip, es->apu[0]);
  1403. kfree(es);
  1404. return 0;
  1405. }
  1406. static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
  1407. {
  1408. struct es1968 *chip = snd_pcm_substream_chip(substream);
  1409. struct esschan *es;
  1410. if (substream->runtime->private_data == NULL)
  1411. return 0;
  1412. es = substream->runtime->private_data;
  1413. spin_lock_irq(&chip->substream_lock);
  1414. list_del(&es->list);
  1415. spin_unlock_irq(&chip->substream_lock);
  1416. snd_es1968_free_memory(chip, es->mixbuf);
  1417. snd_es1968_free_apu_pair(chip, es->apu[0]);
  1418. snd_es1968_free_apu_pair(chip, es->apu[2]);
  1419. kfree(es);
  1420. return 0;
  1421. }
  1422. static struct snd_pcm_ops snd_es1968_playback_ops = {
  1423. .open = snd_es1968_playback_open,
  1424. .close = snd_es1968_playback_close,
  1425. .ioctl = snd_pcm_lib_ioctl,
  1426. .hw_params = snd_es1968_hw_params,
  1427. .hw_free = snd_es1968_hw_free,
  1428. .prepare = snd_es1968_pcm_prepare,
  1429. .trigger = snd_es1968_pcm_trigger,
  1430. .pointer = snd_es1968_pcm_pointer,
  1431. };
  1432. static struct snd_pcm_ops snd_es1968_capture_ops = {
  1433. .open = snd_es1968_capture_open,
  1434. .close = snd_es1968_capture_close,
  1435. .ioctl = snd_pcm_lib_ioctl,
  1436. .hw_params = snd_es1968_hw_params,
  1437. .hw_free = snd_es1968_hw_free,
  1438. .prepare = snd_es1968_pcm_prepare,
  1439. .trigger = snd_es1968_pcm_trigger,
  1440. .pointer = snd_es1968_pcm_pointer,
  1441. };
  1442. /*
  1443. * measure clock
  1444. */
  1445. #define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
  1446. static void __devinit es1968_measure_clock(struct es1968 *chip)
  1447. {
  1448. int i, apu;
  1449. unsigned int pa, offset, t;
  1450. struct esm_memory *memory;
  1451. struct timeval start_time, stop_time;
  1452. if (chip->clock == 0)
  1453. chip->clock = 48000; /* default clock value */
  1454. /* search 2 APUs (although one apu is enough) */
  1455. if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
  1456. snd_printk(KERN_ERR "Hmm, cannot find empty APU pair!?\n");
  1457. return;
  1458. }
  1459. if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
  1460. snd_printk(KERN_ERR "cannot allocate dma buffer - using default clock %d\n", chip->clock);
  1461. snd_es1968_free_apu_pair(chip, apu);
  1462. return;
  1463. }
  1464. memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
  1465. wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
  1466. pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
  1467. pa |= 0x00400000; /* System RAM (Bit 22) */
  1468. /* initialize apu */
  1469. for (i = 0; i < 16; i++)
  1470. apu_set_register(chip, apu, i, 0x0000);
  1471. apu_set_register(chip, apu, 0, 0x400f);
  1472. apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
  1473. apu_set_register(chip, apu, 5, pa & 0xffff);
  1474. apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
  1475. apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
  1476. apu_set_register(chip, apu, 8, 0x0000);
  1477. apu_set_register(chip, apu, 9, 0xD000);
  1478. apu_set_register(chip, apu, 10, 0x8F08);
  1479. apu_set_register(chip, apu, 11, 0x0000);
  1480. spin_lock_irq(&chip->reg_lock);
  1481. outw(1, chip->io_port + 0x04); /* clear WP interrupts */
  1482. outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
  1483. spin_unlock_irq(&chip->reg_lock);
  1484. snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
  1485. chip->in_measurement = 1;
  1486. chip->measure_apu = apu;
  1487. spin_lock_irq(&chip->reg_lock);
  1488. snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
  1489. __apu_set_register(chip, apu, 5, pa & 0xffff);
  1490. snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
  1491. do_gettimeofday(&start_time);
  1492. spin_unlock_irq(&chip->reg_lock);
  1493. msleep(50);
  1494. spin_lock_irq(&chip->reg_lock);
  1495. offset = __apu_get_register(chip, apu, 5);
  1496. do_gettimeofday(&stop_time);
  1497. snd_es1968_trigger_apu(chip, apu, 0); /* stop */
  1498. snd_es1968_bob_dec(chip);
  1499. chip->in_measurement = 0;
  1500. spin_unlock_irq(&chip->reg_lock);
  1501. /* check the current position */
  1502. offset -= (pa & 0xffff);
  1503. offset &= 0xfffe;
  1504. offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
  1505. t = stop_time.tv_sec - start_time.tv_sec;
  1506. t *= 1000000;
  1507. if (stop_time.tv_usec < start_time.tv_usec)
  1508. t -= start_time.tv_usec - stop_time.tv_usec;
  1509. else
  1510. t += stop_time.tv_usec - start_time.tv_usec;
  1511. if (t == 0) {
  1512. snd_printk(KERN_ERR "?? calculation error..\n");
  1513. } else {
  1514. offset *= 1000;
  1515. offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
  1516. if (offset < 47500 || offset > 48500) {
  1517. if (offset >= 40000 && offset <= 50000)
  1518. chip->clock = (chip->clock * offset) / 48000;
  1519. }
  1520. printk(KERN_INFO "es1968: clocking to %d\n", chip->clock);
  1521. }
  1522. snd_es1968_free_memory(chip, memory);
  1523. snd_es1968_free_apu_pair(chip, apu);
  1524. }
  1525. /*
  1526. */
  1527. static void snd_es1968_pcm_free(struct snd_pcm *pcm)
  1528. {
  1529. struct es1968 *esm = pcm->private_data;
  1530. snd_es1968_free_dmabuf(esm);
  1531. esm->pcm = NULL;
  1532. }
  1533. static int __devinit
  1534. snd_es1968_pcm(struct es1968 *chip, int device)
  1535. {
  1536. struct snd_pcm *pcm;
  1537. int err;
  1538. /* get DMA buffer */
  1539. if ((err = snd_es1968_init_dmabuf(chip)) < 0)
  1540. return err;
  1541. /* set PCMBAR */
  1542. wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
  1543. wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
  1544. wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
  1545. wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
  1546. if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
  1547. chip->playback_streams,
  1548. chip->capture_streams, &pcm)) < 0)
  1549. return err;
  1550. pcm->private_data = chip;
  1551. pcm->private_free = snd_es1968_pcm_free;
  1552. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
  1553. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
  1554. pcm->info_flags = 0;
  1555. strcpy(pcm->name, "ESS Maestro");
  1556. chip->pcm = pcm;
  1557. return 0;
  1558. }
  1559. /*
  1560. * update pointer
  1561. */
  1562. static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
  1563. {
  1564. unsigned int hwptr;
  1565. unsigned int diff;
  1566. struct snd_pcm_substream *subs = es->substream;
  1567. if (subs == NULL || !es->running)
  1568. return;
  1569. hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
  1570. hwptr %= es->dma_size;
  1571. diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
  1572. es->hwptr = hwptr;
  1573. es->count += diff;
  1574. if (es->count > es->frag_size) {
  1575. spin_unlock(&chip->substream_lock);
  1576. snd_pcm_period_elapsed(subs);
  1577. spin_lock(&chip->substream_lock);
  1578. es->count %= es->frag_size;
  1579. }
  1580. }
  1581. /*
  1582. */
  1583. static void es1968_update_hw_volume(unsigned long private_data)
  1584. {
  1585. struct es1968 *chip = (struct es1968 *) private_data;
  1586. int x, val;
  1587. unsigned long flags;
  1588. /* Figure out which volume control button was pushed,
  1589. based on differences from the default register
  1590. values. */
  1591. x = inb(chip->io_port + 0x1c) & 0xee;
  1592. /* Reset the volume control registers. */
  1593. outb(0x88, chip->io_port + 0x1c);
  1594. outb(0x88, chip->io_port + 0x1d);
  1595. outb(0x88, chip->io_port + 0x1e);
  1596. outb(0x88, chip->io_port + 0x1f);
  1597. if (chip->in_suspend)
  1598. return;
  1599. if (! chip->master_switch || ! chip->master_volume)
  1600. return;
  1601. /* FIXME: we can't call snd_ac97_* functions since here is in tasklet. */
  1602. spin_lock_irqsave(&chip->ac97_lock, flags);
  1603. val = chip->ac97->regs[AC97_MASTER];
  1604. switch (x) {
  1605. case 0x88:
  1606. /* mute */
  1607. val ^= 0x8000;
  1608. chip->ac97->regs[AC97_MASTER] = val;
  1609. outw(val, chip->io_port + ESM_AC97_DATA);
  1610. outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
  1611. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1612. &chip->master_switch->id);
  1613. break;
  1614. case 0xaa:
  1615. /* volume up */
  1616. if ((val & 0x7f) > 0)
  1617. val--;
  1618. if ((val & 0x7f00) > 0)
  1619. val -= 0x0100;
  1620. chip->ac97->regs[AC97_MASTER] = val;
  1621. outw(val, chip->io_port + ESM_AC97_DATA);
  1622. outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
  1623. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1624. &chip->master_volume->id);
  1625. break;
  1626. case 0x66:
  1627. /* volume down */
  1628. if ((val & 0x7f) < 0x1f)
  1629. val++;
  1630. if ((val & 0x7f00) < 0x1f00)
  1631. val += 0x0100;
  1632. chip->ac97->regs[AC97_MASTER] = val;
  1633. outw(val, chip->io_port + ESM_AC97_DATA);
  1634. outb(AC97_MASTER, chip->io_port + ESM_AC97_INDEX);
  1635. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  1636. &chip->master_volume->id);
  1637. break;
  1638. }
  1639. spin_unlock_irqrestore(&chip->ac97_lock, flags);
  1640. }
  1641. /*
  1642. * interrupt handler
  1643. */
  1644. static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
  1645. {
  1646. struct es1968 *chip = dev_id;
  1647. u32 event;
  1648. if (!(event = inb(chip->io_port + 0x1A)))
  1649. return IRQ_NONE;
  1650. outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
  1651. if (event & ESM_HWVOL_IRQ)
  1652. tasklet_hi_schedule(&chip->hwvol_tq); /* we'll do this later */
  1653. /* else ack 'em all, i imagine */
  1654. outb(0xFF, chip->io_port + 0x1A);
  1655. if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
  1656. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1657. }
  1658. if (event & ESM_SOUND_IRQ) {
  1659. struct list_head *p;
  1660. spin_lock(&chip->substream_lock);
  1661. list_for_each(p, &chip->substream_list) {
  1662. struct esschan *es = list_entry(p, struct esschan, list);
  1663. if (es->running)
  1664. snd_es1968_update_pcm(chip, es);
  1665. }
  1666. spin_unlock(&chip->substream_lock);
  1667. if (chip->in_measurement) {
  1668. unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
  1669. if (curp < chip->measure_lastpos)
  1670. chip->measure_count++;
  1671. chip->measure_lastpos = curp;
  1672. }
  1673. }
  1674. return IRQ_HANDLED;
  1675. }
  1676. /*
  1677. * Mixer stuff
  1678. */
  1679. static int __devinit
  1680. snd_es1968_mixer(struct es1968 *chip)
  1681. {
  1682. struct snd_ac97_bus *pbus;
  1683. struct snd_ac97_template ac97;
  1684. struct snd_ctl_elem_id id;
  1685. int err;
  1686. static struct snd_ac97_bus_ops ops = {
  1687. .write = snd_es1968_ac97_write,
  1688. .read = snd_es1968_ac97_read,
  1689. };
  1690. if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
  1691. return err;
  1692. pbus->no_vra = 1; /* ES1968 doesn't need VRA */
  1693. memset(&ac97, 0, sizeof(ac97));
  1694. ac97.private_data = chip;
  1695. if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
  1696. return err;
  1697. /* attach master switch / volumes for h/w volume control */
  1698. memset(&id, 0, sizeof(id));
  1699. id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1700. strcpy(id.name, "Master Playback Switch");
  1701. chip->master_switch = snd_ctl_find_id(chip->card, &id);
  1702. memset(&id, 0, sizeof(id));
  1703. id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  1704. strcpy(id.name, "Master Playback Volume");
  1705. chip->master_volume = snd_ctl_find_id(chip->card, &id);
  1706. return 0;
  1707. }
  1708. /*
  1709. * reset ac97 codec
  1710. */
  1711. static void snd_es1968_ac97_reset(struct es1968 *chip)
  1712. {
  1713. unsigned long ioaddr = chip->io_port;
  1714. unsigned short save_ringbus_a;
  1715. unsigned short save_68;
  1716. unsigned short w;
  1717. unsigned int vend;
  1718. /* save configuration */
  1719. save_ringbus_a = inw(ioaddr + 0x36);
  1720. //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
  1721. /* set command/status address i/o to 1st codec */
  1722. outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
  1723. outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
  1724. /* disable ac link */
  1725. outw(0x0000, ioaddr + 0x36);
  1726. save_68 = inw(ioaddr + 0x68);
  1727. pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
  1728. pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
  1729. if (w & 1)
  1730. save_68 |= 0x10;
  1731. outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
  1732. outw(0x0001, ioaddr + 0x68); /* gpio write */
  1733. outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
  1734. udelay(20);
  1735. outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
  1736. msleep(20);
  1737. outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
  1738. outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
  1739. outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
  1740. outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
  1741. /* now the second codec */
  1742. /* disable ac link */
  1743. outw(0x0000, ioaddr + 0x36);
  1744. outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
  1745. save_68 = inw(ioaddr + 0x68);
  1746. outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
  1747. outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
  1748. udelay(20);
  1749. outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
  1750. msleep(500);
  1751. //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
  1752. outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
  1753. outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
  1754. #if 0 /* the loop here needs to be much better if we want it.. */
  1755. snd_printk(KERN_INFO "trying software reset\n");
  1756. /* try and do a software reset */
  1757. outb(0x80 | 0x7c, ioaddr + 0x30);
  1758. for (w = 0;; w++) {
  1759. if ((inw(ioaddr + 0x30) & 1) == 0) {
  1760. if (inb(ioaddr + 0x32) != 0)
  1761. break;
  1762. outb(0x80 | 0x7d, ioaddr + 0x30);
  1763. if (((inw(ioaddr + 0x30) & 1) == 0)
  1764. && (inb(ioaddr + 0x32) != 0))
  1765. break;
  1766. outb(0x80 | 0x7f, ioaddr + 0x30);
  1767. if (((inw(ioaddr + 0x30) & 1) == 0)
  1768. && (inb(ioaddr + 0x32) != 0))
  1769. break;
  1770. }
  1771. if (w > 10000) {
  1772. outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
  1773. msleep(500); /* oh my.. */
  1774. outb(inb(ioaddr + 0x37) & ~0x08,
  1775. ioaddr + 0x37);
  1776. udelay(1);
  1777. outw(0x80, ioaddr + 0x30);
  1778. for (w = 0; w < 10000; w++) {
  1779. if ((inw(ioaddr + 0x30) & 1) == 0)
  1780. break;
  1781. }
  1782. }
  1783. }
  1784. #endif
  1785. if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
  1786. /* turn on external amp? */
  1787. outw(0xf9ff, ioaddr + 0x64);
  1788. outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
  1789. outw(0x0209, ioaddr + 0x60);
  1790. }
  1791. /* restore.. */
  1792. outw(save_ringbus_a, ioaddr + 0x36);
  1793. /* Turn on the 978 docking chip.
  1794. First frob the "master output enable" bit,
  1795. then set most of the playback volume control registers to max. */
  1796. outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
  1797. outb(0xff, ioaddr+0xc3);
  1798. outb(0xff, ioaddr+0xc4);
  1799. outb(0xff, ioaddr+0xc6);
  1800. outb(0xff, ioaddr+0xc8);
  1801. outb(0x3f, ioaddr+0xcf);
  1802. outb(0x3f, ioaddr+0xd0);
  1803. }
  1804. static void snd_es1968_reset(struct es1968 *chip)
  1805. {
  1806. /* Reset */
  1807. outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
  1808. chip->io_port + ESM_PORT_HOST_IRQ);
  1809. udelay(10);
  1810. outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
  1811. udelay(10);
  1812. }
  1813. /*
  1814. * initialize maestro chip
  1815. */
  1816. static void snd_es1968_chip_init(struct es1968 *chip)
  1817. {
  1818. struct pci_dev *pci = chip->pci;
  1819. int i;
  1820. unsigned long iobase = chip->io_port;
  1821. u16 w;
  1822. u32 n;
  1823. /* We used to muck around with pci config space that
  1824. * we had no business messing with. We don't know enough
  1825. * about the machine to know which DMA mode is appropriate,
  1826. * etc. We were guessing wrong on some machines and making
  1827. * them unhappy. We now trust in the BIOS to do things right,
  1828. * which almost certainly means a new host of problems will
  1829. * arise with broken BIOS implementations. screw 'em.
  1830. * We're already intolerant of machines that don't assign
  1831. * IRQs.
  1832. */
  1833. /* Config Reg A */
  1834. pci_read_config_word(pci, ESM_CONFIG_A, &w);
  1835. w &= ~DMA_CLEAR; /* Clear DMA bits */
  1836. w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
  1837. w &= ~SAFEGUARD; /* Safeguard off */
  1838. w |= POST_WRITE; /* Posted write */
  1839. w |= PCI_TIMING; /* PCI timing on */
  1840. /* XXX huh? claims to be reserved.. */
  1841. w &= ~SWAP_LR; /* swap left/right
  1842. seems to only have effect on SB
  1843. Emulation */
  1844. w &= ~SUBTR_DECODE; /* Subtractive decode off */
  1845. pci_write_config_word(pci, ESM_CONFIG_A, w);
  1846. /* Config Reg B */
  1847. pci_read_config_word(pci, ESM_CONFIG_B, &w);
  1848. w &= ~(1 << 15); /* Turn off internal clock multiplier */
  1849. /* XXX how do we know which to use? */
  1850. w &= ~(1 << 14); /* External clock */
  1851. w &= ~SPDIF_CONFB; /* disable S/PDIF output */
  1852. w |= HWV_CONFB; /* HWV on */
  1853. w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
  1854. w &= ~GPIO_CONFB; /* GPIO 4:5 */
  1855. w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
  1856. w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
  1857. w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
  1858. w &= ~(1 << 1); /* reserved, always write 0 */
  1859. w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
  1860. pci_write_config_word(pci, ESM_CONFIG_B, w);
  1861. /* DDMA off */
  1862. pci_read_config_word(pci, ESM_DDMA, &w);
  1863. w &= ~(1 << 0);
  1864. pci_write_config_word(pci, ESM_DDMA, w);
  1865. /*
  1866. * Legacy mode
  1867. */
  1868. pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
  1869. w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
  1870. w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
  1871. w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
  1872. pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
  1873. /* Set up 978 docking control chip. */
  1874. pci_read_config_word(pci, 0x58, &w);
  1875. w|=1<<2; /* Enable 978. */
  1876. w|=1<<3; /* Turn on 978 hardware volume control. */
  1877. w&=~(1<<11); /* Turn on 978 mixer volume control. */
  1878. pci_write_config_word(pci, 0x58, w);
  1879. /* Sound Reset */
  1880. snd_es1968_reset(chip);
  1881. /*
  1882. * Ring Bus Setup
  1883. */
  1884. /* setup usual 0x34 stuff.. 0x36 may be chip specific */
  1885. outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
  1886. udelay(20);
  1887. outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
  1888. udelay(20);
  1889. /*
  1890. * Reset the CODEC
  1891. */
  1892. snd_es1968_ac97_reset(chip);
  1893. /* Ring Bus Control B */
  1894. n = inl(iobase + ESM_RING_BUS_CONTR_B);
  1895. n &= ~RINGB_EN_SPDIF; /* SPDIF off */
  1896. //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
  1897. outl(n, iobase + ESM_RING_BUS_CONTR_B);
  1898. /* Set hardware volume control registers to midpoints.
  1899. We can tell which button was pushed based on how they change. */
  1900. outb(0x88, iobase+0x1c);
  1901. outb(0x88, iobase+0x1d);
  1902. outb(0x88, iobase+0x1e);
  1903. outb(0x88, iobase+0x1f);
  1904. /* it appears some maestros (dell 7500) only work if these are set,
  1905. regardless of wether we use the assp or not. */
  1906. outb(0, iobase + ASSP_CONTROL_B);
  1907. outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
  1908. outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
  1909. /*
  1910. * set up wavecache
  1911. */
  1912. for (i = 0; i < 16; i++) {
  1913. /* Write 0 into the buffer area 0x1E0->1EF */
  1914. outw(0x01E0 + i, iobase + WC_INDEX);
  1915. outw(0x0000, iobase + WC_DATA);
  1916. /* The 1.10 test program seem to write 0 into the buffer area
  1917. * 0x1D0-0x1DF too.*/
  1918. outw(0x01D0 + i, iobase + WC_INDEX);
  1919. outw(0x0000, iobase + WC_DATA);
  1920. }
  1921. wave_set_register(chip, IDR7_WAVE_ROMRAM,
  1922. (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
  1923. wave_set_register(chip, IDR7_WAVE_ROMRAM,
  1924. wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
  1925. wave_set_register(chip, IDR7_WAVE_ROMRAM,
  1926. wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
  1927. wave_set_register(chip, IDR7_WAVE_ROMRAM,
  1928. wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
  1929. maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
  1930. /* Now back to the DirectSound stuff */
  1931. /* audio serial configuration.. ? */
  1932. maestro_write(chip, 0x08, 0xB004);
  1933. maestro_write(chip, 0x09, 0x001B);
  1934. maestro_write(chip, 0x0A, 0x8000);
  1935. maestro_write(chip, 0x0B, 0x3F37);
  1936. maestro_write(chip, 0x0C, 0x0098);
  1937. /* parallel in, has something to do with recording :) */
  1938. maestro_write(chip, 0x0C,
  1939. (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
  1940. /* parallel out */
  1941. maestro_write(chip, 0x0C,
  1942. (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
  1943. maestro_write(chip, 0x0D, 0x7632);
  1944. /* Wave cache control on - test off, sg off,
  1945. enable, enable extra chans 1Mb */
  1946. w = inw(iobase + WC_CONTROL);
  1947. w &= ~0xFA00; /* Seems to be reserved? I don't know */
  1948. w |= 0xA000; /* reserved... I don't know */
  1949. w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
  1950. Seems to crash the Computer if enabled... */
  1951. w |= 0x0100; /* Wave Cache Operation Enabled */
  1952. w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
  1953. w &= ~0x0060; /* Clear Wavtable Size */
  1954. w |= 0x0020; /* Wavetable Size : 1MB */
  1955. /* Bit 4 is reserved */
  1956. w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
  1957. /* Bit 1 is reserved */
  1958. w &= ~0x0001; /* Test Mode off */
  1959. outw(w, iobase + WC_CONTROL);
  1960. /* Now clear the APU control ram */
  1961. for (i = 0; i < NR_APUS; i++) {
  1962. for (w = 0; w < NR_APU_REGS; w++)
  1963. apu_set_register(chip, i, w, 0);
  1964. }
  1965. }
  1966. /* Enable IRQ's */
  1967. static void snd_es1968_start_irq(struct es1968 *chip)
  1968. {
  1969. unsigned short w;
  1970. w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
  1971. if (chip->rmidi)
  1972. w |= ESM_HIRQ_MPU401;
  1973. outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
  1974. }
  1975. #ifdef CONFIG_PM
  1976. /*
  1977. * PM support
  1978. */
  1979. static int es1968_suspend(struct pci_dev *pci, pm_message_t state)
  1980. {
  1981. struct snd_card *card = pci_get_drvdata(pci);
  1982. struct es1968 *chip = card->private_data;
  1983. if (! chip->do_pm)
  1984. return 0;
  1985. chip->in_suspend = 1;
  1986. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1987. snd_pcm_suspend_all(chip->pcm);
  1988. snd_ac97_suspend(chip->ac97);
  1989. snd_es1968_bob_stop(chip);
  1990. pci_disable_device(pci);
  1991. pci_save_state(pci);
  1992. pci_set_power_state(pci, pci_choose_state(pci, state));
  1993. return 0;
  1994. }
  1995. static int es1968_resume(struct pci_dev *pci)
  1996. {
  1997. struct snd_card *card = pci_get_drvdata(pci);
  1998. struct es1968 *chip = card->private_data;
  1999. struct list_head *p;
  2000. if (! chip->do_pm)
  2001. return 0;
  2002. /* restore all our config */
  2003. pci_set_power_state(pci, PCI_D0);
  2004. pci_restore_state(pci);
  2005. if (pci_enable_device(pci) < 0) {
  2006. printk(KERN_ERR "es1968: pci_enable_device failed, "
  2007. "disabling device\n");
  2008. snd_card_disconnect(card);
  2009. return -EIO;
  2010. }
  2011. pci_set_master(pci);
  2012. snd_es1968_chip_init(chip);
  2013. /* need to restore the base pointers.. */
  2014. if (chip->dma.addr) {
  2015. /* set PCMBAR */
  2016. wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
  2017. }
  2018. snd_es1968_start_irq(chip);
  2019. /* restore ac97 state */
  2020. snd_ac97_resume(chip->ac97);
  2021. list_for_each(p, &chip->substream_list) {
  2022. struct esschan *es = list_entry(p, struct esschan, list);
  2023. switch (es->mode) {
  2024. case ESM_MODE_PLAY:
  2025. snd_es1968_playback_setup(chip, es, es->substream->runtime);
  2026. break;
  2027. case ESM_MODE_CAPTURE:
  2028. snd_es1968_capture_setup(chip, es, es->substream->runtime);
  2029. break;
  2030. }
  2031. }
  2032. /* start timer again */
  2033. if (chip->bobclient)
  2034. snd_es1968_bob_start(chip);
  2035. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  2036. chip->in_suspend = 0;
  2037. return 0;
  2038. }
  2039. #endif /* CONFIG_PM */
  2040. #ifdef SUPPORT_JOYSTICK
  2041. #define JOYSTICK_ADDR 0x200
  2042. static int __devinit snd_es1968_create_gameport(struct es1968 *chip, int dev)
  2043. {
  2044. struct gameport *gp;
  2045. struct resource *r;
  2046. u16 val;
  2047. if (!joystick[dev])
  2048. return -ENODEV;
  2049. r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
  2050. if (!r)
  2051. return -EBUSY;
  2052. chip->gameport = gp = gameport_allocate_port();
  2053. if (!gp) {
  2054. printk(KERN_ERR "es1968: cannot allocate memory for gameport\n");
  2055. release_and_free_resource(r);
  2056. return -ENOMEM;
  2057. }
  2058. pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
  2059. pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
  2060. gameport_set_name(gp, "ES1968 Gameport");
  2061. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  2062. gameport_set_dev_parent(gp, &chip->pci->dev);
  2063. gp->io = JOYSTICK_ADDR;
  2064. gameport_set_port_data(gp, r);
  2065. gameport_register_port(gp);
  2066. return 0;
  2067. }
  2068. static void snd_es1968_free_gameport(struct es1968 *chip)
  2069. {
  2070. if (chip->gameport) {
  2071. struct resource *r = gameport_get_port_data(chip->gameport);
  2072. gameport_unregister_port(chip->gameport);
  2073. chip->gameport = NULL;
  2074. release_and_free_resource(r);
  2075. }
  2076. }
  2077. #else
  2078. static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
  2079. static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
  2080. #endif
  2081. static int snd_es1968_free(struct es1968 *chip)
  2082. {
  2083. if (chip->io_port) {
  2084. synchronize_irq(chip->irq);
  2085. outw(1, chip->io_port + 0x04); /* clear WP interrupts */
  2086. outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
  2087. }
  2088. if (chip->irq >= 0)
  2089. free_irq(chip->irq, chip);
  2090. snd_es1968_free_gameport(chip);
  2091. chip->master_switch = NULL;
  2092. chip->master_volume = NULL;
  2093. pci_release_regions(chip->pci);
  2094. pci_disable_device(chip->pci);
  2095. kfree(chip);
  2096. return 0;
  2097. }
  2098. static int snd_es1968_dev_free(struct snd_device *device)
  2099. {
  2100. struct es1968 *chip = device->device_data;
  2101. return snd_es1968_free(chip);
  2102. }
  2103. struct ess_device_list {
  2104. unsigned short type; /* chip type */
  2105. unsigned short vendor; /* subsystem vendor id */
  2106. };
  2107. static struct ess_device_list pm_whitelist[] __devinitdata = {
  2108. { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
  2109. { TYPE_MAESTRO2E, 0x1028 },
  2110. { TYPE_MAESTRO2E, 0x103c },
  2111. { TYPE_MAESTRO2E, 0x1179 },
  2112. { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
  2113. { TYPE_MAESTRO2E, 0x1558 },
  2114. };
  2115. static struct ess_device_list mpu_blacklist[] __devinitdata = {
  2116. { TYPE_MAESTRO2, 0x125d },
  2117. };
  2118. static int __devinit snd_es1968_create(struct snd_card *card,
  2119. struct pci_dev *pci,
  2120. int total_bufsize,
  2121. int play_streams,
  2122. int capt_streams,
  2123. int chip_type,
  2124. int do_pm,
  2125. struct es1968 **chip_ret)
  2126. {
  2127. static struct snd_device_ops ops = {
  2128. .dev_free = snd_es1968_dev_free,
  2129. };
  2130. struct es1968 *chip;
  2131. int i, err;
  2132. *chip_ret = NULL;
  2133. /* enable PCI device */
  2134. if ((err = pci_enable_device(pci)) < 0)
  2135. return err;
  2136. /* check, if we can restrict PCI DMA transfers to 28 bits */
  2137. if (pci_set_dma_mask(pci, DMA_28BIT_MASK) < 0 ||
  2138. pci_set_consistent_dma_mask(pci, DMA_28BIT_MASK) < 0) {
  2139. snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n");
  2140. pci_disable_device(pci);
  2141. return -ENXIO;
  2142. }
  2143. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  2144. if (! chip) {
  2145. pci_disable_device(pci);
  2146. return -ENOMEM;
  2147. }
  2148. /* Set Vars */
  2149. chip->type = chip_type;
  2150. spin_lock_init(&chip->reg_lock);
  2151. spin_lock_init(&chip->substream_lock);
  2152. INIT_LIST_HEAD(&chip->buf_list);
  2153. INIT_LIST_HEAD(&chip->substream_list);
  2154. spin_lock_init(&chip->ac97_lock);
  2155. mutex_init(&chip->memory_mutex);
  2156. tasklet_init(&chip->hwvol_tq, es1968_update_hw_volume, (unsigned long)chip);
  2157. chip->card = card;
  2158. chip->pci = pci;
  2159. chip->irq = -1;
  2160. chip->total_bufsize = total_bufsize; /* in bytes */
  2161. chip->playback_streams = play_streams;
  2162. chip->capture_streams = capt_streams;
  2163. if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
  2164. kfree(chip);
  2165. pci_disable_device(pci);
  2166. return err;
  2167. }
  2168. chip->io_port = pci_resource_start(pci, 0);
  2169. if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
  2170. "ESS Maestro", chip)) {
  2171. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  2172. snd_es1968_free(chip);
  2173. return -EBUSY;
  2174. }
  2175. chip->irq = pci->irq;
  2176. /* Clear Maestro_map */
  2177. for (i = 0; i < 32; i++)
  2178. chip->maestro_map[i] = 0;
  2179. /* Clear Apu Map */
  2180. for (i = 0; i < NR_APUS; i++)
  2181. chip->apu[i] = ESM_APU_FREE;
  2182. /* just to be sure */
  2183. pci_set_master(pci);
  2184. if (do_pm > 1) {
  2185. /* disable power-management if not on the whitelist */
  2186. unsigned short vend;
  2187. pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
  2188. for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
  2189. if (chip->type == pm_whitelist[i].type &&
  2190. vend == pm_whitelist[i].vendor) {
  2191. do_pm = 1;
  2192. break;
  2193. }
  2194. }
  2195. if (do_pm > 1) {
  2196. /* not matched; disabling pm */
  2197. printk(KERN_INFO "es1968: not attempting power management.\n");
  2198. do_pm = 0;
  2199. }
  2200. }
  2201. chip->do_pm = do_pm;
  2202. snd_es1968_chip_init(chip);
  2203. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  2204. snd_es1968_free(chip);
  2205. return err;
  2206. }
  2207. snd_card_set_dev(card, &pci->dev);
  2208. *chip_ret = chip;
  2209. return 0;
  2210. }
  2211. /*
  2212. */
  2213. static int __devinit snd_es1968_probe(struct pci_dev *pci,
  2214. const struct pci_device_id *pci_id)
  2215. {
  2216. static int dev;
  2217. struct snd_card *card;
  2218. struct es1968 *chip;
  2219. unsigned int i;
  2220. int err;
  2221. if (dev >= SNDRV_CARDS)
  2222. return -ENODEV;
  2223. if (!enable[dev]) {
  2224. dev++;
  2225. return -ENOENT;
  2226. }
  2227. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
  2228. if (!card)
  2229. return -ENOMEM;
  2230. if (total_bufsize[dev] < 128)
  2231. total_bufsize[dev] = 128;
  2232. if (total_bufsize[dev] > 4096)
  2233. total_bufsize[dev] = 4096;
  2234. if ((err = snd_es1968_create(card, pci,
  2235. total_bufsize[dev] * 1024, /* in bytes */
  2236. pcm_substreams_p[dev],
  2237. pcm_substreams_c[dev],
  2238. pci_id->driver_data,
  2239. use_pm[dev],
  2240. &chip)) < 0) {
  2241. snd_card_free(card);
  2242. return err;
  2243. }
  2244. card->private_data = chip;
  2245. switch (chip->type) {
  2246. case TYPE_MAESTRO2E:
  2247. strcpy(card->driver, "ES1978");
  2248. strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
  2249. break;
  2250. case TYPE_MAESTRO2:
  2251. strcpy(card->driver, "ES1968");
  2252. strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
  2253. break;
  2254. case TYPE_MAESTRO:
  2255. strcpy(card->driver, "ESM1");
  2256. strcpy(card->shortname, "ESS Maestro 1");
  2257. break;
  2258. }
  2259. if ((err = snd_es1968_pcm(chip, 0)) < 0) {
  2260. snd_card_free(card);
  2261. return err;
  2262. }
  2263. if ((err = snd_es1968_mixer(chip)) < 0) {
  2264. snd_card_free(card);
  2265. return err;
  2266. }
  2267. if (enable_mpu[dev] == 2) {
  2268. /* check the black list */
  2269. unsigned short vend;
  2270. pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
  2271. for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
  2272. if (chip->type == mpu_blacklist[i].type &&
  2273. vend == mpu_blacklist[i].vendor) {
  2274. enable_mpu[dev] = 0;
  2275. break;
  2276. }
  2277. }
  2278. }
  2279. if (enable_mpu[dev]) {
  2280. if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
  2281. chip->io_port + ESM_MPU401_PORT,
  2282. MPU401_INFO_INTEGRATED,
  2283. chip->irq, 0, &chip->rmidi)) < 0) {
  2284. printk(KERN_WARNING "es1968: skipping MPU-401 MIDI support..\n");
  2285. }
  2286. }
  2287. snd_es1968_create_gameport(chip, dev);
  2288. snd_es1968_start_irq(chip);
  2289. chip->clock = clock[dev];
  2290. if (! chip->clock)
  2291. es1968_measure_clock(chip);
  2292. sprintf(card->longname, "%s at 0x%lx, irq %i",
  2293. card->shortname, chip->io_port, chip->irq);
  2294. if ((err = snd_card_register(card)) < 0) {
  2295. snd_card_free(card);
  2296. return err;
  2297. }
  2298. pci_set_drvdata(pci, card);
  2299. dev++;
  2300. return 0;
  2301. }
  2302. static void __devexit snd_es1968_remove(struct pci_dev *pci)
  2303. {
  2304. snd_card_free(pci_get_drvdata(pci));
  2305. pci_set_drvdata(pci, NULL);
  2306. }
  2307. static struct pci_driver driver = {
  2308. .name = "ES1968 (ESS Maestro)",
  2309. .id_table = snd_es1968_ids,
  2310. .probe = snd_es1968_probe,
  2311. .remove = __devexit_p(snd_es1968_remove),
  2312. #ifdef CONFIG_PM
  2313. .suspend = es1968_suspend,
  2314. .resume = es1968_resume,
  2315. #endif
  2316. };
  2317. static int __init alsa_card_es1968_init(void)
  2318. {
  2319. return pci_register_driver(&driver);
  2320. }
  2321. static void __exit alsa_card_es1968_exit(void)
  2322. {
  2323. pci_unregister_driver(&driver);
  2324. }
  2325. module_init(alsa_card_es1968_init)
  2326. module_exit(alsa_card_es1968_exit)