dsp_spos_scb_lib.c 48 KB

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  1. /*
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. *
  17. */
  18. /*
  19. * 2002-07 Benny Sjostrand benny@hostmobility.com
  20. */
  21. #include <sound/driver.h>
  22. #include <asm/io.h>
  23. #include <linux/delay.h>
  24. #include <linux/pci.h>
  25. #include <linux/pm.h>
  26. #include <linux/init.h>
  27. #include <linux/slab.h>
  28. #include <linux/mutex.h>
  29. #include <sound/core.h>
  30. #include <sound/control.h>
  31. #include <sound/info.h>
  32. #include <sound/cs46xx.h>
  33. #include "cs46xx_lib.h"
  34. #include "dsp_spos.h"
  35. struct proc_scb_info {
  36. struct dsp_scb_descriptor * scb_desc;
  37. struct snd_cs46xx *chip;
  38. };
  39. static void remove_symbol (struct snd_cs46xx * chip, struct dsp_symbol_entry * symbol)
  40. {
  41. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  42. int symbol_index = (int)(symbol - ins->symbol_table.symbols);
  43. snd_assert(ins->symbol_table.nsymbols > 0,return);
  44. snd_assert(symbol_index >= 0 && symbol_index < ins->symbol_table.nsymbols, return);
  45. ins->symbol_table.symbols[symbol_index].deleted = 1;
  46. if (symbol_index < ins->symbol_table.highest_frag_index) {
  47. ins->symbol_table.highest_frag_index = symbol_index;
  48. }
  49. if (symbol_index == ins->symbol_table.nsymbols - 1)
  50. ins->symbol_table.nsymbols --;
  51. if (ins->symbol_table.highest_frag_index > ins->symbol_table.nsymbols) {
  52. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  53. }
  54. }
  55. #ifdef CONFIG_PROC_FS
  56. static void cs46xx_dsp_proc_scb_info_read (struct snd_info_entry *entry,
  57. struct snd_info_buffer *buffer)
  58. {
  59. struct proc_scb_info * scb_info = entry->private_data;
  60. struct dsp_scb_descriptor * scb = scb_info->scb_desc;
  61. struct dsp_spos_instance * ins;
  62. struct snd_cs46xx *chip = scb_info->chip;
  63. int j,col;
  64. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  65. ins = chip->dsp_spos_instance;
  66. mutex_lock(&chip->spos_mutex);
  67. snd_iprintf(buffer,"%04x %s:\n",scb->address,scb->scb_name);
  68. for (col = 0,j = 0;j < 0x10; j++,col++) {
  69. if (col == 4) {
  70. snd_iprintf(buffer,"\n");
  71. col = 0;
  72. }
  73. snd_iprintf(buffer,"%08x ",readl(dst + (scb->address + j) * sizeof(u32)));
  74. }
  75. snd_iprintf(buffer,"\n");
  76. if (scb->parent_scb_ptr != NULL) {
  77. snd_iprintf(buffer,"parent [%s:%04x] ",
  78. scb->parent_scb_ptr->scb_name,
  79. scb->parent_scb_ptr->address);
  80. } else snd_iprintf(buffer,"parent [none] ");
  81. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  82. scb->sub_list_ptr->scb_name,
  83. scb->sub_list_ptr->address,
  84. scb->next_scb_ptr->scb_name,
  85. scb->next_scb_ptr->address,
  86. scb->task_entry->symbol_name,
  87. scb->task_entry->address);
  88. snd_iprintf(buffer,"index [%d] ref_count [%d]\n",scb->index,scb->ref_count);
  89. mutex_unlock(&chip->spos_mutex);
  90. }
  91. #endif
  92. static void _dsp_unlink_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  93. {
  94. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  95. unsigned long flags;
  96. if ( scb->parent_scb_ptr ) {
  97. /* unlink parent SCB */
  98. snd_assert ((scb->parent_scb_ptr->sub_list_ptr == scb ||
  99. scb->parent_scb_ptr->next_scb_ptr == scb),return);
  100. if (scb->parent_scb_ptr->sub_list_ptr == scb) {
  101. if (scb->next_scb_ptr == ins->the_null_scb) {
  102. /* last and only node in parent sublist */
  103. scb->parent_scb_ptr->sub_list_ptr = scb->sub_list_ptr;
  104. if (scb->sub_list_ptr != ins->the_null_scb) {
  105. scb->sub_list_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  106. }
  107. scb->sub_list_ptr = ins->the_null_scb;
  108. } else {
  109. /* first node in parent sublist */
  110. scb->parent_scb_ptr->sub_list_ptr = scb->next_scb_ptr;
  111. if (scb->next_scb_ptr != ins->the_null_scb) {
  112. /* update next node parent ptr. */
  113. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  114. }
  115. scb->next_scb_ptr = ins->the_null_scb;
  116. }
  117. } else {
  118. /* snd_assert ( (scb->sub_list_ptr == ins->the_null_scb), return); */
  119. scb->parent_scb_ptr->next_scb_ptr = scb->next_scb_ptr;
  120. if (scb->next_scb_ptr != ins->the_null_scb) {
  121. /* update next node parent ptr. */
  122. scb->next_scb_ptr->parent_scb_ptr = scb->parent_scb_ptr;
  123. }
  124. scb->next_scb_ptr = ins->the_null_scb;
  125. }
  126. spin_lock_irqsave(&chip->reg_lock, flags);
  127. /* update parent first entry in DSP RAM */
  128. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  129. /* then update entry in DSP RAM */
  130. cs46xx_dsp_spos_update_scb(chip,scb);
  131. scb->parent_scb_ptr = NULL;
  132. spin_unlock_irqrestore(&chip->reg_lock, flags);
  133. }
  134. }
  135. static void _dsp_clear_sample_buffer (struct snd_cs46xx *chip, u32 sample_buffer_addr,
  136. int dword_count)
  137. {
  138. void __iomem *dst = chip->region.idx[2].remap_addr + sample_buffer_addr;
  139. int i;
  140. for (i = 0; i < dword_count ; ++i ) {
  141. writel(0, dst);
  142. dst += 4;
  143. }
  144. }
  145. void cs46xx_dsp_remove_scb (struct snd_cs46xx *chip, struct dsp_scb_descriptor * scb)
  146. {
  147. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  148. unsigned long flags;
  149. /* check integrety */
  150. snd_assert ( (scb->index >= 0 &&
  151. scb->index < ins->nscb &&
  152. (ins->scbs + scb->index) == scb), return );
  153. #if 0
  154. /* can't remove a SCB with childs before
  155. removing childs first */
  156. snd_assert ( (scb->sub_list_ptr == ins->the_null_scb &&
  157. scb->next_scb_ptr == ins->the_null_scb),
  158. goto _end);
  159. #endif
  160. spin_lock_irqsave(&scb->lock, flags);
  161. _dsp_unlink_scb (chip,scb);
  162. spin_unlock_irqrestore(&scb->lock, flags);
  163. cs46xx_dsp_proc_free_scb_desc(scb);
  164. snd_assert (scb->scb_symbol != NULL, return );
  165. remove_symbol (chip,scb->scb_symbol);
  166. ins->scbs[scb->index].deleted = 1;
  167. if (scb->index < ins->scb_highest_frag_index)
  168. ins->scb_highest_frag_index = scb->index;
  169. if (scb->index == ins->nscb - 1) {
  170. ins->nscb --;
  171. }
  172. if (ins->scb_highest_frag_index > ins->nscb) {
  173. ins->scb_highest_frag_index = ins->nscb;
  174. }
  175. #if 0
  176. /* !!!! THIS IS A PIECE OF SHIT MADE BY ME !!! */
  177. for(i = scb->index + 1;i < ins->nscb; ++i) {
  178. ins->scbs[i - 1].index = i - 1;
  179. }
  180. #endif
  181. }
  182. #ifdef CONFIG_PROC_FS
  183. void cs46xx_dsp_proc_free_scb_desc (struct dsp_scb_descriptor * scb)
  184. {
  185. if (scb->proc_info) {
  186. struct proc_scb_info * scb_info = scb->proc_info->private_data;
  187. snd_printdd("cs46xx_dsp_proc_free_scb_desc: freeing %s\n",scb->scb_name);
  188. snd_info_free_entry(scb->proc_info);
  189. scb->proc_info = NULL;
  190. snd_assert (scb_info != NULL, return);
  191. kfree (scb_info);
  192. }
  193. }
  194. void cs46xx_dsp_proc_register_scb_desc (struct snd_cs46xx *chip,
  195. struct dsp_scb_descriptor * scb)
  196. {
  197. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  198. struct snd_info_entry * entry;
  199. struct proc_scb_info * scb_info;
  200. /* register to proc */
  201. if (ins->snd_card != NULL && ins->proc_dsp_dir != NULL &&
  202. scb->proc_info == NULL) {
  203. if ((entry = snd_info_create_card_entry(ins->snd_card, scb->scb_name,
  204. ins->proc_dsp_dir)) != NULL) {
  205. scb_info = kmalloc(sizeof(struct proc_scb_info), GFP_KERNEL);
  206. if (!scb_info) {
  207. snd_info_free_entry(entry);
  208. entry = NULL;
  209. goto out;
  210. }
  211. scb_info->chip = chip;
  212. scb_info->scb_desc = scb;
  213. entry->content = SNDRV_INFO_CONTENT_TEXT;
  214. entry->private_data = scb_info;
  215. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  216. entry->c.text.read = cs46xx_dsp_proc_scb_info_read;
  217. if (snd_info_register(entry) < 0) {
  218. snd_info_free_entry(entry);
  219. kfree (scb_info);
  220. entry = NULL;
  221. }
  222. }
  223. out:
  224. scb->proc_info = entry;
  225. }
  226. }
  227. #endif /* CONFIG_PROC_FS */
  228. static struct dsp_scb_descriptor *
  229. _dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest,
  230. struct dsp_symbol_entry * task_entry,
  231. struct dsp_scb_descriptor * parent_scb,
  232. int scb_child_type)
  233. {
  234. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  235. struct dsp_scb_descriptor * scb;
  236. unsigned long flags;
  237. snd_assert (ins->the_null_scb != NULL,return NULL);
  238. /* fill the data that will be wroten to DSP */
  239. scb_data[SCBsubListPtr] =
  240. (ins->the_null_scb->address << 0x10) | ins->the_null_scb->address;
  241. scb_data[SCBfuncEntryPtr] &= 0xFFFF0000;
  242. scb_data[SCBfuncEntryPtr] |= task_entry->address;
  243. snd_printdd("dsp_spos: creating SCB <%s>\n",name);
  244. scb = cs46xx_dsp_create_scb(chip,name,scb_data,dest);
  245. scb->sub_list_ptr = ins->the_null_scb;
  246. scb->next_scb_ptr = ins->the_null_scb;
  247. scb->parent_scb_ptr = parent_scb;
  248. scb->task_entry = task_entry;
  249. /* update parent SCB */
  250. if (scb->parent_scb_ptr) {
  251. #if 0
  252. printk ("scb->parent_scb_ptr = %s\n",scb->parent_scb_ptr->scb_name);
  253. printk ("scb->parent_scb_ptr->next_scb_ptr = %s\n",scb->parent_scb_ptr->next_scb_ptr->scb_name);
  254. printk ("scb->parent_scb_ptr->sub_list_ptr = %s\n",scb->parent_scb_ptr->sub_list_ptr->scb_name);
  255. #endif
  256. /* link to parent SCB */
  257. if (scb_child_type == SCB_ON_PARENT_NEXT_SCB) {
  258. snd_assert ( (scb->parent_scb_ptr->next_scb_ptr == ins->the_null_scb),
  259. return NULL);
  260. scb->parent_scb_ptr->next_scb_ptr = scb;
  261. } else if (scb_child_type == SCB_ON_PARENT_SUBLIST_SCB) {
  262. snd_assert ( (scb->parent_scb_ptr->sub_list_ptr == ins->the_null_scb),
  263. return NULL);
  264. scb->parent_scb_ptr->sub_list_ptr = scb;
  265. } else {
  266. snd_assert (0,return NULL);
  267. }
  268. spin_lock_irqsave(&chip->reg_lock, flags);
  269. /* update entry in DSP RAM */
  270. cs46xx_dsp_spos_update_scb(chip,scb->parent_scb_ptr);
  271. spin_unlock_irqrestore(&chip->reg_lock, flags);
  272. }
  273. cs46xx_dsp_proc_register_scb_desc (chip,scb);
  274. return scb;
  275. }
  276. static struct dsp_scb_descriptor *
  277. cs46xx_dsp_create_generic_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data,
  278. u32 dest, char * task_entry_name,
  279. struct dsp_scb_descriptor * parent_scb,
  280. int scb_child_type)
  281. {
  282. struct dsp_symbol_entry * task_entry;
  283. task_entry = cs46xx_dsp_lookup_symbol (chip,task_entry_name,
  284. SYMBOL_CODE);
  285. if (task_entry == NULL) {
  286. snd_printk (KERN_ERR "dsp_spos: symbol %s not found\n",task_entry_name);
  287. return NULL;
  288. }
  289. return _dsp_create_generic_scb (chip,name,scb_data,dest,task_entry,
  290. parent_scb,scb_child_type);
  291. }
  292. struct dsp_scb_descriptor *
  293. cs46xx_dsp_create_timing_master_scb (struct snd_cs46xx *chip)
  294. {
  295. struct dsp_scb_descriptor * scb;
  296. struct dsp_timing_master_scb timing_master_scb = {
  297. { 0,
  298. 0,
  299. 0,
  300. 0
  301. },
  302. { 0,
  303. 0,
  304. 0,
  305. 0,
  306. 0
  307. },
  308. 0,0,
  309. 0,NULL_SCB_ADDR,
  310. 0,0, /* extraSampleAccum:TMreserved */
  311. 0,0, /* codecFIFOptr:codecFIFOsyncd */
  312. 0x0001,0x8000, /* fracSampAccumQm1:TMfrmsLeftInGroup */
  313. 0x0001,0x0000, /* fracSampCorrectionQm1:TMfrmGroupLength */
  314. 0x00060000 /* nSampPerFrmQ15 */
  315. };
  316. scb = cs46xx_dsp_create_generic_scb(chip,"TimingMasterSCBInst",(u32 *)&timing_master_scb,
  317. TIMINGMASTER_SCB_ADDR,
  318. "TIMINGMASTER",NULL,SCB_NO_PARENT);
  319. return scb;
  320. }
  321. struct dsp_scb_descriptor *
  322. cs46xx_dsp_create_codec_out_scb(struct snd_cs46xx * chip, char * codec_name,
  323. u16 channel_disp, u16 fifo_addr, u16 child_scb_addr,
  324. u32 dest, struct dsp_scb_descriptor * parent_scb,
  325. int scb_child_type)
  326. {
  327. struct dsp_scb_descriptor * scb;
  328. struct dsp_codec_output_scb codec_out_scb = {
  329. { 0,
  330. 0,
  331. 0,
  332. 0
  333. },
  334. {
  335. 0,
  336. 0,
  337. 0,
  338. 0,
  339. 0
  340. },
  341. 0,0,
  342. 0,NULL_SCB_ADDR,
  343. 0, /* COstrmRsConfig */
  344. 0, /* COstrmBufPtr */
  345. channel_disp,fifo_addr, /* leftChanBaseIOaddr:rightChanIOdisp */
  346. 0x0000,0x0080, /* (!AC97!) COexpVolChangeRate:COscaleShiftCount */
  347. 0,child_scb_addr /* COreserved - need child scb to work with rom code */
  348. };
  349. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_out_scb,
  350. dest,"S16_CODECOUTPUTTASK",parent_scb,
  351. scb_child_type);
  352. return scb;
  353. }
  354. struct dsp_scb_descriptor *
  355. cs46xx_dsp_create_codec_in_scb(struct snd_cs46xx * chip, char * codec_name,
  356. u16 channel_disp, u16 fifo_addr, u16 sample_buffer_addr,
  357. u32 dest, struct dsp_scb_descriptor * parent_scb,
  358. int scb_child_type)
  359. {
  360. struct dsp_scb_descriptor * scb;
  361. struct dsp_codec_input_scb codec_input_scb = {
  362. { 0,
  363. 0,
  364. 0,
  365. 0
  366. },
  367. {
  368. 0,
  369. 0,
  370. 0,
  371. 0,
  372. 0
  373. },
  374. #if 0 /* cs4620 */
  375. SyncIOSCB,NULL_SCB_ADDR
  376. #else
  377. 0 , 0,
  378. #endif
  379. 0,0,
  380. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64, /* strmRsConfig */
  381. sample_buffer_addr << 0x10, /* strmBufPtr; defined as a dword ptr, used as a byte ptr */
  382. channel_disp,fifo_addr, /* (!AC97!) leftChanBaseINaddr=AC97primary
  383. link input slot 3 :rightChanINdisp=""slot 4 */
  384. 0x0000,0x0000, /* (!AC97!) ????:scaleShiftCount; no shift needed
  385. because AC97 is already 20 bits */
  386. 0x80008000 /* ??clw cwcgame.scb has 0 */
  387. };
  388. scb = cs46xx_dsp_create_generic_scb(chip,codec_name,(u32 *)&codec_input_scb,
  389. dest,"S16_CODECINPUTTASK",parent_scb,
  390. scb_child_type);
  391. return scb;
  392. }
  393. static struct dsp_scb_descriptor *
  394. cs46xx_dsp_create_pcm_reader_scb(struct snd_cs46xx * chip, char * scb_name,
  395. u16 sample_buffer_addr, u32 dest,
  396. int virtual_channel, u32 playback_hw_addr,
  397. struct dsp_scb_descriptor * parent_scb,
  398. int scb_child_type)
  399. {
  400. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  401. struct dsp_scb_descriptor * scb;
  402. struct dsp_generic_scb pcm_reader_scb = {
  403. /*
  404. Play DMA Task xfers data from host buffer to SP buffer
  405. init/runtime variables:
  406. PlayAC: Play Audio Data Conversion - SCB loc: 2nd dword, mask: 0x0000F000L
  407. DATA_FMT_16BIT_ST_LTLEND(0x00000000L) from 16-bit stereo, little-endian
  408. DATA_FMT_8_BIT_ST_SIGNED(0x00001000L) from 8-bit stereo, signed
  409. DATA_FMT_16BIT_MN_LTLEND(0x00002000L) from 16-bit mono, little-endian
  410. DATA_FMT_8_BIT_MN_SIGNED(0x00003000L) from 8-bit mono, signed
  411. DATA_FMT_16BIT_ST_BIGEND(0x00004000L) from 16-bit stereo, big-endian
  412. DATA_FMT_16BIT_MN_BIGEND(0x00006000L) from 16-bit mono, big-endian
  413. DATA_FMT_8_BIT_ST_UNSIGNED(0x00009000L) from 8-bit stereo, unsigned
  414. DATA_FMT_8_BIT_MN_UNSIGNED(0x0000b000L) from 8-bit mono, unsigned
  415. ? Other combinations possible from:
  416. DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000L
  417. DMA_RQ_C2_AC_NONE 0x00000000L
  418. DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000L
  419. DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000L
  420. DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000L
  421. DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000L
  422. HostBuffAddr: Host Buffer Physical Byte Address - SCB loc:3rd dword, Mask: 0xFFFFFFFFL
  423. aligned to dword boundary
  424. */
  425. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  426. { DMA_RQ_C1_SOURCE_ON_HOST + /* source buffer is on the host */
  427. DMA_RQ_C1_SOURCE_MOD1024 + /* source buffer is 1024 dwords (4096 bytes) */
  428. DMA_RQ_C1_DEST_MOD32 + /* dest buffer(PCMreaderBuf) is 32 dwords*/
  429. DMA_RQ_C1_WRITEBACK_SRC_FLAG + /* ?? */
  430. DMA_RQ_C1_WRITEBACK_DEST_FLAG + /* ?? */
  431. 15, /* DwordCount-1: picked 16 for DwordCount because Jim */
  432. /* Barnette said that is what we should use since */
  433. /* we are not running in optimized mode? */
  434. DMA_RQ_C2_AC_NONE +
  435. DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG + /* set play interrupt (bit0) in HISR when source */
  436. /* buffer (on host) crosses half-way point */
  437. virtual_channel, /* Play DMA channel arbitrarily set to 0 */
  438. playback_hw_addr, /* HostBuffAddr (source) */
  439. DMA_RQ_SD_SP_SAMPLE_ADDR + /* destination buffer is in SP Sample Memory */
  440. sample_buffer_addr /* SP Buffer Address (destination) */
  441. },
  442. /* Scatter/gather DMA requestor extension (5 ints) */
  443. {
  444. 0,
  445. 0,
  446. 0,
  447. 0,
  448. 0
  449. },
  450. /* Sublist pointer & next stream control block (SCB) link. */
  451. NULL_SCB_ADDR,NULL_SCB_ADDR,
  452. /* Pointer to this tasks parameter block & stream function pointer */
  453. 0,NULL_SCB_ADDR,
  454. /* rsConfig register for stream buffer (rsDMA reg. is loaded from basicReq.daw */
  455. /* for incoming streams, or basicReq.saw, for outgoing streams) */
  456. RSCONFIG_DMA_ENABLE + /* enable DMA */
  457. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) + /* MAX_DMA_SIZE picked to be 19 since SPUD */
  458. /* uses it for some reason */
  459. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) + /* stream number = SCBaddr/16 */
  460. RSCONFIG_SAMPLE_16STEREO +
  461. RSCONFIG_MODULO_32, /* dest buffer(PCMreaderBuf) is 32 dwords (256 bytes) */
  462. /* Stream sample pointer & MAC-unit mode for this stream */
  463. (sample_buffer_addr << 0x10),
  464. /* Fractional increment per output sample in the input sample buffer */
  465. 0,
  466. {
  467. /* Standard stereo volume control
  468. default muted */
  469. 0xffff,0xffff,
  470. 0xffff,0xffff
  471. }
  472. };
  473. if (ins->null_algorithm == NULL) {
  474. ins->null_algorithm = cs46xx_dsp_lookup_symbol (chip,"NULLALGORITHM",
  475. SYMBOL_CODE);
  476. if (ins->null_algorithm == NULL) {
  477. snd_printk (KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  478. return NULL;
  479. }
  480. }
  481. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_reader_scb,
  482. dest,ins->null_algorithm,parent_scb,
  483. scb_child_type);
  484. return scb;
  485. }
  486. #define GOF_PER_SEC 200
  487. struct dsp_scb_descriptor *
  488. cs46xx_dsp_create_src_task_scb(struct snd_cs46xx * chip, char * scb_name,
  489. int rate,
  490. u16 src_buffer_addr,
  491. u16 src_delay_buffer_addr, u32 dest,
  492. struct dsp_scb_descriptor * parent_scb,
  493. int scb_child_type,
  494. int pass_through)
  495. {
  496. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  497. struct dsp_scb_descriptor * scb;
  498. unsigned int tmp1, tmp2;
  499. unsigned int phiIncr;
  500. unsigned int correctionPerGOF, correctionPerSec;
  501. snd_printdd( "dsp_spos: setting %s rate to %u\n",scb_name,rate);
  502. /*
  503. * Compute the values used to drive the actual sample rate conversion.
  504. * The following formulas are being computed, using inline assembly
  505. * since we need to use 64 bit arithmetic to compute the values:
  506. *
  507. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  508. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  509. * GOF_PER_SEC)
  510. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  511. * GOF_PER_SEC * correctionPerGOF
  512. *
  513. * i.e.
  514. *
  515. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  516. * correctionPerGOF:correctionPerSec =
  517. * dividend:remainder(ulOther / GOF_PER_SEC)
  518. */
  519. tmp1 = rate << 16;
  520. phiIncr = tmp1 / 48000;
  521. tmp1 -= phiIncr * 48000;
  522. tmp1 <<= 10;
  523. phiIncr <<= 10;
  524. tmp2 = tmp1 / 48000;
  525. phiIncr += tmp2;
  526. tmp1 -= tmp2 * 48000;
  527. correctionPerGOF = tmp1 / GOF_PER_SEC;
  528. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  529. correctionPerSec = tmp1;
  530. {
  531. struct dsp_src_task_scb src_task_scb = {
  532. 0x0028,0x00c8,
  533. 0x5555,0x0000,
  534. 0x0000,0x0000,
  535. src_buffer_addr,1,
  536. correctionPerGOF,correctionPerSec,
  537. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  538. 0x0000,src_delay_buffer_addr,
  539. 0x0,
  540. 0x080,(src_delay_buffer_addr + (24 * 4)),
  541. 0,0, /* next_scb, sub_list_ptr */
  542. 0,0, /* entry, this_spb */
  543. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  544. src_buffer_addr << 0x10,
  545. phiIncr,
  546. {
  547. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left,
  548. 0xffff - ins->dac_volume_right,0xffff - ins->dac_volume_left
  549. }
  550. };
  551. if (ins->s16_up == NULL) {
  552. ins->s16_up = cs46xx_dsp_lookup_symbol (chip,"S16_UPSRC",
  553. SYMBOL_CODE);
  554. if (ins->s16_up == NULL) {
  555. snd_printk (KERN_ERR "dsp_spos: symbol S16_UPSRC not found\n");
  556. return NULL;
  557. }
  558. }
  559. /* clear buffers */
  560. _dsp_clear_sample_buffer (chip,src_buffer_addr,8);
  561. _dsp_clear_sample_buffer (chip,src_delay_buffer_addr,32);
  562. if (pass_through) {
  563. /* wont work with any other rate than
  564. the native DSP rate */
  565. snd_assert (rate == 48000);
  566. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  567. dest,"DMAREADER",parent_scb,
  568. scb_child_type);
  569. } else {
  570. scb = _dsp_create_generic_scb(chip,scb_name,(u32 *)&src_task_scb,
  571. dest,ins->s16_up,parent_scb,
  572. scb_child_type);
  573. }
  574. }
  575. return scb;
  576. }
  577. #if 0 /* not used */
  578. struct dsp_scb_descriptor *
  579. cs46xx_dsp_create_filter_scb(struct snd_cs46xx * chip, char * scb_name,
  580. u16 buffer_addr, u32 dest,
  581. struct dsp_scb_descriptor * parent_scb,
  582. int scb_child_type) {
  583. struct dsp_scb_descriptor * scb;
  584. struct dsp_filter_scb filter_scb = {
  585. .a0_right = 0x41a9,
  586. .a0_left = 0x41a9,
  587. .a1_right = 0xb8e4,
  588. .a1_left = 0xb8e4,
  589. .a2_right = 0x3e55,
  590. .a2_left = 0x3e55,
  591. .filter_unused3 = 0x0000,
  592. .filter_unused2 = 0x0000,
  593. .output_buf_ptr = buffer_addr,
  594. .init = 0x000,
  595. .prev_sample_output1 = 0x00000000,
  596. .prev_sample_output2 = 0x00000000,
  597. .prev_sample_input1 = 0x00000000,
  598. .prev_sample_input2 = 0x00000000,
  599. .next_scb_ptr = 0x0000,
  600. .sub_list_ptr = 0x0000,
  601. .entry_point = 0x0000,
  602. .spb_ptr = 0x0000,
  603. .b0_right = 0x0e38,
  604. .b0_left = 0x0e38,
  605. .b1_right = 0x1c71,
  606. .b1_left = 0x1c71,
  607. .b2_right = 0x0e38,
  608. .b2_left = 0x0e38,
  609. };
  610. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&filter_scb,
  611. dest,"FILTERTASK",parent_scb,
  612. scb_child_type);
  613. return scb;
  614. }
  615. #endif /* not used */
  616. struct dsp_scb_descriptor *
  617. cs46xx_dsp_create_mix_only_scb(struct snd_cs46xx * chip, char * scb_name,
  618. u16 mix_buffer_addr, u32 dest,
  619. struct dsp_scb_descriptor * parent_scb,
  620. int scb_child_type)
  621. {
  622. struct dsp_scb_descriptor * scb;
  623. struct dsp_mix_only_scb master_mix_scb = {
  624. /* 0 */ { 0,
  625. /* 1 */ 0,
  626. /* 2 */ mix_buffer_addr,
  627. /* 3 */ 0
  628. /* */ },
  629. {
  630. /* 4 */ 0,
  631. /* 5 */ 0,
  632. /* 6 */ 0,
  633. /* 7 */ 0,
  634. /* 8 */ 0x00000080
  635. },
  636. /* 9 */ 0,0,
  637. /* A */ 0,0,
  638. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_32,
  639. /* C */ (mix_buffer_addr + (16 * 4)) << 0x10,
  640. /* D */ 0,
  641. {
  642. /* E */ 0x8000,0x8000,
  643. /* F */ 0x8000,0x8000
  644. }
  645. };
  646. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&master_mix_scb,
  647. dest,"S16_MIX",parent_scb,
  648. scb_child_type);
  649. return scb;
  650. }
  651. struct dsp_scb_descriptor *
  652. cs46xx_dsp_create_mix_to_ostream_scb(struct snd_cs46xx * chip, char * scb_name,
  653. u16 mix_buffer_addr, u16 writeback_spb, u32 dest,
  654. struct dsp_scb_descriptor * parent_scb,
  655. int scb_child_type)
  656. {
  657. struct dsp_scb_descriptor * scb;
  658. struct dsp_mix2_ostream_scb mix2_ostream_scb = {
  659. /* Basic (non scatter/gather) DMA requestor (4 ints) */
  660. {
  661. DMA_RQ_C1_SOURCE_MOD64 +
  662. DMA_RQ_C1_DEST_ON_HOST +
  663. DMA_RQ_C1_DEST_MOD1024 +
  664. DMA_RQ_C1_WRITEBACK_SRC_FLAG +
  665. DMA_RQ_C1_WRITEBACK_DEST_FLAG +
  666. 15,
  667. DMA_RQ_C2_AC_NONE +
  668. DMA_RQ_C2_SIGNAL_DEST_PINGPONG +
  669. CS46XX_DSP_CAPTURE_CHANNEL,
  670. DMA_RQ_SD_SP_SAMPLE_ADDR +
  671. mix_buffer_addr,
  672. 0x0
  673. },
  674. { 0, 0, 0, 0, 0, },
  675. 0,0,
  676. 0,writeback_spb,
  677. RSCONFIG_DMA_ENABLE +
  678. (19 << RSCONFIG_MAX_DMA_SIZE_SHIFT) +
  679. ((dest >> 4) << RSCONFIG_STREAM_NUM_SHIFT) +
  680. RSCONFIG_DMA_TO_HOST +
  681. RSCONFIG_SAMPLE_16STEREO +
  682. RSCONFIG_MODULO_64,
  683. (mix_buffer_addr + (32 * 4)) << 0x10,
  684. 1,0,
  685. 0x0001,0x0080,
  686. 0xFFFF,0
  687. };
  688. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&mix2_ostream_scb,
  689. dest,"S16_MIX_TO_OSTREAM",parent_scb,
  690. scb_child_type);
  691. return scb;
  692. }
  693. struct dsp_scb_descriptor *
  694. cs46xx_dsp_create_vari_decimate_scb(struct snd_cs46xx * chip,char * scb_name,
  695. u16 vari_buffer_addr0,
  696. u16 vari_buffer_addr1,
  697. u32 dest,
  698. struct dsp_scb_descriptor * parent_scb,
  699. int scb_child_type)
  700. {
  701. struct dsp_scb_descriptor * scb;
  702. struct dsp_vari_decimate_scb vari_decimate_scb = {
  703. 0x0028,0x00c8,
  704. 0x5555,0x0000,
  705. 0x0000,0x0000,
  706. vari_buffer_addr0,vari_buffer_addr1,
  707. 0x0028,0x00c8,
  708. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256,
  709. 0xFF800000,
  710. 0,
  711. 0x0080,vari_buffer_addr1 + (25 * 4),
  712. 0,0,
  713. 0,0,
  714. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_8,
  715. vari_buffer_addr0 << 0x10,
  716. 0x04000000,
  717. {
  718. 0x8000,0x8000,
  719. 0xFFFF,0xFFFF
  720. }
  721. };
  722. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&vari_decimate_scb,
  723. dest,"VARIDECIMATE",parent_scb,
  724. scb_child_type);
  725. return scb;
  726. }
  727. static struct dsp_scb_descriptor *
  728. cs46xx_dsp_create_pcm_serial_input_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  729. struct dsp_scb_descriptor * input_scb,
  730. struct dsp_scb_descriptor * parent_scb,
  731. int scb_child_type)
  732. {
  733. struct dsp_scb_descriptor * scb;
  734. struct dsp_pcm_serial_input_scb pcm_serial_input_scb = {
  735. { 0,
  736. 0,
  737. 0,
  738. 0
  739. },
  740. {
  741. 0,
  742. 0,
  743. 0,
  744. 0,
  745. 0
  746. },
  747. 0,0,
  748. 0,0,
  749. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_16,
  750. 0,
  751. /* 0xD */ 0,input_scb->address,
  752. {
  753. /* 0xE */ 0x8000,0x8000,
  754. /* 0xF */ 0x8000,0x8000
  755. }
  756. };
  757. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&pcm_serial_input_scb,
  758. dest,"PCMSERIALINPUTTASK",parent_scb,
  759. scb_child_type);
  760. return scb;
  761. }
  762. static struct dsp_scb_descriptor *
  763. cs46xx_dsp_create_asynch_fg_tx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  764. u16 hfg_scb_address,
  765. u16 asynch_buffer_address,
  766. struct dsp_scb_descriptor * parent_scb,
  767. int scb_child_type)
  768. {
  769. struct dsp_scb_descriptor * scb;
  770. struct dsp_asynch_fg_tx_scb asynch_fg_tx_scb = {
  771. 0xfc00,0x03ff, /* Prototype sample buffer size of 256 dwords */
  772. 0x0058,0x0028, /* Min Delta 7 dwords == 28 bytes */
  773. /* : Max delta 25 dwords == 100 bytes */
  774. 0,hfg_scb_address, /* Point to HFG task SCB */
  775. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  776. 0, /* Initialize accumulated Phi to 0 */
  777. 0,0x2aab, /* Const 1/3 */
  778. {
  779. 0, /* Define the unused elements */
  780. 0,
  781. 0
  782. },
  783. 0,0,
  784. 0,dest + AFGTxAccumPhi,
  785. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_256, /* Stereo, 256 dword */
  786. (asynch_buffer_address) << 0x10, /* This should be automagically synchronized
  787. to the producer pointer */
  788. /* There is no correct initial value, it will depend upon the detected
  789. rate etc */
  790. 0x18000000, /* Phi increment for approx 32k operation */
  791. 0x8000,0x8000, /* Volume controls are unused at this time */
  792. 0x8000,0x8000
  793. };
  794. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_tx_scb,
  795. dest,"ASYNCHFGTXCODE",parent_scb,
  796. scb_child_type);
  797. return scb;
  798. }
  799. struct dsp_scb_descriptor *
  800. cs46xx_dsp_create_asynch_fg_rx_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  801. u16 hfg_scb_address,
  802. u16 asynch_buffer_address,
  803. struct dsp_scb_descriptor * parent_scb,
  804. int scb_child_type)
  805. {
  806. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  807. struct dsp_scb_descriptor * scb;
  808. struct dsp_asynch_fg_rx_scb asynch_fg_rx_scb = {
  809. 0xfe00,0x01ff, /* Prototype sample buffer size of 128 dwords */
  810. 0x0064,0x001c, /* Min Delta 7 dwords == 28 bytes */
  811. /* : Max delta 25 dwords == 100 bytes */
  812. 0,hfg_scb_address, /* Point to HFG task SCB */
  813. 0,0, /* Initialize current Delta and Consumer ptr adjustment count */
  814. {
  815. 0, /* Define the unused elements */
  816. 0,
  817. 0,
  818. 0,
  819. 0
  820. },
  821. 0,0,
  822. 0,dest,
  823. RSCONFIG_MODULO_128 |
  824. RSCONFIG_SAMPLE_16STEREO, /* Stereo, 128 dword */
  825. ( (asynch_buffer_address + (16 * 4)) << 0x10), /* This should be automagically
  826. synchrinized to the producer pointer */
  827. /* There is no correct initial value, it will depend upon the detected
  828. rate etc */
  829. 0x18000000,
  830. /* Set IEC958 input volume */
  831. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  832. 0xffff - ins->spdif_input_volume_right,0xffff - ins->spdif_input_volume_left,
  833. };
  834. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&asynch_fg_rx_scb,
  835. dest,"ASYNCHFGRXCODE",parent_scb,
  836. scb_child_type);
  837. return scb;
  838. }
  839. #if 0 /* not used */
  840. struct dsp_scb_descriptor *
  841. cs46xx_dsp_create_output_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  842. u16 snoop_buffer_address,
  843. struct dsp_scb_descriptor * snoop_scb,
  844. struct dsp_scb_descriptor * parent_scb,
  845. int scb_child_type)
  846. {
  847. struct dsp_scb_descriptor * scb;
  848. struct dsp_output_snoop_scb output_snoop_scb = {
  849. { 0, /* not used. Zero */
  850. 0,
  851. 0,
  852. 0,
  853. },
  854. {
  855. 0, /* not used. Zero */
  856. 0,
  857. 0,
  858. 0,
  859. 0
  860. },
  861. 0,0,
  862. 0,0,
  863. RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  864. snoop_buffer_address << 0x10,
  865. 0,0,
  866. 0,
  867. 0,snoop_scb->address
  868. };
  869. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&output_snoop_scb,
  870. dest,"OUTPUTSNOOP",parent_scb,
  871. scb_child_type);
  872. return scb;
  873. }
  874. #endif /* not used */
  875. struct dsp_scb_descriptor *
  876. cs46xx_dsp_create_spio_write_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  877. struct dsp_scb_descriptor * parent_scb,
  878. int scb_child_type)
  879. {
  880. struct dsp_scb_descriptor * scb;
  881. struct dsp_spio_write_scb spio_write_scb = {
  882. 0,0, /* SPIOWAddress2:SPIOWAddress1; */
  883. 0, /* SPIOWData1; */
  884. 0, /* SPIOWData2; */
  885. 0,0, /* SPIOWAddress4:SPIOWAddress3; */
  886. 0, /* SPIOWData3; */
  887. 0, /* SPIOWData4; */
  888. 0,0, /* SPIOWDataPtr:Unused1; */
  889. { 0,0 }, /* Unused2[2]; */
  890. 0,0, /* SPIOWChildPtr:SPIOWSiblingPtr; */
  891. 0,0, /* SPIOWThisPtr:SPIOWEntryPoint; */
  892. {
  893. 0,
  894. 0,
  895. 0,
  896. 0,
  897. 0 /* Unused3[5]; */
  898. }
  899. };
  900. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&spio_write_scb,
  901. dest,"SPIOWRITE",parent_scb,
  902. scb_child_type);
  903. return scb;
  904. }
  905. struct dsp_scb_descriptor *
  906. cs46xx_dsp_create_magic_snoop_scb(struct snd_cs46xx * chip, char * scb_name, u32 dest,
  907. u16 snoop_buffer_address,
  908. struct dsp_scb_descriptor * snoop_scb,
  909. struct dsp_scb_descriptor * parent_scb,
  910. int scb_child_type)
  911. {
  912. struct dsp_scb_descriptor * scb;
  913. struct dsp_magic_snoop_task magic_snoop_scb = {
  914. /* 0 */ 0, /* i0 */
  915. /* 1 */ 0, /* i1 */
  916. /* 2 */ snoop_buffer_address << 0x10,
  917. /* 3 */ 0,snoop_scb->address,
  918. /* 4 */ 0, /* i3 */
  919. /* 5 */ 0, /* i4 */
  920. /* 6 */ 0, /* i5 */
  921. /* 7 */ 0, /* i6 */
  922. /* 8 */ 0, /* i7 */
  923. /* 9 */ 0,0, /* next_scb, sub_list_ptr */
  924. /* A */ 0,0, /* entry_point, this_ptr */
  925. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  926. /* C */ snoop_buffer_address << 0x10,
  927. /* D */ 0,
  928. /* E */ { 0x8000,0x8000,
  929. /* F */ 0xffff,0xffff
  930. }
  931. };
  932. scb = cs46xx_dsp_create_generic_scb(chip,scb_name,(u32 *)&magic_snoop_scb,
  933. dest,"MAGICSNOOPTASK",parent_scb,
  934. scb_child_type);
  935. return scb;
  936. }
  937. static struct dsp_scb_descriptor *
  938. find_next_free_scb (struct snd_cs46xx * chip, struct dsp_scb_descriptor * from)
  939. {
  940. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  941. struct dsp_scb_descriptor * scb = from;
  942. while (scb->next_scb_ptr != ins->the_null_scb) {
  943. snd_assert (scb->next_scb_ptr != NULL, return NULL);
  944. scb = scb->next_scb_ptr;
  945. }
  946. return scb;
  947. }
  948. static u32 pcm_reader_buffer_addr[DSP_MAX_PCM_CHANNELS] = {
  949. 0x0600, /* 1 */
  950. 0x1500, /* 2 */
  951. 0x1580, /* 3 */
  952. 0x1600, /* 4 */
  953. 0x1680, /* 5 */
  954. 0x1700, /* 6 */
  955. 0x1780, /* 7 */
  956. 0x1800, /* 8 */
  957. 0x1880, /* 9 */
  958. 0x1900, /* 10 */
  959. 0x1980, /* 11 */
  960. 0x1A00, /* 12 */
  961. 0x1A80, /* 13 */
  962. 0x1B00, /* 14 */
  963. 0x1B80, /* 15 */
  964. 0x1C00, /* 16 */
  965. 0x1C80, /* 17 */
  966. 0x1D00, /* 18 */
  967. 0x1D80, /* 19 */
  968. 0x1E00, /* 20 */
  969. 0x1E80, /* 21 */
  970. 0x1F00, /* 22 */
  971. 0x1F80, /* 23 */
  972. 0x2000, /* 24 */
  973. 0x2080, /* 25 */
  974. 0x2100, /* 26 */
  975. 0x2180, /* 27 */
  976. 0x2200, /* 28 */
  977. 0x2280, /* 29 */
  978. 0x2300, /* 30 */
  979. 0x2380, /* 31 */
  980. 0x2400, /* 32 */
  981. };
  982. static u32 src_output_buffer_addr[DSP_MAX_SRC_NR] = {
  983. 0x2B80,
  984. 0x2BA0,
  985. 0x2BC0,
  986. 0x2BE0,
  987. 0x2D00,
  988. 0x2D20,
  989. 0x2D40,
  990. 0x2D60,
  991. 0x2D80,
  992. 0x2DA0,
  993. 0x2DC0,
  994. 0x2DE0,
  995. 0x2E00,
  996. 0x2E20
  997. };
  998. static u32 src_delay_buffer_addr[DSP_MAX_SRC_NR] = {
  999. 0x2480,
  1000. 0x2500,
  1001. 0x2580,
  1002. 0x2600,
  1003. 0x2680,
  1004. 0x2700,
  1005. 0x2780,
  1006. 0x2800,
  1007. 0x2880,
  1008. 0x2900,
  1009. 0x2980,
  1010. 0x2A00,
  1011. 0x2A80,
  1012. 0x2B00
  1013. };
  1014. struct dsp_pcm_channel_descriptor *
  1015. cs46xx_dsp_create_pcm_channel (struct snd_cs46xx * chip,
  1016. u32 sample_rate, void * private_data,
  1017. u32 hw_dma_addr,
  1018. int pcm_channel_id)
  1019. {
  1020. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1021. struct dsp_scb_descriptor * src_scb = NULL, * pcm_scb, * mixer_scb = NULL;
  1022. struct dsp_scb_descriptor * src_parent_scb = NULL;
  1023. /* struct dsp_scb_descriptor * pcm_parent_scb; */
  1024. char scb_name[DSP_MAX_SCB_NAME];
  1025. int i, pcm_index = -1, insert_point, src_index = -1, pass_through = 0;
  1026. unsigned long flags;
  1027. switch (pcm_channel_id) {
  1028. case DSP_PCM_MAIN_CHANNEL:
  1029. mixer_scb = ins->master_mix_scb;
  1030. break;
  1031. case DSP_PCM_REAR_CHANNEL:
  1032. mixer_scb = ins->rear_mix_scb;
  1033. break;
  1034. case DSP_PCM_CENTER_LFE_CHANNEL:
  1035. mixer_scb = ins->center_lfe_mix_scb;
  1036. break;
  1037. case DSP_PCM_S71_CHANNEL:
  1038. /* TODO */
  1039. snd_assert(0);
  1040. break;
  1041. case DSP_IEC958_CHANNEL:
  1042. snd_assert (ins->asynch_tx_scb != NULL, return NULL);
  1043. mixer_scb = ins->asynch_tx_scb;
  1044. /* if sample rate is set to 48khz we pass
  1045. the Sample Rate Converted (which could
  1046. alter the raw data stream ...) */
  1047. if (sample_rate == 48000) {
  1048. snd_printdd ("IEC958 pass through\n");
  1049. /* Hack to bypass creating a new SRC */
  1050. pass_through = 1;
  1051. }
  1052. break;
  1053. default:
  1054. snd_assert (0);
  1055. return NULL;
  1056. }
  1057. /* default sample rate is 44100 */
  1058. if (!sample_rate) sample_rate = 44100;
  1059. /* search for a already created SRC SCB with the same sample rate */
  1060. for (i = 0; i < DSP_MAX_PCM_CHANNELS &&
  1061. (pcm_index == -1 || src_scb == NULL); ++i) {
  1062. /* virtual channel reserved
  1063. for capture */
  1064. if (i == CS46XX_DSP_CAPTURE_CHANNEL) continue;
  1065. if (ins->pcm_channels[i].active) {
  1066. if (!src_scb &&
  1067. ins->pcm_channels[i].sample_rate == sample_rate &&
  1068. ins->pcm_channels[i].mixer_scb == mixer_scb) {
  1069. src_scb = ins->pcm_channels[i].src_scb;
  1070. ins->pcm_channels[i].src_scb->ref_count ++;
  1071. src_index = ins->pcm_channels[i].src_slot;
  1072. }
  1073. } else if (pcm_index == -1) {
  1074. pcm_index = i;
  1075. }
  1076. }
  1077. if (pcm_index == -1) {
  1078. snd_printk (KERN_ERR "dsp_spos: no free PCM channel\n");
  1079. return NULL;
  1080. }
  1081. if (src_scb == NULL) {
  1082. if (ins->nsrc_scb >= DSP_MAX_SRC_NR) {
  1083. snd_printk(KERN_ERR "dsp_spos: to many SRC instances\n!");
  1084. return NULL;
  1085. }
  1086. /* find a free slot */
  1087. for (i = 0; i < DSP_MAX_SRC_NR; ++i) {
  1088. if (ins->src_scb_slots[i] == 0) {
  1089. src_index = i;
  1090. ins->src_scb_slots[i] = 1;
  1091. break;
  1092. }
  1093. }
  1094. snd_assert (src_index != -1,return NULL);
  1095. /* we need to create a new SRC SCB */
  1096. if (mixer_scb->sub_list_ptr == ins->the_null_scb) {
  1097. src_parent_scb = mixer_scb;
  1098. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1099. } else {
  1100. src_parent_scb = find_next_free_scb(chip,mixer_scb->sub_list_ptr);
  1101. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1102. }
  1103. snprintf (scb_name,DSP_MAX_SCB_NAME,"SrcTask_SCB%d",src_index);
  1104. snd_printdd( "dsp_spos: creating SRC \"%s\"\n",scb_name);
  1105. src_scb = cs46xx_dsp_create_src_task_scb(chip,scb_name,
  1106. sample_rate,
  1107. src_output_buffer_addr[src_index],
  1108. src_delay_buffer_addr[src_index],
  1109. /* 0x400 - 0x600 source SCBs */
  1110. 0x400 + (src_index * 0x10) ,
  1111. src_parent_scb,
  1112. insert_point,
  1113. pass_through);
  1114. if (!src_scb) {
  1115. snd_printk (KERN_ERR "dsp_spos: failed to create SRCtaskSCB\n");
  1116. return NULL;
  1117. }
  1118. /* cs46xx_dsp_set_src_sample_rate(chip,src_scb,sample_rate); */
  1119. ins->nsrc_scb ++;
  1120. }
  1121. snprintf (scb_name,DSP_MAX_SCB_NAME,"PCMReader_SCB%d",pcm_index);
  1122. snd_printdd( "dsp_spos: creating PCM \"%s\" (%d)\n",scb_name,
  1123. pcm_channel_id);
  1124. pcm_scb = cs46xx_dsp_create_pcm_reader_scb(chip,scb_name,
  1125. pcm_reader_buffer_addr[pcm_index],
  1126. /* 0x200 - 400 PCMreader SCBs */
  1127. (pcm_index * 0x10) + 0x200,
  1128. pcm_index, /* virtual channel 0-31 */
  1129. hw_dma_addr, /* pcm hw addr */
  1130. NULL, /* parent SCB ptr */
  1131. 0 /* insert point */
  1132. );
  1133. if (!pcm_scb) {
  1134. snd_printk (KERN_ERR "dsp_spos: failed to create PCMreaderSCB\n");
  1135. return NULL;
  1136. }
  1137. spin_lock_irqsave(&chip->reg_lock, flags);
  1138. ins->pcm_channels[pcm_index].sample_rate = sample_rate;
  1139. ins->pcm_channels[pcm_index].pcm_reader_scb = pcm_scb;
  1140. ins->pcm_channels[pcm_index].src_scb = src_scb;
  1141. ins->pcm_channels[pcm_index].unlinked = 1;
  1142. ins->pcm_channels[pcm_index].private_data = private_data;
  1143. ins->pcm_channels[pcm_index].src_slot = src_index;
  1144. ins->pcm_channels[pcm_index].active = 1;
  1145. ins->pcm_channels[pcm_index].pcm_slot = pcm_index;
  1146. ins->pcm_channels[pcm_index].mixer_scb = mixer_scb;
  1147. ins->npcm_channels ++;
  1148. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1149. return (ins->pcm_channels + pcm_index);
  1150. }
  1151. int cs46xx_dsp_pcm_channel_set_period (struct snd_cs46xx * chip,
  1152. struct dsp_pcm_channel_descriptor * pcm_channel,
  1153. int period_size)
  1154. {
  1155. u32 temp = snd_cs46xx_peek (chip,pcm_channel->pcm_reader_scb->address << 2);
  1156. temp &= ~DMA_RQ_C1_SOURCE_SIZE_MASK;
  1157. switch (period_size) {
  1158. case 2048:
  1159. temp |= DMA_RQ_C1_SOURCE_MOD1024;
  1160. break;
  1161. case 1024:
  1162. temp |= DMA_RQ_C1_SOURCE_MOD512;
  1163. break;
  1164. case 512:
  1165. temp |= DMA_RQ_C1_SOURCE_MOD256;
  1166. break;
  1167. case 256:
  1168. temp |= DMA_RQ_C1_SOURCE_MOD128;
  1169. break;
  1170. case 128:
  1171. temp |= DMA_RQ_C1_SOURCE_MOD64;
  1172. break;
  1173. case 64:
  1174. temp |= DMA_RQ_C1_SOURCE_MOD32;
  1175. break;
  1176. case 32:
  1177. temp |= DMA_RQ_C1_SOURCE_MOD16;
  1178. break;
  1179. default:
  1180. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1181. return -EINVAL;
  1182. }
  1183. snd_cs46xx_poke (chip,pcm_channel->pcm_reader_scb->address << 2,temp);
  1184. return 0;
  1185. }
  1186. int cs46xx_dsp_pcm_ostream_set_period (struct snd_cs46xx * chip,
  1187. int period_size)
  1188. {
  1189. u32 temp = snd_cs46xx_peek (chip,WRITEBACK_SCB_ADDR << 2);
  1190. temp &= ~DMA_RQ_C1_DEST_SIZE_MASK;
  1191. switch (period_size) {
  1192. case 2048:
  1193. temp |= DMA_RQ_C1_DEST_MOD1024;
  1194. break;
  1195. case 1024:
  1196. temp |= DMA_RQ_C1_DEST_MOD512;
  1197. break;
  1198. case 512:
  1199. temp |= DMA_RQ_C1_DEST_MOD256;
  1200. break;
  1201. case 256:
  1202. temp |= DMA_RQ_C1_DEST_MOD128;
  1203. break;
  1204. case 128:
  1205. temp |= DMA_RQ_C1_DEST_MOD64;
  1206. break;
  1207. case 64:
  1208. temp |= DMA_RQ_C1_DEST_MOD32;
  1209. break;
  1210. case 32:
  1211. temp |= DMA_RQ_C1_DEST_MOD16;
  1212. break;
  1213. default:
  1214. snd_printdd ("period size (%d) not supported by HW\n", period_size);
  1215. return -EINVAL;
  1216. }
  1217. snd_cs46xx_poke (chip,WRITEBACK_SCB_ADDR << 2,temp);
  1218. return 0;
  1219. }
  1220. void cs46xx_dsp_destroy_pcm_channel (struct snd_cs46xx * chip,
  1221. struct dsp_pcm_channel_descriptor * pcm_channel)
  1222. {
  1223. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1224. unsigned long flags;
  1225. snd_assert(pcm_channel->active, return );
  1226. snd_assert(ins->npcm_channels > 0, return );
  1227. snd_assert(pcm_channel->src_scb->ref_count > 0, return );
  1228. spin_lock_irqsave(&chip->reg_lock, flags);
  1229. pcm_channel->unlinked = 1;
  1230. pcm_channel->active = 0;
  1231. pcm_channel->private_data = NULL;
  1232. pcm_channel->src_scb->ref_count --;
  1233. ins->npcm_channels --;
  1234. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1235. cs46xx_dsp_remove_scb(chip,pcm_channel->pcm_reader_scb);
  1236. if (!pcm_channel->src_scb->ref_count) {
  1237. cs46xx_dsp_remove_scb(chip,pcm_channel->src_scb);
  1238. snd_assert (pcm_channel->src_slot >= 0 && pcm_channel->src_slot <= DSP_MAX_SRC_NR,
  1239. return );
  1240. ins->src_scb_slots[pcm_channel->src_slot] = 0;
  1241. ins->nsrc_scb --;
  1242. }
  1243. }
  1244. int cs46xx_dsp_pcm_unlink (struct snd_cs46xx * chip,
  1245. struct dsp_pcm_channel_descriptor * pcm_channel)
  1246. {
  1247. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1248. unsigned long flags;
  1249. snd_assert(pcm_channel->active,return -EIO);
  1250. snd_assert(ins->npcm_channels > 0,return -EIO);
  1251. spin_lock(&pcm_channel->src_scb->lock);
  1252. if (pcm_channel->unlinked) {
  1253. spin_unlock(&pcm_channel->src_scb->lock);
  1254. return -EIO;
  1255. }
  1256. spin_lock_irqsave(&chip->reg_lock, flags);
  1257. pcm_channel->unlinked = 1;
  1258. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1259. _dsp_unlink_scb (chip,pcm_channel->pcm_reader_scb);
  1260. spin_unlock(&pcm_channel->src_scb->lock);
  1261. return 0;
  1262. }
  1263. int cs46xx_dsp_pcm_link (struct snd_cs46xx * chip,
  1264. struct dsp_pcm_channel_descriptor * pcm_channel)
  1265. {
  1266. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1267. struct dsp_scb_descriptor * parent_scb;
  1268. struct dsp_scb_descriptor * src_scb = pcm_channel->src_scb;
  1269. unsigned long flags;
  1270. spin_lock(&pcm_channel->src_scb->lock);
  1271. if (pcm_channel->unlinked == 0) {
  1272. spin_unlock(&pcm_channel->src_scb->lock);
  1273. return -EIO;
  1274. }
  1275. parent_scb = src_scb;
  1276. if (src_scb->sub_list_ptr != ins->the_null_scb) {
  1277. src_scb->sub_list_ptr->parent_scb_ptr = pcm_channel->pcm_reader_scb;
  1278. pcm_channel->pcm_reader_scb->next_scb_ptr = src_scb->sub_list_ptr;
  1279. }
  1280. src_scb->sub_list_ptr = pcm_channel->pcm_reader_scb;
  1281. snd_assert (pcm_channel->pcm_reader_scb->parent_scb_ptr == NULL, ; );
  1282. pcm_channel->pcm_reader_scb->parent_scb_ptr = parent_scb;
  1283. spin_lock_irqsave(&chip->reg_lock, flags);
  1284. /* update SCB entry in DSP RAM */
  1285. cs46xx_dsp_spos_update_scb(chip,pcm_channel->pcm_reader_scb);
  1286. /* update parent SCB entry */
  1287. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1288. pcm_channel->unlinked = 0;
  1289. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1290. spin_unlock(&pcm_channel->src_scb->lock);
  1291. return 0;
  1292. }
  1293. struct dsp_scb_descriptor *
  1294. cs46xx_add_record_source (struct snd_cs46xx *chip, struct dsp_scb_descriptor * source,
  1295. u16 addr, char * scb_name)
  1296. {
  1297. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1298. struct dsp_scb_descriptor * parent;
  1299. struct dsp_scb_descriptor * pcm_input;
  1300. int insert_point;
  1301. snd_assert (ins->record_mixer_scb != NULL,return NULL);
  1302. if (ins->record_mixer_scb->sub_list_ptr != ins->the_null_scb) {
  1303. parent = find_next_free_scb (chip,ins->record_mixer_scb->sub_list_ptr);
  1304. insert_point = SCB_ON_PARENT_NEXT_SCB;
  1305. } else {
  1306. parent = ins->record_mixer_scb;
  1307. insert_point = SCB_ON_PARENT_SUBLIST_SCB;
  1308. }
  1309. pcm_input = cs46xx_dsp_create_pcm_serial_input_scb(chip,scb_name,addr,
  1310. source, parent,
  1311. insert_point);
  1312. return pcm_input;
  1313. }
  1314. int cs46xx_src_unlink(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1315. {
  1316. snd_assert (src->parent_scb_ptr != NULL, return -EINVAL );
  1317. /* mute SCB */
  1318. cs46xx_dsp_scb_set_volume (chip,src,0,0);
  1319. _dsp_unlink_scb (chip,src);
  1320. return 0;
  1321. }
  1322. int cs46xx_src_link(struct snd_cs46xx *chip, struct dsp_scb_descriptor * src)
  1323. {
  1324. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1325. struct dsp_scb_descriptor * parent_scb;
  1326. snd_assert (src->parent_scb_ptr == NULL, return -EINVAL );
  1327. snd_assert(ins->master_mix_scb !=NULL, return -EINVAL );
  1328. if (ins->master_mix_scb->sub_list_ptr != ins->the_null_scb) {
  1329. parent_scb = find_next_free_scb (chip,ins->master_mix_scb->sub_list_ptr);
  1330. parent_scb->next_scb_ptr = src;
  1331. } else {
  1332. parent_scb = ins->master_mix_scb;
  1333. parent_scb->sub_list_ptr = src;
  1334. }
  1335. src->parent_scb_ptr = parent_scb;
  1336. /* update entry in DSP RAM */
  1337. cs46xx_dsp_spos_update_scb(chip,parent_scb);
  1338. return 0;
  1339. }
  1340. int cs46xx_dsp_enable_spdif_out (struct snd_cs46xx *chip)
  1341. {
  1342. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1343. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1344. cs46xx_dsp_enable_spdif_hw (chip);
  1345. }
  1346. /* dont touch anything if SPDIF is open */
  1347. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1348. /* when cs46xx_iec958_post_close(...) is called it
  1349. will call this function if necessary depending on
  1350. this bit */
  1351. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1352. return -EBUSY;
  1353. }
  1354. snd_assert (ins->asynch_tx_scb == NULL, return -EINVAL);
  1355. snd_assert (ins->master_mix_scb->next_scb_ptr == ins->the_null_scb, return -EINVAL);
  1356. /* reset output snooper sample buffer pointer */
  1357. snd_cs46xx_poke (chip, (ins->ref_snoop_scb->address + 2) << 2,
  1358. (OUTPUT_SNOOP_BUFFER + 0x10) << 0x10 );
  1359. /* The asynch. transfer task */
  1360. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1361. SPDIFO_SCB_INST,
  1362. SPDIFO_IP_OUTPUT_BUFFER1,
  1363. ins->master_mix_scb,
  1364. SCB_ON_PARENT_NEXT_SCB);
  1365. if (!ins->asynch_tx_scb) return -ENOMEM;
  1366. ins->spdif_pcm_input_scb = cs46xx_dsp_create_pcm_serial_input_scb(chip,"PCMSerialInput_II",
  1367. PCMSERIALINII_SCB_ADDR,
  1368. ins->ref_snoop_scb,
  1369. ins->asynch_tx_scb,
  1370. SCB_ON_PARENT_SUBLIST_SCB);
  1371. if (!ins->spdif_pcm_input_scb) return -ENOMEM;
  1372. /* monitor state */
  1373. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1374. return 0;
  1375. }
  1376. int cs46xx_dsp_disable_spdif_out (struct snd_cs46xx *chip)
  1377. {
  1378. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1379. /* dont touch anything if SPDIF is open */
  1380. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) {
  1381. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1382. return -EBUSY;
  1383. }
  1384. /* check integrety */
  1385. snd_assert (ins->asynch_tx_scb != NULL, return -EINVAL);
  1386. snd_assert (ins->spdif_pcm_input_scb != NULL,return -EINVAL);
  1387. snd_assert (ins->master_mix_scb->next_scb_ptr == ins->asynch_tx_scb, return -EINVAL);
  1388. snd_assert (ins->asynch_tx_scb->parent_scb_ptr == ins->master_mix_scb, return -EINVAL);
  1389. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1390. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1391. ins->spdif_pcm_input_scb = NULL;
  1392. ins->asynch_tx_scb = NULL;
  1393. /* clear buffer to prevent any undesired noise */
  1394. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1395. /* monitor state */
  1396. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1397. return 0;
  1398. }
  1399. int cs46xx_iec958_pre_open (struct snd_cs46xx *chip)
  1400. {
  1401. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1402. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1403. /* remove AsynchFGTxSCB and and PCMSerialInput_II */
  1404. cs46xx_dsp_disable_spdif_out (chip);
  1405. /* save state */
  1406. ins->spdif_status_out |= DSP_SPDIF_STATUS_OUTPUT_ENABLED;
  1407. }
  1408. /* if not enabled already */
  1409. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_HW_ENABLED) ) {
  1410. cs46xx_dsp_enable_spdif_hw (chip);
  1411. }
  1412. /* Create the asynch. transfer task for playback */
  1413. ins->asynch_tx_scb = cs46xx_dsp_create_asynch_fg_tx_scb(chip,"AsynchFGTxSCB",ASYNCTX_SCB_ADDR,
  1414. SPDIFO_SCB_INST,
  1415. SPDIFO_IP_OUTPUT_BUFFER1,
  1416. ins->master_mix_scb,
  1417. SCB_ON_PARENT_NEXT_SCB);
  1418. /* set spdif channel status value for streaming */
  1419. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_stream);
  1420. ins->spdif_status_out |= DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1421. return 0;
  1422. }
  1423. int cs46xx_iec958_post_close (struct snd_cs46xx *chip)
  1424. {
  1425. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1426. snd_assert (ins->asynch_tx_scb != NULL, return -EINVAL);
  1427. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_PLAYBACK_OPEN;
  1428. /* restore settings */
  1429. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1430. /* deallocate stuff */
  1431. if (ins->spdif_pcm_input_scb != NULL) {
  1432. cs46xx_dsp_remove_scb (chip,ins->spdif_pcm_input_scb);
  1433. ins->spdif_pcm_input_scb = NULL;
  1434. }
  1435. cs46xx_dsp_remove_scb (chip,ins->asynch_tx_scb);
  1436. ins->asynch_tx_scb = NULL;
  1437. /* clear buffer to prevent any undesired noise */
  1438. _dsp_clear_sample_buffer(chip,SPDIFO_IP_OUTPUT_BUFFER1,256);
  1439. /* restore state */
  1440. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED ) {
  1441. cs46xx_dsp_enable_spdif_out (chip);
  1442. }
  1443. return 0;
  1444. }