dsp_spos.h 7.5 KB

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  1. /*
  2. * The driver for the Cirrus Logic's Sound Fusion CS46XX based soundcards
  3. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. /*
  22. * 2002-07 Benny Sjostrand benny@hostmobility.com
  23. */
  24. #ifdef CONFIG_SND_CS46XX_NEW_DSP /* hack ... */
  25. #ifndef __DSP_SPOS_H__
  26. #define __DSP_SPOS_H__
  27. #define DSP_MAX_SYMBOLS 1024
  28. #define DSP_MAX_MODULES 64
  29. #define DSP_CODE_BYTE_SIZE 0x00007000UL
  30. #define DSP_PARAMETER_BYTE_SIZE 0x00003000UL
  31. #define DSP_SAMPLE_BYTE_SIZE 0x00003800UL
  32. #define DSP_PARAMETER_BYTE_OFFSET 0x00000000UL
  33. #define DSP_SAMPLE_BYTE_OFFSET 0x00010000UL
  34. #define DSP_CODE_BYTE_OFFSET 0x00020000UL
  35. #define WIDE_INSTR_MASK 0x0040
  36. #define WIDE_LADD_INSTR_MASK 0x0380
  37. /* this instruction types
  38. needs to be reallocated when load
  39. code into DSP */
  40. enum wide_opcode {
  41. WIDE_FOR_BEGIN_LOOP = 0x20,
  42. WIDE_FOR_BEGIN_LOOP2,
  43. WIDE_COND_GOTO_ADDR = 0x30,
  44. WIDE_COND_GOTO_CALL,
  45. WIDE_TBEQ_COND_GOTO_ADDR = 0x70,
  46. WIDE_TBEQ_COND_CALL_ADDR,
  47. WIDE_TBEQ_NCOND_GOTO_ADDR,
  48. WIDE_TBEQ_NCOND_CALL_ADDR,
  49. WIDE_TBEQ_COND_GOTO1_ADDR,
  50. WIDE_TBEQ_COND_CALL1_ADDR,
  51. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  52. WIDE_TBEQ_NCOND_CALL1_ADDR,
  53. };
  54. /* SAMPLE segment */
  55. #define VARI_DECIMATE_BUF1 0x0000
  56. #define WRITE_BACK_BUF1 0x0400
  57. #define CODEC_INPUT_BUF1 0x0500
  58. #define PCM_READER_BUF1 0x0600
  59. #define SRC_DELAY_BUF1 0x0680
  60. #define VARI_DECIMATE_BUF0 0x0780
  61. #define SRC_OUTPUT_BUF1 0x07A0
  62. #define ASYNC_IP_OUTPUT_BUFFER1 0x0A00
  63. #define OUTPUT_SNOOP_BUFFER 0x0B00
  64. #define SPDIFI_IP_OUTPUT_BUFFER1 0x0E00
  65. #define SPDIFO_IP_OUTPUT_BUFFER1 0x1000
  66. #define MIX_SAMPLE_BUF1 0x1400
  67. #define MIX_SAMPLE_BUF2 0x2E80
  68. #define MIX_SAMPLE_BUF3 0x2F00
  69. #define MIX_SAMPLE_BUF4 0x2F80
  70. #define MIX_SAMPLE_BUF5 0x3000
  71. /* Task stack address */
  72. #define HFG_STACK 0x066A
  73. #define FG_STACK 0x066E
  74. #define BG_STACK 0x068E
  75. /* SCB's addresses */
  76. #define SPOSCB_ADDR 0x070
  77. #define BG_TREE_SCB_ADDR 0x635
  78. #define NULL_SCB_ADDR 0x000
  79. #define TIMINGMASTER_SCB_ADDR 0x010
  80. #define CODECOUT_SCB_ADDR 0x020
  81. #define PCMREADER_SCB_ADDR 0x030
  82. #define WRITEBACK_SCB_ADDR 0x040
  83. #define CODECIN_SCB_ADDR 0x080
  84. #define MASTERMIX_SCB_ADDR 0x090
  85. #define SRCTASK_SCB_ADDR 0x0A0
  86. #define VARIDECIMATE_SCB_ADDR 0x0B0
  87. #define PCMSERIALIN_SCB_ADDR 0x0C0
  88. #define FG_TASK_HEADER_ADDR 0x600
  89. #define ASYNCTX_SCB_ADDR 0x0E0
  90. #define ASYNCRX_SCB_ADDR 0x0F0
  91. #define SRCTASKII_SCB_ADDR 0x100
  92. #define OUTPUTSNOOP_SCB_ADDR 0x110
  93. #define PCMSERIALINII_SCB_ADDR 0x120
  94. #define SPIOWRITE_SCB_ADDR 0x130
  95. #define REAR_CODECOUT_SCB_ADDR 0x140
  96. #define OUTPUTSNOOPII_SCB_ADDR 0x150
  97. #define PCMSERIALIN_PCM_SCB_ADDR 0x160
  98. #define RECORD_MIXER_SCB_ADDR 0x170
  99. #define REAR_MIXER_SCB_ADDR 0x180
  100. #define CLFE_MIXER_SCB_ADDR 0x190
  101. #define CLFE_CODEC_SCB_ADDR 0x1A0
  102. /* hyperforground SCB's*/
  103. #define HFG_TREE_SCB 0xBA0
  104. #define SPDIFI_SCB_INST 0xBB0
  105. #define SPDIFO_SCB_INST 0xBC0
  106. #define WRITE_BACK_SPB 0x0D0
  107. /* offsets */
  108. #define AsyncCIOFIFOPointer 0xd
  109. #define SPDIFOFIFOPointer 0xd
  110. #define SPDIFIFIFOPointer 0xd
  111. #define TCBData 0xb
  112. #define HFGFlags 0xa
  113. #define TCBContextBlk 0x10
  114. #define AFGTxAccumPhi 0x4
  115. #define SCBsubListPtr 0x9
  116. #define SCBfuncEntryPtr 0xA
  117. #define SRCCorPerGof 0x2
  118. #define SRCPhiIncr6Int26Frac 0xd
  119. #define SCBVolumeCtrl 0xe
  120. /* conf */
  121. #define UseASER1Input 1
  122. /*
  123. * The following defines are for the flags in the rsConfig01/23 registers of
  124. * the SP.
  125. */
  126. #define RSCONFIG_MODULO_SIZE_MASK 0x0000000FL
  127. #define RSCONFIG_MODULO_16 0x00000001L
  128. #define RSCONFIG_MODULO_32 0x00000002L
  129. #define RSCONFIG_MODULO_64 0x00000003L
  130. #define RSCONFIG_MODULO_128 0x00000004L
  131. #define RSCONFIG_MODULO_256 0x00000005L
  132. #define RSCONFIG_MODULO_512 0x00000006L
  133. #define RSCONFIG_MODULO_1024 0x00000007L
  134. #define RSCONFIG_MODULO_4 0x00000008L
  135. #define RSCONFIG_MODULO_8 0x00000009L
  136. #define RSCONFIG_SAMPLE_SIZE_MASK 0x000000C0L
  137. #define RSCONFIG_SAMPLE_8MONO 0x00000000L
  138. #define RSCONFIG_SAMPLE_8STEREO 0x00000040L
  139. #define RSCONFIG_SAMPLE_16MONO 0x00000080L
  140. #define RSCONFIG_SAMPLE_16STEREO 0x000000C0L
  141. #define RSCONFIG_UNDERRUN_ZERO 0x00004000L
  142. #define RSCONFIG_DMA_TO_HOST 0x00008000L
  143. #define RSCONFIG_STREAM_NUM_MASK 0x00FF0000L
  144. #define RSCONFIG_MAX_DMA_SIZE_MASK 0x1F000000L
  145. #define RSCONFIG_DMA_ENABLE 0x20000000L
  146. #define RSCONFIG_PRIORITY_MASK 0xC0000000L
  147. #define RSCONFIG_PRIORITY_HIGH 0x00000000L
  148. #define RSCONFIG_PRIORITY_MEDIUM_HIGH 0x40000000L
  149. #define RSCONFIG_PRIORITY_MEDIUM_LOW 0x80000000L
  150. #define RSCONFIG_PRIORITY_LOW 0xC0000000L
  151. #define RSCONFIG_STREAM_NUM_SHIFT 16L
  152. #define RSCONFIG_MAX_DMA_SIZE_SHIFT 24L
  153. /* SP constants */
  154. #define FG_INTERVAL_TIMER_PERIOD 0x0051
  155. #define BG_INTERVAL_TIMER_PERIOD 0x0100
  156. /* Only SP accessible registers */
  157. #define SP_ASER_COUNTDOWN 0x8040
  158. #define SP_SPDOUT_FIFO 0x0108
  159. #define SP_SPDIN_MI_FIFO 0x01E0
  160. #define SP_SPDIN_D_FIFO 0x01F0
  161. #define SP_SPDIN_STATUS 0x8048
  162. #define SP_SPDIN_CONTROL 0x8049
  163. #define SP_SPDIN_FIFOPTR 0x804A
  164. #define SP_SPDOUT_STATUS 0x804C
  165. #define SP_SPDOUT_CONTROL 0x804D
  166. #define SP_SPDOUT_CSUV 0x808E
  167. static inline u8 _wrap_all_bits (u8 val)
  168. {
  169. u8 wrapped;
  170. /* wrap all 8 bits */
  171. wrapped =
  172. ((val & 0x1 ) << 7) |
  173. ((val & 0x2 ) << 5) |
  174. ((val & 0x4 ) << 3) |
  175. ((val & 0x8 ) << 1) |
  176. ((val & 0x10) >> 1) |
  177. ((val & 0x20) >> 3) |
  178. ((val & 0x40) >> 5) |
  179. ((val & 0x80) >> 7);
  180. return wrapped;
  181. }
  182. static inline void cs46xx_dsp_spos_update_scb (struct snd_cs46xx * chip,
  183. struct dsp_scb_descriptor * scb)
  184. {
  185. /* update nextSCB and subListPtr in SCB */
  186. snd_cs46xx_poke(chip,
  187. (scb->address + SCBsubListPtr) << 2,
  188. (scb->sub_list_ptr->address << 0x10) |
  189. (scb->next_scb_ptr->address));
  190. }
  191. static inline void cs46xx_dsp_scb_set_volume (struct snd_cs46xx * chip,
  192. struct dsp_scb_descriptor * scb,
  193. u16 left, u16 right)
  194. {
  195. unsigned int val = ((0xffff - left) << 16 | (0xffff - right));
  196. snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl) << 2, val);
  197. snd_cs46xx_poke(chip, (scb->address + SCBVolumeCtrl + 1) << 2, val);
  198. }
  199. #endif /* __DSP_SPOS_H__ */
  200. #endif /* CONFIG_SND_CS46XX_NEW_DSP */