dsp_spos.c 53 KB

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  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  15. *
  16. */
  17. /*
  18. * 2002-07 Benny Sjostrand benny@hostmobility.com
  19. */
  20. #include <sound/driver.h>
  21. #include <asm/io.h>
  22. #include <linux/delay.h>
  23. #include <linux/pci.h>
  24. #include <linux/pm.h>
  25. #include <linux/init.h>
  26. #include <linux/slab.h>
  27. #include <linux/vmalloc.h>
  28. #include <linux/mutex.h>
  29. #include <sound/core.h>
  30. #include <sound/control.h>
  31. #include <sound/info.h>
  32. #include <sound/asoundef.h>
  33. #include <sound/cs46xx.h>
  34. #include "cs46xx_lib.h"
  35. #include "dsp_spos.h"
  36. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  37. struct dsp_scb_descriptor * fg_entry);
  38. static enum wide_opcode wide_opcodes[] = {
  39. WIDE_FOR_BEGIN_LOOP,
  40. WIDE_FOR_BEGIN_LOOP2,
  41. WIDE_COND_GOTO_ADDR,
  42. WIDE_COND_GOTO_CALL,
  43. WIDE_TBEQ_COND_GOTO_ADDR,
  44. WIDE_TBEQ_COND_CALL_ADDR,
  45. WIDE_TBEQ_NCOND_GOTO_ADDR,
  46. WIDE_TBEQ_NCOND_CALL_ADDR,
  47. WIDE_TBEQ_COND_GOTO1_ADDR,
  48. WIDE_TBEQ_COND_CALL1_ADDR,
  49. WIDE_TBEQ_NCOND_GOTOI_ADDR,
  50. WIDE_TBEQ_NCOND_CALL1_ADDR
  51. };
  52. static int shadow_and_reallocate_code (struct snd_cs46xx * chip, u32 * data, u32 size,
  53. u32 overlay_begin_address)
  54. {
  55. unsigned int i = 0, j, nreallocated = 0;
  56. u32 hival,loval,address;
  57. u32 mop_operands,mop_type,wide_op;
  58. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  59. snd_assert( ((size % 2) == 0), return -EINVAL);
  60. while (i < size) {
  61. loval = data[i++];
  62. hival = data[i++];
  63. if (ins->code.offset > 0) {
  64. mop_operands = (hival >> 6) & 0x03fff;
  65. mop_type = mop_operands >> 10;
  66. /* check for wide type instruction */
  67. if (mop_type == 0 &&
  68. (mop_operands & WIDE_LADD_INSTR_MASK) == 0 &&
  69. (mop_operands & WIDE_INSTR_MASK) != 0) {
  70. wide_op = loval & 0x7f;
  71. for (j = 0;j < ARRAY_SIZE(wide_opcodes); ++j) {
  72. if (wide_opcodes[j] == wide_op) {
  73. /* need to reallocate instruction */
  74. address = (hival & 0x00FFF) << 5;
  75. address |= loval >> 15;
  76. snd_printdd("handle_wideop[1]: %05x:%05x addr %04x\n",hival,loval,address);
  77. if ( !(address & 0x8000) ) {
  78. address += (ins->code.offset / 2) - overlay_begin_address;
  79. } else {
  80. snd_printdd("handle_wideop[1]: ROM symbol not reallocated\n");
  81. }
  82. hival &= 0xFF000;
  83. loval &= 0x07FFF;
  84. hival |= ( (address >> 5) & 0x00FFF);
  85. loval |= ( (address << 15) & 0xF8000);
  86. address = (hival & 0x00FFF) << 5;
  87. address |= loval >> 15;
  88. snd_printdd("handle_wideop:[2] %05x:%05x addr %04x\n",hival,loval,address);
  89. nreallocated ++;
  90. } /* wide_opcodes[j] == wide_op */
  91. } /* for */
  92. } /* mod_type == 0 ... */
  93. } /* ins->code.offset > 0 */
  94. ins->code.data[ins->code.size++] = loval;
  95. ins->code.data[ins->code.size++] = hival;
  96. }
  97. snd_printdd("dsp_spos: %d instructions reallocated\n",nreallocated);
  98. return nreallocated;
  99. }
  100. static struct dsp_segment_desc * get_segment_desc (struct dsp_module_desc * module, int seg_type)
  101. {
  102. int i;
  103. for (i = 0;i < module->nsegments; ++i) {
  104. if (module->segments[i].segment_type == seg_type) {
  105. return (module->segments + i);
  106. }
  107. }
  108. return NULL;
  109. };
  110. static int find_free_symbol_index (struct dsp_spos_instance * ins)
  111. {
  112. int index = ins->symbol_table.nsymbols,i;
  113. for (i = ins->symbol_table.highest_frag_index; i < ins->symbol_table.nsymbols; ++i) {
  114. if (ins->symbol_table.symbols[i].deleted) {
  115. index = i;
  116. break;
  117. }
  118. }
  119. return index;
  120. }
  121. static int add_symbols (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  122. {
  123. int i;
  124. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  125. if (module->symbol_table.nsymbols > 0) {
  126. if (!strcmp(module->symbol_table.symbols[0].symbol_name, "OVERLAYBEGINADDRESS") &&
  127. module->symbol_table.symbols[0].symbol_type == SYMBOL_CONSTANT ) {
  128. module->overlay_begin_address = module->symbol_table.symbols[0].address;
  129. }
  130. }
  131. for (i = 0;i < module->symbol_table.nsymbols; ++i) {
  132. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  133. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  134. return -ENOMEM;
  135. }
  136. if (cs46xx_dsp_lookup_symbol(chip,
  137. module->symbol_table.symbols[i].symbol_name,
  138. module->symbol_table.symbols[i].symbol_type) == NULL) {
  139. ins->symbol_table.symbols[ins->symbol_table.nsymbols] = module->symbol_table.symbols[i];
  140. ins->symbol_table.symbols[ins->symbol_table.nsymbols].address += ((ins->code.offset / 2) - module->overlay_begin_address);
  141. ins->symbol_table.symbols[ins->symbol_table.nsymbols].module = module;
  142. ins->symbol_table.symbols[ins->symbol_table.nsymbols].deleted = 0;
  143. if (ins->symbol_table.nsymbols > ins->symbol_table.highest_frag_index)
  144. ins->symbol_table.highest_frag_index = ins->symbol_table.nsymbols;
  145. ins->symbol_table.nsymbols++;
  146. } else {
  147. /* if (0) printk ("dsp_spos: symbol <%s> duplicated, probably nothing wrong with that (Cirrus?)\n",
  148. module->symbol_table.symbols[i].symbol_name); */
  149. }
  150. }
  151. return 0;
  152. }
  153. static struct dsp_symbol_entry *
  154. add_symbol (struct snd_cs46xx * chip, char * symbol_name, u32 address, int type)
  155. {
  156. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  157. struct dsp_symbol_entry * symbol = NULL;
  158. int index;
  159. if (ins->symbol_table.nsymbols == (DSP_MAX_SYMBOLS - 1)) {
  160. snd_printk(KERN_ERR "dsp_spos: symbol table is full\n");
  161. return NULL;
  162. }
  163. if (cs46xx_dsp_lookup_symbol(chip,
  164. symbol_name,
  165. type) != NULL) {
  166. snd_printk(KERN_ERR "dsp_spos: symbol <%s> duplicated\n", symbol_name);
  167. return NULL;
  168. }
  169. index = find_free_symbol_index (ins);
  170. strcpy (ins->symbol_table.symbols[index].symbol_name, symbol_name);
  171. ins->symbol_table.symbols[index].address = address;
  172. ins->symbol_table.symbols[index].symbol_type = type;
  173. ins->symbol_table.symbols[index].module = NULL;
  174. ins->symbol_table.symbols[index].deleted = 0;
  175. symbol = (ins->symbol_table.symbols + index);
  176. if (index > ins->symbol_table.highest_frag_index)
  177. ins->symbol_table.highest_frag_index = index;
  178. if (index == ins->symbol_table.nsymbols)
  179. ins->symbol_table.nsymbols++; /* no frag. in list */
  180. return symbol;
  181. }
  182. struct dsp_spos_instance *cs46xx_dsp_spos_create (struct snd_cs46xx * chip)
  183. {
  184. struct dsp_spos_instance * ins = kzalloc(sizeof(struct dsp_spos_instance), GFP_KERNEL);
  185. if (ins == NULL)
  186. return NULL;
  187. /* better to use vmalloc for this big table */
  188. ins->symbol_table.nsymbols = 0;
  189. ins->symbol_table.symbols = vmalloc(sizeof(struct dsp_symbol_entry) *
  190. DSP_MAX_SYMBOLS);
  191. ins->symbol_table.highest_frag_index = 0;
  192. if (ins->symbol_table.symbols == NULL) {
  193. cs46xx_dsp_spos_destroy(chip);
  194. goto error;
  195. }
  196. ins->code.offset = 0;
  197. ins->code.size = 0;
  198. ins->code.data = kmalloc(DSP_CODE_BYTE_SIZE, GFP_KERNEL);
  199. if (ins->code.data == NULL) {
  200. cs46xx_dsp_spos_destroy(chip);
  201. goto error;
  202. }
  203. ins->nscb = 0;
  204. ins->ntask = 0;
  205. ins->nmodules = 0;
  206. ins->modules = kmalloc(sizeof(struct dsp_module_desc) * DSP_MAX_MODULES, GFP_KERNEL);
  207. if (ins->modules == NULL) {
  208. cs46xx_dsp_spos_destroy(chip);
  209. goto error;
  210. }
  211. /* default SPDIF input sample rate
  212. to 48000 khz */
  213. ins->spdif_in_sample_rate = 48000;
  214. /* maximize volume */
  215. ins->dac_volume_right = 0x8000;
  216. ins->dac_volume_left = 0x8000;
  217. ins->spdif_input_volume_right = 0x8000;
  218. ins->spdif_input_volume_left = 0x8000;
  219. /* set left and right validity bits and
  220. default channel status */
  221. ins->spdif_csuv_default =
  222. ins->spdif_csuv_stream =
  223. /* byte 0 */ ((unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF & 0xff)) << 24) |
  224. /* byte 1 */ ((unsigned int)_wrap_all_bits( ((SNDRV_PCM_DEFAULT_CON_SPDIF >> 8) & 0xff)) << 16) |
  225. /* byte 3 */ (unsigned int)_wrap_all_bits( (SNDRV_PCM_DEFAULT_CON_SPDIF >> 24) & 0xff) |
  226. /* left and right validity bits */ (1 << 13) | (1 << 12);
  227. return ins;
  228. error:
  229. kfree(ins);
  230. return NULL;
  231. }
  232. void cs46xx_dsp_spos_destroy (struct snd_cs46xx * chip)
  233. {
  234. int i;
  235. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  236. snd_assert(ins != NULL, return);
  237. mutex_lock(&chip->spos_mutex);
  238. for (i = 0; i < ins->nscb; ++i) {
  239. if (ins->scbs[i].deleted) continue;
  240. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  241. }
  242. kfree(ins->code.data);
  243. vfree(ins->symbol_table.symbols);
  244. kfree(ins->modules);
  245. kfree(ins);
  246. mutex_unlock(&chip->spos_mutex);
  247. }
  248. int cs46xx_dsp_load_module (struct snd_cs46xx * chip, struct dsp_module_desc * module)
  249. {
  250. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  251. struct dsp_segment_desc * code = get_segment_desc (module,SEGTYPE_SP_PROGRAM);
  252. struct dsp_segment_desc * parameter = get_segment_desc (module,SEGTYPE_SP_PARAMETER);
  253. struct dsp_segment_desc * sample = get_segment_desc (module,SEGTYPE_SP_SAMPLE);
  254. u32 doffset, dsize;
  255. if (ins->nmodules == DSP_MAX_MODULES - 1) {
  256. snd_printk(KERN_ERR "dsp_spos: to many modules loaded into DSP\n");
  257. return -ENOMEM;
  258. }
  259. snd_printdd("dsp_spos: loading module %s into DSP\n", module->module_name);
  260. if (ins->nmodules == 0) {
  261. snd_printdd("dsp_spos: clearing parameter area\n");
  262. snd_cs46xx_clear_BA1(chip, DSP_PARAMETER_BYTE_OFFSET, DSP_PARAMETER_BYTE_SIZE);
  263. }
  264. if (parameter == NULL) {
  265. snd_printdd("dsp_spos: module got no parameter segment\n");
  266. } else {
  267. if (ins->nmodules > 0) {
  268. snd_printk(KERN_WARNING "dsp_spos: WARNING current parameter data may be overwriten!\n");
  269. }
  270. doffset = (parameter->offset * 4 + DSP_PARAMETER_BYTE_OFFSET);
  271. dsize = parameter->size * 4;
  272. snd_printdd("dsp_spos: downloading parameter data to chip (%08x-%08x)\n",
  273. doffset,doffset + dsize);
  274. if (snd_cs46xx_download (chip, parameter->data, doffset, dsize)) {
  275. snd_printk(KERN_ERR "dsp_spos: failed to download parameter data to DSP\n");
  276. return -EINVAL;
  277. }
  278. }
  279. if (ins->nmodules == 0) {
  280. snd_printdd("dsp_spos: clearing sample area\n");
  281. snd_cs46xx_clear_BA1(chip, DSP_SAMPLE_BYTE_OFFSET, DSP_SAMPLE_BYTE_SIZE);
  282. }
  283. if (sample == NULL) {
  284. snd_printdd("dsp_spos: module got no sample segment\n");
  285. } else {
  286. if (ins->nmodules > 0) {
  287. snd_printk(KERN_WARNING "dsp_spos: WARNING current sample data may be overwriten\n");
  288. }
  289. doffset = (sample->offset * 4 + DSP_SAMPLE_BYTE_OFFSET);
  290. dsize = sample->size * 4;
  291. snd_printdd("dsp_spos: downloading sample data to chip (%08x-%08x)\n",
  292. doffset,doffset + dsize);
  293. if (snd_cs46xx_download (chip,sample->data,doffset,dsize)) {
  294. snd_printk(KERN_ERR "dsp_spos: failed to sample data to DSP\n");
  295. return -EINVAL;
  296. }
  297. }
  298. if (ins->nmodules == 0) {
  299. snd_printdd("dsp_spos: clearing code area\n");
  300. snd_cs46xx_clear_BA1(chip, DSP_CODE_BYTE_OFFSET, DSP_CODE_BYTE_SIZE);
  301. }
  302. if (code == NULL) {
  303. snd_printdd("dsp_spos: module got no code segment\n");
  304. } else {
  305. if (ins->code.offset + code->size > DSP_CODE_BYTE_SIZE) {
  306. snd_printk(KERN_ERR "dsp_spos: no space available in DSP\n");
  307. return -ENOMEM;
  308. }
  309. module->load_address = ins->code.offset;
  310. module->overlay_begin_address = 0x000;
  311. /* if module has a code segment it must have
  312. symbol table */
  313. snd_assert(module->symbol_table.symbols != NULL ,return -ENOMEM);
  314. if (add_symbols(chip,module)) {
  315. snd_printk(KERN_ERR "dsp_spos: failed to load symbol table\n");
  316. return -ENOMEM;
  317. }
  318. doffset = (code->offset * 4 + ins->code.offset * 4 + DSP_CODE_BYTE_OFFSET);
  319. dsize = code->size * 4;
  320. snd_printdd("dsp_spos: downloading code to chip (%08x-%08x)\n",
  321. doffset,doffset + dsize);
  322. module->nfixups = shadow_and_reallocate_code(chip,code->data,code->size,module->overlay_begin_address);
  323. if (snd_cs46xx_download (chip,(ins->code.data + ins->code.offset),doffset,dsize)) {
  324. snd_printk(KERN_ERR "dsp_spos: failed to download code to DSP\n");
  325. return -EINVAL;
  326. }
  327. ins->code.offset += code->size;
  328. }
  329. /* NOTE: module segments and symbol table must be
  330. statically allocated. Case that module data is
  331. not generated by the ospparser */
  332. ins->modules[ins->nmodules] = *module;
  333. ins->nmodules++;
  334. return 0;
  335. }
  336. struct dsp_symbol_entry *
  337. cs46xx_dsp_lookup_symbol (struct snd_cs46xx * chip, char * symbol_name, int symbol_type)
  338. {
  339. int i;
  340. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  341. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  342. if (ins->symbol_table.symbols[i].deleted)
  343. continue;
  344. if (!strcmp(ins->symbol_table.symbols[i].symbol_name,symbol_name) &&
  345. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  346. return (ins->symbol_table.symbols + i);
  347. }
  348. }
  349. #if 0
  350. printk ("dsp_spos: symbol <%s> type %02x not found\n",
  351. symbol_name,symbol_type);
  352. #endif
  353. return NULL;
  354. }
  355. #ifdef CONFIG_PROC_FS
  356. static struct dsp_symbol_entry *
  357. cs46xx_dsp_lookup_symbol_addr (struct snd_cs46xx * chip, u32 address, int symbol_type)
  358. {
  359. int i;
  360. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  361. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  362. if (ins->symbol_table.symbols[i].deleted)
  363. continue;
  364. if (ins->symbol_table.symbols[i].address == address &&
  365. ins->symbol_table.symbols[i].symbol_type == symbol_type) {
  366. return (ins->symbol_table.symbols + i);
  367. }
  368. }
  369. return NULL;
  370. }
  371. static void cs46xx_dsp_proc_symbol_table_read (struct snd_info_entry *entry,
  372. struct snd_info_buffer *buffer)
  373. {
  374. struct snd_cs46xx *chip = entry->private_data;
  375. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  376. int i;
  377. snd_iprintf(buffer, "SYMBOLS:\n");
  378. for ( i = 0; i < ins->symbol_table.nsymbols; ++i ) {
  379. char *module_str = "system";
  380. if (ins->symbol_table.symbols[i].deleted)
  381. continue;
  382. if (ins->symbol_table.symbols[i].module != NULL) {
  383. module_str = ins->symbol_table.symbols[i].module->module_name;
  384. }
  385. snd_iprintf(buffer, "%04X <%02X> %s [%s]\n",
  386. ins->symbol_table.symbols[i].address,
  387. ins->symbol_table.symbols[i].symbol_type,
  388. ins->symbol_table.symbols[i].symbol_name,
  389. module_str);
  390. }
  391. }
  392. static void cs46xx_dsp_proc_modules_read (struct snd_info_entry *entry,
  393. struct snd_info_buffer *buffer)
  394. {
  395. struct snd_cs46xx *chip = entry->private_data;
  396. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  397. int i,j;
  398. mutex_lock(&chip->spos_mutex);
  399. snd_iprintf(buffer, "MODULES:\n");
  400. for ( i = 0; i < ins->nmodules; ++i ) {
  401. snd_iprintf(buffer, "\n%s:\n", ins->modules[i].module_name);
  402. snd_iprintf(buffer, " %d symbols\n", ins->modules[i].symbol_table.nsymbols);
  403. snd_iprintf(buffer, " %d fixups\n", ins->modules[i].nfixups);
  404. for (j = 0; j < ins->modules[i].nsegments; ++ j) {
  405. struct dsp_segment_desc * desc = (ins->modules[i].segments + j);
  406. snd_iprintf(buffer, " segment %02x offset %08x size %08x\n",
  407. desc->segment_type,desc->offset, desc->size);
  408. }
  409. }
  410. mutex_unlock(&chip->spos_mutex);
  411. }
  412. static void cs46xx_dsp_proc_task_tree_read (struct snd_info_entry *entry,
  413. struct snd_info_buffer *buffer)
  414. {
  415. struct snd_cs46xx *chip = entry->private_data;
  416. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  417. int i, j, col;
  418. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  419. mutex_lock(&chip->spos_mutex);
  420. snd_iprintf(buffer, "TASK TREES:\n");
  421. for ( i = 0; i < ins->ntask; ++i) {
  422. snd_iprintf(buffer,"\n%04x %s:\n",ins->tasks[i].address,ins->tasks[i].task_name);
  423. for (col = 0,j = 0;j < ins->tasks[i].size; j++,col++) {
  424. u32 val;
  425. if (col == 4) {
  426. snd_iprintf(buffer,"\n");
  427. col = 0;
  428. }
  429. val = readl(dst + (ins->tasks[i].address + j) * sizeof(u32));
  430. snd_iprintf(buffer,"%08x ",val);
  431. }
  432. }
  433. snd_iprintf(buffer,"\n");
  434. mutex_unlock(&chip->spos_mutex);
  435. }
  436. static void cs46xx_dsp_proc_scb_read (struct snd_info_entry *entry,
  437. struct snd_info_buffer *buffer)
  438. {
  439. struct snd_cs46xx *chip = entry->private_data;
  440. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  441. int i;
  442. mutex_lock(&chip->spos_mutex);
  443. snd_iprintf(buffer, "SCB's:\n");
  444. for ( i = 0; i < ins->nscb; ++i) {
  445. if (ins->scbs[i].deleted)
  446. continue;
  447. snd_iprintf(buffer,"\n%04x %s:\n\n",ins->scbs[i].address,ins->scbs[i].scb_name);
  448. if (ins->scbs[i].parent_scb_ptr != NULL) {
  449. snd_iprintf(buffer,"parent [%s:%04x] ",
  450. ins->scbs[i].parent_scb_ptr->scb_name,
  451. ins->scbs[i].parent_scb_ptr->address);
  452. } else snd_iprintf(buffer,"parent [none] ");
  453. snd_iprintf(buffer,"sub_list_ptr [%s:%04x]\nnext_scb_ptr [%s:%04x] task_entry [%s:%04x]\n",
  454. ins->scbs[i].sub_list_ptr->scb_name,
  455. ins->scbs[i].sub_list_ptr->address,
  456. ins->scbs[i].next_scb_ptr->scb_name,
  457. ins->scbs[i].next_scb_ptr->address,
  458. ins->scbs[i].task_entry->symbol_name,
  459. ins->scbs[i].task_entry->address);
  460. }
  461. snd_iprintf(buffer,"\n");
  462. mutex_unlock(&chip->spos_mutex);
  463. }
  464. static void cs46xx_dsp_proc_parameter_dump_read (struct snd_info_entry *entry,
  465. struct snd_info_buffer *buffer)
  466. {
  467. struct snd_cs46xx *chip = entry->private_data;
  468. /*struct dsp_spos_instance * ins = chip->dsp_spos_instance; */
  469. unsigned int i, col = 0;
  470. void __iomem *dst = chip->region.idx[1].remap_addr + DSP_PARAMETER_BYTE_OFFSET;
  471. struct dsp_symbol_entry * symbol;
  472. for (i = 0;i < DSP_PARAMETER_BYTE_SIZE; i += sizeof(u32),col ++) {
  473. if (col == 4) {
  474. snd_iprintf(buffer,"\n");
  475. col = 0;
  476. }
  477. if ( (symbol = cs46xx_dsp_lookup_symbol_addr (chip,i / sizeof(u32), SYMBOL_PARAMETER)) != NULL) {
  478. col = 0;
  479. snd_iprintf (buffer,"\n%s:\n",symbol->symbol_name);
  480. }
  481. if (col == 0) {
  482. snd_iprintf(buffer, "%04X ", i / (unsigned int)sizeof(u32));
  483. }
  484. snd_iprintf(buffer,"%08X ",readl(dst + i));
  485. }
  486. }
  487. static void cs46xx_dsp_proc_sample_dump_read (struct snd_info_entry *entry,
  488. struct snd_info_buffer *buffer)
  489. {
  490. struct snd_cs46xx *chip = entry->private_data;
  491. int i,col = 0;
  492. void __iomem *dst = chip->region.idx[2].remap_addr;
  493. snd_iprintf(buffer,"PCMREADER:\n");
  494. for (i = PCM_READER_BUF1;i < PCM_READER_BUF1 + 0x30; i += sizeof(u32),col ++) {
  495. if (col == 4) {
  496. snd_iprintf(buffer,"\n");
  497. col = 0;
  498. }
  499. if (col == 0) {
  500. snd_iprintf(buffer, "%04X ",i);
  501. }
  502. snd_iprintf(buffer,"%08X ",readl(dst + i));
  503. }
  504. snd_iprintf(buffer,"\nMIX_SAMPLE_BUF1:\n");
  505. col = 0;
  506. for (i = MIX_SAMPLE_BUF1;i < MIX_SAMPLE_BUF1 + 0x40; i += sizeof(u32),col ++) {
  507. if (col == 4) {
  508. snd_iprintf(buffer,"\n");
  509. col = 0;
  510. }
  511. if (col == 0) {
  512. snd_iprintf(buffer, "%04X ",i);
  513. }
  514. snd_iprintf(buffer,"%08X ",readl(dst + i));
  515. }
  516. snd_iprintf(buffer,"\nSRC_TASK_SCB1:\n");
  517. col = 0;
  518. for (i = 0x2480 ; i < 0x2480 + 0x40 ; i += sizeof(u32),col ++) {
  519. if (col == 4) {
  520. snd_iprintf(buffer,"\n");
  521. col = 0;
  522. }
  523. if (col == 0) {
  524. snd_iprintf(buffer, "%04X ",i);
  525. }
  526. snd_iprintf(buffer,"%08X ",readl(dst + i));
  527. }
  528. snd_iprintf(buffer,"\nSPDIFO_BUFFER:\n");
  529. col = 0;
  530. for (i = SPDIFO_IP_OUTPUT_BUFFER1;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x30; i += sizeof(u32),col ++) {
  531. if (col == 4) {
  532. snd_iprintf(buffer,"\n");
  533. col = 0;
  534. }
  535. if (col == 0) {
  536. snd_iprintf(buffer, "%04X ",i);
  537. }
  538. snd_iprintf(buffer,"%08X ",readl(dst + i));
  539. }
  540. snd_iprintf(buffer,"\n...\n");
  541. col = 0;
  542. for (i = SPDIFO_IP_OUTPUT_BUFFER1+0xD0;i < SPDIFO_IP_OUTPUT_BUFFER1 + 0x110; i += sizeof(u32),col ++) {
  543. if (col == 4) {
  544. snd_iprintf(buffer,"\n");
  545. col = 0;
  546. }
  547. if (col == 0) {
  548. snd_iprintf(buffer, "%04X ",i);
  549. }
  550. snd_iprintf(buffer,"%08X ",readl(dst + i));
  551. }
  552. snd_iprintf(buffer,"\nOUTPUT_SNOOP:\n");
  553. col = 0;
  554. for (i = OUTPUT_SNOOP_BUFFER;i < OUTPUT_SNOOP_BUFFER + 0x40; i += sizeof(u32),col ++) {
  555. if (col == 4) {
  556. snd_iprintf(buffer,"\n");
  557. col = 0;
  558. }
  559. if (col == 0) {
  560. snd_iprintf(buffer, "%04X ",i);
  561. }
  562. snd_iprintf(buffer,"%08X ",readl(dst + i));
  563. }
  564. snd_iprintf(buffer,"\nCODEC_INPUT_BUF1: \n");
  565. col = 0;
  566. for (i = CODEC_INPUT_BUF1;i < CODEC_INPUT_BUF1 + 0x40; i += sizeof(u32),col ++) {
  567. if (col == 4) {
  568. snd_iprintf(buffer,"\n");
  569. col = 0;
  570. }
  571. if (col == 0) {
  572. snd_iprintf(buffer, "%04X ",i);
  573. }
  574. snd_iprintf(buffer,"%08X ",readl(dst + i));
  575. }
  576. #if 0
  577. snd_iprintf(buffer,"\nWRITE_BACK_BUF1: \n");
  578. col = 0;
  579. for (i = WRITE_BACK_BUF1;i < WRITE_BACK_BUF1 + 0x40; i += sizeof(u32),col ++) {
  580. if (col == 4) {
  581. snd_iprintf(buffer,"\n");
  582. col = 0;
  583. }
  584. if (col == 0) {
  585. snd_iprintf(buffer, "%04X ",i);
  586. }
  587. snd_iprintf(buffer,"%08X ",readl(dst + i));
  588. }
  589. #endif
  590. snd_iprintf(buffer,"\nSPDIFI_IP_OUTPUT_BUFFER1: \n");
  591. col = 0;
  592. for (i = SPDIFI_IP_OUTPUT_BUFFER1;i < SPDIFI_IP_OUTPUT_BUFFER1 + 0x80; i += sizeof(u32),col ++) {
  593. if (col == 4) {
  594. snd_iprintf(buffer,"\n");
  595. col = 0;
  596. }
  597. if (col == 0) {
  598. snd_iprintf(buffer, "%04X ",i);
  599. }
  600. snd_iprintf(buffer,"%08X ",readl(dst + i));
  601. }
  602. snd_iprintf(buffer,"\n");
  603. }
  604. int cs46xx_dsp_proc_init (struct snd_card *card, struct snd_cs46xx *chip)
  605. {
  606. struct snd_info_entry *entry;
  607. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  608. int i;
  609. ins->snd_card = card;
  610. if ((entry = snd_info_create_card_entry(card, "dsp", card->proc_root)) != NULL) {
  611. entry->content = SNDRV_INFO_CONTENT_TEXT;
  612. entry->mode = S_IFDIR | S_IRUGO | S_IXUGO;
  613. if (snd_info_register(entry) < 0) {
  614. snd_info_free_entry(entry);
  615. entry = NULL;
  616. }
  617. }
  618. ins->proc_dsp_dir = entry;
  619. if (!ins->proc_dsp_dir)
  620. return -ENOMEM;
  621. if ((entry = snd_info_create_card_entry(card, "spos_symbols", ins->proc_dsp_dir)) != NULL) {
  622. entry->content = SNDRV_INFO_CONTENT_TEXT;
  623. entry->private_data = chip;
  624. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  625. entry->c.text.read = cs46xx_dsp_proc_symbol_table_read;
  626. if (snd_info_register(entry) < 0) {
  627. snd_info_free_entry(entry);
  628. entry = NULL;
  629. }
  630. }
  631. ins->proc_sym_info_entry = entry;
  632. if ((entry = snd_info_create_card_entry(card, "spos_modules", ins->proc_dsp_dir)) != NULL) {
  633. entry->content = SNDRV_INFO_CONTENT_TEXT;
  634. entry->private_data = chip;
  635. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  636. entry->c.text.read = cs46xx_dsp_proc_modules_read;
  637. if (snd_info_register(entry) < 0) {
  638. snd_info_free_entry(entry);
  639. entry = NULL;
  640. }
  641. }
  642. ins->proc_modules_info_entry = entry;
  643. if ((entry = snd_info_create_card_entry(card, "parameter", ins->proc_dsp_dir)) != NULL) {
  644. entry->content = SNDRV_INFO_CONTENT_TEXT;
  645. entry->private_data = chip;
  646. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  647. entry->c.text.read = cs46xx_dsp_proc_parameter_dump_read;
  648. if (snd_info_register(entry) < 0) {
  649. snd_info_free_entry(entry);
  650. entry = NULL;
  651. }
  652. }
  653. ins->proc_parameter_dump_info_entry = entry;
  654. if ((entry = snd_info_create_card_entry(card, "sample", ins->proc_dsp_dir)) != NULL) {
  655. entry->content = SNDRV_INFO_CONTENT_TEXT;
  656. entry->private_data = chip;
  657. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  658. entry->c.text.read = cs46xx_dsp_proc_sample_dump_read;
  659. if (snd_info_register(entry) < 0) {
  660. snd_info_free_entry(entry);
  661. entry = NULL;
  662. }
  663. }
  664. ins->proc_sample_dump_info_entry = entry;
  665. if ((entry = snd_info_create_card_entry(card, "task_tree", ins->proc_dsp_dir)) != NULL) {
  666. entry->content = SNDRV_INFO_CONTENT_TEXT;
  667. entry->private_data = chip;
  668. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  669. entry->c.text.read = cs46xx_dsp_proc_task_tree_read;
  670. if (snd_info_register(entry) < 0) {
  671. snd_info_free_entry(entry);
  672. entry = NULL;
  673. }
  674. }
  675. ins->proc_task_info_entry = entry;
  676. if ((entry = snd_info_create_card_entry(card, "scb_info", ins->proc_dsp_dir)) != NULL) {
  677. entry->content = SNDRV_INFO_CONTENT_TEXT;
  678. entry->private_data = chip;
  679. entry->mode = S_IFREG | S_IRUGO | S_IWUSR;
  680. entry->c.text.read = cs46xx_dsp_proc_scb_read;
  681. if (snd_info_register(entry) < 0) {
  682. snd_info_free_entry(entry);
  683. entry = NULL;
  684. }
  685. }
  686. ins->proc_scb_info_entry = entry;
  687. mutex_lock(&chip->spos_mutex);
  688. /* register/update SCB's entries on proc */
  689. for (i = 0; i < ins->nscb; ++i) {
  690. if (ins->scbs[i].deleted) continue;
  691. cs46xx_dsp_proc_register_scb_desc (chip, (ins->scbs + i));
  692. }
  693. mutex_unlock(&chip->spos_mutex);
  694. return 0;
  695. }
  696. int cs46xx_dsp_proc_done (struct snd_cs46xx *chip)
  697. {
  698. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  699. int i;
  700. snd_info_free_entry(ins->proc_sym_info_entry);
  701. ins->proc_sym_info_entry = NULL;
  702. snd_info_free_entry(ins->proc_modules_info_entry);
  703. ins->proc_modules_info_entry = NULL;
  704. snd_info_free_entry(ins->proc_parameter_dump_info_entry);
  705. ins->proc_parameter_dump_info_entry = NULL;
  706. snd_info_free_entry(ins->proc_sample_dump_info_entry);
  707. ins->proc_sample_dump_info_entry = NULL;
  708. snd_info_free_entry(ins->proc_scb_info_entry);
  709. ins->proc_scb_info_entry = NULL;
  710. snd_info_free_entry(ins->proc_task_info_entry);
  711. ins->proc_task_info_entry = NULL;
  712. mutex_lock(&chip->spos_mutex);
  713. for (i = 0; i < ins->nscb; ++i) {
  714. if (ins->scbs[i].deleted) continue;
  715. cs46xx_dsp_proc_free_scb_desc ( (ins->scbs + i) );
  716. }
  717. mutex_unlock(&chip->spos_mutex);
  718. snd_info_free_entry(ins->proc_dsp_dir);
  719. ins->proc_dsp_dir = NULL;
  720. return 0;
  721. }
  722. #endif /* CONFIG_PROC_FS */
  723. static int debug_tree;
  724. static void _dsp_create_task_tree (struct snd_cs46xx *chip, u32 * task_data,
  725. u32 dest, int size)
  726. {
  727. void __iomem *spdst = chip->region.idx[1].remap_addr +
  728. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  729. int i;
  730. for (i = 0; i < size; ++i) {
  731. if (debug_tree) printk ("addr %p, val %08x\n",spdst,task_data[i]);
  732. writel(task_data[i],spdst);
  733. spdst += sizeof(u32);
  734. }
  735. }
  736. static int debug_scb;
  737. static void _dsp_create_scb (struct snd_cs46xx *chip, u32 * scb_data, u32 dest)
  738. {
  739. void __iomem *spdst = chip->region.idx[1].remap_addr +
  740. DSP_PARAMETER_BYTE_OFFSET + dest * sizeof(u32);
  741. int i;
  742. for (i = 0; i < 0x10; ++i) {
  743. if (debug_scb) printk ("addr %p, val %08x\n",spdst,scb_data[i]);
  744. writel(scb_data[i],spdst);
  745. spdst += sizeof(u32);
  746. }
  747. }
  748. static int find_free_scb_index (struct dsp_spos_instance * ins)
  749. {
  750. int index = ins->nscb, i;
  751. for (i = ins->scb_highest_frag_index; i < ins->nscb; ++i) {
  752. if (ins->scbs[i].deleted) {
  753. index = i;
  754. break;
  755. }
  756. }
  757. return index;
  758. }
  759. static struct dsp_scb_descriptor * _map_scb (struct snd_cs46xx *chip, char * name, u32 dest)
  760. {
  761. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  762. struct dsp_scb_descriptor * desc = NULL;
  763. int index;
  764. if (ins->nscb == DSP_MAX_SCB_DESC - 1) {
  765. snd_printk(KERN_ERR "dsp_spos: got no place for other SCB\n");
  766. return NULL;
  767. }
  768. index = find_free_scb_index (ins);
  769. strcpy(ins->scbs[index].scb_name, name);
  770. ins->scbs[index].address = dest;
  771. ins->scbs[index].index = index;
  772. ins->scbs[index].proc_info = NULL;
  773. ins->scbs[index].ref_count = 1;
  774. ins->scbs[index].deleted = 0;
  775. spin_lock_init(&ins->scbs[index].lock);
  776. desc = (ins->scbs + index);
  777. ins->scbs[index].scb_symbol = add_symbol (chip, name, dest, SYMBOL_PARAMETER);
  778. if (index > ins->scb_highest_frag_index)
  779. ins->scb_highest_frag_index = index;
  780. if (index == ins->nscb)
  781. ins->nscb++;
  782. return desc;
  783. }
  784. static struct dsp_task_descriptor *
  785. _map_task_tree (struct snd_cs46xx *chip, char * name, u32 dest, u32 size)
  786. {
  787. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  788. struct dsp_task_descriptor * desc = NULL;
  789. if (ins->ntask == DSP_MAX_TASK_DESC - 1) {
  790. snd_printk(KERN_ERR "dsp_spos: got no place for other TASK\n");
  791. return NULL;
  792. }
  793. strcpy(ins->tasks[ins->ntask].task_name,name);
  794. ins->tasks[ins->ntask].address = dest;
  795. ins->tasks[ins->ntask].size = size;
  796. /* quick find in list */
  797. ins->tasks[ins->ntask].index = ins->ntask;
  798. desc = (ins->tasks + ins->ntask);
  799. ins->ntask++;
  800. add_symbol (chip,name,dest,SYMBOL_PARAMETER);
  801. return desc;
  802. }
  803. struct dsp_scb_descriptor *
  804. cs46xx_dsp_create_scb (struct snd_cs46xx *chip, char * name, u32 * scb_data, u32 dest)
  805. {
  806. struct dsp_scb_descriptor * desc;
  807. desc = _map_scb (chip,name,dest);
  808. if (desc) {
  809. _dsp_create_scb(chip,scb_data,dest);
  810. } else {
  811. snd_printk(KERN_ERR "dsp_spos: failed to map SCB\n");
  812. }
  813. return desc;
  814. }
  815. static struct dsp_task_descriptor *
  816. cs46xx_dsp_create_task_tree (struct snd_cs46xx *chip, char * name, u32 * task_data,
  817. u32 dest, int size)
  818. {
  819. struct dsp_task_descriptor * desc;
  820. desc = _map_task_tree (chip,name,dest,size);
  821. if (desc) {
  822. _dsp_create_task_tree(chip,task_data,dest,size);
  823. } else {
  824. snd_printk(KERN_ERR "dsp_spos: failed to map TASK\n");
  825. }
  826. return desc;
  827. }
  828. int cs46xx_dsp_scb_and_task_init (struct snd_cs46xx *chip)
  829. {
  830. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  831. struct dsp_symbol_entry * fg_task_tree_header_code;
  832. struct dsp_symbol_entry * task_tree_header_code;
  833. struct dsp_symbol_entry * task_tree_thread;
  834. struct dsp_symbol_entry * null_algorithm;
  835. struct dsp_symbol_entry * magic_snoop_task;
  836. struct dsp_scb_descriptor * timing_master_scb;
  837. struct dsp_scb_descriptor * codec_out_scb;
  838. struct dsp_scb_descriptor * codec_in_scb;
  839. struct dsp_scb_descriptor * src_task_scb;
  840. struct dsp_scb_descriptor * master_mix_scb;
  841. struct dsp_scb_descriptor * rear_mix_scb;
  842. struct dsp_scb_descriptor * record_mix_scb;
  843. struct dsp_scb_descriptor * write_back_scb;
  844. struct dsp_scb_descriptor * vari_decimate_scb;
  845. struct dsp_scb_descriptor * rear_codec_out_scb;
  846. struct dsp_scb_descriptor * clfe_codec_out_scb;
  847. struct dsp_scb_descriptor * magic_snoop_scb;
  848. int fifo_addr, fifo_span, valid_slots;
  849. static struct dsp_spos_control_block sposcb = {
  850. /* 0 */ HFG_TREE_SCB,HFG_STACK,
  851. /* 1 */ SPOSCB_ADDR,BG_TREE_SCB_ADDR,
  852. /* 2 */ DSP_SPOS_DC,0,
  853. /* 3 */ DSP_SPOS_DC,DSP_SPOS_DC,
  854. /* 4 */ 0,0,
  855. /* 5 */ DSP_SPOS_UU,0,
  856. /* 6 */ FG_TASK_HEADER_ADDR,0,
  857. /* 7 */ 0,0,
  858. /* 8 */ DSP_SPOS_UU,DSP_SPOS_DC,
  859. /* 9 */ 0,
  860. /* A */ 0,HFG_FIRST_EXECUTE_MODE,
  861. /* B */ DSP_SPOS_UU,DSP_SPOS_UU,
  862. /* C */ DSP_SPOS_DC_DC,
  863. /* D */ DSP_SPOS_DC_DC,
  864. /* E */ DSP_SPOS_DC_DC,
  865. /* F */ DSP_SPOS_DC_DC
  866. };
  867. cs46xx_dsp_create_task_tree(chip, "sposCB", (u32 *)&sposcb, SPOSCB_ADDR, 0x10);
  868. null_algorithm = cs46xx_dsp_lookup_symbol(chip, "NULLALGORITHM", SYMBOL_CODE);
  869. if (null_algorithm == NULL) {
  870. snd_printk(KERN_ERR "dsp_spos: symbol NULLALGORITHM not found\n");
  871. return -EIO;
  872. }
  873. fg_task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "FGTASKTREEHEADERCODE", SYMBOL_CODE);
  874. if (fg_task_tree_header_code == NULL) {
  875. snd_printk(KERN_ERR "dsp_spos: symbol FGTASKTREEHEADERCODE not found\n");
  876. return -EIO;
  877. }
  878. task_tree_header_code = cs46xx_dsp_lookup_symbol(chip, "TASKTREEHEADERCODE", SYMBOL_CODE);
  879. if (task_tree_header_code == NULL) {
  880. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREEHEADERCODE not found\n");
  881. return -EIO;
  882. }
  883. task_tree_thread = cs46xx_dsp_lookup_symbol(chip, "TASKTREETHREAD", SYMBOL_CODE);
  884. if (task_tree_thread == NULL) {
  885. snd_printk(KERN_ERR "dsp_spos: symbol TASKTREETHREAD not found\n");
  886. return -EIO;
  887. }
  888. magic_snoop_task = cs46xx_dsp_lookup_symbol(chip, "MAGICSNOOPTASK", SYMBOL_CODE);
  889. if (magic_snoop_task == NULL) {
  890. snd_printk(KERN_ERR "dsp_spos: symbol MAGICSNOOPTASK not found\n");
  891. return -EIO;
  892. }
  893. {
  894. /* create the null SCB */
  895. static struct dsp_generic_scb null_scb = {
  896. { 0, 0, 0, 0 },
  897. { 0, 0, 0, 0, 0 },
  898. NULL_SCB_ADDR, NULL_SCB_ADDR,
  899. 0, 0, 0, 0, 0,
  900. {
  901. 0,0,
  902. 0,0,
  903. }
  904. };
  905. null_scb.entry_point = null_algorithm->address;
  906. ins->the_null_scb = cs46xx_dsp_create_scb(chip, "nullSCB", (u32 *)&null_scb, NULL_SCB_ADDR);
  907. ins->the_null_scb->task_entry = null_algorithm;
  908. ins->the_null_scb->sub_list_ptr = ins->the_null_scb;
  909. ins->the_null_scb->next_scb_ptr = ins->the_null_scb;
  910. ins->the_null_scb->parent_scb_ptr = NULL;
  911. cs46xx_dsp_proc_register_scb_desc (chip,ins->the_null_scb);
  912. }
  913. {
  914. /* setup foreground task tree */
  915. static struct dsp_task_tree_control_block fg_task_tree_hdr = {
  916. { FG_TASK_HEADER_ADDR | (DSP_SPOS_DC << 0x10),
  917. DSP_SPOS_DC_DC,
  918. DSP_SPOS_DC_DC,
  919. 0x0000,DSP_SPOS_DC,
  920. DSP_SPOS_DC, DSP_SPOS_DC,
  921. DSP_SPOS_DC_DC,
  922. DSP_SPOS_DC_DC,
  923. DSP_SPOS_DC_DC,
  924. DSP_SPOS_DC,DSP_SPOS_DC },
  925. {
  926. BG_TREE_SCB_ADDR,TIMINGMASTER_SCB_ADDR,
  927. 0,
  928. FG_TASK_HEADER_ADDR + TCBData,
  929. },
  930. {
  931. 4,0,
  932. 1,0,
  933. 2,SPOSCB_ADDR + HFGFlags,
  934. 0,0,
  935. FG_TASK_HEADER_ADDR + TCBContextBlk,FG_STACK
  936. },
  937. {
  938. DSP_SPOS_DC,0,
  939. DSP_SPOS_DC,DSP_SPOS_DC,
  940. DSP_SPOS_DC,DSP_SPOS_DC,
  941. DSP_SPOS_DC,DSP_SPOS_DC,
  942. DSP_SPOS_DC,DSP_SPOS_DC,
  943. DSP_SPOS_DCDC,
  944. DSP_SPOS_UU,1,
  945. DSP_SPOS_DCDC,
  946. DSP_SPOS_DCDC,
  947. DSP_SPOS_DCDC,
  948. DSP_SPOS_DCDC,
  949. DSP_SPOS_DCDC,
  950. DSP_SPOS_DCDC,
  951. DSP_SPOS_DCDC,
  952. DSP_SPOS_DCDC,
  953. DSP_SPOS_DCDC,
  954. DSP_SPOS_DCDC,
  955. DSP_SPOS_DCDC,
  956. DSP_SPOS_DCDC,
  957. DSP_SPOS_DCDC,
  958. DSP_SPOS_DCDC,
  959. DSP_SPOS_DCDC,
  960. DSP_SPOS_DCDC,
  961. DSP_SPOS_DCDC,
  962. DSP_SPOS_DCDC,
  963. DSP_SPOS_DCDC,
  964. DSP_SPOS_DCDC,
  965. DSP_SPOS_DCDC,
  966. DSP_SPOS_DCDC,
  967. DSP_SPOS_DCDC,
  968. DSP_SPOS_DCDC,
  969. DSP_SPOS_DCDC,
  970. DSP_SPOS_DCDC,
  971. DSP_SPOS_DCDC,
  972. DSP_SPOS_DCDC
  973. },
  974. {
  975. FG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  976. 0,0
  977. }
  978. };
  979. fg_task_tree_hdr.links.entry_point = fg_task_tree_header_code->address;
  980. fg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  981. cs46xx_dsp_create_task_tree(chip,"FGtaskTreeHdr",(u32 *)&fg_task_tree_hdr,FG_TASK_HEADER_ADDR,0x35);
  982. }
  983. {
  984. /* setup foreground task tree */
  985. static struct dsp_task_tree_control_block bg_task_tree_hdr = {
  986. { DSP_SPOS_DC_DC,
  987. DSP_SPOS_DC_DC,
  988. DSP_SPOS_DC_DC,
  989. DSP_SPOS_DC, DSP_SPOS_DC,
  990. DSP_SPOS_DC, DSP_SPOS_DC,
  991. DSP_SPOS_DC_DC,
  992. DSP_SPOS_DC_DC,
  993. DSP_SPOS_DC_DC,
  994. DSP_SPOS_DC,DSP_SPOS_DC },
  995. {
  996. NULL_SCB_ADDR,NULL_SCB_ADDR, /* Set up the background to do nothing */
  997. 0,
  998. BG_TREE_SCB_ADDR + TCBData,
  999. },
  1000. {
  1001. 9999,0,
  1002. 0,1,
  1003. 0,SPOSCB_ADDR + HFGFlags,
  1004. 0,0,
  1005. BG_TREE_SCB_ADDR + TCBContextBlk,BG_STACK
  1006. },
  1007. {
  1008. DSP_SPOS_DC,0,
  1009. DSP_SPOS_DC,DSP_SPOS_DC,
  1010. DSP_SPOS_DC,DSP_SPOS_DC,
  1011. DSP_SPOS_DC,DSP_SPOS_DC,
  1012. DSP_SPOS_DC,DSP_SPOS_DC,
  1013. DSP_SPOS_DCDC,
  1014. DSP_SPOS_UU,1,
  1015. DSP_SPOS_DCDC,
  1016. DSP_SPOS_DCDC,
  1017. DSP_SPOS_DCDC,
  1018. DSP_SPOS_DCDC,
  1019. DSP_SPOS_DCDC,
  1020. DSP_SPOS_DCDC,
  1021. DSP_SPOS_DCDC,
  1022. DSP_SPOS_DCDC,
  1023. DSP_SPOS_DCDC,
  1024. DSP_SPOS_DCDC,
  1025. DSP_SPOS_DCDC,
  1026. DSP_SPOS_DCDC,
  1027. DSP_SPOS_DCDC,
  1028. DSP_SPOS_DCDC,
  1029. DSP_SPOS_DCDC,
  1030. DSP_SPOS_DCDC,
  1031. DSP_SPOS_DCDC,
  1032. DSP_SPOS_DCDC,
  1033. DSP_SPOS_DCDC,
  1034. DSP_SPOS_DCDC,
  1035. DSP_SPOS_DCDC,
  1036. DSP_SPOS_DCDC,
  1037. DSP_SPOS_DCDC,
  1038. DSP_SPOS_DCDC,
  1039. DSP_SPOS_DCDC,
  1040. DSP_SPOS_DCDC,
  1041. DSP_SPOS_DCDC,
  1042. DSP_SPOS_DCDC
  1043. },
  1044. {
  1045. BG_INTERVAL_TIMER_PERIOD,DSP_SPOS_UU,
  1046. 0,0
  1047. }
  1048. };
  1049. bg_task_tree_hdr.links.entry_point = task_tree_header_code->address;
  1050. bg_task_tree_hdr.context_blk.stack0 = task_tree_thread->address;
  1051. cs46xx_dsp_create_task_tree(chip,"BGtaskTreeHdr",(u32 *)&bg_task_tree_hdr,BG_TREE_SCB_ADDR,0x35);
  1052. }
  1053. /* create timing master SCB */
  1054. timing_master_scb = cs46xx_dsp_create_timing_master_scb(chip);
  1055. /* create the CODEC output task */
  1056. codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_I",0x0010,0x0000,
  1057. MASTERMIX_SCB_ADDR,
  1058. CODECOUT_SCB_ADDR,timing_master_scb,
  1059. SCB_ON_PARENT_SUBLIST_SCB);
  1060. if (!codec_out_scb) goto _fail_end;
  1061. /* create the master mix SCB */
  1062. master_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"MasterMixSCB",
  1063. MIX_SAMPLE_BUF1,MASTERMIX_SCB_ADDR,
  1064. codec_out_scb,
  1065. SCB_ON_PARENT_SUBLIST_SCB);
  1066. ins->master_mix_scb = master_mix_scb;
  1067. if (!master_mix_scb) goto _fail_end;
  1068. /* create codec in */
  1069. codec_in_scb = cs46xx_dsp_create_codec_in_scb(chip,"CodecInSCB",0x0010,0x00A0,
  1070. CODEC_INPUT_BUF1,
  1071. CODECIN_SCB_ADDR,codec_out_scb,
  1072. SCB_ON_PARENT_NEXT_SCB);
  1073. if (!codec_in_scb) goto _fail_end;
  1074. ins->codec_in_scb = codec_in_scb;
  1075. /* create write back scb */
  1076. write_back_scb = cs46xx_dsp_create_mix_to_ostream_scb(chip,"WriteBackSCB",
  1077. WRITE_BACK_BUF1,WRITE_BACK_SPB,
  1078. WRITEBACK_SCB_ADDR,
  1079. timing_master_scb,
  1080. SCB_ON_PARENT_NEXT_SCB);
  1081. if (!write_back_scb) goto _fail_end;
  1082. {
  1083. static struct dsp_mix2_ostream_spb mix2_ostream_spb = {
  1084. 0x00020000,
  1085. 0x0000ffff
  1086. };
  1087. /* dirty hack ... */
  1088. _dsp_create_task_tree (chip,(u32 *)&mix2_ostream_spb,WRITE_BACK_SPB,2);
  1089. }
  1090. /* input sample converter */
  1091. vari_decimate_scb = cs46xx_dsp_create_vari_decimate_scb(chip,"VariDecimateSCB",
  1092. VARI_DECIMATE_BUF0,
  1093. VARI_DECIMATE_BUF1,
  1094. VARIDECIMATE_SCB_ADDR,
  1095. write_back_scb,
  1096. SCB_ON_PARENT_SUBLIST_SCB);
  1097. if (!vari_decimate_scb) goto _fail_end;
  1098. /* create the record mixer SCB */
  1099. record_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RecordMixerSCB",
  1100. MIX_SAMPLE_BUF2,
  1101. RECORD_MIXER_SCB_ADDR,
  1102. vari_decimate_scb,
  1103. SCB_ON_PARENT_SUBLIST_SCB);
  1104. ins->record_mixer_scb = record_mix_scb;
  1105. if (!record_mix_scb) goto _fail_end;
  1106. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  1107. snd_assert (chip->nr_ac97_codecs == 1 || chip->nr_ac97_codecs == 2);
  1108. if (chip->nr_ac97_codecs == 1) {
  1109. /* output on slot 5 and 11
  1110. on primary CODEC */
  1111. fifo_addr = 0x20;
  1112. fifo_span = 0x60;
  1113. /* enable slot 5 and 11 */
  1114. valid_slots |= ACOSV_SLV5 | ACOSV_SLV11;
  1115. } else {
  1116. /* output on slot 7 and 8
  1117. on secondary CODEC */
  1118. fifo_addr = 0x40;
  1119. fifo_span = 0x10;
  1120. /* enable slot 7 and 8 */
  1121. valid_slots |= ACOSV_SLV7 | ACOSV_SLV8;
  1122. }
  1123. /* create CODEC tasklet for rear speakers output*/
  1124. rear_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_Rear",fifo_span,fifo_addr,
  1125. REAR_MIXER_SCB_ADDR,
  1126. REAR_CODECOUT_SCB_ADDR,codec_in_scb,
  1127. SCB_ON_PARENT_NEXT_SCB);
  1128. if (!rear_codec_out_scb) goto _fail_end;
  1129. /* create the rear PCM channel mixer SCB */
  1130. rear_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"RearMixerSCB",
  1131. MIX_SAMPLE_BUF3,
  1132. REAR_MIXER_SCB_ADDR,
  1133. rear_codec_out_scb,
  1134. SCB_ON_PARENT_SUBLIST_SCB);
  1135. ins->rear_mix_scb = rear_mix_scb;
  1136. if (!rear_mix_scb) goto _fail_end;
  1137. if (chip->nr_ac97_codecs == 2) {
  1138. /* create CODEC tasklet for rear Center/LFE output
  1139. slot 6 and 9 on seconadry CODEC */
  1140. clfe_codec_out_scb = cs46xx_dsp_create_codec_out_scb(chip,"CodecOutSCB_CLFE",0x0030,0x0030,
  1141. CLFE_MIXER_SCB_ADDR,
  1142. CLFE_CODEC_SCB_ADDR,
  1143. rear_codec_out_scb,
  1144. SCB_ON_PARENT_NEXT_SCB);
  1145. if (!clfe_codec_out_scb) goto _fail_end;
  1146. /* create the rear PCM channel mixer SCB */
  1147. ins->center_lfe_mix_scb = cs46xx_dsp_create_mix_only_scb(chip,"CLFEMixerSCB",
  1148. MIX_SAMPLE_BUF4,
  1149. CLFE_MIXER_SCB_ADDR,
  1150. clfe_codec_out_scb,
  1151. SCB_ON_PARENT_SUBLIST_SCB);
  1152. if (!ins->center_lfe_mix_scb) goto _fail_end;
  1153. /* enable slot 6 and 9 */
  1154. valid_slots |= ACOSV_SLV6 | ACOSV_SLV9;
  1155. } else {
  1156. clfe_codec_out_scb = rear_codec_out_scb;
  1157. ins->center_lfe_mix_scb = rear_mix_scb;
  1158. }
  1159. /* enable slots depending on CODEC configuration */
  1160. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  1161. /* the magic snooper */
  1162. magic_snoop_scb = cs46xx_dsp_create_magic_snoop_scb (chip,"MagicSnoopSCB_I",OUTPUTSNOOP_SCB_ADDR,
  1163. OUTPUT_SNOOP_BUFFER,
  1164. codec_out_scb,
  1165. clfe_codec_out_scb,
  1166. SCB_ON_PARENT_NEXT_SCB);
  1167. if (!magic_snoop_scb) goto _fail_end;
  1168. ins->ref_snoop_scb = magic_snoop_scb;
  1169. /* SP IO access */
  1170. if (!cs46xx_dsp_create_spio_write_scb(chip,"SPIOWriteSCB",SPIOWRITE_SCB_ADDR,
  1171. magic_snoop_scb,
  1172. SCB_ON_PARENT_NEXT_SCB))
  1173. goto _fail_end;
  1174. /* SPDIF input sampel rate converter */
  1175. src_task_scb = cs46xx_dsp_create_src_task_scb(chip,"SrcTaskSCB_SPDIFI",
  1176. ins->spdif_in_sample_rate,
  1177. SRC_OUTPUT_BUF1,
  1178. SRC_DELAY_BUF1,SRCTASK_SCB_ADDR,
  1179. master_mix_scb,
  1180. SCB_ON_PARENT_SUBLIST_SCB,1);
  1181. if (!src_task_scb) goto _fail_end;
  1182. cs46xx_src_unlink(chip,src_task_scb);
  1183. /* NOTE: when we now how to detect the SPDIF input
  1184. sample rate we will use this SRC to adjust it */
  1185. ins->spdif_in_src = src_task_scb;
  1186. cs46xx_dsp_async_init(chip,timing_master_scb);
  1187. return 0;
  1188. _fail_end:
  1189. snd_printk(KERN_ERR "dsp_spos: failed to setup SCB's in DSP\n");
  1190. return -EINVAL;
  1191. }
  1192. static int cs46xx_dsp_async_init (struct snd_cs46xx *chip,
  1193. struct dsp_scb_descriptor * fg_entry)
  1194. {
  1195. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1196. struct dsp_symbol_entry * s16_async_codec_input_task;
  1197. struct dsp_symbol_entry * spdifo_task;
  1198. struct dsp_symbol_entry * spdifi_task;
  1199. struct dsp_scb_descriptor * spdifi_scb_desc, * spdifo_scb_desc, * async_codec_scb_desc;
  1200. s16_async_codec_input_task = cs46xx_dsp_lookup_symbol(chip, "S16_ASYNCCODECINPUTTASK", SYMBOL_CODE);
  1201. if (s16_async_codec_input_task == NULL) {
  1202. snd_printk(KERN_ERR "dsp_spos: symbol S16_ASYNCCODECINPUTTASK not found\n");
  1203. return -EIO;
  1204. }
  1205. spdifo_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFOTASK", SYMBOL_CODE);
  1206. if (spdifo_task == NULL) {
  1207. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFOTASK not found\n");
  1208. return -EIO;
  1209. }
  1210. spdifi_task = cs46xx_dsp_lookup_symbol(chip, "SPDIFITASK", SYMBOL_CODE);
  1211. if (spdifi_task == NULL) {
  1212. snd_printk(KERN_ERR "dsp_spos: symbol SPDIFITASK not found\n");
  1213. return -EIO;
  1214. }
  1215. {
  1216. /* 0xBC0 */
  1217. struct dsp_spdifoscb spdifo_scb = {
  1218. /* 0 */ DSP_SPOS_UUUU,
  1219. {
  1220. /* 1 */ 0xb0,
  1221. /* 2 */ 0,
  1222. /* 3 */ 0,
  1223. /* 4 */ 0,
  1224. },
  1225. /* NOTE: the SPDIF output task read samples in mono
  1226. format, the AsynchFGTxSCB task writes to buffer
  1227. in stereo format
  1228. */
  1229. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_256,
  1230. /* 6 */ ( SPDIFO_IP_OUTPUT_BUFFER1 << 0x10 ) | 0xFFFC,
  1231. /* 7 */ 0,0,
  1232. /* 8 */ 0,
  1233. /* 9 */ FG_TASK_HEADER_ADDR, NULL_SCB_ADDR,
  1234. /* A */ spdifo_task->address,
  1235. SPDIFO_SCB_INST + SPDIFOFIFOPointer,
  1236. {
  1237. /* B */ 0x0040, /*DSP_SPOS_UUUU,*/
  1238. /* C */ 0x20ff, /*DSP_SPOS_UUUU,*/
  1239. },
  1240. /* D */ 0x804c,0, /* SPDIFOFIFOPointer:SPDIFOStatRegAddr; */
  1241. /* E */ 0x0108,0x0001, /* SPDIFOStMoFormat:SPDIFOFIFOBaseAddr; */
  1242. /* F */ DSP_SPOS_UUUU /* SPDIFOFree; */
  1243. };
  1244. /* 0xBB0 */
  1245. struct dsp_spdifiscb spdifi_scb = {
  1246. /* 0 */ DSP_SPOS_UULO,DSP_SPOS_UUHI,
  1247. /* 1 */ 0,
  1248. /* 2 */ 0,
  1249. /* 3 */ 1,4000, /* SPDIFICountLimit SPDIFICount */
  1250. /* 4 */ DSP_SPOS_UUUU, /* SPDIFIStatusData */
  1251. /* 5 */ 0,DSP_SPOS_UUHI, /* StatusData, Free4 */
  1252. /* 6 */ DSP_SPOS_UUUU, /* Free3 */
  1253. /* 7 */ DSP_SPOS_UU,DSP_SPOS_DC, /* Free2 BitCount*/
  1254. /* 8 */ DSP_SPOS_UUUU, /* TempStatus */
  1255. /* 9 */ SPDIFO_SCB_INST, NULL_SCB_ADDR,
  1256. /* A */ spdifi_task->address,
  1257. SPDIFI_SCB_INST + SPDIFIFIFOPointer,
  1258. /* NOTE: The SPDIF input task write the sample in mono
  1259. format from the HW FIFO, the AsynchFGRxSCB task reads
  1260. them in stereo
  1261. */
  1262. /* B */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_128,
  1263. /* C */ (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1264. /* D */ 0x8048,0,
  1265. /* E */ 0x01f0,0x0001,
  1266. /* F */ DSP_SPOS_UUUU /* SPDIN_STATUS monitor */
  1267. };
  1268. /* 0xBA0 */
  1269. struct dsp_async_codec_input_scb async_codec_input_scb = {
  1270. /* 0 */ DSP_SPOS_UUUU,
  1271. /* 1 */ 0,
  1272. /* 2 */ 0,
  1273. /* 3 */ 1,4000,
  1274. /* 4 */ 0x0118,0x0001,
  1275. /* 5 */ RSCONFIG_SAMPLE_16MONO + RSCONFIG_MODULO_64,
  1276. /* 6 */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,
  1277. /* 7 */ DSP_SPOS_UU,0x3,
  1278. /* 8 */ DSP_SPOS_UUUU,
  1279. /* 9 */ SPDIFI_SCB_INST,NULL_SCB_ADDR,
  1280. /* A */ s16_async_codec_input_task->address,
  1281. HFG_TREE_SCB + AsyncCIOFIFOPointer,
  1282. /* B */ RSCONFIG_SAMPLE_16STEREO + RSCONFIG_MODULO_64,
  1283. /* C */ (ASYNC_IP_OUTPUT_BUFFER1 << 0x10), /*(ASYNC_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC,*/
  1284. #ifdef UseASER1Input
  1285. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1286. Init. 0000:8042: for ASER1
  1287. 0000:8044: for ASER2 */
  1288. /* D */ 0x8042,0,
  1289. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1290. Init 1 stero:8050 ASER1
  1291. Init 0 mono:8070 ASER2
  1292. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1293. /* E */ 0x0100,0x0001,
  1294. #endif
  1295. #ifdef UseASER2Input
  1296. /* short AsyncCIFIFOPointer:AsyncCIStatRegAddr;
  1297. Init. 0000:8042: for ASER1
  1298. 0000:8044: for ASER2 */
  1299. /* D */ 0x8044,0,
  1300. /* short AsyncCIStMoFormat:AsyncCIFIFOBaseAddr;
  1301. Init 1 stero:8050 ASER1
  1302. Init 0 mono:8070 ASER2
  1303. Init 1 Stereo : 0100 ASER1 (Set by script) */
  1304. /* E */ 0x0110,0x0001,
  1305. #endif
  1306. /* short AsyncCIOutputBufModulo:AsyncCIFree;
  1307. AsyncCIOutputBufModulo: The modulo size for
  1308. the output buffer of this task */
  1309. /* F */ 0, /* DSP_SPOS_UUUU */
  1310. };
  1311. spdifo_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFOSCB",(u32 *)&spdifo_scb,SPDIFO_SCB_INST);
  1312. snd_assert(spdifo_scb_desc, return -EIO);
  1313. spdifi_scb_desc = cs46xx_dsp_create_scb(chip,"SPDIFISCB",(u32 *)&spdifi_scb,SPDIFI_SCB_INST);
  1314. snd_assert(spdifi_scb_desc, return -EIO);
  1315. async_codec_scb_desc = cs46xx_dsp_create_scb(chip,"AsynCodecInputSCB",(u32 *)&async_codec_input_scb, HFG_TREE_SCB);
  1316. snd_assert(async_codec_scb_desc, return -EIO);
  1317. async_codec_scb_desc->parent_scb_ptr = NULL;
  1318. async_codec_scb_desc->next_scb_ptr = spdifi_scb_desc;
  1319. async_codec_scb_desc->sub_list_ptr = ins->the_null_scb;
  1320. async_codec_scb_desc->task_entry = s16_async_codec_input_task;
  1321. spdifi_scb_desc->parent_scb_ptr = async_codec_scb_desc;
  1322. spdifi_scb_desc->next_scb_ptr = spdifo_scb_desc;
  1323. spdifi_scb_desc->sub_list_ptr = ins->the_null_scb;
  1324. spdifi_scb_desc->task_entry = spdifi_task;
  1325. spdifo_scb_desc->parent_scb_ptr = spdifi_scb_desc;
  1326. spdifo_scb_desc->next_scb_ptr = fg_entry;
  1327. spdifo_scb_desc->sub_list_ptr = ins->the_null_scb;
  1328. spdifo_scb_desc->task_entry = spdifo_task;
  1329. /* this one is faked, as the parnet of SPDIFO task
  1330. is the FG task tree */
  1331. fg_entry->parent_scb_ptr = spdifo_scb_desc;
  1332. /* for proc fs */
  1333. cs46xx_dsp_proc_register_scb_desc (chip,spdifo_scb_desc);
  1334. cs46xx_dsp_proc_register_scb_desc (chip,spdifi_scb_desc);
  1335. cs46xx_dsp_proc_register_scb_desc (chip,async_codec_scb_desc);
  1336. /* Async MASTER ENABLE, affects both SPDIF input and output */
  1337. snd_cs46xx_pokeBA0(chip, BA0_ASER_MASTER, 0x1 );
  1338. }
  1339. return 0;
  1340. }
  1341. static void cs46xx_dsp_disable_spdif_hw (struct snd_cs46xx *chip)
  1342. {
  1343. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1344. /* set SPDIF output FIFO slot */
  1345. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, 0);
  1346. /* SPDIF output MASTER ENABLE */
  1347. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0);
  1348. /* right and left validate bit */
  1349. /*cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);*/
  1350. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, 0x0);
  1351. /* clear fifo pointer */
  1352. cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);
  1353. /* monitor state */
  1354. ins->spdif_status_out &= ~DSP_SPDIF_STATUS_HW_ENABLED;
  1355. }
  1356. int cs46xx_dsp_enable_spdif_hw (struct snd_cs46xx *chip)
  1357. {
  1358. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1359. /* if hw-ctrl already enabled, turn off to reset logic ... */
  1360. cs46xx_dsp_disable_spdif_hw (chip);
  1361. udelay(50);
  1362. /* set SPDIF output FIFO slot */
  1363. snd_cs46xx_pokeBA0(chip, BA0_ASER_FADDR, ( 0x8000 | ((SP_SPDOUT_FIFO >> 4) << 4) ));
  1364. /* SPDIF output MASTER ENABLE */
  1365. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CONTROL, 0x80000000);
  1366. /* right and left validate bit */
  1367. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV, ins->spdif_csuv_default);
  1368. /* monitor state */
  1369. ins->spdif_status_out |= DSP_SPDIF_STATUS_HW_ENABLED;
  1370. return 0;
  1371. }
  1372. int cs46xx_dsp_enable_spdif_in (struct snd_cs46xx *chip)
  1373. {
  1374. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1375. /* turn on amplifier */
  1376. chip->active_ctrl(chip, 1);
  1377. chip->amplifier_ctrl(chip, 1);
  1378. snd_assert (ins->asynch_rx_scb == NULL,return -EINVAL);
  1379. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1380. mutex_lock(&chip->spos_mutex);
  1381. if ( ! (ins->spdif_status_out & DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED) ) {
  1382. /* time countdown enable */
  1383. cs46xx_poke_via_dsp (chip,SP_ASER_COUNTDOWN, 0x80000005);
  1384. /* NOTE: 80000005 value is just magic. With all values
  1385. that I've tested this one seem to give the best result.
  1386. Got no explication why. (Benny) */
  1387. /* SPDIF input MASTER ENABLE */
  1388. cs46xx_poke_via_dsp (chip,SP_SPDIN_CONTROL, 0x800003ff);
  1389. ins->spdif_status_out |= DSP_SPDIF_STATUS_INPUT_CTRL_ENABLED;
  1390. }
  1391. /* create and start the asynchronous receiver SCB */
  1392. ins->asynch_rx_scb = cs46xx_dsp_create_asynch_fg_rx_scb(chip,"AsynchFGRxSCB",
  1393. ASYNCRX_SCB_ADDR,
  1394. SPDIFI_SCB_INST,
  1395. SPDIFI_IP_OUTPUT_BUFFER1,
  1396. ins->spdif_in_src,
  1397. SCB_ON_PARENT_SUBLIST_SCB);
  1398. spin_lock_irq(&chip->reg_lock);
  1399. /* reset SPDIF input sample buffer pointer */
  1400. /*snd_cs46xx_poke (chip, (SPDIFI_SCB_INST + 0x0c) << 2,
  1401. (SPDIFI_IP_OUTPUT_BUFFER1 << 0x10) | 0xFFFC);*/
  1402. /* reset FIFO ptr */
  1403. /*cs46xx_poke_via_dsp (chip,SP_SPDIN_FIFOPTR, 0x0);*/
  1404. cs46xx_src_link(chip,ins->spdif_in_src);
  1405. /* unmute SRC volume */
  1406. cs46xx_dsp_scb_set_volume (chip,ins->spdif_in_src,0x7fff,0x7fff);
  1407. spin_unlock_irq(&chip->reg_lock);
  1408. /* set SPDIF input sample rate and unmute
  1409. NOTE: only 48khz support for SPDIF input this time */
  1410. /* cs46xx_dsp_set_src_sample_rate(chip,ins->spdif_in_src,48000); */
  1411. /* monitor state */
  1412. ins->spdif_status_in = 1;
  1413. mutex_unlock(&chip->spos_mutex);
  1414. return 0;
  1415. }
  1416. int cs46xx_dsp_disable_spdif_in (struct snd_cs46xx *chip)
  1417. {
  1418. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1419. snd_assert (ins->asynch_rx_scb != NULL, return -EINVAL);
  1420. snd_assert (ins->spdif_in_src != NULL,return -EINVAL);
  1421. mutex_lock(&chip->spos_mutex);
  1422. /* Remove the asynchronous receiver SCB */
  1423. cs46xx_dsp_remove_scb (chip,ins->asynch_rx_scb);
  1424. ins->asynch_rx_scb = NULL;
  1425. cs46xx_src_unlink(chip,ins->spdif_in_src);
  1426. /* monitor state */
  1427. ins->spdif_status_in = 0;
  1428. mutex_unlock(&chip->spos_mutex);
  1429. /* restore amplifier */
  1430. chip->active_ctrl(chip, -1);
  1431. chip->amplifier_ctrl(chip, -1);
  1432. return 0;
  1433. }
  1434. int cs46xx_dsp_enable_pcm_capture (struct snd_cs46xx *chip)
  1435. {
  1436. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1437. snd_assert (ins->pcm_input == NULL,return -EINVAL);
  1438. snd_assert (ins->ref_snoop_scb != NULL,return -EINVAL);
  1439. mutex_lock(&chip->spos_mutex);
  1440. ins->pcm_input = cs46xx_add_record_source(chip,ins->ref_snoop_scb,PCMSERIALIN_PCM_SCB_ADDR,
  1441. "PCMSerialInput_Wave");
  1442. mutex_unlock(&chip->spos_mutex);
  1443. return 0;
  1444. }
  1445. int cs46xx_dsp_disable_pcm_capture (struct snd_cs46xx *chip)
  1446. {
  1447. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1448. snd_assert (ins->pcm_input != NULL,return -EINVAL);
  1449. mutex_lock(&chip->spos_mutex);
  1450. cs46xx_dsp_remove_scb (chip,ins->pcm_input);
  1451. ins->pcm_input = NULL;
  1452. mutex_unlock(&chip->spos_mutex);
  1453. return 0;
  1454. }
  1455. int cs46xx_dsp_enable_adc_capture (struct snd_cs46xx *chip)
  1456. {
  1457. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1458. snd_assert (ins->adc_input == NULL,return -EINVAL);
  1459. snd_assert (ins->codec_in_scb != NULL,return -EINVAL);
  1460. mutex_lock(&chip->spos_mutex);
  1461. ins->adc_input = cs46xx_add_record_source(chip,ins->codec_in_scb,PCMSERIALIN_SCB_ADDR,
  1462. "PCMSerialInput_ADC");
  1463. mutex_unlock(&chip->spos_mutex);
  1464. return 0;
  1465. }
  1466. int cs46xx_dsp_disable_adc_capture (struct snd_cs46xx *chip)
  1467. {
  1468. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1469. snd_assert (ins->adc_input != NULL,return -EINVAL);
  1470. mutex_lock(&chip->spos_mutex);
  1471. cs46xx_dsp_remove_scb (chip,ins->adc_input);
  1472. ins->adc_input = NULL;
  1473. mutex_unlock(&chip->spos_mutex);
  1474. return 0;
  1475. }
  1476. int cs46xx_poke_via_dsp (struct snd_cs46xx *chip, u32 address, u32 data)
  1477. {
  1478. u32 temp;
  1479. int i;
  1480. /* santiy check the parameters. (These numbers are not 100% correct. They are
  1481. a rough guess from looking at the controller spec.) */
  1482. if (address < 0x8000 || address >= 0x9000)
  1483. return -EINVAL;
  1484. /* initialize the SP_IO_WRITE SCB with the data. */
  1485. temp = ( address << 16 ) | ( address & 0x0000FFFF); /* offset 0 <-- address2 : address1 */
  1486. snd_cs46xx_poke(chip,( SPIOWRITE_SCB_ADDR << 2), temp);
  1487. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 1) << 2), data); /* offset 1 <-- data1 */
  1488. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 2) << 2), data); /* offset 1 <-- data2 */
  1489. /* Poke this location to tell the task to start */
  1490. snd_cs46xx_poke(chip,((SPIOWRITE_SCB_ADDR + 6) << 2), SPIOWRITE_SCB_ADDR << 0x10);
  1491. /* Verify that the task ran */
  1492. for (i=0; i<25; i++) {
  1493. udelay(125);
  1494. temp = snd_cs46xx_peek(chip,((SPIOWRITE_SCB_ADDR + 6) << 2));
  1495. if (temp == 0x00000000)
  1496. break;
  1497. }
  1498. if (i == 25) {
  1499. snd_printk(KERN_ERR "dsp_spos: SPIOWriteTask not responding\n");
  1500. return -EBUSY;
  1501. }
  1502. return 0;
  1503. }
  1504. int cs46xx_dsp_set_dac_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1505. {
  1506. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1507. struct dsp_scb_descriptor * scb;
  1508. mutex_lock(&chip->spos_mutex);
  1509. /* main output */
  1510. scb = ins->master_mix_scb->sub_list_ptr;
  1511. while (scb != ins->the_null_scb) {
  1512. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1513. scb = scb->next_scb_ptr;
  1514. }
  1515. /* rear output */
  1516. scb = ins->rear_mix_scb->sub_list_ptr;
  1517. while (scb != ins->the_null_scb) {
  1518. cs46xx_dsp_scb_set_volume (chip,scb,left,right);
  1519. scb = scb->next_scb_ptr;
  1520. }
  1521. ins->dac_volume_left = left;
  1522. ins->dac_volume_right = right;
  1523. mutex_unlock(&chip->spos_mutex);
  1524. return 0;
  1525. }
  1526. int cs46xx_dsp_set_iec958_volume (struct snd_cs46xx * chip, u16 left, u16 right)
  1527. {
  1528. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1529. mutex_lock(&chip->spos_mutex);
  1530. if (ins->asynch_rx_scb != NULL)
  1531. cs46xx_dsp_scb_set_volume (chip,ins->asynch_rx_scb,
  1532. left,right);
  1533. ins->spdif_input_volume_left = left;
  1534. ins->spdif_input_volume_right = right;
  1535. mutex_unlock(&chip->spos_mutex);
  1536. return 0;
  1537. }