cs46xx_lib.c 106 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * Abramo Bagnara <abramo@alsa-project.org>
  4. * Cirrus Logic, Inc.
  5. * Routines for control of Cirrus Logic CS461x chips
  6. *
  7. * KNOWN BUGS:
  8. * - Sometimes the SPDIF input DSP tasks get's unsynchronized
  9. * and the SPDIF get somewhat "distorcionated", or/and left right channel
  10. * are swapped. To get around this problem when it happens, mute and unmute
  11. * the SPDIF input mixer controll.
  12. * - On the Hercules Game Theater XP the amplifier are sometimes turned
  13. * off on inadecuate moments which causes distorcions on sound.
  14. *
  15. * TODO:
  16. * - Secondary CODEC on some soundcards
  17. * - SPDIF input support for other sample rates then 48khz
  18. * - Posibility to mix the SPDIF output with analog sources.
  19. * - PCM channels for Center and LFE on secondary codec
  20. *
  21. * NOTE: with CONFIG_SND_CS46XX_NEW_DSP unset uses old DSP image (which
  22. * is default configuration), no SPDIF, no secondary codec, no
  23. * multi channel PCM. But known to work.
  24. *
  25. * FINALLY: A credit to the developers Tom and Jordan
  26. * at Cirrus for have helping me out with the DSP, however we
  27. * still don't have sufficient documentation and technical
  28. * references to be able to implement all fancy feutures
  29. * supported by the cs46xx DSP's.
  30. * Benny <benny@hostmobility.com>
  31. *
  32. * This program is free software; you can redistribute it and/or modify
  33. * it under the terms of the GNU General Public License as published by
  34. * the Free Software Foundation; either version 2 of the License, or
  35. * (at your option) any later version.
  36. *
  37. * This program is distributed in the hope that it will be useful,
  38. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  39. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  40. * GNU General Public License for more details.
  41. *
  42. * You should have received a copy of the GNU General Public License
  43. * along with this program; if not, write to the Free Software
  44. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  45. *
  46. */
  47. #include <sound/driver.h>
  48. #include <linux/delay.h>
  49. #include <linux/pci.h>
  50. #include <linux/pm.h>
  51. #include <linux/init.h>
  52. #include <linux/interrupt.h>
  53. #include <linux/slab.h>
  54. #include <linux/gameport.h>
  55. #include <linux/mutex.h>
  56. #include <sound/core.h>
  57. #include <sound/control.h>
  58. #include <sound/info.h>
  59. #include <sound/pcm.h>
  60. #include <sound/pcm_params.h>
  61. #include <sound/cs46xx.h>
  62. #include <asm/io.h>
  63. #include "cs46xx_lib.h"
  64. #include "dsp_spos.h"
  65. static void amp_voyetra(struct snd_cs46xx *chip, int change);
  66. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  67. static struct snd_pcm_ops snd_cs46xx_playback_rear_ops;
  68. static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops;
  69. static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops;
  70. static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops;
  71. static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops;
  72. static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops;
  73. #endif
  74. static struct snd_pcm_ops snd_cs46xx_playback_ops;
  75. static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops;
  76. static struct snd_pcm_ops snd_cs46xx_capture_ops;
  77. static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops;
  78. static unsigned short snd_cs46xx_codec_read(struct snd_cs46xx *chip,
  79. unsigned short reg,
  80. int codec_index)
  81. {
  82. int count;
  83. unsigned short result,tmp;
  84. u32 offset = 0;
  85. snd_assert ( (codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  86. (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  87. return -EINVAL);
  88. chip->active_ctrl(chip, 1);
  89. if (codec_index == CS46XX_SECONDARY_CODEC_INDEX)
  90. offset = CS46XX_SECONDARY_CODEC_OFFSET;
  91. /*
  92. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  93. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  94. * 3. Write ACCTL = Control Register = 460h for initiating the write7---55
  95. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
  96. * 5. if DCV not cleared, break and return error
  97. * 6. Read ACSTS = Status Register = 464h, check VSTS bit
  98. */
  99. snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
  100. tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL);
  101. if ((tmp & ACCTL_VFRM) == 0) {
  102. snd_printk(KERN_WARNING "cs46xx: ACCTL_VFRM not set 0x%x\n",tmp);
  103. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, (tmp & (~ACCTL_ESYN)) | ACCTL_VFRM );
  104. msleep(50);
  105. tmp = snd_cs46xx_peekBA0(chip, BA0_ACCTL + offset);
  106. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, tmp | ACCTL_ESYN | ACCTL_VFRM );
  107. }
  108. /*
  109. * Setup the AC97 control registers on the CS461x to send the
  110. * appropriate command to the AC97 to perform the read.
  111. * ACCAD = Command Address Register = 46Ch
  112. * ACCDA = Command Data Register = 470h
  113. * ACCTL = Control Register = 460h
  114. * set DCV - will clear when process completed
  115. * set CRW - Read command
  116. * set VFRM - valid frame enabled
  117. * set ESYN - ASYNC generation enabled
  118. * set RSTN - ARST# inactive, AC97 codec not reset
  119. */
  120. snd_cs46xx_pokeBA0(chip, BA0_ACCAD, reg);
  121. snd_cs46xx_pokeBA0(chip, BA0_ACCDA, 0);
  122. if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
  123. snd_cs46xx_pokeBA0(chip, BA0_ACCTL,/* clear ACCTL_DCV */ ACCTL_CRW |
  124. ACCTL_VFRM | ACCTL_ESYN |
  125. ACCTL_RSTN);
  126. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_CRW |
  127. ACCTL_VFRM | ACCTL_ESYN |
  128. ACCTL_RSTN);
  129. } else {
  130. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
  131. ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN |
  132. ACCTL_RSTN);
  133. }
  134. /*
  135. * Wait for the read to occur.
  136. */
  137. for (count = 0; count < 1000; count++) {
  138. /*
  139. * First, we want to wait for a short time.
  140. */
  141. udelay(10);
  142. /*
  143. * Now, check to see if the read has completed.
  144. * ACCTL = 460h, DCV should be reset by now and 460h = 17h
  145. */
  146. if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV))
  147. goto ok1;
  148. }
  149. snd_printk(KERN_ERR "AC'97 read problem (ACCTL_DCV), reg = 0x%x\n", reg);
  150. result = 0xffff;
  151. goto end;
  152. ok1:
  153. /*
  154. * Wait for the valid status bit to go active.
  155. */
  156. for (count = 0; count < 100; count++) {
  157. /*
  158. * Read the AC97 status register.
  159. * ACSTS = Status Register = 464h
  160. * VSTS - Valid Status
  161. */
  162. if (snd_cs46xx_peekBA0(chip, BA0_ACSTS + offset) & ACSTS_VSTS)
  163. goto ok2;
  164. udelay(10);
  165. }
  166. snd_printk(KERN_ERR "AC'97 read problem (ACSTS_VSTS), codec_index %d, reg = 0x%x\n", codec_index, reg);
  167. result = 0xffff;
  168. goto end;
  169. ok2:
  170. /*
  171. * Read the data returned from the AC97 register.
  172. * ACSDA = Status Data Register = 474h
  173. */
  174. #if 0
  175. printk("e) reg = 0x%x, val = 0x%x, BA0_ACCAD = 0x%x\n", reg,
  176. snd_cs46xx_peekBA0(chip, BA0_ACSDA),
  177. snd_cs46xx_peekBA0(chip, BA0_ACCAD));
  178. #endif
  179. //snd_cs46xx_peekBA0(chip, BA0_ACCAD);
  180. result = snd_cs46xx_peekBA0(chip, BA0_ACSDA + offset);
  181. end:
  182. chip->active_ctrl(chip, -1);
  183. return result;
  184. }
  185. static unsigned short snd_cs46xx_ac97_read(struct snd_ac97 * ac97,
  186. unsigned short reg)
  187. {
  188. struct snd_cs46xx *chip = ac97->private_data;
  189. unsigned short val;
  190. int codec_index = ac97->num;
  191. snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
  192. codec_index == CS46XX_SECONDARY_CODEC_INDEX,
  193. return 0xffff);
  194. val = snd_cs46xx_codec_read(chip, reg, codec_index);
  195. return val;
  196. }
  197. static void snd_cs46xx_codec_write(struct snd_cs46xx *chip,
  198. unsigned short reg,
  199. unsigned short val,
  200. int codec_index)
  201. {
  202. int count;
  203. snd_assert ((codec_index == CS46XX_PRIMARY_CODEC_INDEX) ||
  204. (codec_index == CS46XX_SECONDARY_CODEC_INDEX),
  205. return);
  206. chip->active_ctrl(chip, 1);
  207. /*
  208. * 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
  209. * 2. Write ACCDA = Command Data Register = 470h for data to write to AC97
  210. * 3. Write ACCTL = Control Register = 460h for initiating the write
  211. * 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
  212. * 5. if DCV not cleared, break and return error
  213. */
  214. /*
  215. * Setup the AC97 control registers on the CS461x to send the
  216. * appropriate command to the AC97 to perform the read.
  217. * ACCAD = Command Address Register = 46Ch
  218. * ACCDA = Command Data Register = 470h
  219. * ACCTL = Control Register = 460h
  220. * set DCV - will clear when process completed
  221. * reset CRW - Write command
  222. * set VFRM - valid frame enabled
  223. * set ESYN - ASYNC generation enabled
  224. * set RSTN - ARST# inactive, AC97 codec not reset
  225. */
  226. snd_cs46xx_pokeBA0(chip, BA0_ACCAD , reg);
  227. snd_cs46xx_pokeBA0(chip, BA0_ACCDA , val);
  228. snd_cs46xx_peekBA0(chip, BA0_ACCTL);
  229. if (codec_index == CS46XX_PRIMARY_CODEC_INDEX) {
  230. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, /* clear ACCTL_DCV */ ACCTL_VFRM |
  231. ACCTL_ESYN | ACCTL_RSTN);
  232. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_VFRM |
  233. ACCTL_ESYN | ACCTL_RSTN);
  234. } else {
  235. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_DCV | ACCTL_TC |
  236. ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
  237. }
  238. for (count = 0; count < 4000; count++) {
  239. /*
  240. * First, we want to wait for a short time.
  241. */
  242. udelay(10);
  243. /*
  244. * Now, check to see if the write has completed.
  245. * ACCTL = 460h, DCV should be reset by now and 460h = 07h
  246. */
  247. if (!(snd_cs46xx_peekBA0(chip, BA0_ACCTL) & ACCTL_DCV)) {
  248. goto end;
  249. }
  250. }
  251. snd_printk(KERN_ERR "AC'97 write problem, codec_index = %d, reg = 0x%x, val = 0x%x\n", codec_index, reg, val);
  252. end:
  253. chip->active_ctrl(chip, -1);
  254. }
  255. static void snd_cs46xx_ac97_write(struct snd_ac97 *ac97,
  256. unsigned short reg,
  257. unsigned short val)
  258. {
  259. struct snd_cs46xx *chip = ac97->private_data;
  260. int codec_index = ac97->num;
  261. snd_assert(codec_index == CS46XX_PRIMARY_CODEC_INDEX ||
  262. codec_index == CS46XX_SECONDARY_CODEC_INDEX,
  263. return);
  264. snd_cs46xx_codec_write(chip, reg, val, codec_index);
  265. }
  266. /*
  267. * Chip initialization
  268. */
  269. int snd_cs46xx_download(struct snd_cs46xx *chip,
  270. u32 *src,
  271. unsigned long offset,
  272. unsigned long len)
  273. {
  274. void __iomem *dst;
  275. unsigned int bank = offset >> 16;
  276. offset = offset & 0xffff;
  277. snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
  278. dst = chip->region.idx[bank+1].remap_addr + offset;
  279. len /= sizeof(u32);
  280. /* writel already converts 32-bit value to right endianess */
  281. while (len-- > 0) {
  282. writel(*src++, dst);
  283. dst += sizeof(u32);
  284. }
  285. return 0;
  286. }
  287. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  288. #include "imgs/cwc4630.h"
  289. #include "imgs/cwcasync.h"
  290. #include "imgs/cwcsnoop.h"
  291. #include "imgs/cwcbinhack.h"
  292. #include "imgs/cwcdma.h"
  293. int snd_cs46xx_clear_BA1(struct snd_cs46xx *chip,
  294. unsigned long offset,
  295. unsigned long len)
  296. {
  297. void __iomem *dst;
  298. unsigned int bank = offset >> 16;
  299. offset = offset & 0xffff;
  300. snd_assert(!(offset & 3) && !(len & 3), return -EINVAL);
  301. dst = chip->region.idx[bank+1].remap_addr + offset;
  302. len /= sizeof(u32);
  303. /* writel already converts 32-bit value to right endianess */
  304. while (len-- > 0) {
  305. writel(0, dst);
  306. dst += sizeof(u32);
  307. }
  308. return 0;
  309. }
  310. #else /* old DSP image */
  311. #include "cs46xx_image.h"
  312. int snd_cs46xx_download_image(struct snd_cs46xx *chip)
  313. {
  314. int idx, err;
  315. unsigned long offset = 0;
  316. for (idx = 0; idx < BA1_MEMORY_COUNT; idx++) {
  317. if ((err = snd_cs46xx_download(chip,
  318. &BA1Struct.map[offset],
  319. BA1Struct.memory[idx].offset,
  320. BA1Struct.memory[idx].size)) < 0)
  321. return err;
  322. offset += BA1Struct.memory[idx].size >> 2;
  323. }
  324. return 0;
  325. }
  326. #endif /* CONFIG_SND_CS46XX_NEW_DSP */
  327. /*
  328. * Chip reset
  329. */
  330. static void snd_cs46xx_reset(struct snd_cs46xx *chip)
  331. {
  332. int idx;
  333. /*
  334. * Write the reset bit of the SP control register.
  335. */
  336. snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RSTSP);
  337. /*
  338. * Write the control register.
  339. */
  340. snd_cs46xx_poke(chip, BA1_SPCR, SPCR_DRQEN);
  341. /*
  342. * Clear the trap registers.
  343. */
  344. for (idx = 0; idx < 8; idx++) {
  345. snd_cs46xx_poke(chip, BA1_DREG, DREG_REGID_TRAP_SELECT + idx);
  346. snd_cs46xx_poke(chip, BA1_TWPR, 0xFFFF);
  347. }
  348. snd_cs46xx_poke(chip, BA1_DREG, 0);
  349. /*
  350. * Set the frame timer to reflect the number of cycles per frame.
  351. */
  352. snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
  353. }
  354. static int cs46xx_wait_for_fifo(struct snd_cs46xx * chip,int retry_timeout)
  355. {
  356. u32 i, status = 0;
  357. /*
  358. * Make sure the previous FIFO write operation has completed.
  359. */
  360. for(i = 0; i < 50; i++){
  361. status = snd_cs46xx_peekBA0(chip, BA0_SERBST);
  362. if( !(status & SERBST_WBSY) )
  363. break;
  364. mdelay(retry_timeout);
  365. }
  366. if(status & SERBST_WBSY) {
  367. snd_printk( KERN_ERR "cs46xx: failure waiting for FIFO command to complete\n");
  368. return -EINVAL;
  369. }
  370. return 0;
  371. }
  372. static void snd_cs46xx_clear_serial_FIFOs(struct snd_cs46xx *chip)
  373. {
  374. int idx, powerdown = 0;
  375. unsigned int tmp;
  376. /*
  377. * See if the devices are powered down. If so, we must power them up first
  378. * or they will not respond.
  379. */
  380. tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
  381. if (!(tmp & CLKCR1_SWCE)) {
  382. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
  383. powerdown = 1;
  384. }
  385. /*
  386. * We want to clear out the serial port FIFOs so we don't end up playing
  387. * whatever random garbage happens to be in them. We fill the sample FIFOS
  388. * with zero (silence).
  389. */
  390. snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0);
  391. /*
  392. * Fill all 256 sample FIFO locations.
  393. */
  394. for (idx = 0; idx < 0xFF; idx++) {
  395. /*
  396. * Make sure the previous FIFO write operation has completed.
  397. */
  398. if (cs46xx_wait_for_fifo(chip,1)) {
  399. snd_printdd ("failed waiting for FIFO at addr (%02X)\n",idx);
  400. if (powerdown)
  401. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
  402. break;
  403. }
  404. /*
  405. * Write the serial port FIFO index.
  406. */
  407. snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
  408. /*
  409. * Tell the serial port to load the new value into the FIFO location.
  410. */
  411. snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
  412. }
  413. /*
  414. * Now, if we powered up the devices, then power them back down again.
  415. * This is kinda ugly, but should never happen.
  416. */
  417. if (powerdown)
  418. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
  419. }
  420. static void snd_cs46xx_proc_start(struct snd_cs46xx *chip)
  421. {
  422. int cnt;
  423. /*
  424. * Set the frame timer to reflect the number of cycles per frame.
  425. */
  426. snd_cs46xx_poke(chip, BA1_FRMT, 0xadf);
  427. /*
  428. * Turn on the run, run at frame, and DMA enable bits in the local copy of
  429. * the SP control register.
  430. */
  431. snd_cs46xx_poke(chip, BA1_SPCR, SPCR_RUN | SPCR_RUNFR | SPCR_DRQEN);
  432. /*
  433. * Wait until the run at frame bit resets itself in the SP control
  434. * register.
  435. */
  436. for (cnt = 0; cnt < 25; cnt++) {
  437. udelay(50);
  438. if (!(snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR))
  439. break;
  440. }
  441. if (snd_cs46xx_peek(chip, BA1_SPCR) & SPCR_RUNFR)
  442. snd_printk(KERN_ERR "SPCR_RUNFR never reset\n");
  443. }
  444. static void snd_cs46xx_proc_stop(struct snd_cs46xx *chip)
  445. {
  446. /*
  447. * Turn off the run, run at frame, and DMA enable bits in the local copy of
  448. * the SP control register.
  449. */
  450. snd_cs46xx_poke(chip, BA1_SPCR, 0);
  451. }
  452. /*
  453. * Sample rate routines
  454. */
  455. #define GOF_PER_SEC 200
  456. static void snd_cs46xx_set_play_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
  457. {
  458. unsigned long flags;
  459. unsigned int tmp1, tmp2;
  460. unsigned int phiIncr;
  461. unsigned int correctionPerGOF, correctionPerSec;
  462. /*
  463. * Compute the values used to drive the actual sample rate conversion.
  464. * The following formulas are being computed, using inline assembly
  465. * since we need to use 64 bit arithmetic to compute the values:
  466. *
  467. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  468. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  469. * GOF_PER_SEC)
  470. * ulCorrectionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -M
  471. * GOF_PER_SEC * correctionPerGOF
  472. *
  473. * i.e.
  474. *
  475. * phiIncr:other = dividend:remainder((Fs,in * 2^26) / Fs,out)
  476. * correctionPerGOF:correctionPerSec =
  477. * dividend:remainder(ulOther / GOF_PER_SEC)
  478. */
  479. tmp1 = rate << 16;
  480. phiIncr = tmp1 / 48000;
  481. tmp1 -= phiIncr * 48000;
  482. tmp1 <<= 10;
  483. phiIncr <<= 10;
  484. tmp2 = tmp1 / 48000;
  485. phiIncr += tmp2;
  486. tmp1 -= tmp2 * 48000;
  487. correctionPerGOF = tmp1 / GOF_PER_SEC;
  488. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  489. correctionPerSec = tmp1;
  490. /*
  491. * Fill in the SampleRateConverter control block.
  492. */
  493. spin_lock_irqsave(&chip->reg_lock, flags);
  494. snd_cs46xx_poke(chip, BA1_PSRC,
  495. ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
  496. snd_cs46xx_poke(chip, BA1_PPI, phiIncr);
  497. spin_unlock_irqrestore(&chip->reg_lock, flags);
  498. }
  499. static void snd_cs46xx_set_capture_sample_rate(struct snd_cs46xx *chip, unsigned int rate)
  500. {
  501. unsigned long flags;
  502. unsigned int phiIncr, coeffIncr, tmp1, tmp2;
  503. unsigned int correctionPerGOF, correctionPerSec, initialDelay;
  504. unsigned int frameGroupLength, cnt;
  505. /*
  506. * We can only decimate by up to a factor of 1/9th the hardware rate.
  507. * Correct the value if an attempt is made to stray outside that limit.
  508. */
  509. if ((rate * 9) < 48000)
  510. rate = 48000 / 9;
  511. /*
  512. * We can not capture at at rate greater than the Input Rate (48000).
  513. * Return an error if an attempt is made to stray outside that limit.
  514. */
  515. if (rate > 48000)
  516. rate = 48000;
  517. /*
  518. * Compute the values used to drive the actual sample rate conversion.
  519. * The following formulas are being computed, using inline assembly
  520. * since we need to use 64 bit arithmetic to compute the values:
  521. *
  522. * coeffIncr = -floor((Fs,out * 2^23) / Fs,in)
  523. * phiIncr = floor((Fs,in * 2^26) / Fs,out)
  524. * correctionPerGOF = floor((Fs,in * 2^26 - Fs,out * phiIncr) /
  525. * GOF_PER_SEC)
  526. * correctionPerSec = Fs,in * 2^26 - Fs,out * phiIncr -
  527. * GOF_PER_SEC * correctionPerGOF
  528. * initialDelay = ceil((24 * Fs,in) / Fs,out)
  529. *
  530. * i.e.
  531. *
  532. * coeffIncr = neg(dividend((Fs,out * 2^23) / Fs,in))
  533. * phiIncr:ulOther = dividend:remainder((Fs,in * 2^26) / Fs,out)
  534. * correctionPerGOF:correctionPerSec =
  535. * dividend:remainder(ulOther / GOF_PER_SEC)
  536. * initialDelay = dividend(((24 * Fs,in) + Fs,out - 1) / Fs,out)
  537. */
  538. tmp1 = rate << 16;
  539. coeffIncr = tmp1 / 48000;
  540. tmp1 -= coeffIncr * 48000;
  541. tmp1 <<= 7;
  542. coeffIncr <<= 7;
  543. coeffIncr += tmp1 / 48000;
  544. coeffIncr ^= 0xFFFFFFFF;
  545. coeffIncr++;
  546. tmp1 = 48000 << 16;
  547. phiIncr = tmp1 / rate;
  548. tmp1 -= phiIncr * rate;
  549. tmp1 <<= 10;
  550. phiIncr <<= 10;
  551. tmp2 = tmp1 / rate;
  552. phiIncr += tmp2;
  553. tmp1 -= tmp2 * rate;
  554. correctionPerGOF = tmp1 / GOF_PER_SEC;
  555. tmp1 -= correctionPerGOF * GOF_PER_SEC;
  556. correctionPerSec = tmp1;
  557. initialDelay = ((48000 * 24) + rate - 1) / rate;
  558. /*
  559. * Fill in the VariDecimate control block.
  560. */
  561. spin_lock_irqsave(&chip->reg_lock, flags);
  562. snd_cs46xx_poke(chip, BA1_CSRC,
  563. ((correctionPerSec << 16) & 0xFFFF0000) | (correctionPerGOF & 0xFFFF));
  564. snd_cs46xx_poke(chip, BA1_CCI, coeffIncr);
  565. snd_cs46xx_poke(chip, BA1_CD,
  566. (((BA1_VARIDEC_BUF_1 + (initialDelay << 2)) << 16) & 0xFFFF0000) | 0x80);
  567. snd_cs46xx_poke(chip, BA1_CPI, phiIncr);
  568. spin_unlock_irqrestore(&chip->reg_lock, flags);
  569. /*
  570. * Figure out the frame group length for the write back task. Basically,
  571. * this is just the factors of 24000 (2^6*3*5^3) that are not present in
  572. * the output sample rate.
  573. */
  574. frameGroupLength = 1;
  575. for (cnt = 2; cnt <= 64; cnt *= 2) {
  576. if (((rate / cnt) * cnt) != rate)
  577. frameGroupLength *= 2;
  578. }
  579. if (((rate / 3) * 3) != rate) {
  580. frameGroupLength *= 3;
  581. }
  582. for (cnt = 5; cnt <= 125; cnt *= 5) {
  583. if (((rate / cnt) * cnt) != rate)
  584. frameGroupLength *= 5;
  585. }
  586. /*
  587. * Fill in the WriteBack control block.
  588. */
  589. spin_lock_irqsave(&chip->reg_lock, flags);
  590. snd_cs46xx_poke(chip, BA1_CFG1, frameGroupLength);
  591. snd_cs46xx_poke(chip, BA1_CFG2, (0x00800000 | frameGroupLength));
  592. snd_cs46xx_poke(chip, BA1_CCST, 0x0000FFFF);
  593. snd_cs46xx_poke(chip, BA1_CSPB, ((65536 * rate) / 24000));
  594. snd_cs46xx_poke(chip, (BA1_CSPB + 4), 0x0000FFFF);
  595. spin_unlock_irqrestore(&chip->reg_lock, flags);
  596. }
  597. /*
  598. * PCM part
  599. */
  600. static void snd_cs46xx_pb_trans_copy(struct snd_pcm_substream *substream,
  601. struct snd_pcm_indirect *rec, size_t bytes)
  602. {
  603. struct snd_pcm_runtime *runtime = substream->runtime;
  604. struct snd_cs46xx_pcm * cpcm = runtime->private_data;
  605. memcpy(cpcm->hw_buf.area + rec->hw_data, runtime->dma_area + rec->sw_data, bytes);
  606. }
  607. static int snd_cs46xx_playback_transfer(struct snd_pcm_substream *substream)
  608. {
  609. struct snd_pcm_runtime *runtime = substream->runtime;
  610. struct snd_cs46xx_pcm * cpcm = runtime->private_data;
  611. snd_pcm_indirect_playback_transfer(substream, &cpcm->pcm_rec, snd_cs46xx_pb_trans_copy);
  612. return 0;
  613. }
  614. static void snd_cs46xx_cp_trans_copy(struct snd_pcm_substream *substream,
  615. struct snd_pcm_indirect *rec, size_t bytes)
  616. {
  617. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  618. struct snd_pcm_runtime *runtime = substream->runtime;
  619. memcpy(runtime->dma_area + rec->sw_data,
  620. chip->capt.hw_buf.area + rec->hw_data, bytes);
  621. }
  622. static int snd_cs46xx_capture_transfer(struct snd_pcm_substream *substream)
  623. {
  624. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  625. snd_pcm_indirect_capture_transfer(substream, &chip->capt.pcm_rec, snd_cs46xx_cp_trans_copy);
  626. return 0;
  627. }
  628. static snd_pcm_uframes_t snd_cs46xx_playback_direct_pointer(struct snd_pcm_substream *substream)
  629. {
  630. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  631. size_t ptr;
  632. struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
  633. snd_assert (cpcm->pcm_channel,return -ENXIO);
  634. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  635. ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
  636. #else
  637. ptr = snd_cs46xx_peek(chip, BA1_PBA);
  638. #endif
  639. ptr -= cpcm->hw_buf.addr;
  640. return ptr >> cpcm->shift;
  641. }
  642. static snd_pcm_uframes_t snd_cs46xx_playback_indirect_pointer(struct snd_pcm_substream *substream)
  643. {
  644. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  645. size_t ptr;
  646. struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
  647. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  648. snd_assert (cpcm->pcm_channel,return -ENXIO);
  649. ptr = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 2) << 2);
  650. #else
  651. ptr = snd_cs46xx_peek(chip, BA1_PBA);
  652. #endif
  653. ptr -= cpcm->hw_buf.addr;
  654. return snd_pcm_indirect_playback_pointer(substream, &cpcm->pcm_rec, ptr);
  655. }
  656. static snd_pcm_uframes_t snd_cs46xx_capture_direct_pointer(struct snd_pcm_substream *substream)
  657. {
  658. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  659. size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
  660. return ptr >> chip->capt.shift;
  661. }
  662. static snd_pcm_uframes_t snd_cs46xx_capture_indirect_pointer(struct snd_pcm_substream *substream)
  663. {
  664. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  665. size_t ptr = snd_cs46xx_peek(chip, BA1_CBA) - chip->capt.hw_buf.addr;
  666. return snd_pcm_indirect_capture_pointer(substream, &chip->capt.pcm_rec, ptr);
  667. }
  668. static int snd_cs46xx_playback_trigger(struct snd_pcm_substream *substream,
  669. int cmd)
  670. {
  671. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  672. /*struct snd_pcm_runtime *runtime = substream->runtime;*/
  673. int result = 0;
  674. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  675. struct snd_cs46xx_pcm *cpcm = substream->runtime->private_data;
  676. if (! cpcm->pcm_channel) {
  677. return -ENXIO;
  678. }
  679. #endif
  680. switch (cmd) {
  681. case SNDRV_PCM_TRIGGER_START:
  682. case SNDRV_PCM_TRIGGER_RESUME:
  683. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  684. /* magic value to unmute PCM stream playback volume */
  685. snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
  686. SCBVolumeCtrl) << 2, 0x80008000);
  687. if (cpcm->pcm_channel->unlinked)
  688. cs46xx_dsp_pcm_link(chip,cpcm->pcm_channel);
  689. if (substream->runtime->periods != CS46XX_FRAGS)
  690. snd_cs46xx_playback_transfer(substream);
  691. #else
  692. spin_lock(&chip->reg_lock);
  693. if (substream->runtime->periods != CS46XX_FRAGS)
  694. snd_cs46xx_playback_transfer(substream);
  695. { unsigned int tmp;
  696. tmp = snd_cs46xx_peek(chip, BA1_PCTL);
  697. tmp &= 0x0000ffff;
  698. snd_cs46xx_poke(chip, BA1_PCTL, chip->play_ctl | tmp);
  699. }
  700. spin_unlock(&chip->reg_lock);
  701. #endif
  702. break;
  703. case SNDRV_PCM_TRIGGER_STOP:
  704. case SNDRV_PCM_TRIGGER_SUSPEND:
  705. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  706. /* magic mute channel */
  707. snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address +
  708. SCBVolumeCtrl) << 2, 0xffffffff);
  709. if (!cpcm->pcm_channel->unlinked)
  710. cs46xx_dsp_pcm_unlink(chip,cpcm->pcm_channel);
  711. #else
  712. spin_lock(&chip->reg_lock);
  713. { unsigned int tmp;
  714. tmp = snd_cs46xx_peek(chip, BA1_PCTL);
  715. tmp &= 0x0000ffff;
  716. snd_cs46xx_poke(chip, BA1_PCTL, tmp);
  717. }
  718. spin_unlock(&chip->reg_lock);
  719. #endif
  720. break;
  721. default:
  722. result = -EINVAL;
  723. break;
  724. }
  725. return result;
  726. }
  727. static int snd_cs46xx_capture_trigger(struct snd_pcm_substream *substream,
  728. int cmd)
  729. {
  730. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  731. unsigned int tmp;
  732. int result = 0;
  733. spin_lock(&chip->reg_lock);
  734. switch (cmd) {
  735. case SNDRV_PCM_TRIGGER_START:
  736. case SNDRV_PCM_TRIGGER_RESUME:
  737. tmp = snd_cs46xx_peek(chip, BA1_CCTL);
  738. tmp &= 0xffff0000;
  739. snd_cs46xx_poke(chip, BA1_CCTL, chip->capt.ctl | tmp);
  740. break;
  741. case SNDRV_PCM_TRIGGER_STOP:
  742. case SNDRV_PCM_TRIGGER_SUSPEND:
  743. tmp = snd_cs46xx_peek(chip, BA1_CCTL);
  744. tmp &= 0xffff0000;
  745. snd_cs46xx_poke(chip, BA1_CCTL, tmp);
  746. break;
  747. default:
  748. result = -EINVAL;
  749. break;
  750. }
  751. spin_unlock(&chip->reg_lock);
  752. return result;
  753. }
  754. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  755. static int _cs46xx_adjust_sample_rate (struct snd_cs46xx *chip, struct snd_cs46xx_pcm *cpcm,
  756. int sample_rate)
  757. {
  758. /* If PCMReaderSCB and SrcTaskSCB not created yet ... */
  759. if ( cpcm->pcm_channel == NULL) {
  760. cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate,
  761. cpcm, cpcm->hw_buf.addr,cpcm->pcm_channel_id);
  762. if (cpcm->pcm_channel == NULL) {
  763. snd_printk(KERN_ERR "cs46xx: failed to create virtual PCM channel\n");
  764. return -ENOMEM;
  765. }
  766. cpcm->pcm_channel->sample_rate = sample_rate;
  767. } else
  768. /* if sample rate is changed */
  769. if ((int)cpcm->pcm_channel->sample_rate != sample_rate) {
  770. int unlinked = cpcm->pcm_channel->unlinked;
  771. cs46xx_dsp_destroy_pcm_channel (chip,cpcm->pcm_channel);
  772. if ( (cpcm->pcm_channel = cs46xx_dsp_create_pcm_channel (chip, sample_rate, cpcm,
  773. cpcm->hw_buf.addr,
  774. cpcm->pcm_channel_id)) == NULL) {
  775. snd_printk(KERN_ERR "cs46xx: failed to re-create virtual PCM channel\n");
  776. return -ENOMEM;
  777. }
  778. if (!unlinked) cs46xx_dsp_pcm_link (chip,cpcm->pcm_channel);
  779. cpcm->pcm_channel->sample_rate = sample_rate;
  780. }
  781. return 0;
  782. }
  783. #endif
  784. static int snd_cs46xx_playback_hw_params(struct snd_pcm_substream *substream,
  785. struct snd_pcm_hw_params *hw_params)
  786. {
  787. struct snd_pcm_runtime *runtime = substream->runtime;
  788. struct snd_cs46xx_pcm *cpcm;
  789. int err;
  790. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  791. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  792. int sample_rate = params_rate(hw_params);
  793. int period_size = params_period_bytes(hw_params);
  794. #endif
  795. cpcm = runtime->private_data;
  796. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  797. snd_assert (sample_rate != 0, return -ENXIO);
  798. mutex_lock(&chip->spos_mutex);
  799. if (_cs46xx_adjust_sample_rate (chip,cpcm,sample_rate)) {
  800. mutex_unlock(&chip->spos_mutex);
  801. return -ENXIO;
  802. }
  803. snd_assert (cpcm->pcm_channel != NULL);
  804. if (!cpcm->pcm_channel) {
  805. mutex_unlock(&chip->spos_mutex);
  806. return -ENXIO;
  807. }
  808. if (cs46xx_dsp_pcm_channel_set_period (chip,cpcm->pcm_channel,period_size)) {
  809. mutex_unlock(&chip->spos_mutex);
  810. return -EINVAL;
  811. }
  812. snd_printdd ("period_size (%d), periods (%d) buffer_size(%d)\n",
  813. period_size, params_periods(hw_params),
  814. params_buffer_bytes(hw_params));
  815. #endif
  816. if (params_periods(hw_params) == CS46XX_FRAGS) {
  817. if (runtime->dma_area != cpcm->hw_buf.area)
  818. snd_pcm_lib_free_pages(substream);
  819. runtime->dma_area = cpcm->hw_buf.area;
  820. runtime->dma_addr = cpcm->hw_buf.addr;
  821. runtime->dma_bytes = cpcm->hw_buf.bytes;
  822. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  823. if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
  824. substream->ops = &snd_cs46xx_playback_ops;
  825. } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
  826. substream->ops = &snd_cs46xx_playback_rear_ops;
  827. } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
  828. substream->ops = &snd_cs46xx_playback_clfe_ops;
  829. } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
  830. substream->ops = &snd_cs46xx_playback_iec958_ops;
  831. } else {
  832. snd_assert(0);
  833. }
  834. #else
  835. substream->ops = &snd_cs46xx_playback_ops;
  836. #endif
  837. } else {
  838. if (runtime->dma_area == cpcm->hw_buf.area) {
  839. runtime->dma_area = NULL;
  840. runtime->dma_addr = 0;
  841. runtime->dma_bytes = 0;
  842. }
  843. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0) {
  844. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  845. mutex_unlock(&chip->spos_mutex);
  846. #endif
  847. return err;
  848. }
  849. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  850. if (cpcm->pcm_channel_id == DSP_PCM_MAIN_CHANNEL) {
  851. substream->ops = &snd_cs46xx_playback_indirect_ops;
  852. } else if (cpcm->pcm_channel_id == DSP_PCM_REAR_CHANNEL) {
  853. substream->ops = &snd_cs46xx_playback_indirect_rear_ops;
  854. } else if (cpcm->pcm_channel_id == DSP_PCM_CENTER_LFE_CHANNEL) {
  855. substream->ops = &snd_cs46xx_playback_indirect_clfe_ops;
  856. } else if (cpcm->pcm_channel_id == DSP_IEC958_CHANNEL) {
  857. substream->ops = &snd_cs46xx_playback_indirect_iec958_ops;
  858. } else {
  859. snd_assert(0);
  860. }
  861. #else
  862. substream->ops = &snd_cs46xx_playback_indirect_ops;
  863. #endif
  864. }
  865. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  866. mutex_unlock(&chip->spos_mutex);
  867. #endif
  868. return 0;
  869. }
  870. static int snd_cs46xx_playback_hw_free(struct snd_pcm_substream *substream)
  871. {
  872. /*struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);*/
  873. struct snd_pcm_runtime *runtime = substream->runtime;
  874. struct snd_cs46xx_pcm *cpcm;
  875. cpcm = runtime->private_data;
  876. /* if play_back open fails, then this function
  877. is called and cpcm can actually be NULL here */
  878. if (!cpcm) return -ENXIO;
  879. if (runtime->dma_area != cpcm->hw_buf.area)
  880. snd_pcm_lib_free_pages(substream);
  881. runtime->dma_area = NULL;
  882. runtime->dma_addr = 0;
  883. runtime->dma_bytes = 0;
  884. return 0;
  885. }
  886. static int snd_cs46xx_playback_prepare(struct snd_pcm_substream *substream)
  887. {
  888. unsigned int tmp;
  889. unsigned int pfie;
  890. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  891. struct snd_pcm_runtime *runtime = substream->runtime;
  892. struct snd_cs46xx_pcm *cpcm;
  893. cpcm = runtime->private_data;
  894. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  895. snd_assert (cpcm->pcm_channel != NULL, return -ENXIO);
  896. pfie = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2 );
  897. pfie &= ~0x0000f03f;
  898. #else
  899. /* old dsp */
  900. pfie = snd_cs46xx_peek(chip, BA1_PFIE);
  901. pfie &= ~0x0000f03f;
  902. #endif
  903. cpcm->shift = 2;
  904. /* if to convert from stereo to mono */
  905. if (runtime->channels == 1) {
  906. cpcm->shift--;
  907. pfie |= 0x00002000;
  908. }
  909. /* if to convert from 8 bit to 16 bit */
  910. if (snd_pcm_format_width(runtime->format) == 8) {
  911. cpcm->shift--;
  912. pfie |= 0x00001000;
  913. }
  914. /* if to convert to unsigned */
  915. if (snd_pcm_format_unsigned(runtime->format))
  916. pfie |= 0x00008000;
  917. /* Never convert byte order when sample stream is 8 bit */
  918. if (snd_pcm_format_width(runtime->format) != 8) {
  919. /* convert from big endian to little endian */
  920. if (snd_pcm_format_big_endian(runtime->format))
  921. pfie |= 0x00004000;
  922. }
  923. memset(&cpcm->pcm_rec, 0, sizeof(cpcm->pcm_rec));
  924. cpcm->pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  925. cpcm->pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << cpcm->shift;
  926. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  927. tmp = snd_cs46xx_peek(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2);
  928. tmp &= ~0x000003ff;
  929. tmp |= (4 << cpcm->shift) - 1;
  930. /* playback transaction count register */
  931. snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address) << 2, tmp);
  932. /* playback format && interrupt enable */
  933. snd_cs46xx_poke(chip, (cpcm->pcm_channel->pcm_reader_scb->address + 1) << 2, pfie | cpcm->pcm_channel->pcm_slot);
  934. #else
  935. snd_cs46xx_poke(chip, BA1_PBA, cpcm->hw_buf.addr);
  936. tmp = snd_cs46xx_peek(chip, BA1_PDTC);
  937. tmp &= ~0x000003ff;
  938. tmp |= (4 << cpcm->shift) - 1;
  939. snd_cs46xx_poke(chip, BA1_PDTC, tmp);
  940. snd_cs46xx_poke(chip, BA1_PFIE, pfie);
  941. snd_cs46xx_set_play_sample_rate(chip, runtime->rate);
  942. #endif
  943. return 0;
  944. }
  945. static int snd_cs46xx_capture_hw_params(struct snd_pcm_substream *substream,
  946. struct snd_pcm_hw_params *hw_params)
  947. {
  948. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  949. struct snd_pcm_runtime *runtime = substream->runtime;
  950. int err;
  951. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  952. cs46xx_dsp_pcm_ostream_set_period (chip, params_period_bytes(hw_params));
  953. #endif
  954. if (runtime->periods == CS46XX_FRAGS) {
  955. if (runtime->dma_area != chip->capt.hw_buf.area)
  956. snd_pcm_lib_free_pages(substream);
  957. runtime->dma_area = chip->capt.hw_buf.area;
  958. runtime->dma_addr = chip->capt.hw_buf.addr;
  959. runtime->dma_bytes = chip->capt.hw_buf.bytes;
  960. substream->ops = &snd_cs46xx_capture_ops;
  961. } else {
  962. if (runtime->dma_area == chip->capt.hw_buf.area) {
  963. runtime->dma_area = NULL;
  964. runtime->dma_addr = 0;
  965. runtime->dma_bytes = 0;
  966. }
  967. if ((err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params))) < 0)
  968. return err;
  969. substream->ops = &snd_cs46xx_capture_indirect_ops;
  970. }
  971. return 0;
  972. }
  973. static int snd_cs46xx_capture_hw_free(struct snd_pcm_substream *substream)
  974. {
  975. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  976. struct snd_pcm_runtime *runtime = substream->runtime;
  977. if (runtime->dma_area != chip->capt.hw_buf.area)
  978. snd_pcm_lib_free_pages(substream);
  979. runtime->dma_area = NULL;
  980. runtime->dma_addr = 0;
  981. runtime->dma_bytes = 0;
  982. return 0;
  983. }
  984. static int snd_cs46xx_capture_prepare(struct snd_pcm_substream *substream)
  985. {
  986. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  987. struct snd_pcm_runtime *runtime = substream->runtime;
  988. snd_cs46xx_poke(chip, BA1_CBA, chip->capt.hw_buf.addr);
  989. chip->capt.shift = 2;
  990. memset(&chip->capt.pcm_rec, 0, sizeof(chip->capt.pcm_rec));
  991. chip->capt.pcm_rec.sw_buffer_size = snd_pcm_lib_buffer_bytes(substream);
  992. chip->capt.pcm_rec.hw_buffer_size = runtime->period_size * CS46XX_FRAGS << 2;
  993. snd_cs46xx_set_capture_sample_rate(chip, runtime->rate);
  994. return 0;
  995. }
  996. static irqreturn_t snd_cs46xx_interrupt(int irq, void *dev_id)
  997. {
  998. struct snd_cs46xx *chip = dev_id;
  999. u32 status1;
  1000. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1001. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1002. u32 status2;
  1003. int i;
  1004. struct snd_cs46xx_pcm *cpcm = NULL;
  1005. #endif
  1006. /*
  1007. * Read the Interrupt Status Register to clear the interrupt
  1008. */
  1009. status1 = snd_cs46xx_peekBA0(chip, BA0_HISR);
  1010. if ((status1 & 0x7fffffff) == 0) {
  1011. snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
  1012. return IRQ_NONE;
  1013. }
  1014. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1015. status2 = snd_cs46xx_peekBA0(chip, BA0_HSR0);
  1016. for (i = 0; i < DSP_MAX_PCM_CHANNELS; ++i) {
  1017. if (i <= 15) {
  1018. if ( status1 & (1 << i) ) {
  1019. if (i == CS46XX_DSP_CAPTURE_CHANNEL) {
  1020. if (chip->capt.substream)
  1021. snd_pcm_period_elapsed(chip->capt.substream);
  1022. } else {
  1023. if (ins->pcm_channels[i].active &&
  1024. ins->pcm_channels[i].private_data &&
  1025. !ins->pcm_channels[i].unlinked) {
  1026. cpcm = ins->pcm_channels[i].private_data;
  1027. snd_pcm_period_elapsed(cpcm->substream);
  1028. }
  1029. }
  1030. }
  1031. } else {
  1032. if ( status2 & (1 << (i - 16))) {
  1033. if (ins->pcm_channels[i].active &&
  1034. ins->pcm_channels[i].private_data &&
  1035. !ins->pcm_channels[i].unlinked) {
  1036. cpcm = ins->pcm_channels[i].private_data;
  1037. snd_pcm_period_elapsed(cpcm->substream);
  1038. }
  1039. }
  1040. }
  1041. }
  1042. #else
  1043. /* old dsp */
  1044. if ((status1 & HISR_VC0) && chip->playback_pcm) {
  1045. if (chip->playback_pcm->substream)
  1046. snd_pcm_period_elapsed(chip->playback_pcm->substream);
  1047. }
  1048. if ((status1 & HISR_VC1) && chip->pcm) {
  1049. if (chip->capt.substream)
  1050. snd_pcm_period_elapsed(chip->capt.substream);
  1051. }
  1052. #endif
  1053. if ((status1 & HISR_MIDI) && chip->rmidi) {
  1054. unsigned char c;
  1055. spin_lock(&chip->reg_lock);
  1056. while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_RBE) == 0) {
  1057. c = snd_cs46xx_peekBA0(chip, BA0_MIDRP);
  1058. if ((chip->midcr & MIDCR_RIE) == 0)
  1059. continue;
  1060. snd_rawmidi_receive(chip->midi_input, &c, 1);
  1061. }
  1062. while ((snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
  1063. if ((chip->midcr & MIDCR_TIE) == 0)
  1064. break;
  1065. if (snd_rawmidi_transmit(chip->midi_output, &c, 1) != 1) {
  1066. chip->midcr &= ~MIDCR_TIE;
  1067. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  1068. break;
  1069. }
  1070. snd_cs46xx_pokeBA0(chip, BA0_MIDWP, c);
  1071. }
  1072. spin_unlock(&chip->reg_lock);
  1073. }
  1074. /*
  1075. * EOI to the PCI part....reenables interrupts
  1076. */
  1077. snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_CHGM | HICR_IEV);
  1078. return IRQ_HANDLED;
  1079. }
  1080. static struct snd_pcm_hardware snd_cs46xx_playback =
  1081. {
  1082. .info = (SNDRV_PCM_INFO_MMAP |
  1083. SNDRV_PCM_INFO_INTERLEAVED |
  1084. SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
  1085. /*SNDRV_PCM_INFO_RESUME*/),
  1086. .formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_U8 |
  1087. SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S16_BE |
  1088. SNDRV_PCM_FMTBIT_U16_LE | SNDRV_PCM_FMTBIT_U16_BE),
  1089. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1090. .rate_min = 5500,
  1091. .rate_max = 48000,
  1092. .channels_min = 1,
  1093. .channels_max = 2,
  1094. .buffer_bytes_max = (256 * 1024),
  1095. .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
  1096. .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
  1097. .periods_min = CS46XX_FRAGS,
  1098. .periods_max = 1024,
  1099. .fifo_size = 0,
  1100. };
  1101. static struct snd_pcm_hardware snd_cs46xx_capture =
  1102. {
  1103. .info = (SNDRV_PCM_INFO_MMAP |
  1104. SNDRV_PCM_INFO_INTERLEAVED |
  1105. SNDRV_PCM_INFO_BLOCK_TRANSFER /*|*/
  1106. /*SNDRV_PCM_INFO_RESUME*/),
  1107. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  1108. .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
  1109. .rate_min = 5500,
  1110. .rate_max = 48000,
  1111. .channels_min = 2,
  1112. .channels_max = 2,
  1113. .buffer_bytes_max = (256 * 1024),
  1114. .period_bytes_min = CS46XX_MIN_PERIOD_SIZE,
  1115. .period_bytes_max = CS46XX_MAX_PERIOD_SIZE,
  1116. .periods_min = CS46XX_FRAGS,
  1117. .periods_max = 1024,
  1118. .fifo_size = 0,
  1119. };
  1120. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1121. static unsigned int period_sizes[] = { 32, 64, 128, 256, 512, 1024, 2048 };
  1122. static struct snd_pcm_hw_constraint_list hw_constraints_period_sizes = {
  1123. .count = ARRAY_SIZE(period_sizes),
  1124. .list = period_sizes,
  1125. .mask = 0
  1126. };
  1127. #endif
  1128. static void snd_cs46xx_pcm_free_substream(struct snd_pcm_runtime *runtime)
  1129. {
  1130. kfree(runtime->private_data);
  1131. }
  1132. static int _cs46xx_playback_open_channel (struct snd_pcm_substream *substream,int pcm_channel_id)
  1133. {
  1134. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1135. struct snd_cs46xx_pcm * cpcm;
  1136. struct snd_pcm_runtime *runtime = substream->runtime;
  1137. cpcm = kzalloc(sizeof(*cpcm), GFP_KERNEL);
  1138. if (cpcm == NULL)
  1139. return -ENOMEM;
  1140. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1141. PAGE_SIZE, &cpcm->hw_buf) < 0) {
  1142. kfree(cpcm);
  1143. return -ENOMEM;
  1144. }
  1145. runtime->hw = snd_cs46xx_playback;
  1146. runtime->private_data = cpcm;
  1147. runtime->private_free = snd_cs46xx_pcm_free_substream;
  1148. cpcm->substream = substream;
  1149. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1150. mutex_lock(&chip->spos_mutex);
  1151. cpcm->pcm_channel = NULL;
  1152. cpcm->pcm_channel_id = pcm_channel_id;
  1153. snd_pcm_hw_constraint_list(runtime, 0,
  1154. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1155. &hw_constraints_period_sizes);
  1156. mutex_unlock(&chip->spos_mutex);
  1157. #else
  1158. chip->playback_pcm = cpcm; /* HACK */
  1159. #endif
  1160. if (chip->accept_valid)
  1161. substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
  1162. chip->active_ctrl(chip, 1);
  1163. return 0;
  1164. }
  1165. static int snd_cs46xx_playback_open(struct snd_pcm_substream *substream)
  1166. {
  1167. snd_printdd("open front channel\n");
  1168. return _cs46xx_playback_open_channel(substream,DSP_PCM_MAIN_CHANNEL);
  1169. }
  1170. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1171. static int snd_cs46xx_playback_open_rear(struct snd_pcm_substream *substream)
  1172. {
  1173. snd_printdd("open rear channel\n");
  1174. return _cs46xx_playback_open_channel(substream,DSP_PCM_REAR_CHANNEL);
  1175. }
  1176. static int snd_cs46xx_playback_open_clfe(struct snd_pcm_substream *substream)
  1177. {
  1178. snd_printdd("open center - LFE channel\n");
  1179. return _cs46xx_playback_open_channel(substream,DSP_PCM_CENTER_LFE_CHANNEL);
  1180. }
  1181. static int snd_cs46xx_playback_open_iec958(struct snd_pcm_substream *substream)
  1182. {
  1183. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1184. snd_printdd("open raw iec958 channel\n");
  1185. mutex_lock(&chip->spos_mutex);
  1186. cs46xx_iec958_pre_open (chip);
  1187. mutex_unlock(&chip->spos_mutex);
  1188. return _cs46xx_playback_open_channel(substream,DSP_IEC958_CHANNEL);
  1189. }
  1190. static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream);
  1191. static int snd_cs46xx_playback_close_iec958(struct snd_pcm_substream *substream)
  1192. {
  1193. int err;
  1194. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1195. snd_printdd("close raw iec958 channel\n");
  1196. err = snd_cs46xx_playback_close(substream);
  1197. mutex_lock(&chip->spos_mutex);
  1198. cs46xx_iec958_post_close (chip);
  1199. mutex_unlock(&chip->spos_mutex);
  1200. return err;
  1201. }
  1202. #endif
  1203. static int snd_cs46xx_capture_open(struct snd_pcm_substream *substream)
  1204. {
  1205. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1206. if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
  1207. PAGE_SIZE, &chip->capt.hw_buf) < 0)
  1208. return -ENOMEM;
  1209. chip->capt.substream = substream;
  1210. substream->runtime->hw = snd_cs46xx_capture;
  1211. if (chip->accept_valid)
  1212. substream->runtime->hw.info |= SNDRV_PCM_INFO_MMAP_VALID;
  1213. chip->active_ctrl(chip, 1);
  1214. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1215. snd_pcm_hw_constraint_list(substream->runtime, 0,
  1216. SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
  1217. &hw_constraints_period_sizes);
  1218. #endif
  1219. return 0;
  1220. }
  1221. static int snd_cs46xx_playback_close(struct snd_pcm_substream *substream)
  1222. {
  1223. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1224. struct snd_pcm_runtime *runtime = substream->runtime;
  1225. struct snd_cs46xx_pcm * cpcm;
  1226. cpcm = runtime->private_data;
  1227. /* when playback_open fails, then cpcm can be NULL */
  1228. if (!cpcm) return -ENXIO;
  1229. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1230. mutex_lock(&chip->spos_mutex);
  1231. if (cpcm->pcm_channel) {
  1232. cs46xx_dsp_destroy_pcm_channel(chip,cpcm->pcm_channel);
  1233. cpcm->pcm_channel = NULL;
  1234. }
  1235. mutex_unlock(&chip->spos_mutex);
  1236. #else
  1237. chip->playback_pcm = NULL;
  1238. #endif
  1239. cpcm->substream = NULL;
  1240. snd_dma_free_pages(&cpcm->hw_buf);
  1241. chip->active_ctrl(chip, -1);
  1242. return 0;
  1243. }
  1244. static int snd_cs46xx_capture_close(struct snd_pcm_substream *substream)
  1245. {
  1246. struct snd_cs46xx *chip = snd_pcm_substream_chip(substream);
  1247. chip->capt.substream = NULL;
  1248. snd_dma_free_pages(&chip->capt.hw_buf);
  1249. chip->active_ctrl(chip, -1);
  1250. return 0;
  1251. }
  1252. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1253. static struct snd_pcm_ops snd_cs46xx_playback_rear_ops = {
  1254. .open = snd_cs46xx_playback_open_rear,
  1255. .close = snd_cs46xx_playback_close,
  1256. .ioctl = snd_pcm_lib_ioctl,
  1257. .hw_params = snd_cs46xx_playback_hw_params,
  1258. .hw_free = snd_cs46xx_playback_hw_free,
  1259. .prepare = snd_cs46xx_playback_prepare,
  1260. .trigger = snd_cs46xx_playback_trigger,
  1261. .pointer = snd_cs46xx_playback_direct_pointer,
  1262. };
  1263. static struct snd_pcm_ops snd_cs46xx_playback_indirect_rear_ops = {
  1264. .open = snd_cs46xx_playback_open_rear,
  1265. .close = snd_cs46xx_playback_close,
  1266. .ioctl = snd_pcm_lib_ioctl,
  1267. .hw_params = snd_cs46xx_playback_hw_params,
  1268. .hw_free = snd_cs46xx_playback_hw_free,
  1269. .prepare = snd_cs46xx_playback_prepare,
  1270. .trigger = snd_cs46xx_playback_trigger,
  1271. .pointer = snd_cs46xx_playback_indirect_pointer,
  1272. .ack = snd_cs46xx_playback_transfer,
  1273. };
  1274. static struct snd_pcm_ops snd_cs46xx_playback_clfe_ops = {
  1275. .open = snd_cs46xx_playback_open_clfe,
  1276. .close = snd_cs46xx_playback_close,
  1277. .ioctl = snd_pcm_lib_ioctl,
  1278. .hw_params = snd_cs46xx_playback_hw_params,
  1279. .hw_free = snd_cs46xx_playback_hw_free,
  1280. .prepare = snd_cs46xx_playback_prepare,
  1281. .trigger = snd_cs46xx_playback_trigger,
  1282. .pointer = snd_cs46xx_playback_direct_pointer,
  1283. };
  1284. static struct snd_pcm_ops snd_cs46xx_playback_indirect_clfe_ops = {
  1285. .open = snd_cs46xx_playback_open_clfe,
  1286. .close = snd_cs46xx_playback_close,
  1287. .ioctl = snd_pcm_lib_ioctl,
  1288. .hw_params = snd_cs46xx_playback_hw_params,
  1289. .hw_free = snd_cs46xx_playback_hw_free,
  1290. .prepare = snd_cs46xx_playback_prepare,
  1291. .trigger = snd_cs46xx_playback_trigger,
  1292. .pointer = snd_cs46xx_playback_indirect_pointer,
  1293. .ack = snd_cs46xx_playback_transfer,
  1294. };
  1295. static struct snd_pcm_ops snd_cs46xx_playback_iec958_ops = {
  1296. .open = snd_cs46xx_playback_open_iec958,
  1297. .close = snd_cs46xx_playback_close_iec958,
  1298. .ioctl = snd_pcm_lib_ioctl,
  1299. .hw_params = snd_cs46xx_playback_hw_params,
  1300. .hw_free = snd_cs46xx_playback_hw_free,
  1301. .prepare = snd_cs46xx_playback_prepare,
  1302. .trigger = snd_cs46xx_playback_trigger,
  1303. .pointer = snd_cs46xx_playback_direct_pointer,
  1304. };
  1305. static struct snd_pcm_ops snd_cs46xx_playback_indirect_iec958_ops = {
  1306. .open = snd_cs46xx_playback_open_iec958,
  1307. .close = snd_cs46xx_playback_close_iec958,
  1308. .ioctl = snd_pcm_lib_ioctl,
  1309. .hw_params = snd_cs46xx_playback_hw_params,
  1310. .hw_free = snd_cs46xx_playback_hw_free,
  1311. .prepare = snd_cs46xx_playback_prepare,
  1312. .trigger = snd_cs46xx_playback_trigger,
  1313. .pointer = snd_cs46xx_playback_indirect_pointer,
  1314. .ack = snd_cs46xx_playback_transfer,
  1315. };
  1316. #endif
  1317. static struct snd_pcm_ops snd_cs46xx_playback_ops = {
  1318. .open = snd_cs46xx_playback_open,
  1319. .close = snd_cs46xx_playback_close,
  1320. .ioctl = snd_pcm_lib_ioctl,
  1321. .hw_params = snd_cs46xx_playback_hw_params,
  1322. .hw_free = snd_cs46xx_playback_hw_free,
  1323. .prepare = snd_cs46xx_playback_prepare,
  1324. .trigger = snd_cs46xx_playback_trigger,
  1325. .pointer = snd_cs46xx_playback_direct_pointer,
  1326. };
  1327. static struct snd_pcm_ops snd_cs46xx_playback_indirect_ops = {
  1328. .open = snd_cs46xx_playback_open,
  1329. .close = snd_cs46xx_playback_close,
  1330. .ioctl = snd_pcm_lib_ioctl,
  1331. .hw_params = snd_cs46xx_playback_hw_params,
  1332. .hw_free = snd_cs46xx_playback_hw_free,
  1333. .prepare = snd_cs46xx_playback_prepare,
  1334. .trigger = snd_cs46xx_playback_trigger,
  1335. .pointer = snd_cs46xx_playback_indirect_pointer,
  1336. .ack = snd_cs46xx_playback_transfer,
  1337. };
  1338. static struct snd_pcm_ops snd_cs46xx_capture_ops = {
  1339. .open = snd_cs46xx_capture_open,
  1340. .close = snd_cs46xx_capture_close,
  1341. .ioctl = snd_pcm_lib_ioctl,
  1342. .hw_params = snd_cs46xx_capture_hw_params,
  1343. .hw_free = snd_cs46xx_capture_hw_free,
  1344. .prepare = snd_cs46xx_capture_prepare,
  1345. .trigger = snd_cs46xx_capture_trigger,
  1346. .pointer = snd_cs46xx_capture_direct_pointer,
  1347. };
  1348. static struct snd_pcm_ops snd_cs46xx_capture_indirect_ops = {
  1349. .open = snd_cs46xx_capture_open,
  1350. .close = snd_cs46xx_capture_close,
  1351. .ioctl = snd_pcm_lib_ioctl,
  1352. .hw_params = snd_cs46xx_capture_hw_params,
  1353. .hw_free = snd_cs46xx_capture_hw_free,
  1354. .prepare = snd_cs46xx_capture_prepare,
  1355. .trigger = snd_cs46xx_capture_trigger,
  1356. .pointer = snd_cs46xx_capture_indirect_pointer,
  1357. .ack = snd_cs46xx_capture_transfer,
  1358. };
  1359. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1360. #define MAX_PLAYBACK_CHANNELS (DSP_MAX_PCM_CHANNELS - 1)
  1361. #else
  1362. #define MAX_PLAYBACK_CHANNELS 1
  1363. #endif
  1364. int __devinit snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
  1365. {
  1366. struct snd_pcm *pcm;
  1367. int err;
  1368. if (rpcm)
  1369. *rpcm = NULL;
  1370. if ((err = snd_pcm_new(chip->card, "CS46xx", device, MAX_PLAYBACK_CHANNELS, 1, &pcm)) < 0)
  1371. return err;
  1372. pcm->private_data = chip;
  1373. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_ops);
  1374. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_cs46xx_capture_ops);
  1375. /* global setup */
  1376. pcm->info_flags = 0;
  1377. strcpy(pcm->name, "CS46xx");
  1378. chip->pcm = pcm;
  1379. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1380. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1381. if (rpcm)
  1382. *rpcm = pcm;
  1383. return 0;
  1384. }
  1385. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1386. int __devinit snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
  1387. {
  1388. struct snd_pcm *pcm;
  1389. int err;
  1390. if (rpcm)
  1391. *rpcm = NULL;
  1392. if ((err = snd_pcm_new(chip->card, "CS46xx - Rear", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
  1393. return err;
  1394. pcm->private_data = chip;
  1395. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_rear_ops);
  1396. /* global setup */
  1397. pcm->info_flags = 0;
  1398. strcpy(pcm->name, "CS46xx - Rear");
  1399. chip->pcm_rear = pcm;
  1400. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1401. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1402. if (rpcm)
  1403. *rpcm = pcm;
  1404. return 0;
  1405. }
  1406. int __devinit snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
  1407. {
  1408. struct snd_pcm *pcm;
  1409. int err;
  1410. if (rpcm)
  1411. *rpcm = NULL;
  1412. if ((err = snd_pcm_new(chip->card, "CS46xx - Center LFE", device, MAX_PLAYBACK_CHANNELS, 0, &pcm)) < 0)
  1413. return err;
  1414. pcm->private_data = chip;
  1415. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_clfe_ops);
  1416. /* global setup */
  1417. pcm->info_flags = 0;
  1418. strcpy(pcm->name, "CS46xx - Center LFE");
  1419. chip->pcm_center_lfe = pcm;
  1420. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1421. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1422. if (rpcm)
  1423. *rpcm = pcm;
  1424. return 0;
  1425. }
  1426. int __devinit snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm ** rpcm)
  1427. {
  1428. struct snd_pcm *pcm;
  1429. int err;
  1430. if (rpcm)
  1431. *rpcm = NULL;
  1432. if ((err = snd_pcm_new(chip->card, "CS46xx - IEC958", device, 1, 0, &pcm)) < 0)
  1433. return err;
  1434. pcm->private_data = chip;
  1435. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_cs46xx_playback_iec958_ops);
  1436. /* global setup */
  1437. pcm->info_flags = 0;
  1438. strcpy(pcm->name, "CS46xx - IEC958");
  1439. chip->pcm_rear = pcm;
  1440. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1441. snd_dma_pci_data(chip->pci), 64*1024, 256*1024);
  1442. if (rpcm)
  1443. *rpcm = pcm;
  1444. return 0;
  1445. }
  1446. #endif
  1447. /*
  1448. * Mixer routines
  1449. */
  1450. static void snd_cs46xx_mixer_free_ac97_bus(struct snd_ac97_bus *bus)
  1451. {
  1452. struct snd_cs46xx *chip = bus->private_data;
  1453. chip->ac97_bus = NULL;
  1454. }
  1455. static void snd_cs46xx_mixer_free_ac97(struct snd_ac97 *ac97)
  1456. {
  1457. struct snd_cs46xx *chip = ac97->private_data;
  1458. snd_assert ((ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) ||
  1459. (ac97 == chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]),
  1460. return);
  1461. if (ac97 == chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]) {
  1462. chip->ac97[CS46XX_PRIMARY_CODEC_INDEX] = NULL;
  1463. chip->eapd_switch = NULL;
  1464. }
  1465. else
  1466. chip->ac97[CS46XX_SECONDARY_CODEC_INDEX] = NULL;
  1467. }
  1468. static int snd_cs46xx_vol_info(struct snd_kcontrol *kcontrol,
  1469. struct snd_ctl_elem_info *uinfo)
  1470. {
  1471. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1472. uinfo->count = 2;
  1473. uinfo->value.integer.min = 0;
  1474. uinfo->value.integer.max = 0x7fff;
  1475. return 0;
  1476. }
  1477. static int snd_cs46xx_vol_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1478. {
  1479. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1480. int reg = kcontrol->private_value;
  1481. unsigned int val = snd_cs46xx_peek(chip, reg);
  1482. ucontrol->value.integer.value[0] = 0xffff - (val >> 16);
  1483. ucontrol->value.integer.value[1] = 0xffff - (val & 0xffff);
  1484. return 0;
  1485. }
  1486. static int snd_cs46xx_vol_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1487. {
  1488. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1489. int reg = kcontrol->private_value;
  1490. unsigned int val = ((0xffff - ucontrol->value.integer.value[0]) << 16 |
  1491. (0xffff - ucontrol->value.integer.value[1]));
  1492. unsigned int old = snd_cs46xx_peek(chip, reg);
  1493. int change = (old != val);
  1494. if (change) {
  1495. snd_cs46xx_poke(chip, reg, val);
  1496. }
  1497. return change;
  1498. }
  1499. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1500. static int snd_cs46xx_vol_dac_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1501. {
  1502. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1503. ucontrol->value.integer.value[0] = chip->dsp_spos_instance->dac_volume_left;
  1504. ucontrol->value.integer.value[1] = chip->dsp_spos_instance->dac_volume_right;
  1505. return 0;
  1506. }
  1507. static int snd_cs46xx_vol_dac_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1508. {
  1509. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1510. int change = 0;
  1511. if (chip->dsp_spos_instance->dac_volume_right != ucontrol->value.integer.value[0] ||
  1512. chip->dsp_spos_instance->dac_volume_left != ucontrol->value.integer.value[1]) {
  1513. cs46xx_dsp_set_dac_volume(chip,
  1514. ucontrol->value.integer.value[0],
  1515. ucontrol->value.integer.value[1]);
  1516. change = 1;
  1517. }
  1518. return change;
  1519. }
  1520. #if 0
  1521. static int snd_cs46xx_vol_iec958_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1522. {
  1523. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1524. ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_input_volume_left;
  1525. ucontrol->value.integer.value[1] = chip->dsp_spos_instance->spdif_input_volume_right;
  1526. return 0;
  1527. }
  1528. static int snd_cs46xx_vol_iec958_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  1529. {
  1530. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1531. int change = 0;
  1532. if (chip->dsp_spos_instance->spdif_input_volume_left != ucontrol->value.integer.value[0] ||
  1533. chip->dsp_spos_instance->spdif_input_volume_right!= ucontrol->value.integer.value[1]) {
  1534. cs46xx_dsp_set_iec958_volume (chip,
  1535. ucontrol->value.integer.value[0],
  1536. ucontrol->value.integer.value[1]);
  1537. change = 1;
  1538. }
  1539. return change;
  1540. }
  1541. #endif
  1542. static int snd_mixer_boolean_info(struct snd_kcontrol *kcontrol,
  1543. struct snd_ctl_elem_info *uinfo)
  1544. {
  1545. uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
  1546. uinfo->count = 1;
  1547. uinfo->value.integer.min = 0;
  1548. uinfo->value.integer.max = 1;
  1549. return 0;
  1550. }
  1551. static int snd_cs46xx_iec958_get(struct snd_kcontrol *kcontrol,
  1552. struct snd_ctl_elem_value *ucontrol)
  1553. {
  1554. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1555. int reg = kcontrol->private_value;
  1556. if (reg == CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT)
  1557. ucontrol->value.integer.value[0] = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
  1558. else
  1559. ucontrol->value.integer.value[0] = chip->dsp_spos_instance->spdif_status_in;
  1560. return 0;
  1561. }
  1562. static int snd_cs46xx_iec958_put(struct snd_kcontrol *kcontrol,
  1563. struct snd_ctl_elem_value *ucontrol)
  1564. {
  1565. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1566. int change, res;
  1567. switch (kcontrol->private_value) {
  1568. case CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT:
  1569. mutex_lock(&chip->spos_mutex);
  1570. change = (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED);
  1571. if (ucontrol->value.integer.value[0] && !change)
  1572. cs46xx_dsp_enable_spdif_out(chip);
  1573. else if (change && !ucontrol->value.integer.value[0])
  1574. cs46xx_dsp_disable_spdif_out(chip);
  1575. res = (change != (chip->dsp_spos_instance->spdif_status_out & DSP_SPDIF_STATUS_OUTPUT_ENABLED));
  1576. mutex_unlock(&chip->spos_mutex);
  1577. break;
  1578. case CS46XX_MIXER_SPDIF_INPUT_ELEMENT:
  1579. change = chip->dsp_spos_instance->spdif_status_in;
  1580. if (ucontrol->value.integer.value[0] && !change) {
  1581. cs46xx_dsp_enable_spdif_in(chip);
  1582. /* restore volume */
  1583. }
  1584. else if (change && !ucontrol->value.integer.value[0])
  1585. cs46xx_dsp_disable_spdif_in(chip);
  1586. res = (change != chip->dsp_spos_instance->spdif_status_in);
  1587. break;
  1588. default:
  1589. res = -EINVAL;
  1590. snd_assert(0, (void)0);
  1591. }
  1592. return res;
  1593. }
  1594. static int snd_cs46xx_adc_capture_get(struct snd_kcontrol *kcontrol,
  1595. struct snd_ctl_elem_value *ucontrol)
  1596. {
  1597. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1598. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1599. if (ins->adc_input != NULL)
  1600. ucontrol->value.integer.value[0] = 1;
  1601. else
  1602. ucontrol->value.integer.value[0] = 0;
  1603. return 0;
  1604. }
  1605. static int snd_cs46xx_adc_capture_put(struct snd_kcontrol *kcontrol,
  1606. struct snd_ctl_elem_value *ucontrol)
  1607. {
  1608. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1609. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1610. int change = 0;
  1611. if (ucontrol->value.integer.value[0] && !ins->adc_input) {
  1612. cs46xx_dsp_enable_adc_capture(chip);
  1613. change = 1;
  1614. } else if (!ucontrol->value.integer.value[0] && ins->adc_input) {
  1615. cs46xx_dsp_disable_adc_capture(chip);
  1616. change = 1;
  1617. }
  1618. return change;
  1619. }
  1620. static int snd_cs46xx_pcm_capture_get(struct snd_kcontrol *kcontrol,
  1621. struct snd_ctl_elem_value *ucontrol)
  1622. {
  1623. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1624. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1625. if (ins->pcm_input != NULL)
  1626. ucontrol->value.integer.value[0] = 1;
  1627. else
  1628. ucontrol->value.integer.value[0] = 0;
  1629. return 0;
  1630. }
  1631. static int snd_cs46xx_pcm_capture_put(struct snd_kcontrol *kcontrol,
  1632. struct snd_ctl_elem_value *ucontrol)
  1633. {
  1634. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1635. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1636. int change = 0;
  1637. if (ucontrol->value.integer.value[0] && !ins->pcm_input) {
  1638. cs46xx_dsp_enable_pcm_capture(chip);
  1639. change = 1;
  1640. } else if (!ucontrol->value.integer.value[0] && ins->pcm_input) {
  1641. cs46xx_dsp_disable_pcm_capture(chip);
  1642. change = 1;
  1643. }
  1644. return change;
  1645. }
  1646. static int snd_herc_spdif_select_get(struct snd_kcontrol *kcontrol,
  1647. struct snd_ctl_elem_value *ucontrol)
  1648. {
  1649. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1650. int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
  1651. if (val1 & EGPIODR_GPOE0)
  1652. ucontrol->value.integer.value[0] = 1;
  1653. else
  1654. ucontrol->value.integer.value[0] = 0;
  1655. return 0;
  1656. }
  1657. /*
  1658. * Game Theatre XP card - EGPIO[0] is used to select SPDIF input optical or coaxial.
  1659. */
  1660. static int snd_herc_spdif_select_put(struct snd_kcontrol *kcontrol,
  1661. struct snd_ctl_elem_value *ucontrol)
  1662. {
  1663. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1664. int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
  1665. int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
  1666. if (ucontrol->value.integer.value[0]) {
  1667. /* optical is default */
  1668. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
  1669. EGPIODR_GPOE0 | val1); /* enable EGPIO0 output */
  1670. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
  1671. EGPIOPTR_GPPT0 | val2); /* open-drain on output */
  1672. } else {
  1673. /* coaxial */
  1674. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE0); /* disable */
  1675. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT0); /* disable */
  1676. }
  1677. /* checking diff from the EGPIO direction register
  1678. should be enough */
  1679. return (val1 != (int)snd_cs46xx_peekBA0(chip, BA0_EGPIODR));
  1680. }
  1681. static int snd_cs46xx_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  1682. {
  1683. uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
  1684. uinfo->count = 1;
  1685. return 0;
  1686. }
  1687. static int snd_cs46xx_spdif_default_get(struct snd_kcontrol *kcontrol,
  1688. struct snd_ctl_elem_value *ucontrol)
  1689. {
  1690. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1691. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1692. mutex_lock(&chip->spos_mutex);
  1693. ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_default >> 24) & 0xff);
  1694. ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_default >> 16) & 0xff);
  1695. ucontrol->value.iec958.status[2] = 0;
  1696. ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_default) & 0xff);
  1697. mutex_unlock(&chip->spos_mutex);
  1698. return 0;
  1699. }
  1700. static int snd_cs46xx_spdif_default_put(struct snd_kcontrol *kcontrol,
  1701. struct snd_ctl_elem_value *ucontrol)
  1702. {
  1703. struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
  1704. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1705. unsigned int val;
  1706. int change;
  1707. mutex_lock(&chip->spos_mutex);
  1708. val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
  1709. ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[2]) << 16) |
  1710. ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
  1711. /* left and right validity bit */
  1712. (1 << 13) | (1 << 12);
  1713. change = (unsigned int)ins->spdif_csuv_default != val;
  1714. ins->spdif_csuv_default = val;
  1715. if ( !(ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN) )
  1716. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
  1717. mutex_unlock(&chip->spos_mutex);
  1718. return change;
  1719. }
  1720. static int snd_cs46xx_spdif_mask_get(struct snd_kcontrol *kcontrol,
  1721. struct snd_ctl_elem_value *ucontrol)
  1722. {
  1723. ucontrol->value.iec958.status[0] = 0xff;
  1724. ucontrol->value.iec958.status[1] = 0xff;
  1725. ucontrol->value.iec958.status[2] = 0x00;
  1726. ucontrol->value.iec958.status[3] = 0xff;
  1727. return 0;
  1728. }
  1729. static int snd_cs46xx_spdif_stream_get(struct snd_kcontrol *kcontrol,
  1730. struct snd_ctl_elem_value *ucontrol)
  1731. {
  1732. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1733. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1734. mutex_lock(&chip->spos_mutex);
  1735. ucontrol->value.iec958.status[0] = _wrap_all_bits((ins->spdif_csuv_stream >> 24) & 0xff);
  1736. ucontrol->value.iec958.status[1] = _wrap_all_bits((ins->spdif_csuv_stream >> 16) & 0xff);
  1737. ucontrol->value.iec958.status[2] = 0;
  1738. ucontrol->value.iec958.status[3] = _wrap_all_bits((ins->spdif_csuv_stream) & 0xff);
  1739. mutex_unlock(&chip->spos_mutex);
  1740. return 0;
  1741. }
  1742. static int snd_cs46xx_spdif_stream_put(struct snd_kcontrol *kcontrol,
  1743. struct snd_ctl_elem_value *ucontrol)
  1744. {
  1745. struct snd_cs46xx * chip = snd_kcontrol_chip(kcontrol);
  1746. struct dsp_spos_instance * ins = chip->dsp_spos_instance;
  1747. unsigned int val;
  1748. int change;
  1749. mutex_lock(&chip->spos_mutex);
  1750. val = ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[0]) << 24) |
  1751. ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[1]) << 16) |
  1752. ((unsigned int)_wrap_all_bits(ucontrol->value.iec958.status[3])) |
  1753. /* left and right validity bit */
  1754. (1 << 13) | (1 << 12);
  1755. change = ins->spdif_csuv_stream != val;
  1756. ins->spdif_csuv_stream = val;
  1757. if ( ins->spdif_status_out & DSP_SPDIF_STATUS_PLAYBACK_OPEN )
  1758. cs46xx_poke_via_dsp (chip,SP_SPDOUT_CSUV,val);
  1759. mutex_unlock(&chip->spos_mutex);
  1760. return change;
  1761. }
  1762. #endif /* CONFIG_SND_CS46XX_NEW_DSP */
  1763. #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
  1764. static int snd_cs46xx_egpio_select_info(struct snd_kcontrol *kcontrol,
  1765. struct snd_ctl_elem_info *uinfo)
  1766. {
  1767. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  1768. uinfo->count = 1;
  1769. uinfo->value.integer.min = 0;
  1770. uinfo->value.integer.max = 8;
  1771. return 0;
  1772. }
  1773. static int snd_cs46xx_egpio_select_get(struct snd_kcontrol *kcontrol,
  1774. struct snd_ctl_elem_value *ucontrol)
  1775. {
  1776. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1777. ucontrol->value.integer.value[0] = chip->current_gpio;
  1778. return 0;
  1779. }
  1780. static int snd_cs46xx_egpio_select_put(struct snd_kcontrol *kcontrol,
  1781. struct snd_ctl_elem_value *ucontrol)
  1782. {
  1783. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1784. int change = (chip->current_gpio != ucontrol->value.integer.value[0]);
  1785. chip->current_gpio = ucontrol->value.integer.value[0];
  1786. return change;
  1787. }
  1788. static int snd_cs46xx_egpio_get(struct snd_kcontrol *kcontrol,
  1789. struct snd_ctl_elem_value *ucontrol)
  1790. {
  1791. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1792. int reg = kcontrol->private_value;
  1793. snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
  1794. ucontrol->value.integer.value[0] =
  1795. (snd_cs46xx_peekBA0(chip, reg) & (1 << chip->current_gpio)) ? 1 : 0;
  1796. return 0;
  1797. }
  1798. static int snd_cs46xx_egpio_put(struct snd_kcontrol *kcontrol,
  1799. struct snd_ctl_elem_value *ucontrol)
  1800. {
  1801. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1802. int reg = kcontrol->private_value;
  1803. int val = snd_cs46xx_peekBA0(chip, reg);
  1804. int oldval = val;
  1805. snd_printdd ("put: reg = %04x, gpio %02x\n",reg,chip->current_gpio);
  1806. if (ucontrol->value.integer.value[0])
  1807. val |= (1 << chip->current_gpio);
  1808. else
  1809. val &= ~(1 << chip->current_gpio);
  1810. snd_cs46xx_pokeBA0(chip, reg,val);
  1811. snd_printdd ("put: val %08x oldval %08x\n",val,oldval);
  1812. return (oldval != val);
  1813. }
  1814. #endif /* CONFIG_SND_CS46XX_DEBUG_GPIO */
  1815. static struct snd_kcontrol_new snd_cs46xx_controls[] __devinitdata = {
  1816. {
  1817. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1818. .name = "DAC Volume",
  1819. .info = snd_cs46xx_vol_info,
  1820. #ifndef CONFIG_SND_CS46XX_NEW_DSP
  1821. .get = snd_cs46xx_vol_get,
  1822. .put = snd_cs46xx_vol_put,
  1823. .private_value = BA1_PVOL,
  1824. #else
  1825. .get = snd_cs46xx_vol_dac_get,
  1826. .put = snd_cs46xx_vol_dac_put,
  1827. #endif
  1828. },
  1829. {
  1830. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1831. .name = "ADC Volume",
  1832. .info = snd_cs46xx_vol_info,
  1833. .get = snd_cs46xx_vol_get,
  1834. .put = snd_cs46xx_vol_put,
  1835. #ifndef CONFIG_SND_CS46XX_NEW_DSP
  1836. .private_value = BA1_CVOL,
  1837. #else
  1838. .private_value = (VARIDECIMATE_SCB_ADDR + 0xE) << 2,
  1839. #endif
  1840. },
  1841. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1842. {
  1843. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1844. .name = "ADC Capture Switch",
  1845. .info = snd_mixer_boolean_info,
  1846. .get = snd_cs46xx_adc_capture_get,
  1847. .put = snd_cs46xx_adc_capture_put
  1848. },
  1849. {
  1850. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1851. .name = "DAC Capture Switch",
  1852. .info = snd_mixer_boolean_info,
  1853. .get = snd_cs46xx_pcm_capture_get,
  1854. .put = snd_cs46xx_pcm_capture_put
  1855. },
  1856. {
  1857. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1858. .name = SNDRV_CTL_NAME_IEC958("Output ",NONE,SWITCH),
  1859. .info = snd_mixer_boolean_info,
  1860. .get = snd_cs46xx_iec958_get,
  1861. .put = snd_cs46xx_iec958_put,
  1862. .private_value = CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT,
  1863. },
  1864. {
  1865. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1866. .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,SWITCH),
  1867. .info = snd_mixer_boolean_info,
  1868. .get = snd_cs46xx_iec958_get,
  1869. .put = snd_cs46xx_iec958_put,
  1870. .private_value = CS46XX_MIXER_SPDIF_INPUT_ELEMENT,
  1871. },
  1872. #if 0
  1873. /* Input IEC958 volume does not work for the moment. (Benny) */
  1874. {
  1875. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1876. .name = SNDRV_CTL_NAME_IEC958("Input ",NONE,VOLUME),
  1877. .info = snd_cs46xx_vol_info,
  1878. .get = snd_cs46xx_vol_iec958_get,
  1879. .put = snd_cs46xx_vol_iec958_put,
  1880. .private_value = (ASYNCRX_SCB_ADDR + 0xE) << 2,
  1881. },
  1882. #endif
  1883. {
  1884. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1885. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
  1886. .info = snd_cs46xx_spdif_info,
  1887. .get = snd_cs46xx_spdif_default_get,
  1888. .put = snd_cs46xx_spdif_default_put,
  1889. },
  1890. {
  1891. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1892. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,MASK),
  1893. .info = snd_cs46xx_spdif_info,
  1894. .get = snd_cs46xx_spdif_mask_get,
  1895. .access = SNDRV_CTL_ELEM_ACCESS_READ
  1896. },
  1897. {
  1898. .iface = SNDRV_CTL_ELEM_IFACE_PCM,
  1899. .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
  1900. .info = snd_cs46xx_spdif_info,
  1901. .get = snd_cs46xx_spdif_stream_get,
  1902. .put = snd_cs46xx_spdif_stream_put
  1903. },
  1904. #endif
  1905. #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
  1906. {
  1907. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1908. .name = "EGPIO select",
  1909. .info = snd_cs46xx_egpio_select_info,
  1910. .get = snd_cs46xx_egpio_select_get,
  1911. .put = snd_cs46xx_egpio_select_put,
  1912. .private_value = 0,
  1913. },
  1914. {
  1915. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1916. .name = "EGPIO Input/Output",
  1917. .info = snd_mixer_boolean_info,
  1918. .get = snd_cs46xx_egpio_get,
  1919. .put = snd_cs46xx_egpio_put,
  1920. .private_value = BA0_EGPIODR,
  1921. },
  1922. {
  1923. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1924. .name = "EGPIO CMOS/Open drain",
  1925. .info = snd_mixer_boolean_info,
  1926. .get = snd_cs46xx_egpio_get,
  1927. .put = snd_cs46xx_egpio_put,
  1928. .private_value = BA0_EGPIOPTR,
  1929. },
  1930. {
  1931. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1932. .name = "EGPIO On/Off",
  1933. .info = snd_mixer_boolean_info,
  1934. .get = snd_cs46xx_egpio_get,
  1935. .put = snd_cs46xx_egpio_put,
  1936. .private_value = BA0_EGPIOSR,
  1937. },
  1938. #endif
  1939. };
  1940. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1941. /* set primary cs4294 codec into Extended Audio Mode */
  1942. static int snd_cs46xx_front_dup_get(struct snd_kcontrol *kcontrol,
  1943. struct snd_ctl_elem_value *ucontrol)
  1944. {
  1945. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1946. unsigned short val;
  1947. val = snd_ac97_read(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX], AC97_CSR_ACMODE);
  1948. ucontrol->value.integer.value[0] = (val & 0x200) ? 0 : 1;
  1949. return 0;
  1950. }
  1951. static int snd_cs46xx_front_dup_put(struct snd_kcontrol *kcontrol,
  1952. struct snd_ctl_elem_value *ucontrol)
  1953. {
  1954. struct snd_cs46xx *chip = snd_kcontrol_chip(kcontrol);
  1955. return snd_ac97_update_bits(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
  1956. AC97_CSR_ACMODE, 0x200,
  1957. ucontrol->value.integer.value[0] ? 0 : 0x200);
  1958. }
  1959. static struct snd_kcontrol_new snd_cs46xx_front_dup_ctl = {
  1960. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1961. .name = "Duplicate Front",
  1962. .info = snd_mixer_boolean_info,
  1963. .get = snd_cs46xx_front_dup_get,
  1964. .put = snd_cs46xx_front_dup_put,
  1965. };
  1966. #endif
  1967. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1968. /* Only available on the Hercules Game Theater XP soundcard */
  1969. static struct snd_kcontrol_new snd_hercules_controls[] = {
  1970. {
  1971. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  1972. .name = "Optical/Coaxial SPDIF Input Switch",
  1973. .info = snd_mixer_boolean_info,
  1974. .get = snd_herc_spdif_select_get,
  1975. .put = snd_herc_spdif_select_put,
  1976. },
  1977. };
  1978. static void snd_cs46xx_codec_reset (struct snd_ac97 * ac97)
  1979. {
  1980. unsigned long end_time;
  1981. int err;
  1982. /* reset to defaults */
  1983. snd_ac97_write(ac97, AC97_RESET, 0);
  1984. /* set the desired CODEC mode */
  1985. if (ac97->num == CS46XX_PRIMARY_CODEC_INDEX) {
  1986. snd_printdd("cs46xx: CODOEC1 mode %04x\n",0x0);
  1987. snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x0);
  1988. } else if (ac97->num == CS46XX_SECONDARY_CODEC_INDEX) {
  1989. snd_printdd("cs46xx: CODOEC2 mode %04x\n",0x3);
  1990. snd_cs46xx_ac97_write(ac97,AC97_CSR_ACMODE,0x3);
  1991. } else {
  1992. snd_assert(0); /* should never happen ... */
  1993. }
  1994. udelay(50);
  1995. /* it's necessary to wait awhile until registers are accessible after RESET */
  1996. /* because the PCM or MASTER volume registers can be modified, */
  1997. /* the REC_GAIN register is used for tests */
  1998. end_time = jiffies + HZ;
  1999. do {
  2000. unsigned short ext_mid;
  2001. /* use preliminary reads to settle the communication */
  2002. snd_ac97_read(ac97, AC97_RESET);
  2003. snd_ac97_read(ac97, AC97_VENDOR_ID1);
  2004. snd_ac97_read(ac97, AC97_VENDOR_ID2);
  2005. /* modem? */
  2006. ext_mid = snd_ac97_read(ac97, AC97_EXTENDED_MID);
  2007. if (ext_mid != 0xffff && (ext_mid & 1) != 0)
  2008. return;
  2009. /* test if we can write to the record gain volume register */
  2010. snd_ac97_write_cache(ac97, AC97_REC_GAIN, 0x8a05);
  2011. if ((err = snd_ac97_read(ac97, AC97_REC_GAIN)) == 0x8a05)
  2012. return;
  2013. msleep(10);
  2014. } while (time_after_eq(end_time, jiffies));
  2015. snd_printk(KERN_ERR "CS46xx secondary codec doesn't respond!\n");
  2016. }
  2017. #endif
  2018. static int __devinit cs46xx_detect_codec(struct snd_cs46xx *chip, int codec)
  2019. {
  2020. int idx, err;
  2021. struct snd_ac97_template ac97;
  2022. memset(&ac97, 0, sizeof(ac97));
  2023. ac97.private_data = chip;
  2024. ac97.private_free = snd_cs46xx_mixer_free_ac97;
  2025. ac97.num = codec;
  2026. if (chip->amplifier_ctrl == amp_voyetra)
  2027. ac97.scaps = AC97_SCAP_INV_EAPD;
  2028. if (codec == CS46XX_SECONDARY_CODEC_INDEX) {
  2029. snd_cs46xx_codec_write(chip, AC97_RESET, 0, codec);
  2030. udelay(10);
  2031. if (snd_cs46xx_codec_read(chip, AC97_RESET, codec) & 0x8000) {
  2032. snd_printdd("snd_cs46xx: seconadry codec not present\n");
  2033. return -ENXIO;
  2034. }
  2035. }
  2036. snd_cs46xx_codec_write(chip, AC97_MASTER, 0x8000, codec);
  2037. for (idx = 0; idx < 100; ++idx) {
  2038. if (snd_cs46xx_codec_read(chip, AC97_MASTER, codec) == 0x8000) {
  2039. err = snd_ac97_mixer(chip->ac97_bus, &ac97, &chip->ac97[codec]);
  2040. return err;
  2041. }
  2042. msleep(10);
  2043. }
  2044. snd_printdd("snd_cs46xx: codec %d detection timeout\n", codec);
  2045. return -ENXIO;
  2046. }
  2047. int __devinit snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device)
  2048. {
  2049. struct snd_card *card = chip->card;
  2050. struct snd_ctl_elem_id id;
  2051. int err;
  2052. unsigned int idx;
  2053. static struct snd_ac97_bus_ops ops = {
  2054. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2055. .reset = snd_cs46xx_codec_reset,
  2056. #endif
  2057. .write = snd_cs46xx_ac97_write,
  2058. .read = snd_cs46xx_ac97_read,
  2059. };
  2060. /* detect primary codec */
  2061. chip->nr_ac97_codecs = 0;
  2062. snd_printdd("snd_cs46xx: detecting primary codec\n");
  2063. if ((err = snd_ac97_bus(card, 0, &ops, chip, &chip->ac97_bus)) < 0)
  2064. return err;
  2065. chip->ac97_bus->private_free = snd_cs46xx_mixer_free_ac97_bus;
  2066. if (cs46xx_detect_codec(chip, CS46XX_PRIMARY_CODEC_INDEX) < 0)
  2067. return -ENXIO;
  2068. chip->nr_ac97_codecs = 1;
  2069. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2070. snd_printdd("snd_cs46xx: detecting seconadry codec\n");
  2071. /* try detect a secondary codec */
  2072. if (! cs46xx_detect_codec(chip, CS46XX_SECONDARY_CODEC_INDEX))
  2073. chip->nr_ac97_codecs = 2;
  2074. #endif /* CONFIG_SND_CS46XX_NEW_DSP */
  2075. /* add cs4630 mixer controls */
  2076. for (idx = 0; idx < ARRAY_SIZE(snd_cs46xx_controls); idx++) {
  2077. struct snd_kcontrol *kctl;
  2078. kctl = snd_ctl_new1(&snd_cs46xx_controls[idx], chip);
  2079. if (kctl && kctl->id.iface == SNDRV_CTL_ELEM_IFACE_PCM)
  2080. kctl->id.device = spdif_device;
  2081. if ((err = snd_ctl_add(card, kctl)) < 0)
  2082. return err;
  2083. }
  2084. /* get EAPD mixer switch (for voyetra hack) */
  2085. memset(&id, 0, sizeof(id));
  2086. id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
  2087. strcpy(id.name, "External Amplifier");
  2088. chip->eapd_switch = snd_ctl_find_id(chip->card, &id);
  2089. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2090. if (chip->nr_ac97_codecs == 1) {
  2091. unsigned int id2 = chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]->id & 0xffff;
  2092. if (id2 == 0x592b || id2 == 0x592d) {
  2093. err = snd_ctl_add(card, snd_ctl_new1(&snd_cs46xx_front_dup_ctl, chip));
  2094. if (err < 0)
  2095. return err;
  2096. snd_ac97_write_cache(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX],
  2097. AC97_CSR_ACMODE, 0x200);
  2098. }
  2099. }
  2100. /* do soundcard specific mixer setup */
  2101. if (chip->mixer_init) {
  2102. snd_printdd ("calling chip->mixer_init(chip);\n");
  2103. chip->mixer_init(chip);
  2104. }
  2105. #endif
  2106. /* turn on amplifier */
  2107. chip->amplifier_ctrl(chip, 1);
  2108. return 0;
  2109. }
  2110. /*
  2111. * RawMIDI interface
  2112. */
  2113. static void snd_cs46xx_midi_reset(struct snd_cs46xx *chip)
  2114. {
  2115. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, MIDCR_MRST);
  2116. udelay(100);
  2117. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2118. }
  2119. static int snd_cs46xx_midi_input_open(struct snd_rawmidi_substream *substream)
  2120. {
  2121. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2122. chip->active_ctrl(chip, 1);
  2123. spin_lock_irq(&chip->reg_lock);
  2124. chip->uartm |= CS46XX_MODE_INPUT;
  2125. chip->midcr |= MIDCR_RXE;
  2126. chip->midi_input = substream;
  2127. if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
  2128. snd_cs46xx_midi_reset(chip);
  2129. } else {
  2130. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2131. }
  2132. spin_unlock_irq(&chip->reg_lock);
  2133. return 0;
  2134. }
  2135. static int snd_cs46xx_midi_input_close(struct snd_rawmidi_substream *substream)
  2136. {
  2137. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2138. spin_lock_irq(&chip->reg_lock);
  2139. chip->midcr &= ~(MIDCR_RXE | MIDCR_RIE);
  2140. chip->midi_input = NULL;
  2141. if (!(chip->uartm & CS46XX_MODE_OUTPUT)) {
  2142. snd_cs46xx_midi_reset(chip);
  2143. } else {
  2144. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2145. }
  2146. chip->uartm &= ~CS46XX_MODE_INPUT;
  2147. spin_unlock_irq(&chip->reg_lock);
  2148. chip->active_ctrl(chip, -1);
  2149. return 0;
  2150. }
  2151. static int snd_cs46xx_midi_output_open(struct snd_rawmidi_substream *substream)
  2152. {
  2153. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2154. chip->active_ctrl(chip, 1);
  2155. spin_lock_irq(&chip->reg_lock);
  2156. chip->uartm |= CS46XX_MODE_OUTPUT;
  2157. chip->midcr |= MIDCR_TXE;
  2158. chip->midi_output = substream;
  2159. if (!(chip->uartm & CS46XX_MODE_INPUT)) {
  2160. snd_cs46xx_midi_reset(chip);
  2161. } else {
  2162. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2163. }
  2164. spin_unlock_irq(&chip->reg_lock);
  2165. return 0;
  2166. }
  2167. static int snd_cs46xx_midi_output_close(struct snd_rawmidi_substream *substream)
  2168. {
  2169. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2170. spin_lock_irq(&chip->reg_lock);
  2171. chip->midcr &= ~(MIDCR_TXE | MIDCR_TIE);
  2172. chip->midi_output = NULL;
  2173. if (!(chip->uartm & CS46XX_MODE_INPUT)) {
  2174. snd_cs46xx_midi_reset(chip);
  2175. } else {
  2176. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2177. }
  2178. chip->uartm &= ~CS46XX_MODE_OUTPUT;
  2179. spin_unlock_irq(&chip->reg_lock);
  2180. chip->active_ctrl(chip, -1);
  2181. return 0;
  2182. }
  2183. static void snd_cs46xx_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
  2184. {
  2185. unsigned long flags;
  2186. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2187. spin_lock_irqsave(&chip->reg_lock, flags);
  2188. if (up) {
  2189. if ((chip->midcr & MIDCR_RIE) == 0) {
  2190. chip->midcr |= MIDCR_RIE;
  2191. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2192. }
  2193. } else {
  2194. if (chip->midcr & MIDCR_RIE) {
  2195. chip->midcr &= ~MIDCR_RIE;
  2196. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2197. }
  2198. }
  2199. spin_unlock_irqrestore(&chip->reg_lock, flags);
  2200. }
  2201. static void snd_cs46xx_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
  2202. {
  2203. unsigned long flags;
  2204. struct snd_cs46xx *chip = substream->rmidi->private_data;
  2205. unsigned char byte;
  2206. spin_lock_irqsave(&chip->reg_lock, flags);
  2207. if (up) {
  2208. if ((chip->midcr & MIDCR_TIE) == 0) {
  2209. chip->midcr |= MIDCR_TIE;
  2210. /* fill UART FIFO buffer at first, and turn Tx interrupts only if necessary */
  2211. while ((chip->midcr & MIDCR_TIE) &&
  2212. (snd_cs46xx_peekBA0(chip, BA0_MIDSR) & MIDSR_TBF) == 0) {
  2213. if (snd_rawmidi_transmit(substream, &byte, 1) != 1) {
  2214. chip->midcr &= ~MIDCR_TIE;
  2215. } else {
  2216. snd_cs46xx_pokeBA0(chip, BA0_MIDWP, byte);
  2217. }
  2218. }
  2219. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2220. }
  2221. } else {
  2222. if (chip->midcr & MIDCR_TIE) {
  2223. chip->midcr &= ~MIDCR_TIE;
  2224. snd_cs46xx_pokeBA0(chip, BA0_MIDCR, chip->midcr);
  2225. }
  2226. }
  2227. spin_unlock_irqrestore(&chip->reg_lock, flags);
  2228. }
  2229. static struct snd_rawmidi_ops snd_cs46xx_midi_output =
  2230. {
  2231. .open = snd_cs46xx_midi_output_open,
  2232. .close = snd_cs46xx_midi_output_close,
  2233. .trigger = snd_cs46xx_midi_output_trigger,
  2234. };
  2235. static struct snd_rawmidi_ops snd_cs46xx_midi_input =
  2236. {
  2237. .open = snd_cs46xx_midi_input_open,
  2238. .close = snd_cs46xx_midi_input_close,
  2239. .trigger = snd_cs46xx_midi_input_trigger,
  2240. };
  2241. int __devinit snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rrawmidi)
  2242. {
  2243. struct snd_rawmidi *rmidi;
  2244. int err;
  2245. if (rrawmidi)
  2246. *rrawmidi = NULL;
  2247. if ((err = snd_rawmidi_new(chip->card, "CS46XX", device, 1, 1, &rmidi)) < 0)
  2248. return err;
  2249. strcpy(rmidi->name, "CS46XX");
  2250. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_cs46xx_midi_output);
  2251. snd_rawmidi_set_ops(rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_cs46xx_midi_input);
  2252. rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT | SNDRV_RAWMIDI_INFO_INPUT | SNDRV_RAWMIDI_INFO_DUPLEX;
  2253. rmidi->private_data = chip;
  2254. chip->rmidi = rmidi;
  2255. if (rrawmidi)
  2256. *rrawmidi = NULL;
  2257. return 0;
  2258. }
  2259. /*
  2260. * gameport interface
  2261. */
  2262. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  2263. static void snd_cs46xx_gameport_trigger(struct gameport *gameport)
  2264. {
  2265. struct snd_cs46xx *chip = gameport_get_port_data(gameport);
  2266. snd_assert(chip, return);
  2267. snd_cs46xx_pokeBA0(chip, BA0_JSPT, 0xFF); //outb(gameport->io, 0xFF);
  2268. }
  2269. static unsigned char snd_cs46xx_gameport_read(struct gameport *gameport)
  2270. {
  2271. struct snd_cs46xx *chip = gameport_get_port_data(gameport);
  2272. snd_assert(chip, return 0);
  2273. return snd_cs46xx_peekBA0(chip, BA0_JSPT); //inb(gameport->io);
  2274. }
  2275. static int snd_cs46xx_gameport_cooked_read(struct gameport *gameport, int *axes, int *buttons)
  2276. {
  2277. struct snd_cs46xx *chip = gameport_get_port_data(gameport);
  2278. unsigned js1, js2, jst;
  2279. snd_assert(chip, return 0);
  2280. js1 = snd_cs46xx_peekBA0(chip, BA0_JSC1);
  2281. js2 = snd_cs46xx_peekBA0(chip, BA0_JSC2);
  2282. jst = snd_cs46xx_peekBA0(chip, BA0_JSPT);
  2283. *buttons = (~jst >> 4) & 0x0F;
  2284. axes[0] = ((js1 & JSC1_Y1V_MASK) >> JSC1_Y1V_SHIFT) & 0xFFFF;
  2285. axes[1] = ((js1 & JSC1_X1V_MASK) >> JSC1_X1V_SHIFT) & 0xFFFF;
  2286. axes[2] = ((js2 & JSC2_Y2V_MASK) >> JSC2_Y2V_SHIFT) & 0xFFFF;
  2287. axes[3] = ((js2 & JSC2_X2V_MASK) >> JSC2_X2V_SHIFT) & 0xFFFF;
  2288. for(jst=0;jst<4;++jst)
  2289. if(axes[jst]==0xFFFF) axes[jst] = -1;
  2290. return 0;
  2291. }
  2292. static int snd_cs46xx_gameport_open(struct gameport *gameport, int mode)
  2293. {
  2294. switch (mode) {
  2295. case GAMEPORT_MODE_COOKED:
  2296. return 0;
  2297. case GAMEPORT_MODE_RAW:
  2298. return 0;
  2299. default:
  2300. return -1;
  2301. }
  2302. return 0;
  2303. }
  2304. int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip)
  2305. {
  2306. struct gameport *gp;
  2307. chip->gameport = gp = gameport_allocate_port();
  2308. if (!gp) {
  2309. printk(KERN_ERR "cs46xx: cannot allocate memory for gameport\n");
  2310. return -ENOMEM;
  2311. }
  2312. gameport_set_name(gp, "CS46xx Gameport");
  2313. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  2314. gameport_set_dev_parent(gp, &chip->pci->dev);
  2315. gameport_set_port_data(gp, chip);
  2316. gp->open = snd_cs46xx_gameport_open;
  2317. gp->read = snd_cs46xx_gameport_read;
  2318. gp->trigger = snd_cs46xx_gameport_trigger;
  2319. gp->cooked_read = snd_cs46xx_gameport_cooked_read;
  2320. snd_cs46xx_pokeBA0(chip, BA0_JSIO, 0xFF); // ?
  2321. snd_cs46xx_pokeBA0(chip, BA0_JSCTL, JSCTL_SP_MEDIUM_SLOW);
  2322. gameport_register_port(gp);
  2323. return 0;
  2324. }
  2325. static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip)
  2326. {
  2327. if (chip->gameport) {
  2328. gameport_unregister_port(chip->gameport);
  2329. chip->gameport = NULL;
  2330. }
  2331. }
  2332. #else
  2333. int __devinit snd_cs46xx_gameport(struct snd_cs46xx *chip) { return -ENOSYS; }
  2334. static inline void snd_cs46xx_remove_gameport(struct snd_cs46xx *chip) { }
  2335. #endif /* CONFIG_GAMEPORT */
  2336. #ifdef CONFIG_PROC_FS
  2337. /*
  2338. * proc interface
  2339. */
  2340. static long snd_cs46xx_io_read(struct snd_info_entry *entry, void *file_private_data,
  2341. struct file *file, char __user *buf,
  2342. unsigned long count, unsigned long pos)
  2343. {
  2344. long size;
  2345. struct snd_cs46xx_region *region = entry->private_data;
  2346. size = count;
  2347. if (pos + (size_t)size > region->size)
  2348. size = region->size - pos;
  2349. if (size > 0) {
  2350. if (copy_to_user_fromio(buf, region->remap_addr + pos, size))
  2351. return -EFAULT;
  2352. }
  2353. return size;
  2354. }
  2355. static struct snd_info_entry_ops snd_cs46xx_proc_io_ops = {
  2356. .read = snd_cs46xx_io_read,
  2357. };
  2358. static int __devinit snd_cs46xx_proc_init(struct snd_card *card, struct snd_cs46xx *chip)
  2359. {
  2360. struct snd_info_entry *entry;
  2361. int idx;
  2362. for (idx = 0; idx < 5; idx++) {
  2363. struct snd_cs46xx_region *region = &chip->region.idx[idx];
  2364. if (! snd_card_proc_new(card, region->name, &entry)) {
  2365. entry->content = SNDRV_INFO_CONTENT_DATA;
  2366. entry->private_data = chip;
  2367. entry->c.ops = &snd_cs46xx_proc_io_ops;
  2368. entry->size = region->size;
  2369. entry->mode = S_IFREG | S_IRUSR;
  2370. }
  2371. }
  2372. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2373. cs46xx_dsp_proc_init(card, chip);
  2374. #endif
  2375. return 0;
  2376. }
  2377. static int snd_cs46xx_proc_done(struct snd_cs46xx *chip)
  2378. {
  2379. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2380. cs46xx_dsp_proc_done(chip);
  2381. #endif
  2382. return 0;
  2383. }
  2384. #else /* !CONFIG_PROC_FS */
  2385. #define snd_cs46xx_proc_init(card, chip)
  2386. #define snd_cs46xx_proc_done(chip)
  2387. #endif
  2388. /*
  2389. * stop the h/w
  2390. */
  2391. static void snd_cs46xx_hw_stop(struct snd_cs46xx *chip)
  2392. {
  2393. unsigned int tmp;
  2394. tmp = snd_cs46xx_peek(chip, BA1_PFIE);
  2395. tmp &= ~0x0000f03f;
  2396. tmp |= 0x00000010;
  2397. snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt disable */
  2398. tmp = snd_cs46xx_peek(chip, BA1_CIE);
  2399. tmp &= ~0x0000003f;
  2400. tmp |= 0x00000011;
  2401. snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt disable */
  2402. /*
  2403. * Stop playback DMA.
  2404. */
  2405. tmp = snd_cs46xx_peek(chip, BA1_PCTL);
  2406. snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
  2407. /*
  2408. * Stop capture DMA.
  2409. */
  2410. tmp = snd_cs46xx_peek(chip, BA1_CCTL);
  2411. snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
  2412. /*
  2413. * Reset the processor.
  2414. */
  2415. snd_cs46xx_reset(chip);
  2416. snd_cs46xx_proc_stop(chip);
  2417. /*
  2418. * Power down the PLL.
  2419. */
  2420. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
  2421. /*
  2422. * Turn off the Processor by turning off the software clock enable flag in
  2423. * the clock control register.
  2424. */
  2425. tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE;
  2426. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
  2427. }
  2428. static int snd_cs46xx_free(struct snd_cs46xx *chip)
  2429. {
  2430. int idx;
  2431. snd_assert(chip != NULL, return -EINVAL);
  2432. if (chip->active_ctrl)
  2433. chip->active_ctrl(chip, 1);
  2434. snd_cs46xx_remove_gameport(chip);
  2435. if (chip->amplifier_ctrl)
  2436. chip->amplifier_ctrl(chip, -chip->amplifier); /* force to off */
  2437. snd_cs46xx_proc_done(chip);
  2438. if (chip->region.idx[0].resource)
  2439. snd_cs46xx_hw_stop(chip);
  2440. if (chip->irq >= 0)
  2441. free_irq(chip->irq, chip);
  2442. for (idx = 0; idx < 5; idx++) {
  2443. struct snd_cs46xx_region *region = &chip->region.idx[idx];
  2444. if (region->remap_addr)
  2445. iounmap(region->remap_addr);
  2446. release_and_free_resource(region->resource);
  2447. }
  2448. if (chip->active_ctrl)
  2449. chip->active_ctrl(chip, -chip->amplifier);
  2450. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2451. if (chip->dsp_spos_instance) {
  2452. cs46xx_dsp_spos_destroy(chip);
  2453. chip->dsp_spos_instance = NULL;
  2454. }
  2455. #endif
  2456. pci_disable_device(chip->pci);
  2457. kfree(chip);
  2458. return 0;
  2459. }
  2460. static int snd_cs46xx_dev_free(struct snd_device *device)
  2461. {
  2462. struct snd_cs46xx *chip = device->device_data;
  2463. return snd_cs46xx_free(chip);
  2464. }
  2465. /*
  2466. * initialize chip
  2467. */
  2468. static int snd_cs46xx_chip_init(struct snd_cs46xx *chip)
  2469. {
  2470. int timeout;
  2471. /*
  2472. * First, blast the clock control register to zero so that the PLL starts
  2473. * out in a known state, and blast the master serial port control register
  2474. * to zero so that the serial ports also start out in a known state.
  2475. */
  2476. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, 0);
  2477. snd_cs46xx_pokeBA0(chip, BA0_SERMC1, 0);
  2478. /*
  2479. * If we are in AC97 mode, then we must set the part to a host controlled
  2480. * AC-link. Otherwise, we won't be able to bring up the link.
  2481. */
  2482. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2483. snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0 |
  2484. SERACC_TWO_CODECS); /* 2.00 dual codecs */
  2485. /* snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_2_0); */ /* 2.00 codec */
  2486. #else
  2487. snd_cs46xx_pokeBA0(chip, BA0_SERACC, SERACC_HSP | SERACC_CHIP_TYPE_1_03); /* 1.03 codec */
  2488. #endif
  2489. /*
  2490. * Drive the ARST# pin low for a minimum of 1uS (as defined in the AC97
  2491. * spec) and then drive it high. This is done for non AC97 modes since
  2492. * there might be logic external to the CS461x that uses the ARST# line
  2493. * for a reset.
  2494. */
  2495. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, 0);
  2496. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2497. snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, 0);
  2498. #endif
  2499. udelay(50);
  2500. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_RSTN);
  2501. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2502. snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_RSTN);
  2503. #endif
  2504. /*
  2505. * The first thing we do here is to enable sync generation. As soon
  2506. * as we start receiving bit clock, we'll start producing the SYNC
  2507. * signal.
  2508. */
  2509. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_ESYN | ACCTL_RSTN);
  2510. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2511. snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_ESYN | ACCTL_RSTN);
  2512. #endif
  2513. /*
  2514. * Now wait for a short while to allow the AC97 part to start
  2515. * generating bit clock (so we don't try to start the PLL without an
  2516. * input clock).
  2517. */
  2518. mdelay(10);
  2519. /*
  2520. * Set the serial port timing configuration, so that
  2521. * the clock control circuit gets its clock from the correct place.
  2522. */
  2523. snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97);
  2524. /*
  2525. * Write the selected clock control setup to the hardware. Do not turn on
  2526. * SWCE yet (if requested), so that the devices clocked by the output of
  2527. * PLL are not clocked until the PLL is stable.
  2528. */
  2529. snd_cs46xx_pokeBA0(chip, BA0_PLLCC, PLLCC_LPF_1050_2780_KHZ | PLLCC_CDR_73_104_MHZ);
  2530. snd_cs46xx_pokeBA0(chip, BA0_PLLM, 0x3a);
  2531. snd_cs46xx_pokeBA0(chip, BA0_CLKCR2, CLKCR2_PDIVS_8);
  2532. /*
  2533. * Power up the PLL.
  2534. */
  2535. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP);
  2536. /*
  2537. * Wait until the PLL has stabilized.
  2538. */
  2539. msleep(100);
  2540. /*
  2541. * Turn on clocking of the core so that we can setup the serial ports.
  2542. */
  2543. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, CLKCR1_PLLP | CLKCR1_SWCE);
  2544. /*
  2545. * Enable FIFO Host Bypass
  2546. */
  2547. snd_cs46xx_pokeBA0(chip, BA0_SERBCF, SERBCF_HBP);
  2548. /*
  2549. * Fill the serial port FIFOs with silence.
  2550. */
  2551. snd_cs46xx_clear_serial_FIFOs(chip);
  2552. /*
  2553. * Set the serial port FIFO pointer to the first sample in the FIFO.
  2554. */
  2555. /* snd_cs46xx_pokeBA0(chip, BA0_SERBSP, 0); */
  2556. /*
  2557. * Write the serial port configuration to the part. The master
  2558. * enable bit is not set until all other values have been written.
  2559. */
  2560. snd_cs46xx_pokeBA0(chip, BA0_SERC1, SERC1_SO1F_AC97 | SERC1_SO1EN);
  2561. snd_cs46xx_pokeBA0(chip, BA0_SERC2, SERC2_SI1F_AC97 | SERC1_SO1EN);
  2562. snd_cs46xx_pokeBA0(chip, BA0_SERMC1, SERMC1_PTC_AC97 | SERMC1_MSPE);
  2563. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2564. snd_cs46xx_pokeBA0(chip, BA0_SERC7, SERC7_ASDI2EN);
  2565. snd_cs46xx_pokeBA0(chip, BA0_SERC3, 0);
  2566. snd_cs46xx_pokeBA0(chip, BA0_SERC4, 0);
  2567. snd_cs46xx_pokeBA0(chip, BA0_SERC5, 0);
  2568. snd_cs46xx_pokeBA0(chip, BA0_SERC6, 1);
  2569. #endif
  2570. mdelay(5);
  2571. /*
  2572. * Wait for the codec ready signal from the AC97 codec.
  2573. */
  2574. timeout = 150;
  2575. while (timeout-- > 0) {
  2576. /*
  2577. * Read the AC97 status register to see if we've seen a CODEC READY
  2578. * signal from the AC97 codec.
  2579. */
  2580. if (snd_cs46xx_peekBA0(chip, BA0_ACSTS) & ACSTS_CRDY)
  2581. goto ok1;
  2582. msleep(10);
  2583. }
  2584. snd_printk(KERN_ERR "create - never read codec ready from AC'97\n");
  2585. snd_printk(KERN_ERR "it is not probably bug, try to use CS4236 driver\n");
  2586. return -EIO;
  2587. ok1:
  2588. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2589. {
  2590. int count;
  2591. for (count = 0; count < 150; count++) {
  2592. /* First, we want to wait for a short time. */
  2593. udelay(25);
  2594. if (snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY)
  2595. break;
  2596. }
  2597. /*
  2598. * Make sure CODEC is READY.
  2599. */
  2600. if (!(snd_cs46xx_peekBA0(chip, BA0_ACSTS2) & ACSTS_CRDY))
  2601. snd_printdd("cs46xx: never read card ready from secondary AC'97\n");
  2602. }
  2603. #endif
  2604. /*
  2605. * Assert the vaid frame signal so that we can start sending commands
  2606. * to the AC97 codec.
  2607. */
  2608. snd_cs46xx_pokeBA0(chip, BA0_ACCTL, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
  2609. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2610. snd_cs46xx_pokeBA0(chip, BA0_ACCTL2, ACCTL_VFRM | ACCTL_ESYN | ACCTL_RSTN);
  2611. #endif
  2612. /*
  2613. * Wait until we've sampled input slots 3 and 4 as valid, meaning that
  2614. * the codec is pumping ADC data across the AC-link.
  2615. */
  2616. timeout = 150;
  2617. while (timeout-- > 0) {
  2618. /*
  2619. * Read the input slot valid register and see if input slots 3 and
  2620. * 4 are valid yet.
  2621. */
  2622. if ((snd_cs46xx_peekBA0(chip, BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4)) == (ACISV_ISV3 | ACISV_ISV4))
  2623. goto ok2;
  2624. msleep(10);
  2625. }
  2626. #ifndef CONFIG_SND_CS46XX_NEW_DSP
  2627. snd_printk(KERN_ERR "create - never read ISV3 & ISV4 from AC'97\n");
  2628. return -EIO;
  2629. #else
  2630. /* This may happen on a cold boot with a Terratec SiXPack 5.1.
  2631. Reloading the driver may help, if there's other soundcards
  2632. with the same problem I would like to know. (Benny) */
  2633. snd_printk(KERN_ERR "ERROR: snd-cs46xx: never read ISV3 & ISV4 from AC'97\n");
  2634. snd_printk(KERN_ERR " Try reloading the ALSA driver, if you find something\n");
  2635. snd_printk(KERN_ERR " broken or not working on your soundcard upon\n");
  2636. snd_printk(KERN_ERR " this message please report to alsa-devel@lists.sourceforge.net\n");
  2637. return -EIO;
  2638. #endif
  2639. ok2:
  2640. /*
  2641. * Now, assert valid frame and the slot 3 and 4 valid bits. This will
  2642. * commense the transfer of digital audio data to the AC97 codec.
  2643. */
  2644. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, ACOSV_SLV3 | ACOSV_SLV4);
  2645. /*
  2646. * Power down the DAC and ADC. We will power them up (if) when we need
  2647. * them.
  2648. */
  2649. /* snd_cs46xx_pokeBA0(chip, BA0_AC97_POWERDOWN, 0x300); */
  2650. /*
  2651. * Turn off the Processor by turning off the software clock enable flag in
  2652. * the clock control register.
  2653. */
  2654. /* tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1) & ~CLKCR1_SWCE; */
  2655. /* snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp); */
  2656. return 0;
  2657. }
  2658. /*
  2659. * start and load DSP
  2660. */
  2661. int __devinit snd_cs46xx_start_dsp(struct snd_cs46xx *chip)
  2662. {
  2663. unsigned int tmp;
  2664. /*
  2665. * Reset the processor.
  2666. */
  2667. snd_cs46xx_reset(chip);
  2668. /*
  2669. * Download the image to the processor.
  2670. */
  2671. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2672. #if 0
  2673. if (cs46xx_dsp_load_module(chip, &cwcemb80_module) < 0) {
  2674. snd_printk(KERN_ERR "image download error\n");
  2675. return -EIO;
  2676. }
  2677. #endif
  2678. if (cs46xx_dsp_load_module(chip, &cwc4630_module) < 0) {
  2679. snd_printk(KERN_ERR "image download error [cwc4630]\n");
  2680. return -EIO;
  2681. }
  2682. if (cs46xx_dsp_load_module(chip, &cwcasync_module) < 0) {
  2683. snd_printk(KERN_ERR "image download error [cwcasync]\n");
  2684. return -EIO;
  2685. }
  2686. if (cs46xx_dsp_load_module(chip, &cwcsnoop_module) < 0) {
  2687. snd_printk(KERN_ERR "image download error [cwcsnoop]\n");
  2688. return -EIO;
  2689. }
  2690. if (cs46xx_dsp_load_module(chip, &cwcbinhack_module) < 0) {
  2691. snd_printk(KERN_ERR "image download error [cwcbinhack]\n");
  2692. return -EIO;
  2693. }
  2694. if (cs46xx_dsp_load_module(chip, &cwcdma_module) < 0) {
  2695. snd_printk(KERN_ERR "image download error [cwcdma]\n");
  2696. return -EIO;
  2697. }
  2698. if (cs46xx_dsp_scb_and_task_init(chip) < 0)
  2699. return -EIO;
  2700. #else
  2701. /* old image */
  2702. if (snd_cs46xx_download_image(chip) < 0) {
  2703. snd_printk(KERN_ERR "image download error\n");
  2704. return -EIO;
  2705. }
  2706. /*
  2707. * Stop playback DMA.
  2708. */
  2709. tmp = snd_cs46xx_peek(chip, BA1_PCTL);
  2710. chip->play_ctl = tmp & 0xffff0000;
  2711. snd_cs46xx_poke(chip, BA1_PCTL, tmp & 0x0000ffff);
  2712. #endif
  2713. /*
  2714. * Stop capture DMA.
  2715. */
  2716. tmp = snd_cs46xx_peek(chip, BA1_CCTL);
  2717. chip->capt.ctl = tmp & 0x0000ffff;
  2718. snd_cs46xx_poke(chip, BA1_CCTL, tmp & 0xffff0000);
  2719. mdelay(5);
  2720. snd_cs46xx_set_play_sample_rate(chip, 8000);
  2721. snd_cs46xx_set_capture_sample_rate(chip, 8000);
  2722. snd_cs46xx_proc_start(chip);
  2723. /*
  2724. * Enable interrupts on the part.
  2725. */
  2726. snd_cs46xx_pokeBA0(chip, BA0_HICR, HICR_IEV | HICR_CHGM);
  2727. tmp = snd_cs46xx_peek(chip, BA1_PFIE);
  2728. tmp &= ~0x0000f03f;
  2729. snd_cs46xx_poke(chip, BA1_PFIE, tmp); /* playback interrupt enable */
  2730. tmp = snd_cs46xx_peek(chip, BA1_CIE);
  2731. tmp &= ~0x0000003f;
  2732. tmp |= 0x00000001;
  2733. snd_cs46xx_poke(chip, BA1_CIE, tmp); /* capture interrupt enable */
  2734. #ifndef CONFIG_SND_CS46XX_NEW_DSP
  2735. /* set the attenuation to 0dB */
  2736. snd_cs46xx_poke(chip, BA1_PVOL, 0x80008000);
  2737. snd_cs46xx_poke(chip, BA1_CVOL, 0x80008000);
  2738. #endif
  2739. return 0;
  2740. }
  2741. /*
  2742. * AMP control - null AMP
  2743. */
  2744. static void amp_none(struct snd_cs46xx *chip, int change)
  2745. {
  2746. }
  2747. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2748. static int voyetra_setup_eapd_slot(struct snd_cs46xx *chip)
  2749. {
  2750. u32 idx, valid_slots,tmp,powerdown = 0;
  2751. u16 modem_power,pin_config,logic_type;
  2752. snd_printdd ("cs46xx: cs46xx_setup_eapd_slot()+\n");
  2753. /*
  2754. * See if the devices are powered down. If so, we must power them up first
  2755. * or they will not respond.
  2756. */
  2757. tmp = snd_cs46xx_peekBA0(chip, BA0_CLKCR1);
  2758. if (!(tmp & CLKCR1_SWCE)) {
  2759. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp | CLKCR1_SWCE);
  2760. powerdown = 1;
  2761. }
  2762. /*
  2763. * Clear PRA. The Bonzo chip will be used for GPIO not for modem
  2764. * stuff.
  2765. */
  2766. if(chip->nr_ac97_codecs != 2) {
  2767. snd_printk (KERN_ERR "cs46xx: cs46xx_setup_eapd_slot() - no secondary codec configured\n");
  2768. return -EINVAL;
  2769. }
  2770. modem_power = snd_cs46xx_codec_read (chip,
  2771. AC97_EXTENDED_MSTATUS,
  2772. CS46XX_SECONDARY_CODEC_INDEX);
  2773. modem_power &=0xFEFF;
  2774. snd_cs46xx_codec_write(chip,
  2775. AC97_EXTENDED_MSTATUS, modem_power,
  2776. CS46XX_SECONDARY_CODEC_INDEX);
  2777. /*
  2778. * Set GPIO pin's 7 and 8 so that they are configured for output.
  2779. */
  2780. pin_config = snd_cs46xx_codec_read (chip,
  2781. AC97_GPIO_CFG,
  2782. CS46XX_SECONDARY_CODEC_INDEX);
  2783. pin_config &=0x27F;
  2784. snd_cs46xx_codec_write(chip,
  2785. AC97_GPIO_CFG, pin_config,
  2786. CS46XX_SECONDARY_CODEC_INDEX);
  2787. /*
  2788. * Set GPIO pin's 7 and 8 so that they are compatible with CMOS logic.
  2789. */
  2790. logic_type = snd_cs46xx_codec_read(chip, AC97_GPIO_POLARITY,
  2791. CS46XX_SECONDARY_CODEC_INDEX);
  2792. logic_type &=0x27F;
  2793. snd_cs46xx_codec_write (chip, AC97_GPIO_POLARITY, logic_type,
  2794. CS46XX_SECONDARY_CODEC_INDEX);
  2795. valid_slots = snd_cs46xx_peekBA0(chip, BA0_ACOSV);
  2796. valid_slots |= 0x200;
  2797. snd_cs46xx_pokeBA0(chip, BA0_ACOSV, valid_slots);
  2798. if ( cs46xx_wait_for_fifo(chip,1) ) {
  2799. snd_printdd("FIFO is busy\n");
  2800. return -EINVAL;
  2801. }
  2802. /*
  2803. * Fill slots 12 with the correct value for the GPIO pins.
  2804. */
  2805. for(idx = 0x90; idx <= 0x9F; idx++) {
  2806. /*
  2807. * Initialize the fifo so that bits 7 and 8 are on.
  2808. *
  2809. * Remember that the GPIO pins in bonzo are shifted by 4 bits to
  2810. * the left. 0x1800 corresponds to bits 7 and 8.
  2811. */
  2812. snd_cs46xx_pokeBA0(chip, BA0_SERBWP, 0x1800);
  2813. /*
  2814. * Wait for command to complete
  2815. */
  2816. if ( cs46xx_wait_for_fifo(chip,200) ) {
  2817. snd_printdd("failed waiting for FIFO at addr (%02X)\n",idx);
  2818. return -EINVAL;
  2819. }
  2820. /*
  2821. * Write the serial port FIFO index.
  2822. */
  2823. snd_cs46xx_pokeBA0(chip, BA0_SERBAD, idx);
  2824. /*
  2825. * Tell the serial port to load the new value into the FIFO location.
  2826. */
  2827. snd_cs46xx_pokeBA0(chip, BA0_SERBCM, SERBCM_WRC);
  2828. }
  2829. /* wait for last command to complete */
  2830. cs46xx_wait_for_fifo(chip,200);
  2831. /*
  2832. * Now, if we powered up the devices, then power them back down again.
  2833. * This is kinda ugly, but should never happen.
  2834. */
  2835. if (powerdown)
  2836. snd_cs46xx_pokeBA0(chip, BA0_CLKCR1, tmp);
  2837. return 0;
  2838. }
  2839. #endif
  2840. /*
  2841. * Crystal EAPD mode
  2842. */
  2843. static void amp_voyetra(struct snd_cs46xx *chip, int change)
  2844. {
  2845. /* Manage the EAPD bit on the Crystal 4297
  2846. and the Analog AD1885 */
  2847. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2848. int old = chip->amplifier;
  2849. #endif
  2850. int oval, val;
  2851. chip->amplifier += change;
  2852. oval = snd_cs46xx_codec_read(chip, AC97_POWERDOWN,
  2853. CS46XX_PRIMARY_CODEC_INDEX);
  2854. val = oval;
  2855. if (chip->amplifier) {
  2856. /* Turn the EAPD amp on */
  2857. val |= 0x8000;
  2858. } else {
  2859. /* Turn the EAPD amp off */
  2860. val &= ~0x8000;
  2861. }
  2862. if (val != oval) {
  2863. snd_cs46xx_codec_write(chip, AC97_POWERDOWN, val,
  2864. CS46XX_PRIMARY_CODEC_INDEX);
  2865. if (chip->eapd_switch)
  2866. snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
  2867. &chip->eapd_switch->id);
  2868. }
  2869. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2870. if (chip->amplifier && !old) {
  2871. voyetra_setup_eapd_slot(chip);
  2872. }
  2873. #endif
  2874. }
  2875. static void hercules_init(struct snd_cs46xx *chip)
  2876. {
  2877. /* default: AMP off, and SPDIF input optical */
  2878. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
  2879. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
  2880. }
  2881. /*
  2882. * Game Theatre XP card - EGPIO[2] is used to enable the external amp.
  2883. */
  2884. static void amp_hercules(struct snd_cs46xx *chip, int change)
  2885. {
  2886. int old = chip->amplifier;
  2887. int val1 = snd_cs46xx_peekBA0(chip, BA0_EGPIODR);
  2888. int val2 = snd_cs46xx_peekBA0(chip, BA0_EGPIOPTR);
  2889. chip->amplifier += change;
  2890. if (chip->amplifier && !old) {
  2891. snd_printdd ("Hercules amplifier ON\n");
  2892. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR,
  2893. EGPIODR_GPOE2 | val1); /* enable EGPIO2 output */
  2894. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR,
  2895. EGPIOPTR_GPPT2 | val2); /* open-drain on output */
  2896. } else if (old && !chip->amplifier) {
  2897. snd_printdd ("Hercules amplifier OFF\n");
  2898. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, val1 & ~EGPIODR_GPOE2); /* disable */
  2899. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, val2 & ~EGPIOPTR_GPPT2); /* disable */
  2900. }
  2901. }
  2902. static void voyetra_mixer_init (struct snd_cs46xx *chip)
  2903. {
  2904. snd_printdd ("initializing Voyetra mixer\n");
  2905. /* Enable SPDIF out */
  2906. snd_cs46xx_pokeBA0(chip, BA0_EGPIODR, EGPIODR_GPOE0);
  2907. snd_cs46xx_pokeBA0(chip, BA0_EGPIOPTR, EGPIODR_GPOE0);
  2908. }
  2909. static void hercules_mixer_init (struct snd_cs46xx *chip)
  2910. {
  2911. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2912. unsigned int idx;
  2913. int err;
  2914. struct snd_card *card = chip->card;
  2915. #endif
  2916. /* set EGPIO to default */
  2917. hercules_init(chip);
  2918. snd_printdd ("initializing Hercules mixer\n");
  2919. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  2920. if (chip->in_suspend)
  2921. return;
  2922. for (idx = 0 ; idx < ARRAY_SIZE(snd_hercules_controls); idx++) {
  2923. struct snd_kcontrol *kctl;
  2924. kctl = snd_ctl_new1(&snd_hercules_controls[idx], chip);
  2925. if ((err = snd_ctl_add(card, kctl)) < 0) {
  2926. printk (KERN_ERR "cs46xx: failed to initialize Hercules mixer (%d)\n",err);
  2927. break;
  2928. }
  2929. }
  2930. #endif
  2931. }
  2932. #if 0
  2933. /*
  2934. * Untested
  2935. */
  2936. static void amp_voyetra_4294(struct snd_cs46xx *chip, int change)
  2937. {
  2938. chip->amplifier += change;
  2939. if (chip->amplifier) {
  2940. /* Switch the GPIO pins 7 and 8 to open drain */
  2941. snd_cs46xx_codec_write(chip, 0x4C,
  2942. snd_cs46xx_codec_read(chip, 0x4C) & 0xFE7F);
  2943. snd_cs46xx_codec_write(chip, 0x4E,
  2944. snd_cs46xx_codec_read(chip, 0x4E) | 0x0180);
  2945. /* Now wake the AMP (this might be backwards) */
  2946. snd_cs46xx_codec_write(chip, 0x54,
  2947. snd_cs46xx_codec_read(chip, 0x54) & ~0x0180);
  2948. } else {
  2949. snd_cs46xx_codec_write(chip, 0x54,
  2950. snd_cs46xx_codec_read(chip, 0x54) | 0x0180);
  2951. }
  2952. }
  2953. #endif
  2954. /*
  2955. * Handle the CLKRUN on a thinkpad. We must disable CLKRUN support
  2956. * whenever we need to beat on the chip.
  2957. *
  2958. * The original idea and code for this hack comes from David Kaiser at
  2959. * Linuxcare. Perhaps one day Crystal will document their chips well
  2960. * enough to make them useful.
  2961. */
  2962. static void clkrun_hack(struct snd_cs46xx *chip, int change)
  2963. {
  2964. u16 control, nval;
  2965. if (!chip->acpi_port)
  2966. return;
  2967. chip->amplifier += change;
  2968. /* Read ACPI port */
  2969. nval = control = inw(chip->acpi_port + 0x10);
  2970. /* Flip CLKRUN off while running */
  2971. if (! chip->amplifier)
  2972. nval |= 0x2000;
  2973. else
  2974. nval &= ~0x2000;
  2975. if (nval != control)
  2976. outw(nval, chip->acpi_port + 0x10);
  2977. }
  2978. /*
  2979. * detect intel piix4
  2980. */
  2981. static void clkrun_init(struct snd_cs46xx *chip)
  2982. {
  2983. struct pci_dev *pdev;
  2984. u8 pp;
  2985. chip->acpi_port = 0;
  2986. pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
  2987. PCI_DEVICE_ID_INTEL_82371AB_3, NULL);
  2988. if (pdev == NULL)
  2989. return; /* Not a thinkpad thats for sure */
  2990. /* Find the control port */
  2991. pci_read_config_byte(pdev, 0x41, &pp);
  2992. chip->acpi_port = pp << 8;
  2993. pci_dev_put(pdev);
  2994. }
  2995. /*
  2996. * Card subid table
  2997. */
  2998. struct cs_card_type
  2999. {
  3000. u16 vendor;
  3001. u16 id;
  3002. char *name;
  3003. void (*init)(struct snd_cs46xx *);
  3004. void (*amp)(struct snd_cs46xx *, int);
  3005. void (*active)(struct snd_cs46xx *, int);
  3006. void (*mixer_init)(struct snd_cs46xx *);
  3007. };
  3008. static struct cs_card_type __devinitdata cards[] = {
  3009. {
  3010. .vendor = 0x1489,
  3011. .id = 0x7001,
  3012. .name = "Genius Soundmaker 128 value",
  3013. /* nothing special */
  3014. },
  3015. {
  3016. .vendor = 0x5053,
  3017. .id = 0x3357,
  3018. .name = "Voyetra",
  3019. .amp = amp_voyetra,
  3020. .mixer_init = voyetra_mixer_init,
  3021. },
  3022. {
  3023. .vendor = 0x1071,
  3024. .id = 0x6003,
  3025. .name = "Mitac MI6020/21",
  3026. .amp = amp_voyetra,
  3027. },
  3028. {
  3029. .vendor = 0x14AF,
  3030. .id = 0x0050,
  3031. .name = "Hercules Game Theatre XP",
  3032. .amp = amp_hercules,
  3033. .mixer_init = hercules_mixer_init,
  3034. },
  3035. {
  3036. .vendor = 0x1681,
  3037. .id = 0x0050,
  3038. .name = "Hercules Game Theatre XP",
  3039. .amp = amp_hercules,
  3040. .mixer_init = hercules_mixer_init,
  3041. },
  3042. {
  3043. .vendor = 0x1681,
  3044. .id = 0x0051,
  3045. .name = "Hercules Game Theatre XP",
  3046. .amp = amp_hercules,
  3047. .mixer_init = hercules_mixer_init,
  3048. },
  3049. {
  3050. .vendor = 0x1681,
  3051. .id = 0x0052,
  3052. .name = "Hercules Game Theatre XP",
  3053. .amp = amp_hercules,
  3054. .mixer_init = hercules_mixer_init,
  3055. },
  3056. {
  3057. .vendor = 0x1681,
  3058. .id = 0x0053,
  3059. .name = "Hercules Game Theatre XP",
  3060. .amp = amp_hercules,
  3061. .mixer_init = hercules_mixer_init,
  3062. },
  3063. {
  3064. .vendor = 0x1681,
  3065. .id = 0x0054,
  3066. .name = "Hercules Game Theatre XP",
  3067. .amp = amp_hercules,
  3068. .mixer_init = hercules_mixer_init,
  3069. },
  3070. /* Teratec */
  3071. {
  3072. .vendor = 0x153b,
  3073. .id = 0x1136,
  3074. .name = "Terratec SiXPack 5.1",
  3075. },
  3076. /* Not sure if the 570 needs the clkrun hack */
  3077. {
  3078. .vendor = PCI_VENDOR_ID_IBM,
  3079. .id = 0x0132,
  3080. .name = "Thinkpad 570",
  3081. .init = clkrun_init,
  3082. .active = clkrun_hack,
  3083. },
  3084. {
  3085. .vendor = PCI_VENDOR_ID_IBM,
  3086. .id = 0x0153,
  3087. .name = "Thinkpad 600X/A20/T20",
  3088. .init = clkrun_init,
  3089. .active = clkrun_hack,
  3090. },
  3091. {
  3092. .vendor = PCI_VENDOR_ID_IBM,
  3093. .id = 0x1010,
  3094. .name = "Thinkpad 600E (unsupported)",
  3095. },
  3096. {} /* terminator */
  3097. };
  3098. /*
  3099. * APM support
  3100. */
  3101. #ifdef CONFIG_PM
  3102. int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state)
  3103. {
  3104. struct snd_card *card = pci_get_drvdata(pci);
  3105. struct snd_cs46xx *chip = card->private_data;
  3106. int amp_saved;
  3107. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  3108. chip->in_suspend = 1;
  3109. snd_pcm_suspend_all(chip->pcm);
  3110. // chip->ac97_powerdown = snd_cs46xx_codec_read(chip, AC97_POWER_CONTROL);
  3111. // chip->ac97_general_purpose = snd_cs46xx_codec_read(chip, BA0_AC97_GENERAL_PURPOSE);
  3112. snd_ac97_suspend(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
  3113. snd_ac97_suspend(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
  3114. amp_saved = chip->amplifier;
  3115. /* turn off amp */
  3116. chip->amplifier_ctrl(chip, -chip->amplifier);
  3117. snd_cs46xx_hw_stop(chip);
  3118. /* disable CLKRUN */
  3119. chip->active_ctrl(chip, -chip->amplifier);
  3120. chip->amplifier = amp_saved; /* restore the status */
  3121. pci_disable_device(pci);
  3122. pci_save_state(pci);
  3123. pci_set_power_state(pci, pci_choose_state(pci, state));
  3124. return 0;
  3125. }
  3126. int snd_cs46xx_resume(struct pci_dev *pci)
  3127. {
  3128. struct snd_card *card = pci_get_drvdata(pci);
  3129. struct snd_cs46xx *chip = card->private_data;
  3130. int amp_saved;
  3131. pci_set_power_state(pci, PCI_D0);
  3132. pci_restore_state(pci);
  3133. if (pci_enable_device(pci) < 0) {
  3134. printk(KERN_ERR "cs46xx: pci_enable_device failed, "
  3135. "disabling device\n");
  3136. snd_card_disconnect(card);
  3137. return -EIO;
  3138. }
  3139. pci_set_master(pci);
  3140. amp_saved = chip->amplifier;
  3141. chip->amplifier = 0;
  3142. chip->active_ctrl(chip, 1); /* force to on */
  3143. snd_cs46xx_chip_init(chip);
  3144. #if 0
  3145. snd_cs46xx_codec_write(chip, BA0_AC97_GENERAL_PURPOSE,
  3146. chip->ac97_general_purpose);
  3147. snd_cs46xx_codec_write(chip, AC97_POWER_CONTROL,
  3148. chip->ac97_powerdown);
  3149. mdelay(10);
  3150. snd_cs46xx_codec_write(chip, BA0_AC97_POWERDOWN,
  3151. chip->ac97_powerdown);
  3152. mdelay(5);
  3153. #endif
  3154. snd_ac97_resume(chip->ac97[CS46XX_PRIMARY_CODEC_INDEX]);
  3155. snd_ac97_resume(chip->ac97[CS46XX_SECONDARY_CODEC_INDEX]);
  3156. if (amp_saved)
  3157. chip->amplifier_ctrl(chip, 1); /* turn amp on */
  3158. else
  3159. chip->active_ctrl(chip, -1); /* disable CLKRUN */
  3160. chip->amplifier = amp_saved;
  3161. chip->in_suspend = 0;
  3162. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  3163. return 0;
  3164. }
  3165. #endif /* CONFIG_PM */
  3166. /*
  3167. */
  3168. int __devinit snd_cs46xx_create(struct snd_card *card,
  3169. struct pci_dev * pci,
  3170. int external_amp, int thinkpad,
  3171. struct snd_cs46xx ** rchip)
  3172. {
  3173. struct snd_cs46xx *chip;
  3174. int err, idx;
  3175. struct snd_cs46xx_region *region;
  3176. struct cs_card_type *cp;
  3177. u16 ss_card, ss_vendor;
  3178. static struct snd_device_ops ops = {
  3179. .dev_free = snd_cs46xx_dev_free,
  3180. };
  3181. *rchip = NULL;
  3182. /* enable PCI device */
  3183. if ((err = pci_enable_device(pci)) < 0)
  3184. return err;
  3185. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  3186. if (chip == NULL) {
  3187. pci_disable_device(pci);
  3188. return -ENOMEM;
  3189. }
  3190. spin_lock_init(&chip->reg_lock);
  3191. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  3192. mutex_init(&chip->spos_mutex);
  3193. #endif
  3194. chip->card = card;
  3195. chip->pci = pci;
  3196. chip->irq = -1;
  3197. chip->ba0_addr = pci_resource_start(pci, 0);
  3198. chip->ba1_addr = pci_resource_start(pci, 1);
  3199. if (chip->ba0_addr == 0 || chip->ba0_addr == (unsigned long)~0 ||
  3200. chip->ba1_addr == 0 || chip->ba1_addr == (unsigned long)~0) {
  3201. snd_printk(KERN_ERR "wrong address(es) - ba0 = 0x%lx, ba1 = 0x%lx\n",
  3202. chip->ba0_addr, chip->ba1_addr);
  3203. snd_cs46xx_free(chip);
  3204. return -ENOMEM;
  3205. }
  3206. region = &chip->region.name.ba0;
  3207. strcpy(region->name, "CS46xx_BA0");
  3208. region->base = chip->ba0_addr;
  3209. region->size = CS46XX_BA0_SIZE;
  3210. region = &chip->region.name.data0;
  3211. strcpy(region->name, "CS46xx_BA1_data0");
  3212. region->base = chip->ba1_addr + BA1_SP_DMEM0;
  3213. region->size = CS46XX_BA1_DATA0_SIZE;
  3214. region = &chip->region.name.data1;
  3215. strcpy(region->name, "CS46xx_BA1_data1");
  3216. region->base = chip->ba1_addr + BA1_SP_DMEM1;
  3217. region->size = CS46XX_BA1_DATA1_SIZE;
  3218. region = &chip->region.name.pmem;
  3219. strcpy(region->name, "CS46xx_BA1_pmem");
  3220. region->base = chip->ba1_addr + BA1_SP_PMEM;
  3221. region->size = CS46XX_BA1_PRG_SIZE;
  3222. region = &chip->region.name.reg;
  3223. strcpy(region->name, "CS46xx_BA1_reg");
  3224. region->base = chip->ba1_addr + BA1_SP_REG;
  3225. region->size = CS46XX_BA1_REG_SIZE;
  3226. /* set up amp and clkrun hack */
  3227. pci_read_config_word(pci, PCI_SUBSYSTEM_VENDOR_ID, &ss_vendor);
  3228. pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &ss_card);
  3229. for (cp = &cards[0]; cp->name; cp++) {
  3230. if (cp->vendor == ss_vendor && cp->id == ss_card) {
  3231. snd_printdd ("hack for %s enabled\n", cp->name);
  3232. chip->amplifier_ctrl = cp->amp;
  3233. chip->active_ctrl = cp->active;
  3234. chip->mixer_init = cp->mixer_init;
  3235. if (cp->init)
  3236. cp->init(chip);
  3237. break;
  3238. }
  3239. }
  3240. if (external_amp) {
  3241. snd_printk(KERN_INFO "Crystal EAPD support forced on.\n");
  3242. chip->amplifier_ctrl = amp_voyetra;
  3243. }
  3244. if (thinkpad) {
  3245. snd_printk(KERN_INFO "Activating CLKRUN hack for Thinkpad.\n");
  3246. chip->active_ctrl = clkrun_hack;
  3247. clkrun_init(chip);
  3248. }
  3249. if (chip->amplifier_ctrl == NULL)
  3250. chip->amplifier_ctrl = amp_none;
  3251. if (chip->active_ctrl == NULL)
  3252. chip->active_ctrl = amp_none;
  3253. chip->active_ctrl(chip, 1); /* enable CLKRUN */
  3254. pci_set_master(pci);
  3255. for (idx = 0; idx < 5; idx++) {
  3256. region = &chip->region.idx[idx];
  3257. if ((region->resource = request_mem_region(region->base, region->size,
  3258. region->name)) == NULL) {
  3259. snd_printk(KERN_ERR "unable to request memory region 0x%lx-0x%lx\n",
  3260. region->base, region->base + region->size - 1);
  3261. snd_cs46xx_free(chip);
  3262. return -EBUSY;
  3263. }
  3264. region->remap_addr = ioremap_nocache(region->base, region->size);
  3265. if (region->remap_addr == NULL) {
  3266. snd_printk(KERN_ERR "%s ioremap problem\n", region->name);
  3267. snd_cs46xx_free(chip);
  3268. return -ENOMEM;
  3269. }
  3270. }
  3271. if (request_irq(pci->irq, snd_cs46xx_interrupt, IRQF_SHARED,
  3272. "CS46XX", chip)) {
  3273. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  3274. snd_cs46xx_free(chip);
  3275. return -EBUSY;
  3276. }
  3277. chip->irq = pci->irq;
  3278. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  3279. chip->dsp_spos_instance = cs46xx_dsp_spos_create(chip);
  3280. if (chip->dsp_spos_instance == NULL) {
  3281. snd_cs46xx_free(chip);
  3282. return -ENOMEM;
  3283. }
  3284. #endif
  3285. err = snd_cs46xx_chip_init(chip);
  3286. if (err < 0) {
  3287. snd_cs46xx_free(chip);
  3288. return err;
  3289. }
  3290. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  3291. snd_cs46xx_free(chip);
  3292. return err;
  3293. }
  3294. snd_cs46xx_proc_init(card, chip);
  3295. chip->active_ctrl(chip, -1); /* disable CLKRUN */
  3296. snd_card_set_dev(card, &pci->dev);
  3297. *rchip = chip;
  3298. return 0;
  3299. }