azt3328.c 62 KB

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  1. /*
  2. * azt3328.c - driver for Aztech AZF3328 based soundcards (e.g. PCI168).
  3. * Copyright (C) 2002, 2005 by Andreas Mohr <andi AT lisas.de>
  4. *
  5. * Framework borrowed from Bart Hartgers's als4000.c.
  6. * Driver developed on PCI168 AP(W) version (PCI rev. 10, subsystem ID 1801),
  7. * found in a Fujitsu-Siemens PC ("Cordant", aluminum case).
  8. * Other versions are:
  9. * PCI168 A(W), sub ID 1800
  10. * PCI168 A/AP, sub ID 8000
  11. * Please give me feedback in case you try my driver with one of these!!
  12. *
  13. * GPL LICENSE
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  26. *
  27. * NOTES
  28. * Since Aztech does not provide any chipset documentation,
  29. * even on repeated request to various addresses,
  30. * and the answer that was finally given was negative
  31. * (and I was stupid enough to manage to get hold of a PCI168 soundcard
  32. * in the first place >:-P}),
  33. * I was forced to base this driver on reverse engineering
  34. * (3 weeks' worth of evenings filled with driver work).
  35. * (and no, I did NOT go the easy way: to pick up a SB PCI128 for 9 Euros)
  36. *
  37. * The AZF3328 chip (note: AZF3328, *not* AZT3328, that's just the driver name
  38. * for compatibility reasons) has the following features:
  39. *
  40. * - builtin AC97 conformant codec (SNR over 80dB)
  41. * Note that "conformant" != "compliant"!! this chip's mixer register layout
  42. * *differs* from the standard AC97 layout:
  43. * they chose to not implement the headphone register (which is not a
  44. * problem since it's merely optional), yet when doing this, they committed
  45. * the grave sin of letting other registers follow immediately instead of
  46. * keeping a headphone dummy register, thereby shifting the mixer register
  47. * addresses illegally. So far unfortunately it looks like the very flexible
  48. * ALSA AC97 support is still not enough to easily compensate for such a
  49. * grave layout violation despite all tweaks and quirks mechanisms it offers.
  50. * - builtin genuine OPL3
  51. * - full duplex 16bit playback/record at independent sampling rate
  52. * - MPU401 (+ legacy address support) FIXME: how to enable legacy addr??
  53. * - game port (legacy address support)
  54. * - built-in General DirectX timer having a 20 bits counter
  55. * with 1us resolution (see below!)
  56. * - I2S serial port for external DAC
  57. * - supports 33MHz PCI spec 2.1, PCI power management 1.0, compliant with ACPI
  58. * - supports hardware volume control
  59. * - single chip low cost solution (128 pin QFP)
  60. * - supports programmable Sub-vendor and Sub-system ID
  61. * required for Microsoft's logo compliance (FIXME: where?)
  62. * - PCI168 AP(W) card: power amplifier with 4 Watts/channel at 4 Ohms
  63. *
  64. * Note that this driver now is actually *better* than the Windows driver,
  65. * since it additionally supports the card's 1MHz DirectX timer - just try
  66. * the following snd-seq module parameters etc.:
  67. * - options snd-seq seq_default_timer_class=2 seq_default_timer_sclass=0
  68. * seq_default_timer_card=0 seq_client_load=1 seq_default_timer_device=0
  69. * seq_default_timer_subdevice=0 seq_default_timer_resolution=1000000
  70. * - "timidity -iAv -B2,8 -Os -EFreverb=0"
  71. * - "pmidi -p 128:0 jazz.mid"
  72. *
  73. * Certain PCI versions of this card are susceptible to DMA traffic underruns
  74. * in some systems (resulting in sound crackling/clicking/popping),
  75. * probably because they don't have a DMA FIFO buffer or so.
  76. * Overview (PCI ID/PCI subID/PCI rev.):
  77. * - no DMA crackling on SiS735: 0x50DC/0x1801/16
  78. * - unknown performance: 0x50DC/0x1801/10
  79. * (well, it's not bad on an Athlon 1800 with now very optimized IRQ handler)
  80. *
  81. * Crackling happens with VIA chipsets or, in my case, an SiS735, which is
  82. * supposed to be very fast and supposed to get rid of crackling much
  83. * better than a VIA, yet ironically I still get crackling, like many other
  84. * people with the same chipset.
  85. * Possible remedies:
  86. * - plug card into a different PCI slot, preferrably one that isn't shared
  87. * too much (this helps a lot, but not completely!)
  88. * - get rid of PCI VGA card, use AGP instead
  89. * - upgrade or downgrade BIOS
  90. * - fiddle with PCI latency settings (setpci -v -s BUSID latency_timer=XX)
  91. * Not too helpful.
  92. * - Disable ACPI/power management/"Auto Detect RAM/PCI Clk" in BIOS
  93. *
  94. * BUGS
  95. * - full-duplex might *still* be problematic, not fully tested recently
  96. *
  97. * TODO
  98. * - test MPU401 MIDI playback etc.
  99. * - add some power micro-management (disable various units of the card
  100. * as long as they're unused). However this requires I/O ports which I
  101. * haven't figured out yet and which thus might not even exist...
  102. * The standard suspend/resume functionality could probably make use of
  103. * some improvement, too...
  104. * - figure out what all unknown port bits are responsible for
  105. * - figure out some cleverly evil scheme to possibly make ALSA AC97 code
  106. * fully accept our quite incompatible ""AC97"" mixer and thus save some
  107. * code (but I'm not too optimistic that doing this is possible at all)
  108. */
  109. #include <sound/driver.h>
  110. #include <asm/io.h>
  111. #include <linux/init.h>
  112. #include <linux/pci.h>
  113. #include <linux/delay.h>
  114. #include <linux/slab.h>
  115. #include <linux/gameport.h>
  116. #include <linux/moduleparam.h>
  117. #include <linux/dma-mapping.h>
  118. #include <sound/core.h>
  119. #include <sound/control.h>
  120. #include <sound/pcm.h>
  121. #include <sound/rawmidi.h>
  122. #include <sound/mpu401.h>
  123. #include <sound/opl3.h>
  124. #include <sound/initval.h>
  125. #include "azt3328.h"
  126. MODULE_AUTHOR("Andreas Mohr <andi AT lisas.de>");
  127. MODULE_DESCRIPTION("Aztech AZF3328 (PCI168)");
  128. MODULE_LICENSE("GPL");
  129. MODULE_SUPPORTED_DEVICE("{{Aztech,AZF3328}}");
  130. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  131. #define SUPPORT_JOYSTICK 1
  132. #endif
  133. #define DEBUG_MISC 0
  134. #define DEBUG_CALLS 0
  135. #define DEBUG_MIXER 0
  136. #define DEBUG_PLAY_REC 0
  137. #define DEBUG_IO 0
  138. #define DEBUG_TIMER 0
  139. #define MIXER_TESTING 0
  140. #if DEBUG_MISC
  141. #define snd_azf3328_dbgmisc(format, args...) printk(KERN_ERR format, ##args)
  142. #else
  143. #define snd_azf3328_dbgmisc(format, args...)
  144. #endif
  145. #if DEBUG_CALLS
  146. #define snd_azf3328_dbgcalls(format, args...) printk(format, ##args)
  147. #define snd_azf3328_dbgcallenter() printk(KERN_ERR "--> %s\n", __FUNCTION__)
  148. #define snd_azf3328_dbgcallleave() printk(KERN_ERR "<-- %s\n", __FUNCTION__)
  149. #else
  150. #define snd_azf3328_dbgcalls(format, args...)
  151. #define snd_azf3328_dbgcallenter()
  152. #define snd_azf3328_dbgcallleave()
  153. #endif
  154. #if DEBUG_MIXER
  155. #define snd_azf3328_dbgmixer(format, args...) printk(format, ##args)
  156. #else
  157. #define snd_azf3328_dbgmixer(format, args...)
  158. #endif
  159. #if DEBUG_PLAY_REC
  160. #define snd_azf3328_dbgplay(format, args...) printk(KERN_ERR format, ##args)
  161. #else
  162. #define snd_azf3328_dbgplay(format, args...)
  163. #endif
  164. #if DEBUG_MISC
  165. #define snd_azf3328_dbgtimer(format, args...) printk(KERN_ERR format, ##args)
  166. #else
  167. #define snd_azf3328_dbgtimer(format, args...)
  168. #endif
  169. static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
  170. module_param_array(index, int, NULL, 0444);
  171. MODULE_PARM_DESC(index, "Index value for AZF3328 soundcard.");
  172. static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
  173. module_param_array(id, charp, NULL, 0444);
  174. MODULE_PARM_DESC(id, "ID string for AZF3328 soundcard.");
  175. static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
  176. module_param_array(enable, bool, NULL, 0444);
  177. MODULE_PARM_DESC(enable, "Enable AZF3328 soundcard.");
  178. #ifdef SUPPORT_JOYSTICK
  179. static int joystick[SNDRV_CARDS];
  180. module_param_array(joystick, bool, NULL, 0444);
  181. MODULE_PARM_DESC(joystick, "Enable joystick for AZF3328 soundcard.");
  182. #endif
  183. static int seqtimer_scaling = 128;
  184. module_param(seqtimer_scaling, int, 0444);
  185. MODULE_PARM_DESC(seqtimer_scaling, "Set 1024000Hz sequencer timer scale factor (lockup danger!). Default 128.");
  186. struct snd_azf3328 {
  187. /* often-used fields towards beginning, then grouped */
  188. unsigned long codec_port;
  189. unsigned long io2_port;
  190. unsigned long mpu_port;
  191. unsigned long synth_port;
  192. unsigned long mixer_port;
  193. spinlock_t reg_lock;
  194. struct snd_timer *timer;
  195. struct snd_pcm *pcm;
  196. struct snd_pcm_substream *playback_substream;
  197. struct snd_pcm_substream *capture_substream;
  198. unsigned int is_playing;
  199. unsigned int is_recording;
  200. struct snd_card *card;
  201. struct snd_rawmidi *rmidi;
  202. #ifdef SUPPORT_JOYSTICK
  203. struct gameport *gameport;
  204. #endif
  205. struct pci_dev *pci;
  206. int irq;
  207. #ifdef CONFIG_PM
  208. /* register value containers for power management
  209. * Note: not always full I/O range preserved (just like Win driver!) */
  210. u16 saved_regs_codec [AZF_IO_SIZE_CODEC_PM / 2];
  211. u16 saved_regs_io2 [AZF_IO_SIZE_IO2_PM / 2];
  212. u16 saved_regs_mpu [AZF_IO_SIZE_MPU_PM / 2];
  213. u16 saved_regs_synth[AZF_IO_SIZE_SYNTH_PM / 2];
  214. u16 saved_regs_mixer[AZF_IO_SIZE_MIXER_PM / 2];
  215. #endif
  216. };
  217. static const struct pci_device_id snd_azf3328_ids[] = {
  218. { 0x122D, 0x50DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* PCI168/3328 */
  219. { 0x122D, 0x80DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* 3328 */
  220. { 0, }
  221. };
  222. MODULE_DEVICE_TABLE(pci, snd_azf3328_ids);
  223. static inline void
  224. snd_azf3328_codec_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  225. {
  226. outb(value, chip->codec_port + reg);
  227. }
  228. static inline u8
  229. snd_azf3328_codec_inb(const struct snd_azf3328 *chip, int reg)
  230. {
  231. return inb(chip->codec_port + reg);
  232. }
  233. static inline void
  234. snd_azf3328_codec_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  235. {
  236. outw(value, chip->codec_port + reg);
  237. }
  238. static inline u16
  239. snd_azf3328_codec_inw(const struct snd_azf3328 *chip, int reg)
  240. {
  241. return inw(chip->codec_port + reg);
  242. }
  243. static inline void
  244. snd_azf3328_codec_outl(const struct snd_azf3328 *chip, int reg, u32 value)
  245. {
  246. outl(value, chip->codec_port + reg);
  247. }
  248. static inline void
  249. snd_azf3328_io2_outb(const struct snd_azf3328 *chip, int reg, u8 value)
  250. {
  251. outb(value, chip->io2_port + reg);
  252. }
  253. static inline u8
  254. snd_azf3328_io2_inb(const struct snd_azf3328 *chip, int reg)
  255. {
  256. return inb(chip->io2_port + reg);
  257. }
  258. static inline void
  259. snd_azf3328_mixer_outw(const struct snd_azf3328 *chip, int reg, u16 value)
  260. {
  261. outw(value, chip->mixer_port + reg);
  262. }
  263. static inline u16
  264. snd_azf3328_mixer_inw(const struct snd_azf3328 *chip, int reg)
  265. {
  266. return inw(chip->mixer_port + reg);
  267. }
  268. static void
  269. snd_azf3328_mixer_set_mute(const struct snd_azf3328 *chip, int reg, int do_mute)
  270. {
  271. unsigned long portbase = chip->mixer_port + reg + 1;
  272. unsigned char oldval;
  273. /* the mute bit is on the *second* (i.e. right) register of a
  274. * left/right channel setting */
  275. oldval = inb(portbase);
  276. if (do_mute)
  277. oldval |= 0x80;
  278. else
  279. oldval &= ~0x80;
  280. outb(oldval, portbase);
  281. }
  282. static void
  283. snd_azf3328_mixer_write_volume_gradually(const struct snd_azf3328 *chip, int reg, unsigned char dst_vol_left, unsigned char dst_vol_right, int chan_sel, int delay)
  284. {
  285. unsigned long portbase = chip->mixer_port + reg;
  286. unsigned char curr_vol_left = 0, curr_vol_right = 0;
  287. int left_done = 0, right_done = 0;
  288. snd_azf3328_dbgcallenter();
  289. if (chan_sel & SET_CHAN_LEFT)
  290. curr_vol_left = inb(portbase + 1);
  291. else
  292. left_done = 1;
  293. if (chan_sel & SET_CHAN_RIGHT)
  294. curr_vol_right = inb(portbase + 0);
  295. else
  296. right_done = 1;
  297. /* take care of muting flag (0x80) contained in left channel */
  298. if (curr_vol_left & 0x80)
  299. dst_vol_left |= 0x80;
  300. else
  301. dst_vol_left &= ~0x80;
  302. do {
  303. if (!left_done) {
  304. if (curr_vol_left > dst_vol_left)
  305. curr_vol_left--;
  306. else
  307. if (curr_vol_left < dst_vol_left)
  308. curr_vol_left++;
  309. else
  310. left_done = 1;
  311. outb(curr_vol_left, portbase + 1);
  312. }
  313. if (!right_done) {
  314. if (curr_vol_right > dst_vol_right)
  315. curr_vol_right--;
  316. else
  317. if (curr_vol_right < dst_vol_right)
  318. curr_vol_right++;
  319. else
  320. right_done = 1;
  321. /* during volume change, the right channel is crackling
  322. * somewhat more than the left channel, unfortunately.
  323. * This seems to be a hardware issue. */
  324. outb(curr_vol_right, portbase + 0);
  325. }
  326. if (delay)
  327. mdelay(delay);
  328. } while ((!left_done) || (!right_done));
  329. snd_azf3328_dbgcallleave();
  330. }
  331. /*
  332. * general mixer element
  333. */
  334. struct azf3328_mixer_reg {
  335. unsigned int reg;
  336. unsigned int lchan_shift, rchan_shift;
  337. unsigned int mask;
  338. unsigned int invert: 1;
  339. unsigned int stereo: 1;
  340. unsigned int enum_c: 4;
  341. };
  342. #define COMPOSE_MIXER_REG(reg,lchan_shift,rchan_shift,mask,invert,stereo,enum_c) \
  343. ((reg) | (lchan_shift << 8) | (rchan_shift << 12) | \
  344. (mask << 16) | \
  345. (invert << 24) | \
  346. (stereo << 25) | \
  347. (enum_c << 26))
  348. static void snd_azf3328_mixer_reg_decode(struct azf3328_mixer_reg *r, unsigned long val)
  349. {
  350. r->reg = val & 0xff;
  351. r->lchan_shift = (val >> 8) & 0x0f;
  352. r->rchan_shift = (val >> 12) & 0x0f;
  353. r->mask = (val >> 16) & 0xff;
  354. r->invert = (val >> 24) & 1;
  355. r->stereo = (val >> 25) & 1;
  356. r->enum_c = (val >> 26) & 0x0f;
  357. }
  358. /*
  359. * mixer switches/volumes
  360. */
  361. #define AZF3328_MIXER_SWITCH(xname, reg, shift, invert) \
  362. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  363. .info = snd_azf3328_info_mixer, \
  364. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  365. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0x1, invert, 0, 0), \
  366. }
  367. #define AZF3328_MIXER_VOL_STEREO(xname, reg, mask, invert) \
  368. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  369. .info = snd_azf3328_info_mixer, \
  370. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  371. .private_value = COMPOSE_MIXER_REG(reg, 8, 0, mask, invert, 1, 0), \
  372. }
  373. #define AZF3328_MIXER_VOL_MONO(xname, reg, mask, is_right_chan) \
  374. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  375. .info = snd_azf3328_info_mixer, \
  376. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  377. .private_value = COMPOSE_MIXER_REG(reg, is_right_chan ? 0 : 8, 0, mask, 1, 0, 0), \
  378. }
  379. #define AZF3328_MIXER_VOL_SPECIAL(xname, reg, mask, shift, invert) \
  380. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  381. .info = snd_azf3328_info_mixer, \
  382. .get = snd_azf3328_get_mixer, .put = snd_azf3328_put_mixer, \
  383. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, mask, invert, 0, 0), \
  384. }
  385. #define AZF3328_MIXER_ENUM(xname, reg, enum_c, shift) \
  386. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  387. .info = snd_azf3328_info_mixer_enum, \
  388. .get = snd_azf3328_get_mixer_enum, .put = snd_azf3328_put_mixer_enum, \
  389. .private_value = COMPOSE_MIXER_REG(reg, shift, 0, 0, 0, 0, enum_c), \
  390. }
  391. static int
  392. snd_azf3328_info_mixer(struct snd_kcontrol *kcontrol,
  393. struct snd_ctl_elem_info *uinfo)
  394. {
  395. struct azf3328_mixer_reg reg;
  396. snd_azf3328_dbgcallenter();
  397. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  398. uinfo->type = reg.mask == 1 ?
  399. SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
  400. uinfo->count = reg.stereo + 1;
  401. uinfo->value.integer.min = 0;
  402. uinfo->value.integer.max = reg.mask;
  403. snd_azf3328_dbgcallleave();
  404. return 0;
  405. }
  406. static int
  407. snd_azf3328_get_mixer(struct snd_kcontrol *kcontrol,
  408. struct snd_ctl_elem_value *ucontrol)
  409. {
  410. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  411. struct azf3328_mixer_reg reg;
  412. unsigned int oreg, val;
  413. snd_azf3328_dbgcallenter();
  414. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  415. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  416. val = (oreg >> reg.lchan_shift) & reg.mask;
  417. if (reg.invert)
  418. val = reg.mask - val;
  419. ucontrol->value.integer.value[0] = val;
  420. if (reg.stereo) {
  421. val = (oreg >> reg.rchan_shift) & reg.mask;
  422. if (reg.invert)
  423. val = reg.mask - val;
  424. ucontrol->value.integer.value[1] = val;
  425. }
  426. snd_azf3328_dbgmixer("get: %02x is %04x -> vol %02lx|%02lx "
  427. "(shift %02d|%02d, mask %02x, inv. %d, stereo %d)\n",
  428. reg.reg, oreg,
  429. ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  430. reg.lchan_shift, reg.rchan_shift, reg.mask, reg.invert, reg.stereo);
  431. snd_azf3328_dbgcallleave();
  432. return 0;
  433. }
  434. static int
  435. snd_azf3328_put_mixer(struct snd_kcontrol *kcontrol,
  436. struct snd_ctl_elem_value *ucontrol)
  437. {
  438. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  439. struct azf3328_mixer_reg reg;
  440. unsigned int oreg, nreg, val;
  441. snd_azf3328_dbgcallenter();
  442. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  443. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  444. val = ucontrol->value.integer.value[0] & reg.mask;
  445. if (reg.invert)
  446. val = reg.mask - val;
  447. nreg = oreg & ~(reg.mask << reg.lchan_shift);
  448. nreg |= (val << reg.lchan_shift);
  449. if (reg.stereo) {
  450. val = ucontrol->value.integer.value[1] & reg.mask;
  451. if (reg.invert)
  452. val = reg.mask - val;
  453. nreg &= ~(reg.mask << reg.rchan_shift);
  454. nreg |= (val << reg.rchan_shift);
  455. }
  456. if (reg.mask >= 0x07) /* it's a volume control, so better take care */
  457. snd_azf3328_mixer_write_volume_gradually(
  458. chip, reg.reg, nreg >> 8, nreg & 0xff,
  459. /* just set both channels, doesn't matter */
  460. SET_CHAN_LEFT|SET_CHAN_RIGHT,
  461. 0);
  462. else
  463. snd_azf3328_mixer_outw(chip, reg.reg, nreg);
  464. snd_azf3328_dbgmixer("put: %02x to %02lx|%02lx, "
  465. "oreg %04x; shift %02d|%02d -> nreg %04x; after: %04x\n",
  466. reg.reg, ucontrol->value.integer.value[0], ucontrol->value.integer.value[1],
  467. oreg, reg.lchan_shift, reg.rchan_shift,
  468. nreg, snd_azf3328_mixer_inw(chip, reg.reg));
  469. snd_azf3328_dbgcallleave();
  470. return (nreg != oreg);
  471. }
  472. static int
  473. snd_azf3328_info_mixer_enum(struct snd_kcontrol *kcontrol,
  474. struct snd_ctl_elem_info *uinfo)
  475. {
  476. static const char * const texts1[] = {
  477. "Mic1", "Mic2"
  478. };
  479. static const char * const texts2[] = {
  480. "Mix", "Mic"
  481. };
  482. static const char * const texts3[] = {
  483. "Mic", "CD", "Video", "Aux",
  484. "Line", "Mix", "Mix Mono", "Phone"
  485. };
  486. static const char * const texts4[] = {
  487. "pre 3D", "post 3D"
  488. };
  489. struct azf3328_mixer_reg reg;
  490. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  491. uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
  492. uinfo->count = (reg.reg == IDX_MIXER_REC_SELECT) ? 2 : 1;
  493. uinfo->value.enumerated.items = reg.enum_c;
  494. if (uinfo->value.enumerated.item > reg.enum_c - 1U)
  495. uinfo->value.enumerated.item = reg.enum_c - 1U;
  496. if (reg.reg == IDX_MIXER_ADVCTL2) {
  497. switch(reg.lchan_shift) {
  498. case 8: /* modem out sel */
  499. strcpy(uinfo->value.enumerated.name, texts1[uinfo->value.enumerated.item]);
  500. break;
  501. case 9: /* mono sel source */
  502. strcpy(uinfo->value.enumerated.name, texts2[uinfo->value.enumerated.item]);
  503. break;
  504. case 15: /* PCM Out Path */
  505. strcpy(uinfo->value.enumerated.name, texts4[uinfo->value.enumerated.item]);
  506. break;
  507. }
  508. } else
  509. strcpy(uinfo->value.enumerated.name, texts3[uinfo->value.enumerated.item]
  510. );
  511. return 0;
  512. }
  513. static int
  514. snd_azf3328_get_mixer_enum(struct snd_kcontrol *kcontrol,
  515. struct snd_ctl_elem_value *ucontrol)
  516. {
  517. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  518. struct azf3328_mixer_reg reg;
  519. unsigned short val;
  520. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  521. val = snd_azf3328_mixer_inw(chip, reg.reg);
  522. if (reg.reg == IDX_MIXER_REC_SELECT) {
  523. ucontrol->value.enumerated.item[0] = (val >> 8) & (reg.enum_c - 1);
  524. ucontrol->value.enumerated.item[1] = (val >> 0) & (reg.enum_c - 1);
  525. } else
  526. ucontrol->value.enumerated.item[0] = (val >> reg.lchan_shift) & (reg.enum_c - 1);
  527. snd_azf3328_dbgmixer("get_enum: %02x is %04x -> %d|%d (shift %02d, enum_c %d)\n",
  528. reg.reg, val, ucontrol->value.enumerated.item[0], ucontrol->value.enumerated.item[1],
  529. reg.lchan_shift, reg.enum_c);
  530. return 0;
  531. }
  532. static int
  533. snd_azf3328_put_mixer_enum(struct snd_kcontrol *kcontrol,
  534. struct snd_ctl_elem_value *ucontrol)
  535. {
  536. struct snd_azf3328 *chip = snd_kcontrol_chip(kcontrol);
  537. struct azf3328_mixer_reg reg;
  538. unsigned int oreg, nreg, val;
  539. snd_azf3328_mixer_reg_decode(&reg, kcontrol->private_value);
  540. oreg = snd_azf3328_mixer_inw(chip, reg.reg);
  541. val = oreg;
  542. if (reg.reg == IDX_MIXER_REC_SELECT) {
  543. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U ||
  544. ucontrol->value.enumerated.item[1] > reg.enum_c - 1U)
  545. return -EINVAL;
  546. val = (ucontrol->value.enumerated.item[0] << 8) |
  547. (ucontrol->value.enumerated.item[1] << 0);
  548. } else {
  549. if (ucontrol->value.enumerated.item[0] > reg.enum_c - 1U)
  550. return -EINVAL;
  551. val &= ~((reg.enum_c - 1) << reg.lchan_shift);
  552. val |= (ucontrol->value.enumerated.item[0] << reg.lchan_shift);
  553. }
  554. snd_azf3328_mixer_outw(chip, reg.reg, val);
  555. nreg = val;
  556. snd_azf3328_dbgmixer("put_enum: %02x to %04x, oreg %04x\n", reg.reg, val, oreg);
  557. return (nreg != oreg);
  558. }
  559. static const struct snd_kcontrol_new snd_azf3328_mixer_controls[] __devinitdata = {
  560. AZF3328_MIXER_SWITCH("Master Playback Switch", IDX_MIXER_PLAY_MASTER, 15, 1),
  561. AZF3328_MIXER_VOL_STEREO("Master Playback Volume", IDX_MIXER_PLAY_MASTER, 0x1f, 1),
  562. AZF3328_MIXER_SWITCH("Wave Playback Switch", IDX_MIXER_WAVEOUT, 15, 1),
  563. AZF3328_MIXER_VOL_STEREO("Wave Playback Volume", IDX_MIXER_WAVEOUT, 0x1f, 1),
  564. AZF3328_MIXER_SWITCH("Wave 3D Bypass Playback Switch", IDX_MIXER_ADVCTL2, 7, 1),
  565. AZF3328_MIXER_SWITCH("FM Playback Switch", IDX_MIXER_FMSYNTH, 15, 1),
  566. AZF3328_MIXER_VOL_STEREO("FM Playback Volume", IDX_MIXER_FMSYNTH, 0x1f, 1),
  567. AZF3328_MIXER_SWITCH("CD Playback Switch", IDX_MIXER_CDAUDIO, 15, 1),
  568. AZF3328_MIXER_VOL_STEREO("CD Playback Volume", IDX_MIXER_CDAUDIO, 0x1f, 1),
  569. AZF3328_MIXER_SWITCH("Capture Switch", IDX_MIXER_REC_VOLUME, 15, 1),
  570. AZF3328_MIXER_VOL_STEREO("Capture Volume", IDX_MIXER_REC_VOLUME, 0x0f, 0),
  571. AZF3328_MIXER_ENUM("Capture Source", IDX_MIXER_REC_SELECT, 8, 0),
  572. AZF3328_MIXER_SWITCH("Mic Playback Switch", IDX_MIXER_MIC, 15, 1),
  573. AZF3328_MIXER_VOL_MONO("Mic Playback Volume", IDX_MIXER_MIC, 0x1f, 1),
  574. AZF3328_MIXER_SWITCH("Mic Boost (+20dB)", IDX_MIXER_MIC, 6, 0),
  575. AZF3328_MIXER_SWITCH("Line Playback Switch", IDX_MIXER_LINEIN, 15, 1),
  576. AZF3328_MIXER_VOL_STEREO("Line Playback Volume", IDX_MIXER_LINEIN, 0x1f, 1),
  577. AZF3328_MIXER_SWITCH("PC Speaker Playback Switch", IDX_MIXER_PCBEEP, 15, 1),
  578. AZF3328_MIXER_VOL_SPECIAL("PC Speaker Playback Volume", IDX_MIXER_PCBEEP, 0x0f, 1, 1),
  579. AZF3328_MIXER_SWITCH("Video Playback Switch", IDX_MIXER_VIDEO, 15, 1),
  580. AZF3328_MIXER_VOL_STEREO("Video Playback Volume", IDX_MIXER_VIDEO, 0x1f, 1),
  581. AZF3328_MIXER_SWITCH("Aux Playback Switch", IDX_MIXER_AUX, 15, 1),
  582. AZF3328_MIXER_VOL_STEREO("Aux Playback Volume", IDX_MIXER_AUX, 0x1f, 1),
  583. AZF3328_MIXER_SWITCH("Modem Playback Switch", IDX_MIXER_MODEMOUT, 15, 1),
  584. AZF3328_MIXER_VOL_MONO("Modem Playback Volume", IDX_MIXER_MODEMOUT, 0x1f, 1),
  585. AZF3328_MIXER_SWITCH("Modem Capture Switch", IDX_MIXER_MODEMIN, 15, 1),
  586. AZF3328_MIXER_VOL_MONO("Modem Capture Volume", IDX_MIXER_MODEMIN, 0x1f, 1),
  587. AZF3328_MIXER_ENUM("Mic Select", IDX_MIXER_ADVCTL2, 2, 8),
  588. AZF3328_MIXER_ENUM("Mono Output Select", IDX_MIXER_ADVCTL2, 2, 9),
  589. AZF3328_MIXER_ENUM("PCM", IDX_MIXER_ADVCTL2, 2, 15), /* PCM Out Path, place in front since it controls *both* 3D and Bass/Treble! */
  590. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Treble", IDX_MIXER_BASSTREBLE, 0x07, 1, 0),
  591. AZF3328_MIXER_VOL_SPECIAL("Tone Control - Bass", IDX_MIXER_BASSTREBLE, 0x07, 9, 0),
  592. AZF3328_MIXER_SWITCH("3D Control - Switch", IDX_MIXER_ADVCTL2, 13, 0),
  593. AZF3328_MIXER_VOL_SPECIAL("3D Control - Width", IDX_MIXER_ADVCTL1, 0x07, 1, 0), /* "3D Width" */
  594. AZF3328_MIXER_VOL_SPECIAL("3D Control - Depth", IDX_MIXER_ADVCTL1, 0x03, 8, 0), /* "Hifi 3D" */
  595. #if MIXER_TESTING
  596. AZF3328_MIXER_SWITCH("0", IDX_MIXER_ADVCTL2, 0, 0),
  597. AZF3328_MIXER_SWITCH("1", IDX_MIXER_ADVCTL2, 1, 0),
  598. AZF3328_MIXER_SWITCH("2", IDX_MIXER_ADVCTL2, 2, 0),
  599. AZF3328_MIXER_SWITCH("3", IDX_MIXER_ADVCTL2, 3, 0),
  600. AZF3328_MIXER_SWITCH("4", IDX_MIXER_ADVCTL2, 4, 0),
  601. AZF3328_MIXER_SWITCH("5", IDX_MIXER_ADVCTL2, 5, 0),
  602. AZF3328_MIXER_SWITCH("6", IDX_MIXER_ADVCTL2, 6, 0),
  603. AZF3328_MIXER_SWITCH("7", IDX_MIXER_ADVCTL2, 7, 0),
  604. AZF3328_MIXER_SWITCH("8", IDX_MIXER_ADVCTL2, 8, 0),
  605. AZF3328_MIXER_SWITCH("9", IDX_MIXER_ADVCTL2, 9, 0),
  606. AZF3328_MIXER_SWITCH("10", IDX_MIXER_ADVCTL2, 10, 0),
  607. AZF3328_MIXER_SWITCH("11", IDX_MIXER_ADVCTL2, 11, 0),
  608. AZF3328_MIXER_SWITCH("12", IDX_MIXER_ADVCTL2, 12, 0),
  609. AZF3328_MIXER_SWITCH("13", IDX_MIXER_ADVCTL2, 13, 0),
  610. AZF3328_MIXER_SWITCH("14", IDX_MIXER_ADVCTL2, 14, 0),
  611. AZF3328_MIXER_SWITCH("15", IDX_MIXER_ADVCTL2, 15, 0),
  612. #endif
  613. };
  614. static const u16 __devinitdata snd_azf3328_init_values[][2] = {
  615. { IDX_MIXER_PLAY_MASTER, MIXER_MUTE_MASK|0x1f1f },
  616. { IDX_MIXER_MODEMOUT, MIXER_MUTE_MASK|0x1f1f },
  617. { IDX_MIXER_BASSTREBLE, 0x0000 },
  618. { IDX_MIXER_PCBEEP, MIXER_MUTE_MASK|0x1f1f },
  619. { IDX_MIXER_MODEMIN, MIXER_MUTE_MASK|0x1f1f },
  620. { IDX_MIXER_MIC, MIXER_MUTE_MASK|0x001f },
  621. { IDX_MIXER_LINEIN, MIXER_MUTE_MASK|0x1f1f },
  622. { IDX_MIXER_CDAUDIO, MIXER_MUTE_MASK|0x1f1f },
  623. { IDX_MIXER_VIDEO, MIXER_MUTE_MASK|0x1f1f },
  624. { IDX_MIXER_AUX, MIXER_MUTE_MASK|0x1f1f },
  625. { IDX_MIXER_WAVEOUT, MIXER_MUTE_MASK|0x1f1f },
  626. { IDX_MIXER_FMSYNTH, MIXER_MUTE_MASK|0x1f1f },
  627. { IDX_MIXER_REC_VOLUME, MIXER_MUTE_MASK|0x0707 },
  628. };
  629. static int __devinit
  630. snd_azf3328_mixer_new(struct snd_azf3328 *chip)
  631. {
  632. struct snd_card *card;
  633. const struct snd_kcontrol_new *sw;
  634. unsigned int idx;
  635. int err;
  636. snd_azf3328_dbgcallenter();
  637. snd_assert(chip != NULL && chip->card != NULL, return -EINVAL);
  638. card = chip->card;
  639. /* mixer reset */
  640. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  641. /* mute and zero volume channels */
  642. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_init_values); idx++) {
  643. snd_azf3328_mixer_outw(chip,
  644. snd_azf3328_init_values[idx][0],
  645. snd_azf3328_init_values[idx][1]);
  646. }
  647. /* add mixer controls */
  648. sw = snd_azf3328_mixer_controls;
  649. for (idx = 0; idx < ARRAY_SIZE(snd_azf3328_mixer_controls); idx++, sw++) {
  650. if ((err = snd_ctl_add(chip->card, snd_ctl_new1(sw, chip))) < 0)
  651. return err;
  652. }
  653. snd_component_add(card, "AZF3328 mixer");
  654. strcpy(card->mixername, "AZF3328 mixer");
  655. snd_azf3328_dbgcallleave();
  656. return 0;
  657. }
  658. static int
  659. snd_azf3328_hw_params(struct snd_pcm_substream *substream,
  660. struct snd_pcm_hw_params *hw_params)
  661. {
  662. int res;
  663. snd_azf3328_dbgcallenter();
  664. res = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
  665. snd_azf3328_dbgcallleave();
  666. return res;
  667. }
  668. static int
  669. snd_azf3328_hw_free(struct snd_pcm_substream *substream)
  670. {
  671. snd_azf3328_dbgcallenter();
  672. snd_pcm_lib_free_pages(substream);
  673. snd_azf3328_dbgcallleave();
  674. return 0;
  675. }
  676. static void
  677. snd_azf3328_setfmt(struct snd_azf3328 *chip,
  678. unsigned int reg,
  679. unsigned int bitrate,
  680. unsigned int format_width,
  681. unsigned int channels
  682. )
  683. {
  684. u16 val = 0xff00;
  685. unsigned long flags;
  686. snd_azf3328_dbgcallenter();
  687. switch (bitrate) {
  688. case 4000: val |= SOUNDFORMAT_FREQ_SUSPECTED_4000; break;
  689. case 4800: val |= SOUNDFORMAT_FREQ_SUSPECTED_4800; break;
  690. case 5512: val |= SOUNDFORMAT_FREQ_5510; break; /* the AZF3328 names it "5510" for some strange reason */
  691. case 6620: val |= SOUNDFORMAT_FREQ_6620; break;
  692. case 8000: val |= SOUNDFORMAT_FREQ_8000; break;
  693. case 9600: val |= SOUNDFORMAT_FREQ_9600; break;
  694. case 11025: val |= SOUNDFORMAT_FREQ_11025; break;
  695. case 13240: val |= SOUNDFORMAT_FREQ_SUSPECTED_13240; break;
  696. case 16000: val |= SOUNDFORMAT_FREQ_16000; break;
  697. case 22050: val |= SOUNDFORMAT_FREQ_22050; break;
  698. case 32000: val |= SOUNDFORMAT_FREQ_32000; break;
  699. case 44100: val |= SOUNDFORMAT_FREQ_44100; break;
  700. case 48000: val |= SOUNDFORMAT_FREQ_48000; break;
  701. case 66200: val |= SOUNDFORMAT_FREQ_SUSPECTED_66200; break;
  702. default:
  703. snd_printk(KERN_WARNING "unknown bitrate %d, assuming 44.1kHz!\n", bitrate);
  704. val |= SOUNDFORMAT_FREQ_44100;
  705. break;
  706. }
  707. /* val = 0xff07; 3m27.993s (65301Hz; -> 64000Hz???) hmm, 66120, 65967, 66123 */
  708. /* val = 0xff09; 17m15.098s (13123,478Hz; -> 12000Hz???) hmm, 13237.2Hz? */
  709. /* val = 0xff0a; 47m30.599s (4764,891Hz; -> 4800Hz???) yup, 4803Hz */
  710. /* val = 0xff0c; 57m0.510s (4010,263Hz; -> 4000Hz???) yup, 4003Hz */
  711. /* val = 0xff05; 5m11.556s (... -> 44100Hz) */
  712. /* val = 0xff03; 10m21.529s (21872,463Hz; -> 22050Hz???) */
  713. /* val = 0xff0f; 20m41.883s (10937,993Hz; -> 11025Hz???) */
  714. /* val = 0xff0d; 41m23.135s (5523,600Hz; -> 5512Hz???) */
  715. /* val = 0xff0e; 28m30.777s (8017Hz; -> 8000Hz???) */
  716. if (channels == 2)
  717. val |= SOUNDFORMAT_FLAG_2CHANNELS;
  718. if (format_width == 16)
  719. val |= SOUNDFORMAT_FLAG_16BIT;
  720. spin_lock_irqsave(&chip->reg_lock, flags);
  721. /* set bitrate/format */
  722. snd_azf3328_codec_outw(chip, reg, val);
  723. /* changing the bitrate/format settings switches off the
  724. * audio output with an annoying click in case of 8/16bit format change
  725. * (maybe shutting down DAC/ADC?), thus immediately
  726. * do some tweaking to reenable it and get rid of the clicking
  727. * (FIXME: yes, it works, but what exactly am I doing here?? :)
  728. * FIXME: does this have some side effects for full-duplex
  729. * or other dramatic side effects? */
  730. if (reg == IDX_IO_PLAY_SOUNDFORMAT) /* only do it for playback */
  731. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  732. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) |
  733. DMA_PLAY_SOMETHING1 |
  734. DMA_PLAY_SOMETHING2 |
  735. SOMETHING_ALMOST_ALWAYS_SET |
  736. DMA_EPILOGUE_SOMETHING |
  737. DMA_SOMETHING_ELSE
  738. );
  739. spin_unlock_irqrestore(&chip->reg_lock, flags);
  740. snd_azf3328_dbgcallleave();
  741. }
  742. static void
  743. snd_azf3328_setdmaa(struct snd_azf3328 *chip,
  744. long unsigned int addr,
  745. unsigned int count,
  746. unsigned int size,
  747. int do_recording)
  748. {
  749. unsigned long flags, portbase;
  750. unsigned int is_running;
  751. snd_azf3328_dbgcallenter();
  752. if (do_recording) {
  753. /* access capture registers, i.e. skip playback reg section */
  754. portbase = chip->codec_port + 0x20;
  755. is_running = chip->is_recording;
  756. } else {
  757. /* access the playback register section */
  758. portbase = chip->codec_port + 0x00;
  759. is_running = chip->is_playing;
  760. }
  761. /* AZF3328 uses a two buffer pointer DMA playback approach */
  762. if (!is_running) {
  763. unsigned long addr_area2;
  764. unsigned long count_areas, count_tmp; /* width 32bit -- overflow!! */
  765. count_areas = size/2;
  766. addr_area2 = addr+count_areas;
  767. count_areas--; /* max. index */
  768. snd_azf3328_dbgplay("set DMA: buf1 %08lx[%lu], buf2 %08lx[%lu]\n", addr, count_areas, addr_area2, count_areas);
  769. /* build combined I/O buffer length word */
  770. count_tmp = count_areas;
  771. count_areas |= (count_tmp << 16);
  772. spin_lock_irqsave(&chip->reg_lock, flags);
  773. outl(addr, portbase + IDX_IO_PLAY_DMA_START_1);
  774. outl(addr_area2, portbase + IDX_IO_PLAY_DMA_START_2);
  775. outl(count_areas, portbase + IDX_IO_PLAY_DMA_LEN_1);
  776. spin_unlock_irqrestore(&chip->reg_lock, flags);
  777. }
  778. snd_azf3328_dbgcallleave();
  779. }
  780. static int
  781. snd_azf3328_playback_prepare(struct snd_pcm_substream *substream)
  782. {
  783. #if 0
  784. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  785. struct snd_pcm_runtime *runtime = substream->runtime;
  786. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  787. unsigned int count = snd_pcm_lib_period_bytes(substream);
  788. #endif
  789. snd_azf3328_dbgcallenter();
  790. #if 0
  791. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  792. runtime->rate,
  793. snd_pcm_format_width(runtime->format),
  794. runtime->channels);
  795. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 0);
  796. #endif
  797. snd_azf3328_dbgcallleave();
  798. return 0;
  799. }
  800. static int
  801. snd_azf3328_capture_prepare(struct snd_pcm_substream *substream)
  802. {
  803. #if 0
  804. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  805. struct snd_pcm_runtime *runtime = substream->runtime;
  806. unsigned int size = snd_pcm_lib_buffer_bytes(substream);
  807. unsigned int count = snd_pcm_lib_period_bytes(substream);
  808. #endif
  809. snd_azf3328_dbgcallenter();
  810. #if 0
  811. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  812. runtime->rate,
  813. snd_pcm_format_width(runtime->format),
  814. runtime->channels);
  815. snd_azf3328_setdmaa(chip, runtime->dma_addr, count, size, 1);
  816. #endif
  817. snd_azf3328_dbgcallleave();
  818. return 0;
  819. }
  820. static int
  821. snd_azf3328_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  822. {
  823. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  824. struct snd_pcm_runtime *runtime = substream->runtime;
  825. int result = 0;
  826. unsigned int status1;
  827. snd_azf3328_dbgcalls("snd_azf3328_playback_trigger cmd %d\n", cmd);
  828. switch (cmd) {
  829. case SNDRV_PCM_TRIGGER_START:
  830. snd_azf3328_dbgplay("START PLAYBACK\n");
  831. /* mute WaveOut */
  832. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  833. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT,
  834. runtime->rate,
  835. snd_pcm_format_width(runtime->format),
  836. runtime->channels);
  837. spin_lock(&chip->reg_lock);
  838. /* stop playback */
  839. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  840. status1 &= ~DMA_RESUME;
  841. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  842. /* FIXME: clear interrupts or what??? */
  843. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_IRQTYPE, 0xffff);
  844. spin_unlock(&chip->reg_lock);
  845. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  846. snd_pcm_lib_period_bytes(substream),
  847. snd_pcm_lib_buffer_bytes(substream),
  848. 0);
  849. spin_lock(&chip->reg_lock);
  850. #ifdef WIN9X
  851. /* FIXME: enable playback/recording??? */
  852. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  853. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  854. /* start playback again */
  855. /* FIXME: what is this value (0x0010)??? */
  856. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  857. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  858. #else /* NT4 */
  859. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  860. 0x0000);
  861. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  862. DMA_PLAY_SOMETHING1);
  863. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  864. DMA_PLAY_SOMETHING1 |
  865. DMA_PLAY_SOMETHING2);
  866. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  867. DMA_RESUME |
  868. SOMETHING_ALMOST_ALWAYS_SET |
  869. DMA_EPILOGUE_SOMETHING |
  870. DMA_SOMETHING_ELSE);
  871. #endif
  872. spin_unlock(&chip->reg_lock);
  873. /* now unmute WaveOut */
  874. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  875. chip->is_playing = 1;
  876. snd_azf3328_dbgplay("STARTED PLAYBACK\n");
  877. break;
  878. case SNDRV_PCM_TRIGGER_RESUME:
  879. snd_azf3328_dbgplay("RESUME PLAYBACK\n");
  880. /* resume playback if we were active */
  881. if (chip->is_playing)
  882. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  883. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) | DMA_RESUME);
  884. break;
  885. case SNDRV_PCM_TRIGGER_STOP:
  886. snd_azf3328_dbgplay("STOP PLAYBACK\n");
  887. /* mute WaveOut */
  888. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  889. spin_lock(&chip->reg_lock);
  890. /* stop playback */
  891. status1 = snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS);
  892. status1 &= ~DMA_RESUME;
  893. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  894. /* hmm, is this really required? we're resetting the same bit
  895. * immediately thereafter... */
  896. status1 |= DMA_PLAY_SOMETHING1;
  897. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  898. status1 &= ~DMA_PLAY_SOMETHING1;
  899. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS, status1);
  900. spin_unlock(&chip->reg_lock);
  901. /* now unmute WaveOut */
  902. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 0);
  903. chip->is_playing = 0;
  904. snd_azf3328_dbgplay("STOPPED PLAYBACK\n");
  905. break;
  906. case SNDRV_PCM_TRIGGER_SUSPEND:
  907. snd_azf3328_dbgplay("SUSPEND PLAYBACK\n");
  908. /* make sure playback is stopped */
  909. snd_azf3328_codec_outw(chip, IDX_IO_PLAY_FLAGS,
  910. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS) & ~DMA_RESUME);
  911. break;
  912. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  913. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  914. break;
  915. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  916. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  917. break;
  918. default:
  919. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  920. return -EINVAL;
  921. }
  922. snd_azf3328_dbgcallleave();
  923. return result;
  924. }
  925. /* this is just analogous to playback; I'm not quite sure whether recording
  926. * should actually be triggered like that */
  927. static int
  928. snd_azf3328_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  929. {
  930. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  931. struct snd_pcm_runtime *runtime = substream->runtime;
  932. int result = 0;
  933. unsigned int status1;
  934. snd_azf3328_dbgcalls("snd_azf3328_capture_trigger cmd %d\n", cmd);
  935. switch (cmd) {
  936. case SNDRV_PCM_TRIGGER_START:
  937. snd_azf3328_dbgplay("START CAPTURE\n");
  938. snd_azf3328_setfmt(chip, IDX_IO_REC_SOUNDFORMAT,
  939. runtime->rate,
  940. snd_pcm_format_width(runtime->format),
  941. runtime->channels);
  942. spin_lock(&chip->reg_lock);
  943. /* stop recording */
  944. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  945. status1 &= ~DMA_RESUME;
  946. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  947. /* FIXME: clear interrupts or what??? */
  948. snd_azf3328_codec_outw(chip, IDX_IO_REC_IRQTYPE, 0xffff);
  949. spin_unlock(&chip->reg_lock);
  950. snd_azf3328_setdmaa(chip, runtime->dma_addr,
  951. snd_pcm_lib_period_bytes(substream),
  952. snd_pcm_lib_buffer_bytes(substream),
  953. 1);
  954. spin_lock(&chip->reg_lock);
  955. #ifdef WIN9X
  956. /* FIXME: enable playback/recording??? */
  957. status1 |= DMA_PLAY_SOMETHING1 | DMA_PLAY_SOMETHING2;
  958. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  959. /* start capture again */
  960. /* FIXME: what is this value (0x0010)??? */
  961. status1 |= DMA_RESUME | DMA_EPILOGUE_SOMETHING;
  962. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  963. #else
  964. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  965. 0x0000);
  966. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  967. DMA_PLAY_SOMETHING1);
  968. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  969. DMA_PLAY_SOMETHING1 |
  970. DMA_PLAY_SOMETHING2);
  971. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  972. DMA_RESUME |
  973. SOMETHING_ALMOST_ALWAYS_SET |
  974. DMA_EPILOGUE_SOMETHING |
  975. DMA_SOMETHING_ELSE);
  976. #endif
  977. spin_unlock(&chip->reg_lock);
  978. chip->is_recording = 1;
  979. snd_azf3328_dbgplay("STARTED CAPTURE\n");
  980. break;
  981. case SNDRV_PCM_TRIGGER_RESUME:
  982. snd_azf3328_dbgplay("RESUME CAPTURE\n");
  983. /* resume recording if we were active */
  984. if (chip->is_recording)
  985. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  986. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) | DMA_RESUME);
  987. break;
  988. case SNDRV_PCM_TRIGGER_STOP:
  989. snd_azf3328_dbgplay("STOP CAPTURE\n");
  990. spin_lock(&chip->reg_lock);
  991. /* stop recording */
  992. status1 = snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS);
  993. status1 &= ~DMA_RESUME;
  994. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  995. status1 |= DMA_PLAY_SOMETHING1;
  996. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  997. status1 &= ~DMA_PLAY_SOMETHING1;
  998. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS, status1);
  999. spin_unlock(&chip->reg_lock);
  1000. chip->is_recording = 0;
  1001. snd_azf3328_dbgplay("STOPPED CAPTURE\n");
  1002. break;
  1003. case SNDRV_PCM_TRIGGER_SUSPEND:
  1004. snd_azf3328_dbgplay("SUSPEND CAPTURE\n");
  1005. /* make sure recording is stopped */
  1006. snd_azf3328_codec_outw(chip, IDX_IO_REC_FLAGS,
  1007. snd_azf3328_codec_inw(chip, IDX_IO_REC_FLAGS) & ~DMA_RESUME);
  1008. break;
  1009. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  1010. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_PUSH NIY!\n");
  1011. break;
  1012. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  1013. snd_printk(KERN_ERR "FIXME: SNDRV_PCM_TRIGGER_PAUSE_RELEASE NIY!\n");
  1014. break;
  1015. default:
  1016. printk(KERN_ERR "FIXME: unknown trigger mode!\n");
  1017. return -EINVAL;
  1018. }
  1019. snd_azf3328_dbgcallleave();
  1020. return result;
  1021. }
  1022. static snd_pcm_uframes_t
  1023. snd_azf3328_playback_pointer(struct snd_pcm_substream *substream)
  1024. {
  1025. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1026. unsigned long bufptr, result;
  1027. snd_pcm_uframes_t frmres;
  1028. #ifdef QUERY_HARDWARE
  1029. bufptr = inl(chip->codec_port+IDX_IO_PLAY_DMA_START_1);
  1030. #else
  1031. bufptr = substream->runtime->dma_addr;
  1032. #endif
  1033. result = inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS);
  1034. /* calculate offset */
  1035. result -= bufptr;
  1036. frmres = bytes_to_frames( substream->runtime, result);
  1037. snd_azf3328_dbgplay("PLAY @ 0x%8lx, frames %8ld\n", result, frmres);
  1038. return frmres;
  1039. }
  1040. static snd_pcm_uframes_t
  1041. snd_azf3328_capture_pointer(struct snd_pcm_substream *substream)
  1042. {
  1043. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1044. unsigned long bufptr, result;
  1045. snd_pcm_uframes_t frmres;
  1046. #ifdef QUERY_HARDWARE
  1047. bufptr = inl(chip->codec_port+IDX_IO_REC_DMA_START_1);
  1048. #else
  1049. bufptr = substream->runtime->dma_addr;
  1050. #endif
  1051. result = inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS);
  1052. /* calculate offset */
  1053. result -= bufptr;
  1054. frmres = bytes_to_frames( substream->runtime, result);
  1055. snd_azf3328_dbgplay("REC @ 0x%8lx, frames %8ld\n", result, frmres);
  1056. return frmres;
  1057. }
  1058. static irqreturn_t
  1059. snd_azf3328_interrupt(int irq, void *dev_id)
  1060. {
  1061. struct snd_azf3328 *chip = dev_id;
  1062. u8 status, which;
  1063. static unsigned long irq_count;
  1064. status = snd_azf3328_codec_inb(chip, IDX_IO_IRQSTATUS);
  1065. /* fast path out, to ease interrupt sharing */
  1066. if (!(status & (IRQ_PLAYBACK|IRQ_RECORDING|IRQ_MPU401|IRQ_TIMER)))
  1067. return IRQ_NONE; /* must be interrupt for another device */
  1068. snd_azf3328_dbgplay("Interrupt %ld!\nIDX_IO_PLAY_FLAGS %04x, IDX_IO_PLAY_IRQTYPE %04x, IDX_IO_IRQSTATUS %04x\n",
  1069. irq_count,
  1070. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_FLAGS),
  1071. snd_azf3328_codec_inw(chip, IDX_IO_PLAY_IRQTYPE),
  1072. status);
  1073. if (status & IRQ_TIMER) {
  1074. /* snd_azf3328_dbgplay("timer %ld\n", inl(chip->codec_port+IDX_IO_TIMER_VALUE) & TIMER_VALUE_MASK); */
  1075. if (chip->timer)
  1076. snd_timer_interrupt(chip->timer, chip->timer->sticks);
  1077. /* ACK timer */
  1078. spin_lock(&chip->reg_lock);
  1079. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x07);
  1080. spin_unlock(&chip->reg_lock);
  1081. snd_azf3328_dbgplay("azt3328: timer IRQ\n");
  1082. }
  1083. if (status & IRQ_PLAYBACK) {
  1084. spin_lock(&chip->reg_lock);
  1085. which = snd_azf3328_codec_inb(chip, IDX_IO_PLAY_IRQTYPE);
  1086. /* ack all IRQ types immediately */
  1087. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_IRQTYPE, which);
  1088. spin_unlock(&chip->reg_lock);
  1089. if (chip->pcm && chip->playback_substream) {
  1090. snd_pcm_period_elapsed(chip->playback_substream);
  1091. snd_azf3328_dbgplay("PLAY period done (#%x), @ %x\n",
  1092. which,
  1093. inl(chip->codec_port+IDX_IO_PLAY_DMA_CURRPOS));
  1094. } else
  1095. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1096. if (which & IRQ_PLAY_SOMETHING)
  1097. snd_azf3328_dbgplay("azt3328: unknown play IRQ type occurred, please report!\n");
  1098. }
  1099. if (status & IRQ_RECORDING) {
  1100. spin_lock(&chip->reg_lock);
  1101. which = snd_azf3328_codec_inb(chip, IDX_IO_REC_IRQTYPE);
  1102. /* ack all IRQ types immediately */
  1103. snd_azf3328_codec_outb(chip, IDX_IO_REC_IRQTYPE, which);
  1104. spin_unlock(&chip->reg_lock);
  1105. if (chip->pcm && chip->capture_substream) {
  1106. snd_pcm_period_elapsed(chip->capture_substream);
  1107. snd_azf3328_dbgplay("REC period done (#%x), @ %x\n",
  1108. which,
  1109. inl(chip->codec_port+IDX_IO_REC_DMA_CURRPOS));
  1110. } else
  1111. snd_azf3328_dbgplay("azt3328: ouch, irq handler problem!\n");
  1112. if (which & IRQ_REC_SOMETHING)
  1113. snd_azf3328_dbgplay("azt3328: unknown rec IRQ type occurred, please report!\n");
  1114. }
  1115. /* MPU401 has less critical IRQ requirements
  1116. * than timer and playback/recording, right? */
  1117. if (status & IRQ_MPU401) {
  1118. snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
  1119. /* hmm, do we have to ack the IRQ here somehow?
  1120. * If so, then I don't know how... */
  1121. snd_azf3328_dbgplay("azt3328: MPU401 IRQ\n");
  1122. }
  1123. irq_count++;
  1124. return IRQ_HANDLED;
  1125. }
  1126. /*****************************************************************/
  1127. static const struct snd_pcm_hardware snd_azf3328_playback =
  1128. {
  1129. /* FIXME!! Correct? */
  1130. .info = SNDRV_PCM_INFO_MMAP |
  1131. SNDRV_PCM_INFO_INTERLEAVED |
  1132. SNDRV_PCM_INFO_MMAP_VALID,
  1133. .formats = SNDRV_PCM_FMTBIT_S8 |
  1134. SNDRV_PCM_FMTBIT_U8 |
  1135. SNDRV_PCM_FMTBIT_S16_LE |
  1136. SNDRV_PCM_FMTBIT_U16_LE,
  1137. .rates = SNDRV_PCM_RATE_5512 |
  1138. SNDRV_PCM_RATE_8000_48000 |
  1139. SNDRV_PCM_RATE_KNOT,
  1140. .rate_min = 4000,
  1141. .rate_max = 66200,
  1142. .channels_min = 1,
  1143. .channels_max = 2,
  1144. .buffer_bytes_max = 65536,
  1145. .period_bytes_min = 64,
  1146. .period_bytes_max = 65536,
  1147. .periods_min = 1,
  1148. .periods_max = 1024,
  1149. /* FIXME: maybe that card actually has a FIFO?
  1150. * Hmm, it seems newer revisions do have one, but we still don't know
  1151. * its size... */
  1152. .fifo_size = 0,
  1153. };
  1154. static const struct snd_pcm_hardware snd_azf3328_capture =
  1155. {
  1156. /* FIXME */
  1157. .info = SNDRV_PCM_INFO_MMAP |
  1158. SNDRV_PCM_INFO_INTERLEAVED |
  1159. SNDRV_PCM_INFO_MMAP_VALID,
  1160. .formats = SNDRV_PCM_FMTBIT_S8 |
  1161. SNDRV_PCM_FMTBIT_U8 |
  1162. SNDRV_PCM_FMTBIT_S16_LE |
  1163. SNDRV_PCM_FMTBIT_U16_LE,
  1164. .rates = SNDRV_PCM_RATE_5512 |
  1165. SNDRV_PCM_RATE_8000_48000 |
  1166. SNDRV_PCM_RATE_KNOT,
  1167. .rate_min = 4000,
  1168. .rate_max = 66200,
  1169. .channels_min = 1,
  1170. .channels_max = 2,
  1171. .buffer_bytes_max = 65536,
  1172. .period_bytes_min = 64,
  1173. .period_bytes_max = 65536,
  1174. .periods_min = 1,
  1175. .periods_max = 1024,
  1176. .fifo_size = 0,
  1177. };
  1178. static unsigned int snd_azf3328_fixed_rates[] = {
  1179. 4000, 4800, 5512, 6620, 8000, 9600, 11025, 13240, 16000, 22050, 32000,
  1180. 44100, 48000, 66200 };
  1181. static struct snd_pcm_hw_constraint_list snd_azf3328_hw_constraints_rates = {
  1182. .count = ARRAY_SIZE(snd_azf3328_fixed_rates),
  1183. .list = snd_azf3328_fixed_rates,
  1184. .mask = 0,
  1185. };
  1186. /*****************************************************************/
  1187. static int
  1188. snd_azf3328_playback_open(struct snd_pcm_substream *substream)
  1189. {
  1190. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1191. struct snd_pcm_runtime *runtime = substream->runtime;
  1192. snd_azf3328_dbgcallenter();
  1193. chip->playback_substream = substream;
  1194. runtime->hw = snd_azf3328_playback;
  1195. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1196. &snd_azf3328_hw_constraints_rates);
  1197. snd_azf3328_dbgcallleave();
  1198. return 0;
  1199. }
  1200. static int
  1201. snd_azf3328_capture_open(struct snd_pcm_substream *substream)
  1202. {
  1203. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1204. struct snd_pcm_runtime *runtime = substream->runtime;
  1205. snd_azf3328_dbgcallenter();
  1206. chip->capture_substream = substream;
  1207. runtime->hw = snd_azf3328_capture;
  1208. snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  1209. &snd_azf3328_hw_constraints_rates);
  1210. snd_azf3328_dbgcallleave();
  1211. return 0;
  1212. }
  1213. static int
  1214. snd_azf3328_playback_close(struct snd_pcm_substream *substream)
  1215. {
  1216. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1217. snd_azf3328_dbgcallenter();
  1218. chip->playback_substream = NULL;
  1219. snd_azf3328_dbgcallleave();
  1220. return 0;
  1221. }
  1222. static int
  1223. snd_azf3328_capture_close(struct snd_pcm_substream *substream)
  1224. {
  1225. struct snd_azf3328 *chip = snd_pcm_substream_chip(substream);
  1226. snd_azf3328_dbgcallenter();
  1227. chip->capture_substream = NULL;
  1228. snd_azf3328_dbgcallleave();
  1229. return 0;
  1230. }
  1231. /******************************************************************/
  1232. static struct snd_pcm_ops snd_azf3328_playback_ops = {
  1233. .open = snd_azf3328_playback_open,
  1234. .close = snd_azf3328_playback_close,
  1235. .ioctl = snd_pcm_lib_ioctl,
  1236. .hw_params = snd_azf3328_hw_params,
  1237. .hw_free = snd_azf3328_hw_free,
  1238. .prepare = snd_azf3328_playback_prepare,
  1239. .trigger = snd_azf3328_playback_trigger,
  1240. .pointer = snd_azf3328_playback_pointer
  1241. };
  1242. static struct snd_pcm_ops snd_azf3328_capture_ops = {
  1243. .open = snd_azf3328_capture_open,
  1244. .close = snd_azf3328_capture_close,
  1245. .ioctl = snd_pcm_lib_ioctl,
  1246. .hw_params = snd_azf3328_hw_params,
  1247. .hw_free = snd_azf3328_hw_free,
  1248. .prepare = snd_azf3328_capture_prepare,
  1249. .trigger = snd_azf3328_capture_trigger,
  1250. .pointer = snd_azf3328_capture_pointer
  1251. };
  1252. static int __devinit
  1253. snd_azf3328_pcm(struct snd_azf3328 *chip, int device)
  1254. {
  1255. struct snd_pcm *pcm;
  1256. int err;
  1257. snd_azf3328_dbgcallenter();
  1258. if ((err = snd_pcm_new(chip->card, "AZF3328 DSP", device, 1, 1, &pcm)) < 0)
  1259. return err;
  1260. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_azf3328_playback_ops);
  1261. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_azf3328_capture_ops);
  1262. pcm->private_data = chip;
  1263. pcm->info_flags = 0;
  1264. strcpy(pcm->name, chip->card->shortname);
  1265. chip->pcm = pcm;
  1266. snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
  1267. snd_dma_pci_data(chip->pci), 64*1024, 64*1024);
  1268. snd_azf3328_dbgcallleave();
  1269. return 0;
  1270. }
  1271. /******************************************************************/
  1272. #ifdef SUPPORT_JOYSTICK
  1273. static int __devinit
  1274. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev)
  1275. {
  1276. struct gameport *gp;
  1277. struct resource *r;
  1278. if (!joystick[dev])
  1279. return -ENODEV;
  1280. if (!(r = request_region(0x200, 8, "AZF3328 gameport"))) {
  1281. printk(KERN_WARNING "azt3328: cannot reserve joystick ports\n");
  1282. return -EBUSY;
  1283. }
  1284. chip->gameport = gp = gameport_allocate_port();
  1285. if (!gp) {
  1286. printk(KERN_ERR "azt3328: cannot allocate memory for gameport\n");
  1287. release_and_free_resource(r);
  1288. return -ENOMEM;
  1289. }
  1290. gameport_set_name(gp, "AZF3328 Gameport");
  1291. gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
  1292. gameport_set_dev_parent(gp, &chip->pci->dev);
  1293. gp->io = 0x200;
  1294. gameport_set_port_data(gp, r);
  1295. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1296. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) | LEGACY_JOY);
  1297. gameport_register_port(chip->gameport);
  1298. return 0;
  1299. }
  1300. static void
  1301. snd_azf3328_free_joystick(struct snd_azf3328 *chip)
  1302. {
  1303. if (chip->gameport) {
  1304. struct resource *r = gameport_get_port_data(chip->gameport);
  1305. gameport_unregister_port(chip->gameport);
  1306. chip->gameport = NULL;
  1307. /* disable gameport */
  1308. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1309. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1310. release_and_free_resource(r);
  1311. }
  1312. }
  1313. #else
  1314. static inline int
  1315. snd_azf3328_config_joystick(struct snd_azf3328 *chip, int dev) { return -ENOSYS; }
  1316. static inline void
  1317. snd_azf3328_free_joystick(struct snd_azf3328 *chip) { }
  1318. #endif
  1319. /******************************************************************/
  1320. static int
  1321. snd_azf3328_free(struct snd_azf3328 *chip)
  1322. {
  1323. if (chip->irq < 0)
  1324. goto __end_hw;
  1325. /* reset (close) mixer */
  1326. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1); /* first mute master volume */
  1327. snd_azf3328_mixer_outw(chip, IDX_MIXER_RESET, 0x0000);
  1328. /* interrupt setup - mask everything (FIXME!) */
  1329. /* well, at least we know how to disable the timer IRQ */
  1330. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00);
  1331. synchronize_irq(chip->irq);
  1332. __end_hw:
  1333. snd_azf3328_free_joystick(chip);
  1334. if (chip->irq >= 0)
  1335. free_irq(chip->irq, chip);
  1336. pci_release_regions(chip->pci);
  1337. pci_disable_device(chip->pci);
  1338. kfree(chip);
  1339. return 0;
  1340. }
  1341. static int
  1342. snd_azf3328_dev_free(struct snd_device *device)
  1343. {
  1344. struct snd_azf3328 *chip = device->device_data;
  1345. return snd_azf3328_free(chip);
  1346. }
  1347. /******************************************************************/
  1348. /*** NOTE: the physical timer resolution actually is 1024000 ticks per second,
  1349. *** but announcing those attributes to user-space would make programs
  1350. *** configure the timer to a 1 tick value, resulting in an absolutely fatal
  1351. *** timer IRQ storm.
  1352. *** Thus I chose to announce a down-scaled virtual timer to the outside and
  1353. *** calculate real timer countdown values internally.
  1354. *** (the scale factor can be set via module parameter "seqtimer_scaling").
  1355. ***/
  1356. static int
  1357. snd_azf3328_timer_start(struct snd_timer *timer)
  1358. {
  1359. struct snd_azf3328 *chip;
  1360. unsigned long flags;
  1361. unsigned int delay;
  1362. snd_azf3328_dbgcallenter();
  1363. chip = snd_timer_chip(timer);
  1364. delay = ((timer->sticks * seqtimer_scaling) - 1) & TIMER_VALUE_MASK;
  1365. if (delay < 49) {
  1366. /* uhoh, that's not good, since user-space won't know about
  1367. * this timing tweak
  1368. * (we need to do it to avoid a lockup, though) */
  1369. snd_azf3328_dbgtimer("delay was too low (%d)!\n", delay);
  1370. delay = 49; /* minimum time is 49 ticks */
  1371. }
  1372. snd_azf3328_dbgtimer("setting timer countdown value %d, add COUNTDOWN|IRQ\n", delay);
  1373. delay |= TIMER_ENABLE_COUNTDOWN | TIMER_ENABLE_IRQ;
  1374. spin_lock_irqsave(&chip->reg_lock, flags);
  1375. snd_azf3328_codec_outl(chip, IDX_IO_TIMER_VALUE, delay);
  1376. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1377. snd_azf3328_dbgcallleave();
  1378. return 0;
  1379. }
  1380. static int
  1381. snd_azf3328_timer_stop(struct snd_timer *timer)
  1382. {
  1383. struct snd_azf3328 *chip;
  1384. unsigned long flags;
  1385. snd_azf3328_dbgcallenter();
  1386. chip = snd_timer_chip(timer);
  1387. spin_lock_irqsave(&chip->reg_lock, flags);
  1388. /* disable timer countdown and interrupt */
  1389. /* FIXME: should we write TIMER_ACK_IRQ here? */
  1390. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0);
  1391. spin_unlock_irqrestore(&chip->reg_lock, flags);
  1392. snd_azf3328_dbgcallleave();
  1393. return 0;
  1394. }
  1395. static int
  1396. snd_azf3328_timer_precise_resolution(struct snd_timer *timer,
  1397. unsigned long *num, unsigned long *den)
  1398. {
  1399. snd_azf3328_dbgcallenter();
  1400. *num = 1;
  1401. *den = 1024000 / seqtimer_scaling;
  1402. snd_azf3328_dbgcallleave();
  1403. return 0;
  1404. }
  1405. static struct snd_timer_hardware snd_azf3328_timer_hw = {
  1406. .flags = SNDRV_TIMER_HW_AUTO,
  1407. .resolution = 977, /* 1000000/1024000 = 0.9765625us */
  1408. .ticks = 1024000, /* max tick count, defined by the value register; actually it's not 1024000, but 1048576, but we don't care */
  1409. .start = snd_azf3328_timer_start,
  1410. .stop = snd_azf3328_timer_stop,
  1411. .precise_resolution = snd_azf3328_timer_precise_resolution,
  1412. };
  1413. static int __devinit
  1414. snd_azf3328_timer(struct snd_azf3328 *chip, int device)
  1415. {
  1416. struct snd_timer *timer = NULL;
  1417. struct snd_timer_id tid;
  1418. int err;
  1419. snd_azf3328_dbgcallenter();
  1420. tid.dev_class = SNDRV_TIMER_CLASS_CARD;
  1421. tid.dev_sclass = SNDRV_TIMER_SCLASS_NONE;
  1422. tid.card = chip->card->number;
  1423. tid.device = device;
  1424. tid.subdevice = 0;
  1425. snd_azf3328_timer_hw.resolution *= seqtimer_scaling;
  1426. snd_azf3328_timer_hw.ticks /= seqtimer_scaling;
  1427. if ((err = snd_timer_new(chip->card, "AZF3328", &tid, &timer)) < 0) {
  1428. goto out;
  1429. }
  1430. strcpy(timer->name, "AZF3328 timer");
  1431. timer->private_data = chip;
  1432. timer->hw = snd_azf3328_timer_hw;
  1433. chip->timer = timer;
  1434. err = 0;
  1435. out:
  1436. snd_azf3328_dbgcallleave();
  1437. return err;
  1438. }
  1439. /******************************************************************/
  1440. #if 0
  1441. /* check whether a bit can be modified */
  1442. static void
  1443. snd_azf3328_test_bit(unsigned int reg, int bit)
  1444. {
  1445. unsigned char val, valoff, valon;
  1446. val = inb(reg);
  1447. outb(val & ~(1 << bit), reg);
  1448. valoff = inb(reg);
  1449. outb(val|(1 << bit), reg);
  1450. valon = inb(reg);
  1451. outb(val, reg);
  1452. printk(KERN_ERR "reg %04x bit %d: %02x %02x %02x\n", reg, bit, val, valoff, valon);
  1453. }
  1454. #endif
  1455. static void
  1456. snd_azf3328_debug_show_ports(const struct snd_azf3328 *chip)
  1457. {
  1458. #if DEBUG_MISC
  1459. u16 tmp;
  1460. snd_azf3328_dbgmisc("codec_port 0x%lx, io2_port 0x%lx, mpu_port 0x%lx, synth_port 0x%lx, mixer_port 0x%lx, irq %d\n", chip->codec_port, chip->io2_port, chip->mpu_port, chip->synth_port, chip->mixer_port, chip->irq);
  1461. snd_azf3328_dbgmisc("io2 %02x %02x %02x %02x %02x %02x\n", snd_azf3328_io2_inb(chip, 0), snd_azf3328_io2_inb(chip, 1), snd_azf3328_io2_inb(chip, 2), snd_azf3328_io2_inb(chip, 3), snd_azf3328_io2_inb(chip, 4), snd_azf3328_io2_inb(chip, 5));
  1462. for (tmp=0; tmp <= 0x01; tmp += 1)
  1463. snd_azf3328_dbgmisc("0x%02x: opl 0x%04x, mpu300 0x%04x, mpu310 0x%04x, mpu320 0x%04x, mpu330 0x%04x\n", tmp, inb(0x388 + tmp), inb(0x300 + tmp), inb(0x310 + tmp), inb(0x320 + tmp), inb(0x330 + tmp));
  1464. for (tmp = 0; tmp <= 0x6E; tmp += 2)
  1465. snd_azf3328_dbgmisc("0x%02x: 0x%04x\n", tmp, snd_azf3328_codec_inb(chip, tmp));
  1466. #endif
  1467. }
  1468. static int __devinit
  1469. snd_azf3328_create(struct snd_card *card,
  1470. struct pci_dev *pci,
  1471. unsigned long device_type,
  1472. struct snd_azf3328 ** rchip)
  1473. {
  1474. struct snd_azf3328 *chip;
  1475. int err;
  1476. static struct snd_device_ops ops = {
  1477. .dev_free = snd_azf3328_dev_free,
  1478. };
  1479. u16 tmp;
  1480. *rchip = NULL;
  1481. if ((err = pci_enable_device(pci)) < 0)
  1482. return err;
  1483. chip = kzalloc(sizeof(*chip), GFP_KERNEL);
  1484. if (chip == NULL) {
  1485. err = -ENOMEM;
  1486. goto out_err;
  1487. }
  1488. spin_lock_init(&chip->reg_lock);
  1489. chip->card = card;
  1490. chip->pci = pci;
  1491. chip->irq = -1;
  1492. /* check if we can restrict PCI DMA transfers to 24 bits */
  1493. if (pci_set_dma_mask(pci, DMA_24BIT_MASK) < 0 ||
  1494. pci_set_consistent_dma_mask(pci, DMA_24BIT_MASK) < 0) {
  1495. snd_printk(KERN_ERR "architecture does not support 24bit PCI busmaster DMA\n");
  1496. err = -ENXIO;
  1497. goto out_err;
  1498. }
  1499. if ((err = pci_request_regions(pci, "Aztech AZF3328")) < 0) {
  1500. goto out_err;
  1501. }
  1502. chip->codec_port = pci_resource_start(pci, 0);
  1503. chip->io2_port = pci_resource_start(pci, 1);
  1504. chip->mpu_port = pci_resource_start(pci, 2);
  1505. chip->synth_port = pci_resource_start(pci, 3);
  1506. chip->mixer_port = pci_resource_start(pci, 4);
  1507. if (request_irq(pci->irq, snd_azf3328_interrupt,
  1508. IRQF_SHARED, card->shortname, chip)) {
  1509. snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
  1510. err = -EBUSY;
  1511. goto out_err;
  1512. }
  1513. chip->irq = pci->irq;
  1514. pci_set_master(pci);
  1515. synchronize_irq(chip->irq);
  1516. snd_azf3328_debug_show_ports(chip);
  1517. if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
  1518. goto out_err;
  1519. }
  1520. /* create mixer interface & switches */
  1521. if ((err = snd_azf3328_mixer_new(chip)) < 0)
  1522. goto out_err;
  1523. #if 0
  1524. /* set very low bitrate to reduce noise and power consumption? */
  1525. snd_azf3328_setfmt(chip, IDX_IO_PLAY_SOUNDFORMAT, 5512, 8, 1);
  1526. #endif
  1527. /* standard chip init stuff */
  1528. /* default IRQ init value */
  1529. tmp = DMA_PLAY_SOMETHING2|DMA_EPILOGUE_SOMETHING|DMA_SOMETHING_ELSE;
  1530. spin_lock_irq(&chip->reg_lock);
  1531. snd_azf3328_codec_outb(chip, IDX_IO_PLAY_FLAGS, tmp);
  1532. snd_azf3328_codec_outb(chip, IDX_IO_REC_FLAGS, tmp);
  1533. snd_azf3328_codec_outb(chip, IDX_IO_SOMETHING_FLAGS, tmp);
  1534. snd_azf3328_codec_outb(chip, IDX_IO_TIMER_VALUE + 3, 0x00); /* disable timer */
  1535. spin_unlock_irq(&chip->reg_lock);
  1536. snd_card_set_dev(card, &pci->dev);
  1537. *rchip = chip;
  1538. err = 0;
  1539. goto out;
  1540. out_err:
  1541. if (chip)
  1542. snd_azf3328_free(chip);
  1543. pci_disable_device(pci);
  1544. out:
  1545. return err;
  1546. }
  1547. static int __devinit
  1548. snd_azf3328_probe(struct pci_dev *pci, const struct pci_device_id *pci_id)
  1549. {
  1550. static int dev;
  1551. struct snd_card *card;
  1552. struct snd_azf3328 *chip;
  1553. struct snd_opl3 *opl3;
  1554. int err;
  1555. snd_azf3328_dbgcallenter();
  1556. if (dev >= SNDRV_CARDS)
  1557. return -ENODEV;
  1558. if (!enable[dev]) {
  1559. dev++;
  1560. return -ENOENT;
  1561. }
  1562. card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0 );
  1563. if (card == NULL)
  1564. return -ENOMEM;
  1565. strcpy(card->driver, "AZF3328");
  1566. strcpy(card->shortname, "Aztech AZF3328 (PCI168)");
  1567. if ((err = snd_azf3328_create(card, pci, pci_id->driver_data, &chip)) < 0) {
  1568. goto out_err;
  1569. }
  1570. card->private_data = chip;
  1571. if ((err = snd_mpu401_uart_new( card, 0, MPU401_HW_MPU401,
  1572. chip->mpu_port, MPU401_INFO_INTEGRATED,
  1573. pci->irq, 0, &chip->rmidi)) < 0) {
  1574. snd_printk(KERN_ERR "azf3328: no MPU-401 device at 0x%lx?\n", chip->mpu_port);
  1575. goto out_err;
  1576. }
  1577. if ((err = snd_azf3328_timer(chip, 0)) < 0) {
  1578. goto out_err;
  1579. }
  1580. if ((err = snd_azf3328_pcm(chip, 0)) < 0) {
  1581. goto out_err;
  1582. }
  1583. if (snd_opl3_create(card, chip->synth_port, chip->synth_port+2,
  1584. OPL3_HW_AUTO, 1, &opl3) < 0) {
  1585. snd_printk(KERN_ERR "azf3328: no OPL3 device at 0x%lx-0x%lx?\n",
  1586. chip->synth_port, chip->synth_port+2 );
  1587. } else {
  1588. if ((err = snd_opl3_hwdep_new(opl3, 0, 1, NULL)) < 0) {
  1589. goto out_err;
  1590. }
  1591. }
  1592. opl3->private_data = chip;
  1593. sprintf(card->longname, "%s at 0x%lx, irq %i",
  1594. card->shortname, chip->codec_port, chip->irq);
  1595. if ((err = snd_card_register(card)) < 0) {
  1596. goto out_err;
  1597. }
  1598. #ifdef MODULE
  1599. printk(
  1600. "azt3328: Sound driver for Aztech AZF3328-based soundcards such as PCI168\n"
  1601. "azt3328: (hardware was completely undocumented - ZERO support from Aztech).\n"
  1602. "azt3328: Feel free to contact andi AT lisas.de for bug reports etc.!\n"
  1603. "azt3328: User-scalable sequencer timer set to %dHz (1024000Hz / %d).\n",
  1604. 1024000 / seqtimer_scaling, seqtimer_scaling);
  1605. #endif
  1606. if (snd_azf3328_config_joystick(chip, dev) < 0)
  1607. snd_azf3328_io2_outb(chip, IDX_IO2_LEGACY_ADDR,
  1608. snd_azf3328_io2_inb(chip, IDX_IO2_LEGACY_ADDR) & ~LEGACY_JOY);
  1609. pci_set_drvdata(pci, card);
  1610. dev++;
  1611. err = 0;
  1612. goto out;
  1613. out_err:
  1614. snd_card_free(card);
  1615. out:
  1616. snd_azf3328_dbgcallleave();
  1617. return err;
  1618. }
  1619. static void __devexit
  1620. snd_azf3328_remove(struct pci_dev *pci)
  1621. {
  1622. snd_azf3328_dbgcallenter();
  1623. snd_card_free(pci_get_drvdata(pci));
  1624. pci_set_drvdata(pci, NULL);
  1625. snd_azf3328_dbgcallleave();
  1626. }
  1627. #ifdef CONFIG_PM
  1628. static int
  1629. snd_azf3328_suspend(struct pci_dev *pci, pm_message_t state)
  1630. {
  1631. struct snd_card *card = pci_get_drvdata(pci);
  1632. struct snd_azf3328 *chip = card->private_data;
  1633. int reg;
  1634. snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
  1635. snd_pcm_suspend_all(chip->pcm);
  1636. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1637. chip->saved_regs_mixer[reg] = inw(chip->mixer_port + reg * 2);
  1638. /* make sure to disable master volume etc. to prevent looping sound */
  1639. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_PLAY_MASTER, 1);
  1640. snd_azf3328_mixer_set_mute(chip, IDX_MIXER_WAVEOUT, 1);
  1641. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1642. chip->saved_regs_codec[reg] = inw(chip->codec_port + reg * 2);
  1643. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1644. chip->saved_regs_io2[reg] = inw(chip->io2_port + reg * 2);
  1645. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1646. chip->saved_regs_mpu[reg] = inw(chip->mpu_port + reg * 2);
  1647. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1648. chip->saved_regs_synth[reg] = inw(chip->synth_port + reg * 2);
  1649. pci_disable_device(pci);
  1650. pci_save_state(pci);
  1651. pci_set_power_state(pci, pci_choose_state(pci, state));
  1652. return 0;
  1653. }
  1654. static int
  1655. snd_azf3328_resume(struct pci_dev *pci)
  1656. {
  1657. struct snd_card *card = pci_get_drvdata(pci);
  1658. struct snd_azf3328 *chip = card->private_data;
  1659. int reg;
  1660. pci_set_power_state(pci, PCI_D0);
  1661. pci_restore_state(pci);
  1662. if (pci_enable_device(pci) < 0) {
  1663. printk(KERN_ERR "azt3328: pci_enable_device failed, "
  1664. "disabling device\n");
  1665. snd_card_disconnect(card);
  1666. return -EIO;
  1667. }
  1668. pci_set_master(pci);
  1669. for (reg = 0; reg < AZF_IO_SIZE_IO2_PM / 2; reg++)
  1670. outw(chip->saved_regs_io2[reg], chip->io2_port + reg * 2);
  1671. for (reg = 0; reg < AZF_IO_SIZE_MPU_PM / 2; reg++)
  1672. outw(chip->saved_regs_mpu[reg], chip->mpu_port + reg * 2);
  1673. for (reg = 0; reg < AZF_IO_SIZE_SYNTH_PM / 2; reg++)
  1674. outw(chip->saved_regs_synth[reg], chip->synth_port + reg * 2);
  1675. for (reg = 0; reg < AZF_IO_SIZE_MIXER_PM / 2; reg++)
  1676. outw(chip->saved_regs_mixer[reg], chip->mixer_port + reg * 2);
  1677. for (reg = 0; reg < AZF_IO_SIZE_CODEC_PM / 2; reg++)
  1678. outw(chip->saved_regs_codec[reg], chip->codec_port + reg * 2);
  1679. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  1680. return 0;
  1681. }
  1682. #endif
  1683. static struct pci_driver driver = {
  1684. .name = "AZF3328",
  1685. .id_table = snd_azf3328_ids,
  1686. .probe = snd_azf3328_probe,
  1687. .remove = __devexit_p(snd_azf3328_remove),
  1688. #ifdef CONFIG_PM
  1689. .suspend = snd_azf3328_suspend,
  1690. .resume = snd_azf3328_resume,
  1691. #endif
  1692. };
  1693. static int __init
  1694. alsa_card_azf3328_init(void)
  1695. {
  1696. int err;
  1697. snd_azf3328_dbgcallenter();
  1698. err = pci_register_driver(&driver);
  1699. snd_azf3328_dbgcallleave();
  1700. return err;
  1701. }
  1702. static void __exit
  1703. alsa_card_azf3328_exit(void)
  1704. {
  1705. snd_azf3328_dbgcallenter();
  1706. pci_unregister_driver(&driver);
  1707. snd_azf3328_dbgcallleave();
  1708. }
  1709. module_init(alsa_card_azf3328_init)
  1710. module_exit(alsa_card_azf3328_exit)