au88x0_sb.h 1.5 KB

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  1. /***************************************************************************
  2. * au88x0_sb.h
  3. *
  4. * Wed Oct 29 22:10:42 2003
  5. *
  6. ****************************************************************************/
  7. #ifdef CHIP_AU8820
  8. /* AU8820 starting @ 64KiB offset */
  9. #define SBEMU_BASE 0x10000
  10. #else
  11. /* AU8810? and AU8830 starting @ 164KiB offset */
  12. #define SBEMU_BASE 0x29000
  13. #endif
  14. #define FM_A_STATUS (SBEMU_BASE + 0x00) /* read */
  15. #define FM_A_ADDRESS (SBEMU_BASE + 0x00) /* write */
  16. #define FM_A_DATA (SBEMU_BASE + 0x04)
  17. #define FM_B_STATUS (SBEMU_BASE + 0x08)
  18. #define FM_B_ADDRESS (SBEMU_BASE + 0x08)
  19. #define FM_B_DATA (SBEMU_BASE + 0x0C)
  20. #define SB_MIXER_ADDR (SBEMU_BASE + 0x10)
  21. #define SB_MIXER_DATA (SBEMU_BASE + 0x14)
  22. #define SB_RESET (SBEMU_BASE + 0x18)
  23. #define SB_RESET_ALIAS (SBEMU_BASE + 0x1C)
  24. #define FM_STATUS2 (SBEMU_BASE + 0x20)
  25. #define FM_ADDR2 (SBEMU_BASE + 0x20)
  26. #define FM_DATA2 (SBEMU_BASE + 0x24)
  27. #define SB_DSP_READ (SBEMU_BASE + 0x28)
  28. #define SB_DSP_WRITE (SBEMU_BASE + 0x30)
  29. #define SB_DSP_WRITE_STATUS (SBEMU_BASE + 0x30) /* bit 7 */
  30. #define SB_DSP_READ_STATUS (SBEMU_BASE + 0x38) /* bit 7 */
  31. #define SB_LACR (SBEMU_BASE + 0x40) /* ? */
  32. #define SB_LADCR (SBEMU_BASE + 0x44) /* ? */
  33. #define SB_LAMR (SBEMU_BASE + 0x48) /* ? */
  34. #define SB_LARR (SBEMU_BASE + 0x4C) /* ? */
  35. #define SB_VERSION (SBEMU_BASE + 0x50)
  36. #define SB_CTRLSTAT (SBEMU_BASE + 0x54)
  37. #define SB_TIMERSTAT (SBEMU_BASE + 0x58)
  38. #define FM_RAM (SBEMU_BASE + 0x100) /* 0x40 ULONG */