au88x0_core.c 77 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498149915001501150215031504150515061507150815091510151115121513151415151516151715181519152015211522152315241525152615271528152915301531153215331534153515361537153815391540154115421543154415451546154715481549155015511552155315541555155615571558155915601561156215631564156515661567156815691570157115721573157415751576157715781579158015811582158315841585158615871588158915901591159215931594159515961597159815991600160116021603160416051606160716081609161016111612161316141615161616171618161916201621162216231624162516261627162816291630163116321633163416351636163716381639164016411642164316441645164616471648164916501651165216531654165516561657165816591660166116621663166416651666166716681669167016711672167316741675167616771678167916801681168216831684168516861687168816891690169116921693169416951696169716981699170017011702170317041705170617071708170917101711171217131714171517161717171817191720172117221723172417251726172717281729173017311732173317341735173617371738173917401741174217431744174517461747174817491750175117521753175417551756175717581759176017611762176317641765176617671768176917701771177217731774177517761777177817791780178117821783178417851786178717881789179017911792179317941795179617971798179918001801180218031804180518061807180818091810181118121813181418151816181718181819182018211822182318241825182618271828182918301831183218331834183518361837183818391840184118421843184418451846184718481849185018511852185318541855185618571858185918601861186218631864186518661867186818691870187118721873187418751876187718781879188018811882188318841885188618871888188918901891189218931894189518961897189818991900190119021903190419051906190719081909191019111912191319141915191619171918191919201921192219231924192519261927192819291930193119321933193419351936193719381939194019411942194319441945194619471948194919501951195219531954195519561957195819591960196119621963196419651966196719681969197019711972197319741975197619771978197919801981198219831984198519861987198819891990199119921993199419951996199719981999200020012002200320042005200620072008200920102011201220132014201520162017201820192020202120222023202420252026202720282029203020312032203320342035203620372038203920402041204220432044204520462047204820492050205120522053205420552056205720582059206020612062206320642065206620672068206920702071207220732074207520762077207820792080208120822083208420852086208720882089209020912092209320942095209620972098209921002101210221032104210521062107210821092110211121122113211421152116211721182119212021212122212321242125212621272128212921302131213221332134213521362137213821392140214121422143214421452146214721482149215021512152215321542155215621572158215921602161216221632164216521662167216821692170217121722173217421752176217721782179218021812182218321842185218621872188218921902191219221932194219521962197219821992200220122022203220422052206220722082209221022112212221322142215221622172218221922202221222222232224222522262227222822292230223122322233223422352236223722382239224022412242224322442245224622472248224922502251225222532254225522562257225822592260226122622263226422652266226722682269227022712272227322742275227622772278227922802281228222832284228522862287228822892290229122922293229422952296229722982299230023012302230323042305230623072308230923102311231223132314231523162317231823192320232123222323232423252326232723282329233023312332233323342335233623372338233923402341234223432344234523462347234823492350235123522353235423552356235723582359236023612362236323642365236623672368236923702371237223732374237523762377237823792380238123822383238423852386238723882389239023912392239323942395239623972398239924002401240224032404240524062407240824092410241124122413241424152416241724182419242024212422242324242425242624272428242924302431243224332434243524362437243824392440244124422443244424452446244724482449245024512452245324542455245624572458245924602461246224632464246524662467246824692470247124722473247424752476247724782479248024812482248324842485248624872488248924902491249224932494249524962497249824992500250125022503250425052506250725082509251025112512251325142515251625172518251925202521252225232524252525262527252825292530253125322533253425352536253725382539254025412542254325442545254625472548254925502551255225532554255525562557255825592560256125622563256425652566256725682569257025712572257325742575257625772578257925802581258225832584258525862587258825892590259125922593259425952596259725982599260026012602260326042605260626072608260926102611261226132614261526162617261826192620262126222623262426252626262726282629263026312632263326342635263626372638263926402641264226432644264526462647264826492650265126522653265426552656265726582659266026612662266326642665266626672668266926702671267226732674267526762677267826792680268126822683268426852686268726882689269026912692269326942695269626972698269927002701270227032704270527062707270827092710271127122713271427152716271727182719272027212722272327242725272627272728272927302731273227332734273527362737273827392740274127422743274427452746274727482749275027512752275327542755275627572758275927602761276227632764276527662767276827692770277127722773277427752776277727782779278027812782278327842785278627872788278927902791279227932794279527962797279827992800280128022803280428052806280728082809281028112812281328142815281628172818281928202821282228232824282528262827282828292830283128322833283428352836283728382839
  1. /*
  2. * This program is free software; you can redistribute it and/or modify
  3. * it under the terms of the GNU General Public License as published by
  4. * the Free Software Foundation; either version 2 of the License, or
  5. * (at your option) any later version.
  6. *
  7. * This program is distributed in the hope that it will be useful,
  8. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. * GNU Library General Public License for more details.
  11. *
  12. * You should have received a copy of the GNU General Public License
  13. * along with this program; if not, write to the Free Software
  14. * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  15. */
  16. /*
  17. Vortex core low level functions.
  18. Author: Manuel Jander (mjander@users.sourceforge.cl)
  19. These functions are mainly the result of translations made
  20. from the original disassembly of the au88x0 binary drivers,
  21. written by Aureal before they went down.
  22. Many thanks to the Jeff Muizelaar, Kester Maddock, and whoever
  23. contributed to the OpenVortex project.
  24. The author of this file, put the few available pieces together
  25. and translated the rest of the riddle (Mix, Src and connection stuff).
  26. Some things are still to be discovered, and their meanings are unclear.
  27. Some of these functions aren't intended to be really used, rather
  28. to help to understand how does the AU88X0 chips work. Keep them in, because
  29. they could be used somewhere in the future.
  30. This code hasn't been tested or proof read thoroughly. If you wanna help,
  31. take a look at the AU88X0 assembly and check if this matches.
  32. Functions tested ok so far are (they show the desired effect
  33. at least):
  34. vortex_routes(); (1 bug fixed).
  35. vortex_adb_addroute();
  36. vortex_adb_addroutes();
  37. vortex_connect_codecplay();
  38. vortex_src_flushbuffers();
  39. vortex_adbdma_setmode(); note: still some unknown arguments!
  40. vortex_adbdma_startfifo();
  41. vortex_adbdma_stopfifo();
  42. vortex_fifo_setadbctrl(); note: still some unknown arguments!
  43. vortex_mix_setinputvolumebyte();
  44. vortex_mix_enableinput();
  45. vortex_mixer_addWTD(); (fixed)
  46. vortex_connection_adbdma_src_src();
  47. vortex_connection_adbdma_src();
  48. vortex_src_change_convratio();
  49. vortex_src_addWTD(); (fixed)
  50. History:
  51. 01-03-2003 First revision.
  52. 01-21-2003 Some bug fixes.
  53. 17-02-2003 many bugfixes after a big versioning mess.
  54. 18-02-2003 JAAAAAHHHUUUUUU!!!! The mixer works !! I'm just so happy !
  55. (2 hours later...) I cant believe it! Im really lucky today.
  56. Now the SRC is working too! Yeah! XMMS works !
  57. 20-02-2003 First steps into the ALSA world.
  58. 28-02-2003 As my birthday present, i discovered how the DMA buffer pages really
  59. work :-). It was all wrong.
  60. 12-03-2003 ALSA driver starts working (2 channels).
  61. 16-03-2003 More srcblock_setupchannel discoveries.
  62. 12-04-2003 AU8830 playback support. Recording in the works.
  63. 17-04-2003 vortex_route() and vortex_routes() bug fixes. AU8830 recording
  64. works now, but chipn' dale effect is still there.
  65. 16-05-2003 SrcSetupChannel cleanup. Moved the Src setup stuff entirely
  66. into au88x0_pcm.c .
  67. 06-06-2003 Buffer shifter bugfix. Mixer volume fix.
  68. 07-12-2003 A3D routing finally fixed. Believed to be OK.
  69. 25-03-2004 Many thanks to Claudia, for such valuable bug reports.
  70. */
  71. #include "au88x0.h"
  72. #include "au88x0_a3d.h"
  73. #include <linux/delay.h>
  74. /* MIXER (CAsp4Mix.s and CAsp4Mixer.s) */
  75. // FIXME: get rid of this.
  76. static int mchannels[NR_MIXIN];
  77. static int rampchs[NR_MIXIN];
  78. static void vortex_mixer_en_sr(vortex_t * vortex, int channel)
  79. {
  80. hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  81. hwread(vortex->mmio, VORTEX_MIXER_SR) | (0x1 << channel));
  82. }
  83. static void vortex_mixer_dis_sr(vortex_t * vortex, int channel)
  84. {
  85. hwwrite(vortex->mmio, VORTEX_MIXER_SR,
  86. hwread(vortex->mmio, VORTEX_MIXER_SR) & ~(0x1 << channel));
  87. }
  88. #if 0
  89. static void
  90. vortex_mix_muteinputgain(vortex_t * vortex, unsigned char mix,
  91. unsigned char channel)
  92. {
  93. hwwrite(vortex->mmio, VORTEX_MIX_INVOL_A + ((mix << 5) + channel),
  94. 0x80);
  95. hwwrite(vortex->mmio, VORTEX_MIX_INVOL_B + ((mix << 5) + channel),
  96. 0x80);
  97. }
  98. static int vortex_mix_getvolume(vortex_t * vortex, unsigned char mix)
  99. {
  100. int a;
  101. a = hwread(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2)) & 0xff;
  102. //FP2LinearFrac(a);
  103. return (a);
  104. }
  105. static int
  106. vortex_mix_getinputvolume(vortex_t * vortex, unsigned char mix,
  107. int channel, int *vol)
  108. {
  109. int a;
  110. if (!(mchannels[mix] & (1 << channel)))
  111. return 0;
  112. a = hwread(vortex->mmio,
  113. VORTEX_MIX_INVOL_A + (((mix << 5) + channel) << 2));
  114. /*
  115. if (rampchs[mix] == 0)
  116. a = FP2LinearFrac(a);
  117. else
  118. a = FP2LinearFracWT(a);
  119. */
  120. *vol = a;
  121. return (0);
  122. }
  123. static unsigned int vortex_mix_boost6db(unsigned char vol)
  124. {
  125. return (vol + 8); /* WOW! what a complex function! */
  126. }
  127. static void vortex_mix_rampvolume(vortex_t * vortex, int mix)
  128. {
  129. int ch;
  130. char a;
  131. // This function is intended for ramping down only (see vortex_disableinput()).
  132. for (ch = 0; ch < 0x20; ch++) {
  133. if (((1 << ch) & rampchs[mix]) == 0)
  134. continue;
  135. a = hwread(vortex->mmio,
  136. VORTEX_MIX_INVOL_B + (((mix << 5) + ch) << 2));
  137. if (a > -126) {
  138. a -= 2;
  139. hwwrite(vortex->mmio,
  140. VORTEX_MIX_INVOL_A +
  141. (((mix << 5) + ch) << 2), a);
  142. hwwrite(vortex->mmio,
  143. VORTEX_MIX_INVOL_B +
  144. (((mix << 5) + ch) << 2), a);
  145. } else
  146. vortex_mix_killinput(vortex, mix, ch);
  147. }
  148. }
  149. static int
  150. vortex_mix_getenablebit(vortex_t * vortex, unsigned char mix, int mixin)
  151. {
  152. int addr, temp;
  153. if (mixin >= 0)
  154. addr = mixin;
  155. else
  156. addr = mixin + 3;
  157. addr = ((mix << 3) + (addr >> 2)) << 2;
  158. temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
  159. return ((temp >> (mixin & 3)) & 1);
  160. }
  161. #endif
  162. static void
  163. vortex_mix_setvolumebyte(vortex_t * vortex, unsigned char mix,
  164. unsigned char vol)
  165. {
  166. int temp;
  167. hwwrite(vortex->mmio, VORTEX_MIX_VOL_A + (mix << 2), vol);
  168. if (1) { /*if (this_10) */
  169. temp = hwread(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2));
  170. if ((temp != 0x80) || (vol == 0x80))
  171. return;
  172. }
  173. hwwrite(vortex->mmio, VORTEX_MIX_VOL_B + (mix << 2), vol);
  174. }
  175. static void
  176. vortex_mix_setinputvolumebyte(vortex_t * vortex, unsigned char mix,
  177. int mixin, unsigned char vol)
  178. {
  179. int temp;
  180. hwwrite(vortex->mmio,
  181. VORTEX_MIX_INVOL_A + (((mix << 5) + mixin) << 2), vol);
  182. if (1) { /* this_10, initialized to 1. */
  183. temp =
  184. hwread(vortex->mmio,
  185. VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2));
  186. if ((temp != 0x80) || (vol == 0x80))
  187. return;
  188. }
  189. hwwrite(vortex->mmio,
  190. VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), vol);
  191. }
  192. static void
  193. vortex_mix_setenablebit(vortex_t * vortex, unsigned char mix, int mixin, int en)
  194. {
  195. int temp, addr;
  196. if (mixin < 0)
  197. addr = (mixin + 3);
  198. else
  199. addr = mixin;
  200. addr = ((mix << 3) + (addr >> 2)) << 2;
  201. temp = hwread(vortex->mmio, VORTEX_MIX_ENIN + addr);
  202. if (en)
  203. temp |= (1 << (mixin & 3));
  204. else
  205. temp &= ~(1 << (mixin & 3));
  206. /* Mute input. Astatic void crackling? */
  207. hwwrite(vortex->mmio,
  208. VORTEX_MIX_INVOL_B + (((mix << 5) + mixin) << 2), 0x80);
  209. /* Looks like clear buffer. */
  210. hwwrite(vortex->mmio, VORTEX_MIX_SMP + (mixin << 2), 0x0);
  211. hwwrite(vortex->mmio, VORTEX_MIX_SMP + 4 + (mixin << 2), 0x0);
  212. /* Write enable bit. */
  213. hwwrite(vortex->mmio, VORTEX_MIX_ENIN + addr, temp);
  214. }
  215. static void
  216. vortex_mix_killinput(vortex_t * vortex, unsigned char mix, int mixin)
  217. {
  218. rampchs[mix] &= ~(1 << mixin);
  219. vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80);
  220. mchannels[mix] &= ~(1 << mixin);
  221. vortex_mix_setenablebit(vortex, mix, mixin, 0);
  222. }
  223. static void
  224. vortex_mix_enableinput(vortex_t * vortex, unsigned char mix, int mixin)
  225. {
  226. vortex_mix_killinput(vortex, mix, mixin);
  227. if ((mchannels[mix] & (1 << mixin)) == 0) {
  228. vortex_mix_setinputvolumebyte(vortex, mix, mixin, 0x80); /*0x80 : mute */
  229. mchannels[mix] |= (1 << mixin);
  230. }
  231. vortex_mix_setenablebit(vortex, mix, mixin, 1);
  232. }
  233. static void
  234. vortex_mix_disableinput(vortex_t * vortex, unsigned char mix, int channel,
  235. int ramp)
  236. {
  237. if (ramp) {
  238. rampchs[mix] |= (1 << channel);
  239. // Register callback.
  240. //vortex_mix_startrampvolume(vortex);
  241. vortex_mix_killinput(vortex, mix, channel);
  242. } else
  243. vortex_mix_killinput(vortex, mix, channel);
  244. }
  245. static int
  246. vortex_mixer_addWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
  247. {
  248. int temp, lifeboat = 0, prev;
  249. temp = hwread(vortex->mmio, VORTEX_MIXER_SR);
  250. if ((temp & (1 << ch)) == 0) {
  251. hwwrite(vortex->mmio, VORTEX_MIXER_CHNBASE + (ch << 2), mix);
  252. vortex_mixer_en_sr(vortex, ch);
  253. return 1;
  254. }
  255. prev = VORTEX_MIXER_CHNBASE + (ch << 2);
  256. temp = hwread(vortex->mmio, prev);
  257. while (temp & 0x10) {
  258. prev = VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2);
  259. temp = hwread(vortex->mmio, prev);
  260. //printk(KERN_INFO "vortex: mixAddWTD: while addr=%x, val=%x\n", prev, temp);
  261. if ((++lifeboat) > 0xf) {
  262. printk(KERN_ERR
  263. "vortex_mixer_addWTD: lifeboat overflow\n");
  264. return 0;
  265. }
  266. }
  267. hwwrite(vortex->mmio, VORTEX_MIXER_RTBASE + ((temp & 0xf) << 2), mix);
  268. hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
  269. return 1;
  270. }
  271. static int
  272. vortex_mixer_delWTD(vortex_t * vortex, unsigned char mix, unsigned char ch)
  273. {
  274. int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
  275. //int esp1f=edi(while)=src, esp10=ch;
  276. eax = hwread(vortex->mmio, VORTEX_MIXER_SR);
  277. if (((1 << ch) & eax) == 0) {
  278. printk(KERN_ERR "mix ALARM %x\n", eax);
  279. return 0;
  280. }
  281. ebp = VORTEX_MIXER_CHNBASE + (ch << 2);
  282. esp18 = hwread(vortex->mmio, ebp);
  283. if (esp18 & 0x10) {
  284. ebx = (esp18 & 0xf);
  285. if (mix == ebx) {
  286. ebx = VORTEX_MIXER_RTBASE + (mix << 2);
  287. edx = hwread(vortex->mmio, ebx);
  288. //7b60
  289. hwwrite(vortex->mmio, ebp, edx);
  290. hwwrite(vortex->mmio, ebx, 0);
  291. } else {
  292. //7ad3
  293. edx =
  294. hwread(vortex->mmio,
  295. VORTEX_MIXER_RTBASE + (ebx << 2));
  296. //printk(KERN_INFO "vortex: mixdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
  297. while ((edx & 0xf) != mix) {
  298. if ((esi) > 0xf) {
  299. printk(KERN_ERR
  300. "vortex: mixdelWTD: error lifeboat overflow\n");
  301. return 0;
  302. }
  303. esp14 = ebx;
  304. ebx = edx & 0xf;
  305. ebp = ebx << 2;
  306. edx =
  307. hwread(vortex->mmio,
  308. VORTEX_MIXER_RTBASE + ebp);
  309. //printk(KERN_INFO "vortex: mixdelWTD: while addr=%x, val=%x\n", ebp, edx);
  310. esi++;
  311. }
  312. //7b30
  313. ebp = ebx << 2;
  314. if (edx & 0x10) { /* Delete entry in between others */
  315. ebx = VORTEX_MIXER_RTBASE + ((edx & 0xf) << 2);
  316. edx = hwread(vortex->mmio, ebx);
  317. //7b60
  318. hwwrite(vortex->mmio,
  319. VORTEX_MIXER_RTBASE + ebp, edx);
  320. hwwrite(vortex->mmio, ebx, 0);
  321. //printk(KERN_INFO "vortex mixdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
  322. } else { /* Delete last entry */
  323. //7b83
  324. if (esp14 == -1)
  325. hwwrite(vortex->mmio,
  326. VORTEX_MIXER_CHNBASE +
  327. (ch << 2), esp18 & 0xef);
  328. else {
  329. ebx = (0xffffffe0 & edx) | (0xf & ebx);
  330. hwwrite(vortex->mmio,
  331. VORTEX_MIXER_RTBASE +
  332. (esp14 << 2), ebx);
  333. //printk(KERN_INFO "vortex mixdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
  334. }
  335. hwwrite(vortex->mmio,
  336. VORTEX_MIXER_RTBASE + ebp, 0);
  337. return 1;
  338. }
  339. }
  340. } else {
  341. //printk(KERN_INFO "removed last mix\n");
  342. //7be0
  343. vortex_mixer_dis_sr(vortex, ch);
  344. hwwrite(vortex->mmio, ebp, 0);
  345. }
  346. return 1;
  347. }
  348. static void vortex_mixer_init(vortex_t * vortex)
  349. {
  350. u32 addr;
  351. int x;
  352. // FIXME: get rid of this crap.
  353. memset(mchannels, 0, NR_MIXOUT * sizeof(int));
  354. memset(rampchs, 0, NR_MIXOUT * sizeof(int));
  355. addr = VORTEX_MIX_SMP + 0x17c;
  356. for (x = 0x5f; x >= 0; x--) {
  357. hwwrite(vortex->mmio, addr, 0);
  358. addr -= 4;
  359. }
  360. addr = VORTEX_MIX_ENIN + 0x1fc;
  361. for (x = 0x7f; x >= 0; x--) {
  362. hwwrite(vortex->mmio, addr, 0);
  363. addr -= 4;
  364. }
  365. addr = VORTEX_MIX_SMP + 0x17c;
  366. for (x = 0x5f; x >= 0; x--) {
  367. hwwrite(vortex->mmio, addr, 0);
  368. addr -= 4;
  369. }
  370. addr = VORTEX_MIX_INVOL_A + 0x7fc;
  371. for (x = 0x1ff; x >= 0; x--) {
  372. hwwrite(vortex->mmio, addr, 0x80);
  373. addr -= 4;
  374. }
  375. addr = VORTEX_MIX_VOL_A + 0x3c;
  376. for (x = 0xf; x >= 0; x--) {
  377. hwwrite(vortex->mmio, addr, 0x80);
  378. addr -= 4;
  379. }
  380. addr = VORTEX_MIX_INVOL_B + 0x7fc;
  381. for (x = 0x1ff; x >= 0; x--) {
  382. hwwrite(vortex->mmio, addr, 0x80);
  383. addr -= 4;
  384. }
  385. addr = VORTEX_MIX_VOL_B + 0x3c;
  386. for (x = 0xf; x >= 0; x--) {
  387. hwwrite(vortex->mmio, addr, 0x80);
  388. addr -= 4;
  389. }
  390. addr = VORTEX_MIXER_RTBASE + (MIXER_RTBASE_SIZE - 1) * 4;
  391. for (x = (MIXER_RTBASE_SIZE - 1); x >= 0; x--) {
  392. hwwrite(vortex->mmio, addr, 0x0);
  393. addr -= 4;
  394. }
  395. hwwrite(vortex->mmio, VORTEX_MIXER_SR, 0);
  396. /* Set clipping ceiling (this may be all wrong). */
  397. /*
  398. for (x = 0; x > 0x80; x++) {
  399. hwwrite(vortex->mmio, VORTEX_MIXER_CLIP + (x << 2), 0x3ffff);
  400. }
  401. */
  402. /*
  403. call CAsp4Mix__Initialize_CAsp4HwIO____CAsp4Mixer____
  404. Register ISR callback for volume smooth fade out.
  405. Maybe this avoids clicks when press "stop" ?
  406. */
  407. }
  408. /* SRC (CAsp4Src.s and CAsp4SrcBlock) */
  409. static void vortex_src_en_sr(vortex_t * vortex, int channel)
  410. {
  411. hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
  412. hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) | (0x1 << channel));
  413. }
  414. static void vortex_src_dis_sr(vortex_t * vortex, int channel)
  415. {
  416. hwwrite(vortex->mmio, VORTEX_SRCBLOCK_SR,
  417. hwread(vortex->mmio, VORTEX_SRCBLOCK_SR) & ~(0x1 << channel));
  418. }
  419. static void vortex_src_flushbuffers(vortex_t * vortex, unsigned char src)
  420. {
  421. int i;
  422. for (i = 0x1f; i >= 0; i--)
  423. hwwrite(vortex->mmio,
  424. VORTEX_SRC_DATA0 + (src << 7) + (i << 2), 0);
  425. hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3), 0);
  426. hwwrite(vortex->mmio, VORTEX_SRC_DATA + (src << 3) + 4, 0);
  427. }
  428. static void vortex_src_cleardrift(vortex_t * vortex, unsigned char src)
  429. {
  430. hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
  431. hwwrite(vortex->mmio, VORTEX_SRC_DRIFT1 + (src << 2), 0);
  432. hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
  433. }
  434. static void
  435. vortex_src_set_throttlesource(vortex_t * vortex, unsigned char src, int en)
  436. {
  437. int temp;
  438. temp = hwread(vortex->mmio, VORTEX_SRC_SOURCE);
  439. if (en)
  440. temp |= 1 << src;
  441. else
  442. temp &= ~(1 << src);
  443. hwwrite(vortex->mmio, VORTEX_SRC_SOURCE, temp);
  444. }
  445. static int
  446. vortex_src_persist_convratio(vortex_t * vortex, unsigned char src, int ratio)
  447. {
  448. int temp, lifeboat = 0;
  449. do {
  450. hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), ratio);
  451. temp = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
  452. if ((++lifeboat) > 0x9) {
  453. printk(KERN_ERR "Vortex: Src cvr fail\n");
  454. break;
  455. }
  456. }
  457. while (temp != ratio);
  458. return temp;
  459. }
  460. #if 0
  461. static void vortex_src_slowlock(vortex_t * vortex, unsigned char src)
  462. {
  463. int temp;
  464. hwwrite(vortex->mmio, VORTEX_SRC_DRIFT2 + (src << 2), 1);
  465. hwwrite(vortex->mmio, VORTEX_SRC_DRIFT0 + (src << 2), 0);
  466. temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
  467. if (temp & 0x200)
  468. hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
  469. temp & ~0x200L);
  470. }
  471. static void
  472. vortex_src_change_convratio(vortex_t * vortex, unsigned char src, int ratio)
  473. {
  474. int temp, a;
  475. if ((ratio & 0x10000) && (ratio != 0x10000)) {
  476. if (ratio & 0x3fff)
  477. a = (0x11 - ((ratio >> 0xe) & 0x3)) - 1;
  478. else
  479. a = (0x11 - ((ratio >> 0xe) & 0x3)) - 2;
  480. } else
  481. a = 0xc;
  482. temp = hwread(vortex->mmio, VORTEX_SRC_U0 + (src << 2));
  483. if (((temp >> 4) & 0xf) != a)
  484. hwwrite(vortex->mmio, VORTEX_SRC_U0 + (src << 2),
  485. (temp & 0xf) | ((a & 0xf) << 4));
  486. vortex_src_persist_convratio(vortex, src, ratio);
  487. }
  488. static int
  489. vortex_src_checkratio(vortex_t * vortex, unsigned char src,
  490. unsigned int desired_ratio)
  491. {
  492. int hw_ratio, lifeboat = 0;
  493. hw_ratio = hwread(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2));
  494. while (hw_ratio != desired_ratio) {
  495. hwwrite(vortex->mmio, VORTEX_SRC_CONVRATIO + (src << 2), desired_ratio);
  496. if ((lifeboat++) > 15) {
  497. printk(KERN_ERR "Vortex: could not set src-%d from %d to %d\n",
  498. src, hw_ratio, desired_ratio);
  499. break;
  500. }
  501. }
  502. return hw_ratio;
  503. }
  504. #endif
  505. /*
  506. Objective: Set samplerate for given SRC module.
  507. Arguments:
  508. card: pointer to vortex_t strcut.
  509. src: Integer index of the SRC module.
  510. cr: Current sample rate conversion factor.
  511. b: unknown 16 bit value.
  512. sweep: Enable Samplerate fade from cr toward tr flag.
  513. dirplay: 1: playback, 0: recording.
  514. sl: Slow Lock flag.
  515. tr: Target samplerate conversion.
  516. thsource: Throttle source flag (no idea what that means).
  517. */
  518. static void vortex_src_setupchannel(vortex_t * card, unsigned char src,
  519. unsigned int cr, unsigned int b, int sweep, int d,
  520. int dirplay, int sl, unsigned int tr, int thsource)
  521. {
  522. // noplayback: d=2,4,7,0xa,0xb when using first 2 src's.
  523. // c: enables pitch sweep.
  524. // looks like g is c related. Maybe g is a sweep parameter ?
  525. // g = cvr
  526. // dirplay: 0 = recording, 1 = playback
  527. // d = src hw index.
  528. int esi, ebp = 0, esp10;
  529. vortex_src_flushbuffers(card, src);
  530. if (sweep) {
  531. if ((tr & 0x10000) && (tr != 0x10000)) {
  532. tr = 0;
  533. esi = 0x7;
  534. } else {
  535. if ((((short)tr) < 0) && (tr != 0x8000)) {
  536. tr = 0;
  537. esi = 0x8;
  538. } else {
  539. tr = 1;
  540. esi = 0xc;
  541. }
  542. }
  543. } else {
  544. if ((cr & 0x10000) && (cr != 0x10000)) {
  545. tr = 0; /*ebx = 0 */
  546. esi = 0x11 - ((cr >> 0xe) & 7);
  547. if (cr & 0x3fff)
  548. esi -= 1;
  549. else
  550. esi -= 2;
  551. } else {
  552. tr = 1;
  553. esi = 0xc;
  554. }
  555. }
  556. vortex_src_cleardrift(card, src);
  557. vortex_src_set_throttlesource(card, src, thsource);
  558. if ((dirplay == 0) && (sweep == 0)) {
  559. if (tr)
  560. esp10 = 0xf;
  561. else
  562. esp10 = 0xc;
  563. ebp = 0;
  564. } else {
  565. if (tr)
  566. ebp = 0xf;
  567. else
  568. ebp = 0xc;
  569. esp10 = 0;
  570. }
  571. hwwrite(card->mmio, VORTEX_SRC_U0 + (src << 2),
  572. (sl << 0x9) | (sweep << 0x8) | ((esi & 0xf) << 4) | d);
  573. /* 0xc0 esi=0xc c=f=0 d=0 */
  574. vortex_src_persist_convratio(card, src, cr);
  575. hwwrite(card->mmio, VORTEX_SRC_U1 + (src << 2), b & 0xffff);
  576. /* 0 b=0 */
  577. hwwrite(card->mmio, VORTEX_SRC_U2 + (src << 2),
  578. (tr << 0x11) | (dirplay << 0x10) | (ebp << 0x8) | esp10);
  579. /* 0x30f00 e=g=1 esp10=0 ebp=f */
  580. //printk(KERN_INFO "vortex: SRC %d, d=0x%x, esi=0x%x, esp10=0x%x, ebp=0x%x\n", src, d, esi, esp10, ebp);
  581. }
  582. static void vortex_srcblock_init(vortex_t * vortex)
  583. {
  584. u32 addr;
  585. int x;
  586. hwwrite(vortex->mmio, VORTEX_SRC_SOURCESIZE, 0x1ff);
  587. /*
  588. for (x=0; x<0x10; x++) {
  589. vortex_src_init(&vortex_src[x], x);
  590. }
  591. */
  592. //addr = 0xcc3c;
  593. //addr = 0x26c3c;
  594. addr = VORTEX_SRC_RTBASE + 0x3c;
  595. for (x = 0xf; x >= 0; x--) {
  596. hwwrite(vortex->mmio, addr, 0);
  597. addr -= 4;
  598. }
  599. //addr = 0xcc94;
  600. //addr = 0x26c94;
  601. addr = VORTEX_SRC_CHNBASE + 0x54;
  602. for (x = 0x15; x >= 0; x--) {
  603. hwwrite(vortex->mmio, addr, 0);
  604. addr -= 4;
  605. }
  606. }
  607. static int
  608. vortex_src_addWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
  609. {
  610. int temp, lifeboat = 0, prev;
  611. // esp13 = src
  612. temp = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
  613. if ((temp & (1 << ch)) == 0) {
  614. hwwrite(vortex->mmio, VORTEX_SRC_CHNBASE + (ch << 2), src);
  615. vortex_src_en_sr(vortex, ch);
  616. return 1;
  617. }
  618. prev = VORTEX_SRC_CHNBASE + (ch << 2); /*ebp */
  619. temp = hwread(vortex->mmio, prev);
  620. //while (temp & NR_SRC) {
  621. while (temp & 0x10) {
  622. prev = VORTEX_SRC_RTBASE + ((temp & 0xf) << 2); /*esp12 */
  623. //prev = VORTEX_SRC_RTBASE + ((temp & (NR_SRC-1)) << 2); /*esp12*/
  624. temp = hwread(vortex->mmio, prev);
  625. //printk(KERN_INFO "vortex: srcAddWTD: while addr=%x, val=%x\n", prev, temp);
  626. if ((++lifeboat) > 0xf) {
  627. printk(KERN_ERR
  628. "vortex_src_addWTD: lifeboat overflow\n");
  629. return 0;
  630. }
  631. }
  632. hwwrite(vortex->mmio, VORTEX_SRC_RTBASE + ((temp & 0xf) << 2), src);
  633. //hwwrite(vortex->mmio, prev, (temp & (NR_SRC-1)) | NR_SRC);
  634. hwwrite(vortex->mmio, prev, (temp & 0xf) | 0x10);
  635. return 1;
  636. }
  637. static int
  638. vortex_src_delWTD(vortex_t * vortex, unsigned char src, unsigned char ch)
  639. {
  640. int esp14 = -1, esp18, eax, ebx, edx, ebp, esi = 0;
  641. //int esp1f=edi(while)=src, esp10=ch;
  642. eax = hwread(vortex->mmio, VORTEX_SRCBLOCK_SR);
  643. if (((1 << ch) & eax) == 0) {
  644. printk(KERN_ERR "src alarm\n");
  645. return 0;
  646. }
  647. ebp = VORTEX_SRC_CHNBASE + (ch << 2);
  648. esp18 = hwread(vortex->mmio, ebp);
  649. if (esp18 & 0x10) {
  650. ebx = (esp18 & 0xf);
  651. if (src == ebx) {
  652. ebx = VORTEX_SRC_RTBASE + (src << 2);
  653. edx = hwread(vortex->mmio, ebx);
  654. //7b60
  655. hwwrite(vortex->mmio, ebp, edx);
  656. hwwrite(vortex->mmio, ebx, 0);
  657. } else {
  658. //7ad3
  659. edx =
  660. hwread(vortex->mmio,
  661. VORTEX_SRC_RTBASE + (ebx << 2));
  662. //printk(KERN_INFO "vortex: srcdelWTD: 1 addr=%x, val=%x, src=%x\n", ebx, edx, src);
  663. while ((edx & 0xf) != src) {
  664. if ((esi) > 0xf) {
  665. printk
  666. ("vortex: srcdelWTD: error, lifeboat overflow\n");
  667. return 0;
  668. }
  669. esp14 = ebx;
  670. ebx = edx & 0xf;
  671. ebp = ebx << 2;
  672. edx =
  673. hwread(vortex->mmio,
  674. VORTEX_SRC_RTBASE + ebp);
  675. //printk(KERN_INFO "vortex: srcdelWTD: while addr=%x, val=%x\n", ebp, edx);
  676. esi++;
  677. }
  678. //7b30
  679. ebp = ebx << 2;
  680. if (edx & 0x10) { /* Delete entry in between others */
  681. ebx = VORTEX_SRC_RTBASE + ((edx & 0xf) << 2);
  682. edx = hwread(vortex->mmio, ebx);
  683. //7b60
  684. hwwrite(vortex->mmio,
  685. VORTEX_SRC_RTBASE + ebp, edx);
  686. hwwrite(vortex->mmio, ebx, 0);
  687. //printk(KERN_INFO "vortex srcdelWTD between addr= 0x%x, val= 0x%x\n", ebp, edx);
  688. } else { /* Delete last entry */
  689. //7b83
  690. if (esp14 == -1)
  691. hwwrite(vortex->mmio,
  692. VORTEX_SRC_CHNBASE +
  693. (ch << 2), esp18 & 0xef);
  694. else {
  695. ebx = (0xffffffe0 & edx) | (0xf & ebx);
  696. hwwrite(vortex->mmio,
  697. VORTEX_SRC_RTBASE +
  698. (esp14 << 2), ebx);
  699. //printk(KERN_INFO"vortex srcdelWTD last addr= 0x%x, val= 0x%x\n", esp14, ebx);
  700. }
  701. hwwrite(vortex->mmio,
  702. VORTEX_SRC_RTBASE + ebp, 0);
  703. return 1;
  704. }
  705. }
  706. } else {
  707. //7be0
  708. vortex_src_dis_sr(vortex, ch);
  709. hwwrite(vortex->mmio, ebp, 0);
  710. }
  711. return 1;
  712. }
  713. /*FIFO*/
  714. static void
  715. vortex_fifo_clearadbdata(vortex_t * vortex, int fifo, int x)
  716. {
  717. for (x--; x >= 0; x--)
  718. hwwrite(vortex->mmio,
  719. VORTEX_FIFO_ADBDATA +
  720. (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
  721. }
  722. #if 0
  723. static void vortex_fifo_adbinitialize(vortex_t * vortex, int fifo, int j)
  724. {
  725. vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
  726. #ifdef CHIP_AU8820
  727. hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
  728. (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
  729. #else
  730. hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
  731. (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
  732. #endif
  733. }
  734. #endif
  735. static void vortex_fifo_setadbvalid(vortex_t * vortex, int fifo, int en)
  736. {
  737. hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2),
  738. (hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2)) &
  739. 0xffffffef) | ((1 & en) << 4) | FIFO_U1);
  740. }
  741. static void
  742. vortex_fifo_setadbctrl(vortex_t * vortex, int fifo, int b, int priority,
  743. int empty, int valid, int f)
  744. {
  745. int temp, lifeboat = 0;
  746. //int this_8[NR_ADB] = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0}; /* position */
  747. int this_4 = 0x2;
  748. /* f seems priority related.
  749. * CAsp4AdbDma::SetPriority is the only place that calls SetAdbCtrl with f set to 1
  750. * every where else it is set to 0. It seems, however, that CAsp4AdbDma::SetPriority
  751. * is never called, thus the f related bits remain a mystery for now.
  752. */
  753. do {
  754. temp = hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
  755. if (lifeboat++ > 0xbb8) {
  756. printk(KERN_ERR
  757. "Vortex: vortex_fifo_setadbctrl fail\n");
  758. break;
  759. }
  760. }
  761. while (temp & FIFO_RDONLY);
  762. // AU8830 semes to take some special care about fifo content (data).
  763. // But i'm just to lazy to translate that :)
  764. if (valid) {
  765. if ((temp & FIFO_VALID) == 0) {
  766. //this_8[fifo] = 0;
  767. vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE); // this_4
  768. #ifdef CHIP_AU8820
  769. temp = (this_4 & 0x1f) << 0xb;
  770. #else
  771. temp = (this_4 & 0x3f) << 0xc;
  772. #endif
  773. temp = (temp & 0xfffffffd) | ((b & 1) << 1);
  774. temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
  775. temp = (temp & 0xffffffef) | ((valid & 1) << 4);
  776. temp |= FIFO_U1;
  777. temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
  778. #ifdef CHIP_AU8820
  779. temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
  780. #endif
  781. #ifdef CHIP_AU8830
  782. temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
  783. temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
  784. #endif
  785. #ifdef CHIP_AU8810
  786. temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
  787. temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
  788. #endif
  789. }
  790. } else {
  791. if (temp & FIFO_VALID) {
  792. #ifdef CHIP_AU8820
  793. temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
  794. #endif
  795. #ifdef CHIP_AU8830
  796. temp =
  797. ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
  798. #endif
  799. #ifdef CHIP_AU8810
  800. temp =
  801. ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
  802. #endif
  803. } else
  804. /*if (this_8[fifo]) */
  805. vortex_fifo_clearadbdata(vortex, fifo, FIFO_SIZE);
  806. }
  807. hwwrite(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2), temp);
  808. hwread(vortex->mmio, VORTEX_FIFO_ADBCTRL + (fifo << 2));
  809. }
  810. #ifndef CHIP_AU8810
  811. static void vortex_fifo_clearwtdata(vortex_t * vortex, int fifo, int x)
  812. {
  813. if (x < 1)
  814. return;
  815. for (x--; x >= 0; x--)
  816. hwwrite(vortex->mmio,
  817. VORTEX_FIFO_WTDATA +
  818. (((fifo << FIFO_SIZE_BITS) + x) << 2), 0);
  819. }
  820. static void vortex_fifo_wtinitialize(vortex_t * vortex, int fifo, int j)
  821. {
  822. vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
  823. #ifdef CHIP_AU8820
  824. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
  825. (FIFO_U1 | ((j & FIFO_MASK) << 0xb)));
  826. #else
  827. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
  828. (FIFO_U1 | ((j & FIFO_MASK) << 0xc)));
  829. #endif
  830. }
  831. static void vortex_fifo_setwtvalid(vortex_t * vortex, int fifo, int en)
  832. {
  833. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2),
  834. (hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2)) &
  835. 0xffffffef) | ((en & 1) << 4) | FIFO_U1);
  836. }
  837. static void
  838. vortex_fifo_setwtctrl(vortex_t * vortex, int fifo, int ctrl, int priority,
  839. int empty, int valid, int f)
  840. {
  841. int temp = 0, lifeboat = 0;
  842. int this_4 = 2;
  843. do {
  844. temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
  845. if (lifeboat++ > 0xbb8) {
  846. printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail\n");
  847. break;
  848. }
  849. }
  850. while (temp & FIFO_RDONLY);
  851. if (valid) {
  852. if ((temp & FIFO_VALID) == 0) {
  853. vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE); // this_4
  854. #ifdef CHIP_AU8820
  855. temp = (this_4 & 0x1f) << 0xb;
  856. #else
  857. temp = (this_4 & 0x3f) << 0xc;
  858. #endif
  859. temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
  860. temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
  861. temp = (temp & 0xffffffef) | ((valid & 1) << 4);
  862. temp |= FIFO_U1;
  863. temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
  864. #ifdef CHIP_AU8820
  865. temp = (temp & 0xfffbffff) | ((f & 1) << 0x12);
  866. #endif
  867. #ifdef CHIP_AU8830
  868. temp = (temp & 0xf7ffffff) | ((f & 1) << 0x1b);
  869. temp = (temp & 0xefffffff) | ((f & 1) << 0x1c);
  870. #endif
  871. #ifdef CHIP_AU8810
  872. temp = (temp & 0xfeffffff) | ((f & 1) << 0x18);
  873. temp = (temp & 0xfdffffff) | ((f & 1) << 0x19);
  874. #endif
  875. }
  876. } else {
  877. if (temp & FIFO_VALID) {
  878. #ifdef CHIP_AU8820
  879. temp = ((f & 1) << 0x12) | (temp & 0xfffbffef);
  880. #endif
  881. #ifdef CHIP_AU8830
  882. temp =
  883. ((f & 1) << 0x1b) | (temp & 0xe7ffffef) | FIFO_BITS;
  884. #endif
  885. #ifdef CHIP_AU8810
  886. temp =
  887. ((f & 1) << 0x18) | (temp & 0xfcffffef) | FIFO_BITS;
  888. #endif
  889. } else
  890. /*if (this_8[fifo]) */
  891. vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
  892. }
  893. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
  894. hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
  895. /*
  896. do {
  897. temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
  898. if (lifeboat++ > 0xbb8) {
  899. printk(KERN_ERR "Vortex: vortex_fifo_setwtctrl fail (hanging)\n");
  900. break;
  901. }
  902. } while ((temp & FIFO_RDONLY)&&(temp & FIFO_VALID)&&(temp != 0xFFFFFFFF));
  903. if (valid) {
  904. if (temp & FIFO_VALID) {
  905. temp = 0x40000;
  906. //temp |= 0x08000000;
  907. //temp |= 0x10000000;
  908. //temp |= 0x04000000;
  909. //temp |= 0x00400000;
  910. temp |= 0x1c400000;
  911. temp &= 0xFFFFFFF3;
  912. temp &= 0xFFFFFFEF;
  913. temp |= (valid & 1) << 4;
  914. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
  915. return;
  916. } else {
  917. vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
  918. return;
  919. }
  920. } else {
  921. temp &= 0xffffffef;
  922. temp |= 0x08000000;
  923. temp |= 0x10000000;
  924. temp |= 0x04000000;
  925. temp |= 0x00400000;
  926. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
  927. temp = hwread(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2));
  928. //((temp >> 6) & 0x3f)
  929. priority = 0;
  930. if (((temp & 0x0fc0) ^ ((temp >> 6) & 0x0fc0)) & 0FFFFFFC0)
  931. vortex_fifo_clearwtdata(vortex, fifo, FIFO_SIZE);
  932. valid = 0xfb;
  933. temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
  934. temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
  935. temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
  936. temp = (temp & 0xffffffef) | ((valid & 1) << 4);
  937. temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
  938. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
  939. }
  940. */
  941. /*
  942. temp = (temp & 0xfffffffd) | ((ctrl & 1) << 1);
  943. temp = (temp & 0xfffdffff) | ((f & 1) << 0x11);
  944. temp = (temp & 0xfffffff3) | ((priority & 3) << 2);
  945. temp = (temp & 0xffffffef) | ((valid & 1) << 4);
  946. temp = (temp & 0xffffffdf) | ((empty & 1) << 5);
  947. #ifdef FIFO_BITS
  948. temp = temp | FIFO_BITS | 40000;
  949. #endif
  950. // 0x1c440010, 0x1c400000
  951. hwwrite(vortex->mmio, VORTEX_FIFO_WTCTRL + (fifo << 2), temp);
  952. */
  953. }
  954. #endif
  955. static void vortex_fifo_init(vortex_t * vortex)
  956. {
  957. int x;
  958. u32 addr;
  959. /* ADB DMA channels fifos. */
  960. addr = VORTEX_FIFO_ADBCTRL + ((NR_ADB - 1) * 4);
  961. for (x = NR_ADB - 1; x >= 0; x--) {
  962. hwwrite(vortex->mmio, addr, (FIFO_U0 | FIFO_U1));
  963. if (hwread(vortex->mmio, addr) != (FIFO_U0 | FIFO_U1))
  964. printk(KERN_ERR "bad adb fifo reset!");
  965. vortex_fifo_clearadbdata(vortex, x, FIFO_SIZE);
  966. addr -= 4;
  967. }
  968. #ifndef CHIP_AU8810
  969. /* WT DMA channels fifos. */
  970. addr = VORTEX_FIFO_WTCTRL + ((NR_WT - 1) * 4);
  971. for (x = NR_WT - 1; x >= 0; x--) {
  972. hwwrite(vortex->mmio, addr, FIFO_U0);
  973. if (hwread(vortex->mmio, addr) != FIFO_U0)
  974. printk(KERN_ERR
  975. "bad wt fifo reset (0x%08x, 0x%08x)!\n",
  976. addr, hwread(vortex->mmio, addr));
  977. vortex_fifo_clearwtdata(vortex, x, FIFO_SIZE);
  978. addr -= 4;
  979. }
  980. #endif
  981. /* trigger... */
  982. #ifdef CHIP_AU8820
  983. hwwrite(vortex->mmio, 0xf8c0, 0xd03); //0x0843 0xd6b
  984. #else
  985. #ifdef CHIP_AU8830
  986. hwwrite(vortex->mmio, 0x17000, 0x61); /* wt a */
  987. hwwrite(vortex->mmio, 0x17004, 0x61); /* wt b */
  988. #endif
  989. hwwrite(vortex->mmio, 0x17008, 0x61); /* adb */
  990. #endif
  991. }
  992. /* ADBDMA */
  993. static void vortex_adbdma_init(vortex_t * vortex)
  994. {
  995. }
  996. static void vortex_adbdma_setfirstbuffer(vortex_t * vortex, int adbdma)
  997. {
  998. stream_t *dma = &vortex->dma_adb[adbdma];
  999. hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
  1000. dma->dma_ctrl);
  1001. }
  1002. static void vortex_adbdma_setstartbuffer(vortex_t * vortex, int adbdma, int sb)
  1003. {
  1004. stream_t *dma = &vortex->dma_adb[adbdma];
  1005. //hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2), sb << (((NR_ADB-1)-((adbdma&0xf)*2))));
  1006. hwwrite(vortex->mmio, VORTEX_ADBDMA_START + (adbdma << 2),
  1007. sb << ((0xf - (adbdma & 0xf)) * 2));
  1008. dma->period_real = dma->period_virt = sb;
  1009. }
  1010. static void
  1011. vortex_adbdma_setbuffers(vortex_t * vortex, int adbdma,
  1012. struct snd_sg_buf * sgbuf, int psize, int count)
  1013. {
  1014. stream_t *dma = &vortex->dma_adb[adbdma];
  1015. if (sgbuf == NULL) {
  1016. printk(KERN_INFO "vortex: FATAL: sgbuf is NULL!\n");
  1017. return;
  1018. }
  1019. //printk(KERN_INFO "vortex: page count = %d, tblcount = %d\n", count, sgbuf->tblsize);
  1020. dma->period_bytes = psize;
  1021. dma->nr_periods = count;
  1022. dma->sgbuf = sgbuf;
  1023. dma->cfg0 = 0;
  1024. dma->cfg1 = 0;
  1025. switch (count) {
  1026. /* Four or more pages */
  1027. default:
  1028. case 4:
  1029. dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize - 1);
  1030. hwwrite(vortex->mmio,
  1031. VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0xc,
  1032. snd_sgbuf_get_addr(sgbuf, psize * 3));
  1033. /* 3 pages */
  1034. case 3:
  1035. dma->cfg0 |= 0x12000000;
  1036. dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
  1037. hwwrite(vortex->mmio,
  1038. VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x8,
  1039. snd_sgbuf_get_addr(sgbuf, psize * 2));
  1040. /* 2 pages */
  1041. case 2:
  1042. dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize - 1);
  1043. hwwrite(vortex->mmio,
  1044. VORTEX_ADBDMA_BUFBASE + (adbdma << 4) + 0x4,
  1045. snd_sgbuf_get_addr(sgbuf, psize));
  1046. /* 1 page */
  1047. case 1:
  1048. dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize - 1) << 0xc);
  1049. hwwrite(vortex->mmio,
  1050. VORTEX_ADBDMA_BUFBASE + (adbdma << 4),
  1051. snd_sgbuf_get_addr(sgbuf, 0));
  1052. break;
  1053. }
  1054. //printk("vortex: cfg0 = 0x%x\nvortex: cfg1=0x%x\n", dma->cfg0, dma->cfg1);
  1055. hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG0 + (adbdma << 3), dma->cfg0);
  1056. hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFCFG1 + (adbdma << 3), dma->cfg1);
  1057. vortex_adbdma_setfirstbuffer(vortex, adbdma);
  1058. vortex_adbdma_setstartbuffer(vortex, adbdma, 0);
  1059. }
  1060. static void
  1061. vortex_adbdma_setmode(vortex_t * vortex, int adbdma, int ie, int dir,
  1062. int fmt, int d, u32 offset)
  1063. {
  1064. stream_t *dma = &vortex->dma_adb[adbdma];
  1065. dma->dma_unknown = d;
  1066. dma->dma_ctrl =
  1067. ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
  1068. /* Enable PCMOUT interrupts. */
  1069. dma->dma_ctrl =
  1070. (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
  1071. dma->dma_ctrl =
  1072. (dma->dma_ctrl & ~DIR_MASK) | ((dir << DIR_SHIFT) & DIR_MASK);
  1073. dma->dma_ctrl =
  1074. (dma->dma_ctrl & ~FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
  1075. hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
  1076. dma->dma_ctrl);
  1077. hwread(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2));
  1078. }
  1079. static int vortex_adbdma_bufshift(vortex_t * vortex, int adbdma)
  1080. {
  1081. stream_t *dma = &vortex->dma_adb[adbdma];
  1082. int page, p, pp, delta, i;
  1083. page =
  1084. (hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2)) &
  1085. ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
  1086. if (dma->nr_periods >= 4)
  1087. delta = (page - dma->period_real) & 3;
  1088. else {
  1089. delta = (page - dma->period_real);
  1090. if (delta < 0)
  1091. delta += dma->nr_periods;
  1092. }
  1093. if (delta == 0)
  1094. return 0;
  1095. /* refresh hw page table */
  1096. if (dma->nr_periods > 4) {
  1097. for (i = 0; i < delta; i++) {
  1098. /* p: audio buffer page index */
  1099. p = dma->period_virt + i + 4;
  1100. if (p >= dma->nr_periods)
  1101. p -= dma->nr_periods;
  1102. /* pp: hardware DMA page index. */
  1103. pp = dma->period_real + i;
  1104. if (pp >= 4)
  1105. pp -= 4;
  1106. //hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), dma->table[p].addr);
  1107. hwwrite(vortex->mmio,
  1108. VORTEX_ADBDMA_BUFBASE + (((adbdma << 2) + pp) << 2),
  1109. snd_sgbuf_get_addr(dma->sgbuf,
  1110. dma->period_bytes * p));
  1111. /* Force write thru cache. */
  1112. hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE +
  1113. (((adbdma << 2) + pp) << 2));
  1114. }
  1115. }
  1116. dma->period_virt += delta;
  1117. dma->period_real = page;
  1118. if (dma->period_virt >= dma->nr_periods)
  1119. dma->period_virt -= dma->nr_periods;
  1120. if (delta != 1)
  1121. printk(KERN_INFO "vortex: %d virt=%d, real=%d, delta=%d\n",
  1122. adbdma, dma->period_virt, dma->period_real, delta);
  1123. return delta;
  1124. }
  1125. static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) {
  1126. stream_t *dma = &vortex->dma_adb[adbdma];
  1127. int p, pp, i;
  1128. /* refresh hw page table */
  1129. for (i=0 ; i < 4 && i < dma->nr_periods; i++) {
  1130. /* p: audio buffer page index */
  1131. p = dma->period_virt + i;
  1132. if (p >= dma->nr_periods)
  1133. p -= dma->nr_periods;
  1134. /* pp: hardware DMA page index. */
  1135. pp = dma->period_real + i;
  1136. if (dma->nr_periods < 4) {
  1137. if (pp >= dma->nr_periods)
  1138. pp -= dma->nr_periods;
  1139. }
  1140. else {
  1141. if (pp >= 4)
  1142. pp -= 4;
  1143. }
  1144. hwwrite(vortex->mmio, VORTEX_ADBDMA_BUFBASE+(((adbdma << 2)+pp) << 2), snd_sgbuf_get_addr(dma->sgbuf, dma->period_bytes * p));
  1145. /* Force write thru cache. */
  1146. hwread(vortex->mmio, VORTEX_ADBDMA_BUFBASE + (((adbdma << 2)+pp) << 2));
  1147. }
  1148. }
  1149. static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
  1150. {
  1151. stream_t *dma = &vortex->dma_adb[adbdma];
  1152. int temp;
  1153. temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
  1154. temp = (dma->period_virt * dma->period_bytes) + (temp & POS_MASK);
  1155. return (temp);
  1156. }
  1157. static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
  1158. {
  1159. int this_8 = 0 /*empty */ , this_4 = 0 /*priority */ ;
  1160. stream_t *dma = &vortex->dma_adb[adbdma];
  1161. switch (dma->fifo_status) {
  1162. case FIFO_START:
  1163. vortex_fifo_setadbvalid(vortex, adbdma,
  1164. dma->fifo_enabled ? 1 : 0);
  1165. break;
  1166. case FIFO_STOP:
  1167. this_8 = 1;
  1168. hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
  1169. dma->dma_ctrl);
  1170. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1171. this_4, this_8,
  1172. dma->fifo_enabled ? 1 : 0, 0);
  1173. break;
  1174. case FIFO_PAUSE:
  1175. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1176. this_4, this_8,
  1177. dma->fifo_enabled ? 1 : 0, 0);
  1178. break;
  1179. }
  1180. dma->fifo_status = FIFO_START;
  1181. }
  1182. static void vortex_adbdma_resumefifo(vortex_t * vortex, int adbdma)
  1183. {
  1184. stream_t *dma = &vortex->dma_adb[adbdma];
  1185. int this_8 = 1, this_4 = 0;
  1186. switch (dma->fifo_status) {
  1187. case FIFO_STOP:
  1188. hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
  1189. dma->dma_ctrl);
  1190. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1191. this_4, this_8,
  1192. dma->fifo_enabled ? 1 : 0, 0);
  1193. break;
  1194. case FIFO_PAUSE:
  1195. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1196. this_4, this_8,
  1197. dma->fifo_enabled ? 1 : 0, 0);
  1198. break;
  1199. }
  1200. dma->fifo_status = FIFO_START;
  1201. }
  1202. static void vortex_adbdma_pausefifo(vortex_t * vortex, int adbdma)
  1203. {
  1204. stream_t *dma = &vortex->dma_adb[adbdma];
  1205. int this_8 = 0, this_4 = 0;
  1206. switch (dma->fifo_status) {
  1207. case FIFO_START:
  1208. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1209. this_4, this_8, 0, 0);
  1210. break;
  1211. case FIFO_STOP:
  1212. hwwrite(vortex->mmio, VORTEX_ADBDMA_CTRL + (adbdma << 2),
  1213. dma->dma_ctrl);
  1214. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1215. this_4, this_8, 0, 0);
  1216. break;
  1217. }
  1218. dma->fifo_status = FIFO_PAUSE;
  1219. }
  1220. #if 0 // Using pause instead
  1221. static void vortex_adbdma_stopfifo(vortex_t * vortex, int adbdma)
  1222. {
  1223. stream_t *dma = &vortex->dma_adb[adbdma];
  1224. int this_4 = 0, this_8 = 0;
  1225. if (dma->fifo_status == FIFO_START)
  1226. vortex_fifo_setadbctrl(vortex, adbdma, dma->dma_unknown,
  1227. this_4, this_8, 0, 0);
  1228. else if (dma->fifo_status == FIFO_STOP)
  1229. return;
  1230. dma->fifo_status = FIFO_STOP;
  1231. dma->fifo_enabled = 0;
  1232. }
  1233. #endif
  1234. /* WTDMA */
  1235. #ifndef CHIP_AU8810
  1236. static void vortex_wtdma_setfirstbuffer(vortex_t * vortex, int wtdma)
  1237. {
  1238. //int this_7c=dma_ctrl;
  1239. stream_t *dma = &vortex->dma_wt[wtdma];
  1240. hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
  1241. }
  1242. static void vortex_wtdma_setstartbuffer(vortex_t * vortex, int wtdma, int sb)
  1243. {
  1244. stream_t *dma = &vortex->dma_wt[wtdma];
  1245. //hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2), sb << ((0x1f-(wtdma&0xf)*2)));
  1246. hwwrite(vortex->mmio, VORTEX_WTDMA_START + (wtdma << 2),
  1247. sb << ((0xf - (wtdma & 0xf)) * 2));
  1248. dma->period_real = dma->period_virt = sb;
  1249. }
  1250. static void
  1251. vortex_wtdma_setbuffers(vortex_t * vortex, int wtdma,
  1252. struct snd_sg_buf * sgbuf, int psize, int count)
  1253. {
  1254. stream_t *dma = &vortex->dma_wt[wtdma];
  1255. dma->period_bytes = psize;
  1256. dma->nr_periods = count;
  1257. dma->sgbuf = sgbuf;
  1258. dma->cfg0 = 0;
  1259. dma->cfg1 = 0;
  1260. switch (count) {
  1261. /* Four or more pages */
  1262. default:
  1263. case 4:
  1264. dma->cfg1 |= 0x88000000 | 0x44000000 | 0x30000000 | (psize-1);
  1265. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0xc,
  1266. snd_sgbuf_get_addr(sgbuf, psize * 3));
  1267. /* 3 pages */
  1268. case 3:
  1269. dma->cfg0 |= 0x12000000;
  1270. dma->cfg1 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
  1271. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x8,
  1272. snd_sgbuf_get_addr(sgbuf, psize * 2));
  1273. /* 2 pages */
  1274. case 2:
  1275. dma->cfg0 |= 0x88000000 | 0x44000000 | 0x10000000 | (psize-1);
  1276. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4) + 0x4,
  1277. snd_sgbuf_get_addr(sgbuf, psize));
  1278. /* 1 page */
  1279. case 1:
  1280. dma->cfg0 |= 0x80000000 | 0x40000000 | ((psize-1) << 0xc);
  1281. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFBASE + (wtdma << 4),
  1282. snd_sgbuf_get_addr(sgbuf, 0));
  1283. break;
  1284. }
  1285. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG0 + (wtdma << 3), dma->cfg0);
  1286. hwwrite(vortex->mmio, VORTEX_WTDMA_BUFCFG1 + (wtdma << 3), dma->cfg1);
  1287. vortex_wtdma_setfirstbuffer(vortex, wtdma);
  1288. vortex_wtdma_setstartbuffer(vortex, wtdma, 0);
  1289. }
  1290. static void
  1291. vortex_wtdma_setmode(vortex_t * vortex, int wtdma, int ie, int fmt, int d,
  1292. /*int e, */ u32 offset)
  1293. {
  1294. stream_t *dma = &vortex->dma_wt[wtdma];
  1295. //dma->this_08 = e;
  1296. dma->dma_unknown = d;
  1297. dma->dma_ctrl = 0;
  1298. dma->dma_ctrl =
  1299. ((offset & OFFSET_MASK) | (dma->dma_ctrl & ~OFFSET_MASK));
  1300. /* PCMOUT interrupt */
  1301. dma->dma_ctrl =
  1302. (dma->dma_ctrl & ~IE_MASK) | ((ie << IE_SHIFT) & IE_MASK);
  1303. /* Always playback. */
  1304. dma->dma_ctrl |= (1 << DIR_SHIFT);
  1305. /* Audio Format */
  1306. dma->dma_ctrl =
  1307. (dma->dma_ctrl & FMT_MASK) | ((fmt << FMT_SHIFT) & FMT_MASK);
  1308. /* Write into hardware */
  1309. hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2), dma->dma_ctrl);
  1310. }
  1311. static int vortex_wtdma_bufshift(vortex_t * vortex, int wtdma)
  1312. {
  1313. stream_t *dma = &vortex->dma_wt[wtdma];
  1314. int page, p, pp, delta, i;
  1315. page =
  1316. (hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) &
  1317. WT_SUBBUF_MASK)
  1318. >> WT_SUBBUF_SHIFT;
  1319. if (dma->nr_periods >= 4)
  1320. delta = (page - dma->period_real) & 3;
  1321. else {
  1322. delta = (page - dma->period_real);
  1323. if (delta < 0)
  1324. delta += dma->nr_periods;
  1325. }
  1326. if (delta == 0)
  1327. return 0;
  1328. /* refresh hw page table */
  1329. if (dma->nr_periods > 4) {
  1330. for (i = 0; i < delta; i++) {
  1331. /* p: audio buffer page index */
  1332. p = dma->period_virt + i + 4;
  1333. if (p >= dma->nr_periods)
  1334. p -= dma->nr_periods;
  1335. /* pp: hardware DMA page index. */
  1336. pp = dma->period_real + i;
  1337. if (pp >= 4)
  1338. pp -= 4;
  1339. hwwrite(vortex->mmio,
  1340. VORTEX_WTDMA_BUFBASE +
  1341. (((wtdma << 2) + pp) << 2),
  1342. snd_sgbuf_get_addr(dma->sgbuf, dma->period_bytes * p));
  1343. /* Force write thru cache. */
  1344. hwread(vortex->mmio, VORTEX_WTDMA_BUFBASE +
  1345. (((wtdma << 2) + pp) << 2));
  1346. }
  1347. }
  1348. dma->period_virt += delta;
  1349. if (dma->period_virt >= dma->nr_periods)
  1350. dma->period_virt -= dma->nr_periods;
  1351. dma->period_real = page;
  1352. if (delta != 1)
  1353. printk(KERN_WARNING "vortex: wt virt = %d, delta = %d\n",
  1354. dma->period_virt, delta);
  1355. return delta;
  1356. }
  1357. #if 0
  1358. static void
  1359. vortex_wtdma_getposition(vortex_t * vortex, int wtdma, int *subbuf, int *pos)
  1360. {
  1361. int temp;
  1362. temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
  1363. *subbuf = (temp >> WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK;
  1364. *pos = temp & POS_MASK;
  1365. }
  1366. static int vortex_wtdma_getcursubuffer(vortex_t * vortex, int wtdma)
  1367. {
  1368. return ((hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2)) >>
  1369. POS_SHIFT) & POS_MASK);
  1370. }
  1371. #endif
  1372. static int inline vortex_wtdma_getlinearpos(vortex_t * vortex, int wtdma)
  1373. {
  1374. stream_t *dma = &vortex->dma_wt[wtdma];
  1375. int temp;
  1376. temp = hwread(vortex->mmio, VORTEX_WTDMA_STAT + (wtdma << 2));
  1377. //temp = (temp & POS_MASK) + (((temp>>WT_SUBBUF_SHIFT) & WT_SUBBUF_MASK)*(dma->cfg0&POS_MASK));
  1378. temp = (temp & POS_MASK) + ((dma->period_virt) * (dma->period_bytes));
  1379. return temp;
  1380. }
  1381. static void vortex_wtdma_startfifo(vortex_t * vortex, int wtdma)
  1382. {
  1383. stream_t *dma = &vortex->dma_wt[wtdma];
  1384. int this_8 = 0, this_4 = 0;
  1385. switch (dma->fifo_status) {
  1386. case FIFO_START:
  1387. vortex_fifo_setwtvalid(vortex, wtdma,
  1388. dma->fifo_enabled ? 1 : 0);
  1389. break;
  1390. case FIFO_STOP:
  1391. this_8 = 1;
  1392. hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
  1393. dma->dma_ctrl);
  1394. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1395. this_4, this_8,
  1396. dma->fifo_enabled ? 1 : 0, 0);
  1397. break;
  1398. case FIFO_PAUSE:
  1399. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1400. this_4, this_8,
  1401. dma->fifo_enabled ? 1 : 0, 0);
  1402. break;
  1403. }
  1404. dma->fifo_status = FIFO_START;
  1405. }
  1406. static void vortex_wtdma_resumefifo(vortex_t * vortex, int wtdma)
  1407. {
  1408. stream_t *dma = &vortex->dma_wt[wtdma];
  1409. int this_8 = 0, this_4 = 0;
  1410. switch (dma->fifo_status) {
  1411. case FIFO_STOP:
  1412. hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
  1413. dma->dma_ctrl);
  1414. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1415. this_4, this_8,
  1416. dma->fifo_enabled ? 1 : 0, 0);
  1417. break;
  1418. case FIFO_PAUSE:
  1419. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1420. this_4, this_8,
  1421. dma->fifo_enabled ? 1 : 0, 0);
  1422. break;
  1423. }
  1424. dma->fifo_status = FIFO_START;
  1425. }
  1426. static void vortex_wtdma_pausefifo(vortex_t * vortex, int wtdma)
  1427. {
  1428. stream_t *dma = &vortex->dma_wt[wtdma];
  1429. int this_8 = 0, this_4 = 0;
  1430. switch (dma->fifo_status) {
  1431. case FIFO_START:
  1432. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1433. this_4, this_8, 0, 0);
  1434. break;
  1435. case FIFO_STOP:
  1436. hwwrite(vortex->mmio, VORTEX_WTDMA_CTRL + (wtdma << 2),
  1437. dma->dma_ctrl);
  1438. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1439. this_4, this_8, 0, 0);
  1440. break;
  1441. }
  1442. dma->fifo_status = FIFO_PAUSE;
  1443. }
  1444. static void vortex_wtdma_stopfifo(vortex_t * vortex, int wtdma)
  1445. {
  1446. stream_t *dma = &vortex->dma_wt[wtdma];
  1447. int this_4 = 0, this_8 = 0;
  1448. if (dma->fifo_status == FIFO_START)
  1449. vortex_fifo_setwtctrl(vortex, wtdma, dma->dma_unknown,
  1450. this_4, this_8, 0, 0);
  1451. else if (dma->fifo_status == FIFO_STOP)
  1452. return;
  1453. dma->fifo_status = FIFO_STOP;
  1454. dma->fifo_enabled = 0;
  1455. }
  1456. #endif
  1457. /* ADB Routes */
  1458. typedef int ADBRamLink;
  1459. static void vortex_adb_init(vortex_t * vortex)
  1460. {
  1461. int i;
  1462. /* it looks like we are writing more than we need to...
  1463. * if we write what we are supposed to it breaks things... */
  1464. hwwrite(vortex->mmio, VORTEX_ADB_SR, 0);
  1465. for (i = 0; i < VORTEX_ADB_RTBASE_COUNT; i++)
  1466. hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (i << 2),
  1467. hwread(vortex->mmio,
  1468. VORTEX_ADB_RTBASE + (i << 2)) | ROUTE_MASK);
  1469. for (i = 0; i < VORTEX_ADB_CHNBASE_COUNT; i++) {
  1470. hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (i << 2),
  1471. hwread(vortex->mmio,
  1472. VORTEX_ADB_CHNBASE + (i << 2)) | ROUTE_MASK);
  1473. }
  1474. }
  1475. static void vortex_adb_en_sr(vortex_t * vortex, int channel)
  1476. {
  1477. hwwrite(vortex->mmio, VORTEX_ADB_SR,
  1478. hwread(vortex->mmio, VORTEX_ADB_SR) | (0x1 << channel));
  1479. }
  1480. static void vortex_adb_dis_sr(vortex_t * vortex, int channel)
  1481. {
  1482. hwwrite(vortex->mmio, VORTEX_ADB_SR,
  1483. hwread(vortex->mmio, VORTEX_ADB_SR) & ~(0x1 << channel));
  1484. }
  1485. static void
  1486. vortex_adb_addroutes(vortex_t * vortex, unsigned char channel,
  1487. ADBRamLink * route, int rnum)
  1488. {
  1489. int temp, prev, lifeboat = 0;
  1490. if ((rnum <= 0) || (route == NULL))
  1491. return;
  1492. /* Write last routes. */
  1493. rnum--;
  1494. hwwrite(vortex->mmio,
  1495. VORTEX_ADB_RTBASE + ((route[rnum] & ADB_MASK) << 2),
  1496. ROUTE_MASK);
  1497. while (rnum > 0) {
  1498. hwwrite(vortex->mmio,
  1499. VORTEX_ADB_RTBASE +
  1500. ((route[rnum - 1] & ADB_MASK) << 2), route[rnum]);
  1501. rnum--;
  1502. }
  1503. /* Write first route. */
  1504. temp =
  1505. hwread(vortex->mmio,
  1506. VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
  1507. if (temp == ADB_MASK) {
  1508. /* First entry on this channel. */
  1509. hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
  1510. route[0]);
  1511. vortex_adb_en_sr(vortex, channel);
  1512. return;
  1513. }
  1514. /* Not first entry on this channel. Need to link. */
  1515. do {
  1516. prev = temp;
  1517. temp =
  1518. hwread(vortex->mmio,
  1519. VORTEX_ADB_RTBASE + (temp << 2)) & ADB_MASK;
  1520. if ((lifeboat++) > ADB_MASK) {
  1521. printk(KERN_ERR
  1522. "vortex_adb_addroutes: unending route! 0x%x\n",
  1523. *route);
  1524. return;
  1525. }
  1526. }
  1527. while (temp != ADB_MASK);
  1528. hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), route[0]);
  1529. }
  1530. static void
  1531. vortex_adb_delroutes(vortex_t * vortex, unsigned char channel,
  1532. ADBRamLink route0, ADBRamLink route1)
  1533. {
  1534. int temp, lifeboat = 0, prev;
  1535. /* Find route. */
  1536. temp =
  1537. hwread(vortex->mmio,
  1538. VORTEX_ADB_CHNBASE + (channel << 2)) & ADB_MASK;
  1539. if (temp == (route0 & ADB_MASK)) {
  1540. temp =
  1541. hwread(vortex->mmio,
  1542. VORTEX_ADB_RTBASE + ((route1 & ADB_MASK) << 2));
  1543. if ((temp & ADB_MASK) == ADB_MASK)
  1544. vortex_adb_dis_sr(vortex, channel);
  1545. hwwrite(vortex->mmio, VORTEX_ADB_CHNBASE + (channel << 2),
  1546. temp);
  1547. return;
  1548. }
  1549. do {
  1550. prev = temp;
  1551. temp =
  1552. hwread(vortex->mmio,
  1553. VORTEX_ADB_RTBASE + (prev << 2)) & ADB_MASK;
  1554. if (((lifeboat++) > ADB_MASK) || (temp == ADB_MASK)) {
  1555. printk(KERN_ERR
  1556. "vortex_adb_delroutes: route not found! 0x%x\n",
  1557. route0);
  1558. return;
  1559. }
  1560. }
  1561. while (temp != (route0 & ADB_MASK));
  1562. temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
  1563. if ((temp & ADB_MASK) == route1)
  1564. temp = hwread(vortex->mmio, VORTEX_ADB_RTBASE + (temp << 2));
  1565. /* Make bridge over deleted route. */
  1566. hwwrite(vortex->mmio, VORTEX_ADB_RTBASE + (prev << 2), temp);
  1567. }
  1568. static void
  1569. vortex_route(vortex_t * vortex, int en, unsigned char channel,
  1570. unsigned char source, unsigned char dest)
  1571. {
  1572. ADBRamLink route;
  1573. route = ((source & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
  1574. if (en) {
  1575. vortex_adb_addroutes(vortex, channel, &route, 1);
  1576. if ((source < (OFFSET_SRCOUT + NR_SRC))
  1577. && (source >= OFFSET_SRCOUT))
  1578. vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
  1579. channel);
  1580. else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
  1581. && (source >= OFFSET_MIXOUT))
  1582. vortex_mixer_addWTD(vortex,
  1583. (source - OFFSET_MIXOUT), channel);
  1584. } else {
  1585. vortex_adb_delroutes(vortex, channel, route, route);
  1586. if ((source < (OFFSET_SRCOUT + NR_SRC))
  1587. && (source >= OFFSET_SRCOUT))
  1588. vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
  1589. channel);
  1590. else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
  1591. && (source >= OFFSET_MIXOUT))
  1592. vortex_mixer_delWTD(vortex,
  1593. (source - OFFSET_MIXOUT), channel);
  1594. }
  1595. }
  1596. #if 0
  1597. static void
  1598. vortex_routes(vortex_t * vortex, int en, unsigned char channel,
  1599. unsigned char source, unsigned char dest0, unsigned char dest1)
  1600. {
  1601. ADBRamLink route[2];
  1602. route[0] = ((source & ADB_MASK) << ADB_SHIFT) | (dest0 & ADB_MASK);
  1603. route[1] = ((source & ADB_MASK) << ADB_SHIFT) | (dest1 & ADB_MASK);
  1604. if (en) {
  1605. vortex_adb_addroutes(vortex, channel, route, 2);
  1606. if ((source < (OFFSET_SRCOUT + NR_SRC))
  1607. && (source >= (OFFSET_SRCOUT)))
  1608. vortex_src_addWTD(vortex, (source - OFFSET_SRCOUT),
  1609. channel);
  1610. else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
  1611. && (source >= (OFFSET_MIXOUT)))
  1612. vortex_mixer_addWTD(vortex,
  1613. (source - OFFSET_MIXOUT), channel);
  1614. } else {
  1615. vortex_adb_delroutes(vortex, channel, route[0], route[1]);
  1616. if ((source < (OFFSET_SRCOUT + NR_SRC))
  1617. && (source >= (OFFSET_SRCOUT)))
  1618. vortex_src_delWTD(vortex, (source - OFFSET_SRCOUT),
  1619. channel);
  1620. else if ((source < (OFFSET_MIXOUT + NR_MIXOUT))
  1621. && (source >= (OFFSET_MIXOUT)))
  1622. vortex_mixer_delWTD(vortex,
  1623. (source - OFFSET_MIXOUT), channel);
  1624. }
  1625. }
  1626. #endif
  1627. /* Route two sources to same target. Sources must be of same class !!! */
  1628. static void
  1629. vortex_routeLRT(vortex_t * vortex, int en, unsigned char ch,
  1630. unsigned char source0, unsigned char source1,
  1631. unsigned char dest)
  1632. {
  1633. ADBRamLink route[2];
  1634. route[0] = ((source0 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
  1635. route[1] = ((source1 & ADB_MASK) << ADB_SHIFT) | (dest & ADB_MASK);
  1636. if (dest < 0x10)
  1637. route[1] = (route[1] & ~ADB_MASK) | (dest + 0x20); /* fifo A */
  1638. if (en) {
  1639. vortex_adb_addroutes(vortex, ch, route, 2);
  1640. if ((source0 < (OFFSET_SRCOUT + NR_SRC))
  1641. && (source0 >= OFFSET_SRCOUT)) {
  1642. vortex_src_addWTD(vortex,
  1643. (source0 - OFFSET_SRCOUT), ch);
  1644. vortex_src_addWTD(vortex,
  1645. (source1 - OFFSET_SRCOUT), ch);
  1646. } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
  1647. && (source0 >= OFFSET_MIXOUT)) {
  1648. vortex_mixer_addWTD(vortex,
  1649. (source0 - OFFSET_MIXOUT), ch);
  1650. vortex_mixer_addWTD(vortex,
  1651. (source1 - OFFSET_MIXOUT), ch);
  1652. }
  1653. } else {
  1654. vortex_adb_delroutes(vortex, ch, route[0], route[1]);
  1655. if ((source0 < (OFFSET_SRCOUT + NR_SRC))
  1656. && (source0 >= OFFSET_SRCOUT)) {
  1657. vortex_src_delWTD(vortex,
  1658. (source0 - OFFSET_SRCOUT), ch);
  1659. vortex_src_delWTD(vortex,
  1660. (source1 - OFFSET_SRCOUT), ch);
  1661. } else if ((source0 < (OFFSET_MIXOUT + NR_MIXOUT))
  1662. && (source0 >= OFFSET_MIXOUT)) {
  1663. vortex_mixer_delWTD(vortex,
  1664. (source0 - OFFSET_MIXOUT), ch);
  1665. vortex_mixer_delWTD(vortex,
  1666. (source1 - OFFSET_MIXOUT), ch);
  1667. }
  1668. }
  1669. }
  1670. /* Connection stuff */
  1671. // Connect adbdma to src('s).
  1672. static void
  1673. vortex_connection_adbdma_src(vortex_t * vortex, int en, unsigned char ch,
  1674. unsigned char adbdma, unsigned char src)
  1675. {
  1676. vortex_route(vortex, en, ch, ADB_DMA(adbdma), ADB_SRCIN(src));
  1677. }
  1678. // Connect SRC to mixin.
  1679. static void
  1680. vortex_connection_src_mixin(vortex_t * vortex, int en,
  1681. unsigned char channel, unsigned char src,
  1682. unsigned char mixin)
  1683. {
  1684. vortex_route(vortex, en, channel, ADB_SRCOUT(src), ADB_MIXIN(mixin));
  1685. }
  1686. // Connect mixin with mix output.
  1687. static void
  1688. vortex_connection_mixin_mix(vortex_t * vortex, int en, unsigned char mixin,
  1689. unsigned char mix, int a)
  1690. {
  1691. if (en) {
  1692. vortex_mix_enableinput(vortex, mix, mixin);
  1693. vortex_mix_setinputvolumebyte(vortex, mix, mixin, MIX_DEFIGAIN); // added to original code.
  1694. } else
  1695. vortex_mix_disableinput(vortex, mix, mixin, a);
  1696. }
  1697. // Connect absolut address to mixin.
  1698. static void
  1699. vortex_connection_adb_mixin(vortex_t * vortex, int en,
  1700. unsigned char channel, unsigned char source,
  1701. unsigned char mixin)
  1702. {
  1703. vortex_route(vortex, en, channel, source, ADB_MIXIN(mixin));
  1704. }
  1705. static void
  1706. vortex_connection_src_adbdma(vortex_t * vortex, int en, unsigned char ch,
  1707. unsigned char src, unsigned char adbdma)
  1708. {
  1709. vortex_route(vortex, en, ch, ADB_SRCOUT(src), ADB_DMA(adbdma));
  1710. }
  1711. static void
  1712. vortex_connection_src_src_adbdma(vortex_t * vortex, int en,
  1713. unsigned char ch, unsigned char src0,
  1714. unsigned char src1, unsigned char adbdma)
  1715. {
  1716. vortex_routeLRT(vortex, en, ch, ADB_SRCOUT(src0), ADB_SRCOUT(src1),
  1717. ADB_DMA(adbdma));
  1718. }
  1719. // mix to absolut address.
  1720. static void
  1721. vortex_connection_mix_adb(vortex_t * vortex, int en, unsigned char ch,
  1722. unsigned char mix, unsigned char dest)
  1723. {
  1724. vortex_route(vortex, en, ch, ADB_MIXOUT(mix), dest);
  1725. vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
  1726. }
  1727. // mixer to src.
  1728. static void
  1729. vortex_connection_mix_src(vortex_t * vortex, int en, unsigned char ch,
  1730. unsigned char mix, unsigned char src)
  1731. {
  1732. vortex_route(vortex, en, ch, ADB_MIXOUT(mix), ADB_SRCIN(src));
  1733. vortex_mix_setvolumebyte(vortex, mix, MIX_DEFOGAIN); // added to original code.
  1734. }
  1735. #if 0
  1736. static void
  1737. vortex_connection_adbdma_src_src(vortex_t * vortex, int en,
  1738. unsigned char channel,
  1739. unsigned char adbdma, unsigned char src0,
  1740. unsigned char src1)
  1741. {
  1742. vortex_routes(vortex, en, channel, ADB_DMA(adbdma),
  1743. ADB_SRCIN(src0), ADB_SRCIN(src1));
  1744. }
  1745. // Connect two mix to AdbDma.
  1746. static void
  1747. vortex_connection_mix_mix_adbdma(vortex_t * vortex, int en,
  1748. unsigned char ch, unsigned char mix0,
  1749. unsigned char mix1, unsigned char adbdma)
  1750. {
  1751. ADBRamLink routes[2];
  1752. routes[0] =
  1753. (((mix0 +
  1754. OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | (adbdma & ADB_MASK);
  1755. routes[1] =
  1756. (((mix1 + OFFSET_MIXOUT) & ADB_MASK) << ADB_SHIFT) | ((adbdma +
  1757. 0x20) &
  1758. ADB_MASK);
  1759. if (en) {
  1760. vortex_adb_addroutes(vortex, ch, routes, 0x2);
  1761. vortex_mixer_addWTD(vortex, mix0, ch);
  1762. vortex_mixer_addWTD(vortex, mix1, ch);
  1763. } else {
  1764. vortex_adb_delroutes(vortex, ch, routes[0], routes[1]);
  1765. vortex_mixer_delWTD(vortex, mix0, ch);
  1766. vortex_mixer_delWTD(vortex, mix1, ch);
  1767. }
  1768. }
  1769. #endif
  1770. /* CODEC connect. */
  1771. static void
  1772. vortex_connect_codecplay(vortex_t * vortex, int en, unsigned char mixers[])
  1773. {
  1774. #ifdef CHIP_AU8820
  1775. vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
  1776. vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
  1777. #else
  1778. #if 1
  1779. // Connect front channels through EQ.
  1780. vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_EQIN(0));
  1781. vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_EQIN(1));
  1782. /* Lower volume, since EQ has some gain. */
  1783. vortex_mix_setvolumebyte(vortex, mixers[0], 0);
  1784. vortex_mix_setvolumebyte(vortex, mixers[1], 0);
  1785. vortex_route(vortex, en, 0x11, ADB_EQOUT(0), ADB_CODECOUT(0));
  1786. vortex_route(vortex, en, 0x11, ADB_EQOUT(1), ADB_CODECOUT(1));
  1787. /* Check if reg 0x28 has SDAC bit set. */
  1788. if (VORTEX_IS_QUAD(vortex)) {
  1789. /* Rear channel. Note: ADB_CODECOUT(0+2) and (1+2) is for AC97 modem */
  1790. vortex_connection_mix_adb(vortex, en, 0x11, mixers[2],
  1791. ADB_CODECOUT(0 + 4));
  1792. vortex_connection_mix_adb(vortex, en, 0x11, mixers[3],
  1793. ADB_CODECOUT(1 + 4));
  1794. //printk("SDAC detected ");
  1795. }
  1796. #else
  1797. // Use plain direct output to codec.
  1798. vortex_connection_mix_adb(vortex, en, 0x11, mixers[0], ADB_CODECOUT(0));
  1799. vortex_connection_mix_adb(vortex, en, 0x11, mixers[1], ADB_CODECOUT(1));
  1800. #endif
  1801. #endif
  1802. }
  1803. static void
  1804. vortex_connect_codecrec(vortex_t * vortex, int en, unsigned char mixin0,
  1805. unsigned char mixin1)
  1806. {
  1807. /*
  1808. Enable: 0x1, 0x1
  1809. Channel: 0x11, 0x11
  1810. ADB Source address: 0x48, 0x49
  1811. Destination Asp4Topology_0x9c,0x98
  1812. */
  1813. vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(0), mixin0);
  1814. vortex_connection_adb_mixin(vortex, en, 0x11, ADB_CODECIN(1), mixin1);
  1815. }
  1816. // Higher level ADB audio path (de)allocator.
  1817. /* Resource manager */
  1818. static int resnum[VORTEX_RESOURCE_LAST] =
  1819. { NR_ADB, NR_SRC, NR_MIXIN, NR_MIXOUT, NR_A3D };
  1820. /*
  1821. Checkout/Checkin resource of given type.
  1822. resmap: resource map to be used. If NULL means that we want to allocate
  1823. a DMA resource (root of all other resources of a dma channel).
  1824. out: Mean checkout if != 0. Else mean Checkin resource.
  1825. restype: Indicates type of resource to be checked in or out.
  1826. */
  1827. static char
  1828. vortex_adb_checkinout(vortex_t * vortex, int resmap[], int out, int restype)
  1829. {
  1830. int i, qty = resnum[restype], resinuse = 0;
  1831. if (out) {
  1832. /* Gather used resources by all streams. */
  1833. for (i = 0; i < NR_ADB; i++) {
  1834. resinuse |= vortex->dma_adb[i].resources[restype];
  1835. }
  1836. resinuse |= vortex->fixed_res[restype];
  1837. /* Find and take free resource. */
  1838. for (i = 0; i < qty; i++) {
  1839. if ((resinuse & (1 << i)) == 0) {
  1840. if (resmap != NULL)
  1841. resmap[restype] |= (1 << i);
  1842. else
  1843. vortex->dma_adb[i].resources[restype] |= (1 << i);
  1844. //printk("vortex: ResManager: type %d out %d\n", restype, i);
  1845. return i;
  1846. }
  1847. }
  1848. } else {
  1849. if (resmap == NULL)
  1850. return -EINVAL;
  1851. /* Checkin first resource of type restype. */
  1852. for (i = 0; i < qty; i++) {
  1853. if (resmap[restype] & (1 << i)) {
  1854. resmap[restype] &= ~(1 << i);
  1855. //printk("vortex: ResManager: type %d in %d\n",restype, i);
  1856. return i;
  1857. }
  1858. }
  1859. }
  1860. printk(KERN_ERR "vortex: FATAL: ResManager: resource type %d exhausted.\n", restype);
  1861. return -ENOMEM;
  1862. }
  1863. /* Default Connections */
  1864. static int
  1865. vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type);
  1866. static void vortex_connect_default(vortex_t * vortex, int en)
  1867. {
  1868. // Connect AC97 codec.
  1869. vortex->mixplayb[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1870. VORTEX_RESOURCE_MIXOUT);
  1871. vortex->mixplayb[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1872. VORTEX_RESOURCE_MIXOUT);
  1873. if (VORTEX_IS_QUAD(vortex)) {
  1874. vortex->mixplayb[2] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1875. VORTEX_RESOURCE_MIXOUT);
  1876. vortex->mixplayb[3] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1877. VORTEX_RESOURCE_MIXOUT);
  1878. }
  1879. vortex_connect_codecplay(vortex, en, vortex->mixplayb);
  1880. vortex->mixcapt[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1881. VORTEX_RESOURCE_MIXIN);
  1882. vortex->mixcapt[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1883. VORTEX_RESOURCE_MIXIN);
  1884. vortex_connect_codecrec(vortex, en, MIX_CAPT(0), MIX_CAPT(1));
  1885. // Connect SPDIF
  1886. #ifndef CHIP_AU8820
  1887. vortex->mixspdif[0] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1888. VORTEX_RESOURCE_MIXOUT);
  1889. vortex->mixspdif[1] = vortex_adb_checkinout(vortex, vortex->fixed_res, en,
  1890. VORTEX_RESOURCE_MIXOUT);
  1891. vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[0],
  1892. ADB_SPDIFOUT(0));
  1893. vortex_connection_mix_adb(vortex, en, 0x14, vortex->mixspdif[1],
  1894. ADB_SPDIFOUT(1));
  1895. #endif
  1896. // Connect WT
  1897. #ifndef CHIP_AU8810
  1898. vortex_wt_connect(vortex, en);
  1899. #endif
  1900. // A3D (crosstalk canceler and A3D slices). AU8810 disabled for now.
  1901. #ifndef CHIP_AU8820
  1902. vortex_Vort3D_connect(vortex, en);
  1903. #endif
  1904. // Connect I2S
  1905. // Connect DSP interface for SQ3500 turbo (not here i think...)
  1906. // Connect AC98 modem codec
  1907. }
  1908. /*
  1909. Allocate nr_ch pcm audio routes if dma < 0. If dma >= 0, existing routes
  1910. are deallocated.
  1911. dma: DMA engine routes to be deallocated when dma >= 0.
  1912. nr_ch: Number of channels to be de/allocated.
  1913. dir: direction of stream. Uses same values as substream->stream.
  1914. type: Type of audio output/source (codec, spdif, i2s, dsp, etc)
  1915. Return: Return allocated DMA or same DMA passed as "dma" when dma >= 0.
  1916. */
  1917. static int
  1918. vortex_adb_allocroute(vortex_t * vortex, int dma, int nr_ch, int dir, int type)
  1919. {
  1920. stream_t *stream;
  1921. int i, en;
  1922. if ((nr_ch == 3)
  1923. || ((dir == SNDRV_PCM_STREAM_CAPTURE) && (nr_ch > 2)))
  1924. return -EBUSY;
  1925. if (dma >= 0) {
  1926. en = 0;
  1927. vortex_adb_checkinout(vortex,
  1928. vortex->dma_adb[dma].resources, en,
  1929. VORTEX_RESOURCE_DMA);
  1930. } else {
  1931. en = 1;
  1932. if ((dma =
  1933. vortex_adb_checkinout(vortex, NULL, en,
  1934. VORTEX_RESOURCE_DMA)) < 0)
  1935. return -EBUSY;
  1936. }
  1937. stream = &vortex->dma_adb[dma];
  1938. stream->dma = dma;
  1939. stream->dir = dir;
  1940. stream->type = type;
  1941. /* PLAYBACK ROUTES. */
  1942. if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
  1943. int src[4], mix[4], ch_top;
  1944. #ifndef CHIP_AU8820
  1945. int a3d = 0;
  1946. #endif
  1947. /* Get SRC and MIXER hardware resources. */
  1948. if (stream->type != VORTEX_PCM_SPDIF) {
  1949. for (i = 0; i < nr_ch; i++) {
  1950. if ((src[i] = vortex_adb_checkinout(vortex,
  1951. stream->resources, en,
  1952. VORTEX_RESOURCE_SRC)) < 0) {
  1953. memset(stream->resources, 0,
  1954. sizeof(unsigned char) *
  1955. VORTEX_RESOURCE_LAST);
  1956. return -EBUSY;
  1957. }
  1958. if (stream->type != VORTEX_PCM_A3D) {
  1959. if ((mix[i] = vortex_adb_checkinout(vortex,
  1960. stream->resources,
  1961. en,
  1962. VORTEX_RESOURCE_MIXIN)) < 0) {
  1963. memset(stream->resources,
  1964. 0,
  1965. sizeof(unsigned char) * VORTEX_RESOURCE_LAST);
  1966. return -EBUSY;
  1967. }
  1968. }
  1969. }
  1970. }
  1971. #ifndef CHIP_AU8820
  1972. if (stream->type == VORTEX_PCM_A3D) {
  1973. if ((a3d =
  1974. vortex_adb_checkinout(vortex,
  1975. stream->resources, en,
  1976. VORTEX_RESOURCE_A3D)) < 0) {
  1977. memset(stream->resources, 0,
  1978. sizeof(unsigned char) *
  1979. VORTEX_RESOURCE_LAST);
  1980. printk(KERN_ERR "vortex: out of A3D sources. Sorry\n");
  1981. return -EBUSY;
  1982. }
  1983. /* (De)Initialize A3D hardware source. */
  1984. vortex_Vort3D_InitializeSource(&(vortex->a3d[a3d]), en);
  1985. }
  1986. /* Make SPDIF out exclusive to "spdif" device when in use. */
  1987. if ((stream->type == VORTEX_PCM_SPDIF) && (en)) {
  1988. vortex_route(vortex, 0, 0x14,
  1989. ADB_MIXOUT(vortex->mixspdif[0]),
  1990. ADB_SPDIFOUT(0));
  1991. vortex_route(vortex, 0, 0x14,
  1992. ADB_MIXOUT(vortex->mixspdif[1]),
  1993. ADB_SPDIFOUT(1));
  1994. }
  1995. #endif
  1996. /* Make playback routes. */
  1997. for (i = 0; i < nr_ch; i++) {
  1998. if (stream->type == VORTEX_PCM_ADB) {
  1999. vortex_connection_adbdma_src(vortex, en,
  2000. src[nr_ch - 1],
  2001. dma,
  2002. src[i]);
  2003. vortex_connection_src_mixin(vortex, en,
  2004. 0x11, src[i],
  2005. mix[i]);
  2006. vortex_connection_mixin_mix(vortex, en,
  2007. mix[i],
  2008. MIX_PLAYB(i), 0);
  2009. #ifndef CHIP_AU8820
  2010. vortex_connection_mixin_mix(vortex, en,
  2011. mix[i],
  2012. MIX_SPDIF(i % 2), 0);
  2013. vortex_mix_setinputvolumebyte(vortex,
  2014. MIX_SPDIF(i % 2),
  2015. mix[i],
  2016. MIX_DEFIGAIN);
  2017. #endif
  2018. }
  2019. #ifndef CHIP_AU8820
  2020. if (stream->type == VORTEX_PCM_A3D) {
  2021. vortex_connection_adbdma_src(vortex, en,
  2022. src[nr_ch - 1],
  2023. dma,
  2024. src[i]);
  2025. vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_A3DIN(a3d));
  2026. /* XTalk test. */
  2027. //vortex_route(vortex, en, 0x11, dma, ADB_XTALKIN(i?9:4));
  2028. //vortex_route(vortex, en, 0x11, ADB_SRCOUT(src[i]), ADB_XTALKIN(i?4:9));
  2029. }
  2030. if (stream->type == VORTEX_PCM_SPDIF)
  2031. vortex_route(vortex, en, 0x14,
  2032. ADB_DMA(stream->dma),
  2033. ADB_SPDIFOUT(i));
  2034. #endif
  2035. }
  2036. if (stream->type != VORTEX_PCM_SPDIF && stream->type != VORTEX_PCM_A3D) {
  2037. ch_top = (VORTEX_IS_QUAD(vortex) ? 4 : 2);
  2038. for (i = nr_ch; i < ch_top; i++) {
  2039. vortex_connection_mixin_mix(vortex, en,
  2040. mix[i % nr_ch],
  2041. MIX_PLAYB(i), 0);
  2042. #ifndef CHIP_AU8820
  2043. vortex_connection_mixin_mix(vortex, en,
  2044. mix[i % nr_ch],
  2045. MIX_SPDIF(i % 2),
  2046. 0);
  2047. vortex_mix_setinputvolumebyte(vortex,
  2048. MIX_SPDIF(i % 2),
  2049. mix[i % nr_ch],
  2050. MIX_DEFIGAIN);
  2051. #endif
  2052. }
  2053. }
  2054. #ifndef CHIP_AU8820
  2055. else {
  2056. if (nr_ch == 1 && stream->type == VORTEX_PCM_SPDIF)
  2057. vortex_route(vortex, en, 0x14,
  2058. ADB_DMA(stream->dma),
  2059. ADB_SPDIFOUT(1));
  2060. }
  2061. /* Reconnect SPDIF out when "spdif" device is down. */
  2062. if ((stream->type == VORTEX_PCM_SPDIF) && (!en)) {
  2063. vortex_route(vortex, 1, 0x14,
  2064. ADB_MIXOUT(vortex->mixspdif[0]),
  2065. ADB_SPDIFOUT(0));
  2066. vortex_route(vortex, 1, 0x14,
  2067. ADB_MIXOUT(vortex->mixspdif[1]),
  2068. ADB_SPDIFOUT(1));
  2069. }
  2070. #endif
  2071. /* CAPTURE ROUTES. */
  2072. } else {
  2073. int src[2], mix[2];
  2074. /* Get SRC and MIXER hardware resources. */
  2075. for (i = 0; i < nr_ch; i++) {
  2076. if ((mix[i] =
  2077. vortex_adb_checkinout(vortex,
  2078. stream->resources, en,
  2079. VORTEX_RESOURCE_MIXOUT))
  2080. < 0) {
  2081. memset(stream->resources, 0,
  2082. sizeof(unsigned char) *
  2083. VORTEX_RESOURCE_LAST);
  2084. return -EBUSY;
  2085. }
  2086. if ((src[i] =
  2087. vortex_adb_checkinout(vortex,
  2088. stream->resources, en,
  2089. VORTEX_RESOURCE_SRC)) < 0) {
  2090. memset(stream->resources, 0,
  2091. sizeof(unsigned char) *
  2092. VORTEX_RESOURCE_LAST);
  2093. return -EBUSY;
  2094. }
  2095. }
  2096. /* Make capture routes. */
  2097. vortex_connection_mixin_mix(vortex, en, MIX_CAPT(0), mix[0], 0);
  2098. vortex_connection_mix_src(vortex, en, 0x11, mix[0], src[0]);
  2099. if (nr_ch == 1) {
  2100. vortex_connection_mixin_mix(vortex, en,
  2101. MIX_CAPT(1), mix[0], 0);
  2102. vortex_connection_src_adbdma(vortex, en,
  2103. src[0],
  2104. src[0], dma);
  2105. } else {
  2106. vortex_connection_mixin_mix(vortex, en,
  2107. MIX_CAPT(1), mix[1], 0);
  2108. vortex_connection_mix_src(vortex, en, 0x11, mix[1],
  2109. src[1]);
  2110. vortex_connection_src_src_adbdma(vortex, en,
  2111. src[1], src[0],
  2112. src[1], dma);
  2113. }
  2114. }
  2115. vortex->dma_adb[dma].nr_ch = nr_ch;
  2116. #if 0
  2117. /* AC97 Codec channel setup. FIXME: this has no effect on some cards !! */
  2118. if (nr_ch < 4) {
  2119. /* Copy stereo to rear channel (surround) */
  2120. snd_ac97_write_cache(vortex->codec,
  2121. AC97_SIGMATEL_DAC2INVERT,
  2122. snd_ac97_read(vortex->codec,
  2123. AC97_SIGMATEL_DAC2INVERT)
  2124. | 4);
  2125. } else {
  2126. /* Allow separate front and rear channels. */
  2127. snd_ac97_write_cache(vortex->codec,
  2128. AC97_SIGMATEL_DAC2INVERT,
  2129. snd_ac97_read(vortex->codec,
  2130. AC97_SIGMATEL_DAC2INVERT)
  2131. & ~((u32)
  2132. 4));
  2133. }
  2134. #endif
  2135. return dma;
  2136. }
  2137. /*
  2138. Set the SampleRate of the SRC's attached to the given DMA engine.
  2139. */
  2140. static void
  2141. vortex_adb_setsrc(vortex_t * vortex, int adbdma, unsigned int rate, int dir)
  2142. {
  2143. stream_t *stream = &(vortex->dma_adb[adbdma]);
  2144. int i, cvrt;
  2145. /* dir=1:play ; dir=0:rec */
  2146. if (dir)
  2147. cvrt = SRC_RATIO(rate, 48000);
  2148. else
  2149. cvrt = SRC_RATIO(48000, rate);
  2150. /* Setup SRC's */
  2151. for (i = 0; i < NR_SRC; i++) {
  2152. if (stream->resources[VORTEX_RESOURCE_SRC] & (1 << i))
  2153. vortex_src_setupchannel(vortex, i, cvrt, 0, 0, i, dir, 1, cvrt, dir);
  2154. }
  2155. }
  2156. // Timer and ISR functions.
  2157. static void vortex_settimer(vortex_t * vortex, int period)
  2158. {
  2159. //set the timer period to <period> 48000ths of a second.
  2160. hwwrite(vortex->mmio, VORTEX_IRQ_STAT, period);
  2161. }
  2162. #if 0
  2163. static void vortex_enable_timer_int(vortex_t * card)
  2164. {
  2165. hwwrite(card->mmio, VORTEX_IRQ_CTRL,
  2166. hwread(card->mmio, VORTEX_IRQ_CTRL) | IRQ_TIMER | 0x60);
  2167. }
  2168. static void vortex_disable_timer_int(vortex_t * card)
  2169. {
  2170. hwwrite(card->mmio, VORTEX_IRQ_CTRL,
  2171. hwread(card->mmio, VORTEX_IRQ_CTRL) & ~IRQ_TIMER);
  2172. }
  2173. #endif
  2174. static void vortex_enable_int(vortex_t * card)
  2175. {
  2176. // CAsp4ISR__EnableVortexInt_void_
  2177. hwwrite(card->mmio, VORTEX_CTRL,
  2178. hwread(card->mmio, VORTEX_CTRL) | CTRL_IRQ_ENABLE);
  2179. hwwrite(card->mmio, VORTEX_IRQ_CTRL,
  2180. (hwread(card->mmio, VORTEX_IRQ_CTRL) & 0xffffefc0) | 0x24);
  2181. }
  2182. static void vortex_disable_int(vortex_t * card)
  2183. {
  2184. hwwrite(card->mmio, VORTEX_CTRL,
  2185. hwread(card->mmio, VORTEX_CTRL) & ~CTRL_IRQ_ENABLE);
  2186. }
  2187. static irqreturn_t vortex_interrupt(int irq, void *dev_id)
  2188. {
  2189. vortex_t *vortex = dev_id;
  2190. int i, handled;
  2191. u32 source;
  2192. //check if the interrupt is ours.
  2193. if (!(hwread(vortex->mmio, VORTEX_STAT) & 0x1))
  2194. return IRQ_NONE;
  2195. // This is the Interrrupt Enable flag we set before (consistency check).
  2196. if (!(hwread(vortex->mmio, VORTEX_CTRL) & CTRL_IRQ_ENABLE))
  2197. return IRQ_NONE;
  2198. source = hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
  2199. // Reset IRQ flags.
  2200. hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, source);
  2201. hwread(vortex->mmio, VORTEX_IRQ_SOURCE);
  2202. // Is at least one IRQ flag set?
  2203. if (source == 0) {
  2204. printk(KERN_ERR "vortex: missing irq source\n");
  2205. return IRQ_NONE;
  2206. }
  2207. handled = 0;
  2208. // Attend every interrupt source.
  2209. if (unlikely(source & IRQ_ERR_MASK)) {
  2210. if (source & IRQ_FATAL) {
  2211. printk(KERN_ERR "vortex: IRQ fatal error\n");
  2212. }
  2213. if (source & IRQ_PARITY) {
  2214. printk(KERN_ERR "vortex: IRQ parity error\n");
  2215. }
  2216. if (source & IRQ_REG) {
  2217. printk(KERN_ERR "vortex: IRQ reg error\n");
  2218. }
  2219. if (source & IRQ_FIFO) {
  2220. printk(KERN_ERR "vortex: IRQ fifo error\n");
  2221. }
  2222. if (source & IRQ_DMA) {
  2223. printk(KERN_ERR "vortex: IRQ dma error\n");
  2224. }
  2225. handled = 1;
  2226. }
  2227. if (source & IRQ_PCMOUT) {
  2228. /* ALSA period acknowledge. */
  2229. spin_lock(&vortex->lock);
  2230. for (i = 0; i < NR_ADB; i++) {
  2231. if (vortex->dma_adb[i].fifo_status == FIFO_START) {
  2232. if (vortex_adbdma_bufshift(vortex, i)) ;
  2233. spin_unlock(&vortex->lock);
  2234. snd_pcm_period_elapsed(vortex->dma_adb[i].
  2235. substream);
  2236. spin_lock(&vortex->lock);
  2237. }
  2238. }
  2239. #ifndef CHIP_AU8810
  2240. for (i = 0; i < NR_WT; i++) {
  2241. if (vortex->dma_wt[i].fifo_status == FIFO_START) {
  2242. if (vortex_wtdma_bufshift(vortex, i)) ;
  2243. spin_unlock(&vortex->lock);
  2244. snd_pcm_period_elapsed(vortex->dma_wt[i].
  2245. substream);
  2246. spin_lock(&vortex->lock);
  2247. }
  2248. }
  2249. #endif
  2250. spin_unlock(&vortex->lock);
  2251. handled = 1;
  2252. }
  2253. //Acknowledge the Timer interrupt
  2254. if (source & IRQ_TIMER) {
  2255. hwread(vortex->mmio, VORTEX_IRQ_STAT);
  2256. handled = 1;
  2257. }
  2258. if (source & IRQ_MIDI) {
  2259. snd_mpu401_uart_interrupt(vortex->irq,
  2260. vortex->rmidi->private_data);
  2261. handled = 1;
  2262. }
  2263. if (!handled) {
  2264. printk(KERN_ERR "vortex: unknown irq source %x\n", source);
  2265. }
  2266. return IRQ_RETVAL(handled);
  2267. }
  2268. /* Codec */
  2269. #define POLL_COUNT 1000
  2270. static void vortex_codec_init(vortex_t * vortex)
  2271. {
  2272. int i;
  2273. for (i = 0; i < 32; i++) {
  2274. /* the windows driver writes -i, so we write -i */
  2275. hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
  2276. msleep(2);
  2277. }
  2278. if (0) {
  2279. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x8068);
  2280. msleep(1);
  2281. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
  2282. msleep(1);
  2283. } else {
  2284. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
  2285. msleep(2);
  2286. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
  2287. msleep(2);
  2288. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80e8);
  2289. msleep(2);
  2290. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x80a8);
  2291. msleep(2);
  2292. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00a8);
  2293. msleep(2);
  2294. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0x00e8);
  2295. }
  2296. for (i = 0; i < 32; i++) {
  2297. hwwrite(vortex->mmio, (VORTEX_CODEC_CHN + (i << 2)), -i);
  2298. msleep(5);
  2299. }
  2300. hwwrite(vortex->mmio, VORTEX_CODEC_CTRL, 0xe8);
  2301. msleep(1);
  2302. /* Enable codec channels 0 and 1. */
  2303. hwwrite(vortex->mmio, VORTEX_CODEC_EN,
  2304. hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_CODEC);
  2305. }
  2306. static void
  2307. vortex_codec_write(struct snd_ac97 * codec, unsigned short addr, unsigned short data)
  2308. {
  2309. vortex_t *card = (vortex_t *) codec->private_data;
  2310. unsigned int lifeboat = 0;
  2311. /* wait for transactions to clear */
  2312. while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
  2313. udelay(100);
  2314. if (lifeboat++ > POLL_COUNT) {
  2315. printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
  2316. return;
  2317. }
  2318. }
  2319. /* write register */
  2320. hwwrite(card->mmio, VORTEX_CODEC_IO,
  2321. ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
  2322. ((data << VORTEX_CODEC_DATSHIFT) & VORTEX_CODEC_DATMASK) |
  2323. VORTEX_CODEC_WRITE |
  2324. (codec->num << VORTEX_CODEC_ID_SHIFT) );
  2325. /* Flush Caches. */
  2326. hwread(card->mmio, VORTEX_CODEC_IO);
  2327. }
  2328. static unsigned short vortex_codec_read(struct snd_ac97 * codec, unsigned short addr)
  2329. {
  2330. vortex_t *card = (vortex_t *) codec->private_data;
  2331. u32 read_addr, data;
  2332. unsigned lifeboat = 0;
  2333. /* wait for transactions to clear */
  2334. while (!(hwread(card->mmio, VORTEX_CODEC_CTRL) & 0x100)) {
  2335. udelay(100);
  2336. if (lifeboat++ > POLL_COUNT) {
  2337. printk(KERN_ERR "vortex: ac97 codec stuck busy\n");
  2338. return 0xffff;
  2339. }
  2340. }
  2341. /* set up read address */
  2342. read_addr = ((addr << VORTEX_CODEC_ADDSHIFT) & VORTEX_CODEC_ADDMASK) |
  2343. (codec->num << VORTEX_CODEC_ID_SHIFT) ;
  2344. hwwrite(card->mmio, VORTEX_CODEC_IO, read_addr);
  2345. /* wait for address */
  2346. do {
  2347. udelay(100);
  2348. data = hwread(card->mmio, VORTEX_CODEC_IO);
  2349. if (lifeboat++ > POLL_COUNT) {
  2350. printk(KERN_ERR "vortex: ac97 address never arrived\n");
  2351. return 0xffff;
  2352. }
  2353. } while ((data & VORTEX_CODEC_ADDMASK) !=
  2354. (addr << VORTEX_CODEC_ADDSHIFT));
  2355. /* return data. */
  2356. return (u16) (data & VORTEX_CODEC_DATMASK);
  2357. }
  2358. /* SPDIF support */
  2359. static void vortex_spdif_init(vortex_t * vortex, int spdif_sr, int spdif_mode)
  2360. {
  2361. int i, this_38 = 0, this_04 = 0, this_08 = 0, this_0c = 0;
  2362. /* CAsp4Spdif::InitializeSpdifHardware(void) */
  2363. hwwrite(vortex->mmio, VORTEX_SPDIF_FLAGS,
  2364. hwread(vortex->mmio, VORTEX_SPDIF_FLAGS) & 0xfff3fffd);
  2365. //for (i=0x291D4; i<0x29200; i+=4)
  2366. for (i = 0; i < 11; i++)
  2367. hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1 + (i << 2), 0);
  2368. //hwwrite(vortex->mmio, 0x29190, hwread(vortex->mmio, 0x29190) | 0xc0000);
  2369. hwwrite(vortex->mmio, VORTEX_CODEC_EN,
  2370. hwread(vortex->mmio, VORTEX_CODEC_EN) | EN_SPDIF);
  2371. /* CAsp4Spdif::ProgramSRCInHardware(enum SPDIF_SR,enum SPDIFMODE) */
  2372. if (this_04 && this_08) {
  2373. int edi;
  2374. i = (((0x5DC00000 / spdif_sr) + 1) >> 1);
  2375. if (i > 0x800) {
  2376. if (i < 0x1ffff)
  2377. edi = (i >> 1);
  2378. else
  2379. edi = 0x1ffff;
  2380. } else {
  2381. i = edi = 0x800;
  2382. }
  2383. /* this_04 and this_08 are the CASp4Src's (samplerate converters) */
  2384. vortex_src_setupchannel(vortex, this_04, edi, 0, 1,
  2385. this_0c, 1, 0, edi, 1);
  2386. vortex_src_setupchannel(vortex, this_08, edi, 0, 1,
  2387. this_0c, 1, 0, edi, 1);
  2388. }
  2389. i = spdif_sr;
  2390. spdif_sr |= 0x8c;
  2391. switch (i) {
  2392. case 32000:
  2393. this_38 &= 0xFFFFFFFE;
  2394. this_38 &= 0xFFFFFFFD;
  2395. this_38 &= 0xF3FFFFFF;
  2396. this_38 |= 0x03000000; /* set 32khz samplerate */
  2397. this_38 &= 0xFFFFFF3F;
  2398. spdif_sr &= 0xFFFFFFFD;
  2399. spdif_sr |= 1;
  2400. break;
  2401. case 44100:
  2402. this_38 &= 0xFFFFFFFE;
  2403. this_38 &= 0xFFFFFFFD;
  2404. this_38 &= 0xF0FFFFFF;
  2405. this_38 |= 0x03000000;
  2406. this_38 &= 0xFFFFFF3F;
  2407. spdif_sr &= 0xFFFFFFFC;
  2408. break;
  2409. case 48000:
  2410. if (spdif_mode == 1) {
  2411. this_38 &= 0xFFFFFFFE;
  2412. this_38 &= 0xFFFFFFFD;
  2413. this_38 &= 0xF2FFFFFF;
  2414. this_38 |= 0x02000000; /* set 48khz samplerate */
  2415. this_38 &= 0xFFFFFF3F;
  2416. } else {
  2417. /* J. Gordon Wolfe: I think this stuff is for AC3 */
  2418. this_38 |= 0x00000003;
  2419. this_38 &= 0xFFFFFFBF;
  2420. this_38 |= 0x80;
  2421. }
  2422. spdif_sr |= 2;
  2423. spdif_sr &= 0xFFFFFFFE;
  2424. break;
  2425. }
  2426. /* looks like the next 2 lines transfer a 16-bit value into 2 8-bit
  2427. registers. seems to be for the standard IEC/SPDIF initialization
  2428. stuff */
  2429. hwwrite(vortex->mmio, VORTEX_SPDIF_CFG0, this_38 & 0xffff);
  2430. hwwrite(vortex->mmio, VORTEX_SPDIF_CFG1, this_38 >> 0x10);
  2431. hwwrite(vortex->mmio, VORTEX_SPDIF_SMPRATE, spdif_sr);
  2432. }
  2433. /* Initialization */
  2434. static int __devinit vortex_core_init(vortex_t * vortex)
  2435. {
  2436. printk(KERN_INFO "Vortex: init.... ");
  2437. /* Hardware Init. */
  2438. hwwrite(vortex->mmio, VORTEX_CTRL, 0xffffffff);
  2439. msleep(5);
  2440. hwwrite(vortex->mmio, VORTEX_CTRL,
  2441. hwread(vortex->mmio, VORTEX_CTRL) & 0xffdfffff);
  2442. msleep(5);
  2443. /* Reset IRQ flags */
  2444. hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffffffff);
  2445. hwread(vortex->mmio, VORTEX_IRQ_STAT);
  2446. vortex_codec_init(vortex);
  2447. #ifdef CHIP_AU8830
  2448. hwwrite(vortex->mmio, VORTEX_CTRL,
  2449. hwread(vortex->mmio, VORTEX_CTRL) | 0x1000000);
  2450. #endif
  2451. /* Init audio engine. */
  2452. vortex_adbdma_init(vortex);
  2453. hwwrite(vortex->mmio, VORTEX_ENGINE_CTRL, 0x0); //, 0xc83c7e58, 0xc5f93e58
  2454. vortex_adb_init(vortex);
  2455. /* Init processing blocks. */
  2456. vortex_fifo_init(vortex);
  2457. vortex_mixer_init(vortex);
  2458. vortex_srcblock_init(vortex);
  2459. #ifndef CHIP_AU8820
  2460. vortex_eq_init(vortex);
  2461. vortex_spdif_init(vortex, 48000, 1);
  2462. vortex_Vort3D_enable(vortex);
  2463. #endif
  2464. #ifndef CHIP_AU8810
  2465. vortex_wt_init(vortex);
  2466. #endif
  2467. // Moved to au88x0.c
  2468. //vortex_connect_default(vortex, 1);
  2469. vortex_settimer(vortex, 0x90);
  2470. // Enable Interrupts.
  2471. // vortex_enable_int() must be first !!
  2472. // hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
  2473. // vortex_enable_int(vortex);
  2474. //vortex_enable_timer_int(vortex);
  2475. //vortex_disable_timer_int(vortex);
  2476. printk(KERN_INFO "done.\n");
  2477. spin_lock_init(&vortex->lock);
  2478. return 0;
  2479. }
  2480. static int vortex_core_shutdown(vortex_t * vortex)
  2481. {
  2482. printk(KERN_INFO "Vortex: shutdown...");
  2483. #ifndef CHIP_AU8820
  2484. vortex_eq_free(vortex);
  2485. vortex_Vort3D_disable(vortex);
  2486. #endif
  2487. //vortex_disable_timer_int(vortex);
  2488. vortex_disable_int(vortex);
  2489. vortex_connect_default(vortex, 0);
  2490. /* Reset all DMA fifos. */
  2491. vortex_fifo_init(vortex);
  2492. /* Erase all audio routes. */
  2493. vortex_adb_init(vortex);
  2494. /* Disable MPU401 */
  2495. //hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, hwread(vortex->mmio, VORTEX_IRQ_CTRL) & ~IRQ_MIDI);
  2496. //hwwrite(vortex->mmio, VORTEX_CTRL, hwread(vortex->mmio, VORTEX_CTRL) & ~CTRL_MIDI_EN);
  2497. hwwrite(vortex->mmio, VORTEX_IRQ_CTRL, 0);
  2498. hwwrite(vortex->mmio, VORTEX_CTRL, 0);
  2499. msleep(5);
  2500. hwwrite(vortex->mmio, VORTEX_IRQ_SOURCE, 0xffff);
  2501. printk(KERN_INFO "done.\n");
  2502. return 0;
  2503. }
  2504. /* Alsa support. */
  2505. static int vortex_alsafmt_aspfmt(int alsafmt)
  2506. {
  2507. int fmt;
  2508. switch (alsafmt) {
  2509. case SNDRV_PCM_FORMAT_U8:
  2510. fmt = 0x1;
  2511. break;
  2512. case SNDRV_PCM_FORMAT_MU_LAW:
  2513. fmt = 0x2;
  2514. break;
  2515. case SNDRV_PCM_FORMAT_A_LAW:
  2516. fmt = 0x3;
  2517. break;
  2518. case SNDRV_PCM_FORMAT_SPECIAL:
  2519. fmt = 0x4; /* guess. */
  2520. break;
  2521. case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
  2522. fmt = 0x5; /* guess. */
  2523. break;
  2524. case SNDRV_PCM_FORMAT_S16_LE:
  2525. fmt = 0x8;
  2526. break;
  2527. case SNDRV_PCM_FORMAT_S16_BE:
  2528. fmt = 0x9; /* check this... */
  2529. break;
  2530. default:
  2531. fmt = 0x8;
  2532. printk(KERN_ERR "vortex: format unsupported %d\n", alsafmt);
  2533. break;
  2534. }
  2535. return fmt;
  2536. }
  2537. /* Some not yet useful translations. */
  2538. #if 0
  2539. typedef enum {
  2540. ASPFMTLINEAR16 = 0, /* 0x8 */
  2541. ASPFMTLINEAR8, /* 0x1 */
  2542. ASPFMTULAW, /* 0x2 */
  2543. ASPFMTALAW, /* 0x3 */
  2544. ASPFMTSPORT, /* ? */
  2545. ASPFMTSPDIF, /* ? */
  2546. } ASPENCODING;
  2547. static int
  2548. vortex_translateformat(vortex_t * vortex, char bits, char nch, int encod)
  2549. {
  2550. int a, this_194;
  2551. if ((bits != 8) || (bits != 16))
  2552. return -1;
  2553. switch (encod) {
  2554. case 0:
  2555. if (bits == 0x10)
  2556. a = 8; // 16 bit
  2557. break;
  2558. case 1:
  2559. if (bits == 8)
  2560. a = 1; // 8 bit
  2561. break;
  2562. case 2:
  2563. a = 2; // U_LAW
  2564. break;
  2565. case 3:
  2566. a = 3; // A_LAW
  2567. break;
  2568. }
  2569. switch (nch) {
  2570. case 1:
  2571. this_194 = 0;
  2572. break;
  2573. case 2:
  2574. this_194 = 1;
  2575. break;
  2576. case 4:
  2577. this_194 = 1;
  2578. break;
  2579. case 6:
  2580. this_194 = 1;
  2581. break;
  2582. }
  2583. return (a);
  2584. }
  2585. static void vortex_cdmacore_setformat(vortex_t * vortex, int bits, int nch)
  2586. {
  2587. short int d, this_148;
  2588. d = ((bits >> 3) * nch);
  2589. this_148 = 0xbb80 / d;
  2590. }
  2591. #endif