au8820.h 6.3 KB

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  1. /*
  2. Aureal Vortex Soundcard driver.
  3. IO addr collected from asp4core.vxd:
  4. function address
  5. 0005D5A0 13004
  6. 00080674 14004
  7. 00080AFF 12818
  8. */
  9. #define CHIP_AU8820
  10. #define CARD_NAME "Aureal Vortex 3D Sound Processor"
  11. #define CARD_NAME_SHORT "au8820"
  12. /* Number of ADB and WT channels */
  13. #define NR_ADB 0x10
  14. #define NR_WT 0x20
  15. #define NR_SRC 0x10
  16. #define NR_A3D 0x00
  17. #define NR_MIXIN 0x10
  18. #define NR_MIXOUT 0x10
  19. /* ADBDMA */
  20. #define VORTEX_ADBDMA_STAT 0x105c0 /* read only, subbuffer, DMA pos */
  21. #define POS_MASK 0x00000fff
  22. #define POS_SHIFT 0x0
  23. #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
  24. #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
  25. #define VORTEX_ADBDMA_CTRL 0x10580 /* write only, format, flags, DMA pos */
  26. #define OFFSET_MASK 0x00000fff
  27. #define OFFSET_SHIFT 0x0
  28. #define IE_MASK 0x00001000 /* interrupt enable. */
  29. #define IE_SHIFT 0xc
  30. #define DIR_MASK 0x00002000 /* Direction. */
  31. #define DIR_SHIFT 0xd
  32. #define FMT_MASK 0x0003c000
  33. #define FMT_SHIFT 0xe
  34. // The masks and shift also work for the wtdma, if not specified otherwise.
  35. #define VORTEX_ADBDMA_BUFCFG0 0x10400
  36. #define VORTEX_ADBDMA_BUFCFG1 0x10404
  37. #define VORTEX_ADBDMA_BUFBASE 0x10200
  38. #define VORTEX_ADBDMA_START 0x106c0 /* Which subbuffer starts */
  39. #define VORTEX_ADBDMA_STATUS 0x10600 /* stored at AdbDma->this_10 / 2 DWORD in size. */
  40. /* ADB */
  41. #define VORTEX_ADB_SR 0x10a00 /* Samplerates enable/disable */
  42. #define VORTEX_ADB_RTBASE 0x10800
  43. #define VORTEX_ADB_RTBASE_COUNT 103
  44. #define VORTEX_ADB_CHNBASE 0x1099c
  45. #define VORTEX_ADB_CHNBASE_COUNT 22
  46. #define ROUTE_MASK 0x3fff
  47. #define ADB_MASK 0x7f
  48. #define ADB_SHIFT 0x7
  49. //#define ADB_MIX_MASK 0xf
  50. /* ADB address */
  51. #define OFFSET_ADBDMA 0x00
  52. #define OFFSET_SRCOUT 0x10 /* on channel 0x11 */
  53. #define OFFSET_SRCIN 0x10 /* on channel < 0x11 */
  54. #define OFFSET_MIXOUT 0x20 /* source */
  55. #define OFFSET_MIXIN 0x30 /* sink */
  56. #define OFFSET_CODECIN 0x48 /* ADB source */
  57. #define OFFSET_CODECOUT 0x58 /* ADB sink/target */
  58. #define OFFSET_SPORTOUT 0x60 /* sink */
  59. #define OFFSET_SPORTIN 0x50 /* source */
  60. #define OFFSET_EFXOUT 0x50 /* sink */
  61. #define OFFSET_EFXIN 0x40 /* source */
  62. #define OFFSET_A3DOUT 0x00 /* This card has no HRTF :( */
  63. #define OFFSET_A3DIN 0x00
  64. #define OFFSET_WTOUT 0x58 /* */
  65. /* ADB route translate helper */
  66. #define ADB_DMA(x) (x + OFFSET_ADBDMA)
  67. #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
  68. #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
  69. #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
  70. #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
  71. #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
  72. #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
  73. #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
  74. #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN) /* */
  75. #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 8 A3D blocks */
  76. #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
  77. #define ADB_WTOUT(x,y) (y + OFFSET_WTOUT)
  78. /* WTDMA */
  79. #define VORTEX_WTDMA_CTRL 0x10500 /* format, DMA pos */
  80. #define VORTEX_WTDMA_STAT 0x10500 /* DMA subbuf, DMA pos */
  81. #define WT_SUBBUF_MASK (0x3 << WT_SUBBUF_SHIFT)
  82. #define WT_SUBBUF_SHIFT 0x15
  83. #define VORTEX_WTDMA_BUFBASE 0x10000
  84. #define VORTEX_WTDMA_BUFCFG0 0x10300
  85. #define VORTEX_WTDMA_BUFCFG1 0x10304
  86. #define VORTEX_WTDMA_START 0x10640 /* which subbuffer is first */
  87. #define VORTEX_WT_BASE 0x9000
  88. /* MIXER */
  89. #define VORTEX_MIXER_SR 0x9f00
  90. #define VORTEX_MIXER_CLIP 0x9f80
  91. #define VORTEX_MIXER_CHNBASE 0x9e40
  92. #define VORTEX_MIXER_RTBASE 0x9e00
  93. #define MIXER_RTBASE_SIZE 0x26
  94. #define VORTEX_MIX_ENIN 0x9a00 /* Input enable bits. 4 bits wide. */
  95. #define VORTEX_MIX_SMP 0x9c00
  96. /* MIX */
  97. #define VORTEX_MIX_INVOL_A 0x9000 /* in? */
  98. #define VORTEX_MIX_INVOL_B 0x8000 /* out? */
  99. #define VORTEX_MIX_VOL_A 0x9800
  100. #define VORTEX_MIX_VOL_B 0x8800
  101. #define VOL_MIN 0x80 /* Input volume when muted. */
  102. #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
  103. //#define MIX_OUTL 0xe
  104. //#define MIX_OUTR 0xf
  105. //#define MIX_INL 0xe
  106. //#define MIX_INR 0xf
  107. #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
  108. #define MIX_DEFOGAIN 0x08
  109. /* SRC */
  110. #define VORTEX_SRCBLOCK_SR 0xccc0
  111. #define VORTEX_SRC_CHNBASE 0xcc40
  112. #define VORTEX_SRC_RTBASE 0xcc00
  113. #define VORTEX_SRC_SOURCE 0xccc4
  114. #define VORTEX_SRC_SOURCESIZE 0xccc8
  115. #define VORTEX_SRC_U0 0xce00
  116. #define VORTEX_SRC_DRIFT0 0xce80
  117. #define VORTEX_SRC_DRIFT1 0xcec0
  118. #define VORTEX_SRC_U1 0xcf00
  119. #define VORTEX_SRC_DRIFT2 0xcf40
  120. #define VORTEX_SRC_U2 0xcf80
  121. #define VORTEX_SRC_DATA 0xc800
  122. #define VORTEX_SRC_DATA0 0xc000
  123. #define VORTEX_SRC_CONVRATIO 0xce40
  124. //#define SRC_RATIO(x) ((((x<<15)/48000) + 1)/2) /* Playback */
  125. //#define SRC_RATIO2(x) ((((48000<<15)/x) + 1)/2) /* Recording */
  126. /* FIFO */
  127. #define VORTEX_FIFO_ADBCTRL 0xf800 /* Control bits. */
  128. #define VORTEX_FIFO_WTCTRL 0xf840
  129. #define FIFO_RDONLY 0x00000001
  130. #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
  131. #define FIFO_VALID 0x00000010
  132. #define FIFO_EMPTY 0x00000020
  133. #define FIFO_U0 0x00001000 /* Unknown. */
  134. #define FIFO_U1 0x00010000
  135. #define FIFO_SIZE_BITS 5
  136. #define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
  137. #define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
  138. #define VORTEX_FIFO_ADBDATA 0xe000
  139. #define VORTEX_FIFO_WTDATA 0xe800
  140. /* CODEC */
  141. #define VORTEX_CODEC_CTRL 0x11984
  142. #define VORTEX_CODEC_EN 0x11990
  143. #define EN_CODEC 0x00000300
  144. #define EN_SPORT 0x00030000
  145. #define EN_SPDIF 0x000c0000
  146. #define VORTEX_CODEC_CHN 0x11880
  147. #define VORTEX_CODEC_IO 0x11988
  148. #define VORTEX_SPDIF_FLAGS 0x1005c /* FIXME */
  149. #define VORTEX_SPDIF_CFG0 0x119D0
  150. #define VORTEX_SPDIF_CFG1 0x119D4
  151. #define VORTEX_SPDIF_SMPRATE 0x11994
  152. /* Sample timer */
  153. #define VORTEX_SMP_TIME 0x11998
  154. /* IRQ */
  155. #define VORTEX_IRQ_SOURCE 0x12800 /* Interrupt source flags. */
  156. #define VORTEX_IRQ_CTRL 0x12804 /* Interrupt source mask. */
  157. #define VORTEX_STAT 0x12808 /* ?? */
  158. #define VORTEX_CTRL 0x1280c
  159. #define CTRL_MIDI_EN 0x00000001
  160. #define CTRL_MIDI_PORT 0x00000060
  161. #define CTRL_GAME_EN 0x00000008
  162. #define CTRL_GAME_PORT 0x00000e00
  163. #define CTRL_IRQ_ENABLE 0x4000
  164. /* write: Timer period config / read: TIMER IRQ ack. */
  165. #define VORTEX_IRQ_STAT 0x1199c
  166. /* DMA */
  167. #define VORTEX_DMA_BUFFER 0x10200
  168. #define VORTEX_ENGINE_CTRL 0x1060c
  169. #define ENGINE_INIT 0x0L
  170. /* MIDI *//* GAME. */
  171. #define VORTEX_MIDI_DATA 0x11000
  172. #define VORTEX_MIDI_CMD 0x11004 /* Write command / Read status */
  173. #define VORTEX_GAME_LEGACY 0x11008
  174. #define VORTEX_CTRL2 0x1100c
  175. #define CTRL2_GAME_ADCMODE 0x40
  176. #define VORTEX_GAME_AXIS 0x11010
  177. #define AXIS_SIZE 4
  178. #define AXIS_RANGE 0x1fff