au8810.h 6.8 KB

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  1. /*
  2. Aureal Advantage Soundcard driver.
  3. */
  4. #define CHIP_AU8810
  5. #define CARD_NAME "Aureal Advantage 3D Sound Processor"
  6. #define CARD_NAME_SHORT "au8810"
  7. #define NR_ADB 0x10
  8. #define NR_WT 0x00
  9. #define NR_SRC 0x10
  10. #define NR_A3D 0x10
  11. #define NR_MIXIN 0x20
  12. #define NR_MIXOUT 0x10
  13. /* ADBDMA */
  14. #define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
  15. #define POS_MASK 0x00000fff
  16. #define POS_SHIFT 0x0
  17. #define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
  18. #define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
  19. #define VORTEX_ADBDMA_CTRL 0x27180 /* write only; format, flags, DMA pos */
  20. #define OFFSET_MASK 0x00000fff
  21. #define OFFSET_SHIFT 0x0
  22. #define IE_MASK 0x00001000 /* interrupt enable. */
  23. #define IE_SHIFT 0xc
  24. #define DIR_MASK 0x00002000 /* Direction */
  25. #define DIR_SHIFT 0xd
  26. #define FMT_MASK 0x0003c000
  27. #define FMT_SHIFT 0xe
  28. // The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
  29. #define VORTEX_ADBDMA_BUFCFG0 0x27100
  30. #define VORTEX_ADBDMA_BUFCFG1 0x27104
  31. #define VORTEX_ADBDMA_BUFBASE 0x27000
  32. #define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
  33. #define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */
  34. /* WTDMA */
  35. #define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */
  36. #define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */
  37. #define WT_SUBBUF_MASK 0x3
  38. #define WT_SUBBUF_SHIFT 0xc
  39. #define VORTEX_WTDMA_BUFBASE 0x27fc0
  40. #define VORTEX_WTDMA_BUFCFG0 0x27fd0
  41. #define VORTEX_WTDMA_BUFCFG1 0x27fd4
  42. #define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */
  43. /* ADB */
  44. #define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
  45. #define VORTEX_ADB_RTBASE 0x28000
  46. #define VORTEX_ADB_RTBASE_COUNT 173
  47. #define VORTEX_ADB_CHNBASE 0x282b4
  48. #define VORTEX_ADB_CHNBASE_COUNT 24
  49. #define ROUTE_MASK 0xffff
  50. #define SOURCE_MASK 0xff00
  51. #define ADB_MASK 0xff
  52. #define ADB_SHIFT 0x8
  53. /* ADB address */
  54. #define OFFSET_ADBDMA 0x00
  55. #define OFFSET_SRCIN 0x40
  56. #define OFFSET_SRCOUT 0x20
  57. #define OFFSET_MIXIN 0x50
  58. #define OFFSET_MIXOUT 0x30
  59. #define OFFSET_CODECIN 0x70
  60. #define OFFSET_CODECOUT 0x88
  61. #define OFFSET_SPORTIN 0x78 /* ch 0x13 */
  62. #define OFFSET_SPORTOUT 0x90
  63. #define OFFSET_SPDIFOUT 0x92 /* ch 0x14 check this! */
  64. #define OFFSET_EQIN 0xa0
  65. #define OFFSET_EQOUT 0x7e /* 2 routes on ch 0x11 */
  66. #define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) */
  67. #define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink) */
  68. #define OFFSET_A3DIN 0x70 /* ADB sink. */
  69. #define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */
  70. #define OFFSET_EFXIN 0x80 /* ADB sink. */
  71. #define OFFSET_EFXOUT 0x68 /* ADB source. */
  72. /* ADB route translate helper */
  73. #define ADB_DMA(x) (x)
  74. #define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
  75. #define ADB_SRCIN(x) (x + OFFSET_SRCIN)
  76. #define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
  77. #define ADB_MIXIN(x) (x + OFFSET_MIXIN)
  78. #define ADB_CODECIN(x) (x + OFFSET_CODECIN)
  79. #define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
  80. #define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
  81. #define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
  82. #define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
  83. #define ADB_EQIN(x) (x + OFFSET_EQIN)
  84. #define ADB_EQOUT(x) (x + OFFSET_EQOUT)
  85. #define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */
  86. #define ADB_A3DIN(x) (x + OFFSET_A3DIN)
  87. #define ADB_XTALKIN(x) (x + OFFSET_XTALKIN)
  88. #define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT)
  89. #define MIX_OUTL 0xe
  90. #define MIX_OUTR 0xf
  91. #define MIX_INL 0x1e
  92. #define MIX_INR 0x1f
  93. #define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
  94. #define MIX_DEFOGAIN 0x08
  95. /* MIXER */
  96. #define VORTEX_MIXER_SR 0x21f00
  97. #define VORTEX_MIXER_CLIP 0x21f80
  98. #define VORTEX_MIXER_CHNBASE 0x21e40
  99. #define VORTEX_MIXER_RTBASE 0x21e00
  100. #define MIXER_RTBASE_SIZE 0x38
  101. #define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
  102. #define VORTEX_MIX_SMP 0x21c00 /* AU8820: 0x9c00 */
  103. /* MIX */
  104. #define VORTEX_MIX_INVOL_A 0x21000 /* in? */
  105. #define VORTEX_MIX_INVOL_B 0x20000 /* out? */
  106. #define VORTEX_MIX_VOL_A 0x21800
  107. #define VORTEX_MIX_VOL_B 0x20800
  108. #define VOL_MIN 0x80 /* Input volume when muted. */
  109. #define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
  110. /* SRC */
  111. #define VORTEX_SRC_CHNBASE 0x26c40
  112. #define VORTEX_SRC_RTBASE 0x26c00
  113. #define VORTEX_SRCBLOCK_SR 0x26cc0
  114. #define VORTEX_SRC_SOURCE 0x26cc4
  115. #define VORTEX_SRC_SOURCESIZE 0x26cc8
  116. /* Params
  117. 0x26e00 : 1 U0
  118. 0x26e40 : 2 CR
  119. 0x26e80 : 3 U3
  120. 0x26ec0 : 4 DRIFT1
  121. 0x26f00 : 5 U1
  122. 0x26f40 : 6 DRIFT2
  123. 0x26f80 : 7 U2 : Target rate, direction
  124. */
  125. #define VORTEX_SRC_CONVRATIO 0x26e40
  126. #define VORTEX_SRC_DRIFT0 0x26e80
  127. #define VORTEX_SRC_DRIFT1 0x26ec0
  128. #define VORTEX_SRC_DRIFT2 0x26f40
  129. #define VORTEX_SRC_U0 0x26e00
  130. #define U0_SLOWLOCK 0x200
  131. #define VORTEX_SRC_U1 0x26f00
  132. #define VORTEX_SRC_U2 0x26f80
  133. #define VORTEX_SRC_DATA 0x26800 /* 0xc800 */
  134. #define VORTEX_SRC_DATA0 0x26000
  135. /* FIFO */
  136. #define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
  137. #define VORTEX_FIFO_WTCTRL 0x16000
  138. #define FIFO_RDONLY 0x00000001
  139. #define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
  140. #define FIFO_VALID 0x00000010
  141. #define FIFO_EMPTY 0x00000020
  142. #define FIFO_U0 0x00001000 /* Unknown. */
  143. #define FIFO_U1 0x00010000
  144. #define FIFO_SIZE_BITS 5
  145. #define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
  146. #define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
  147. //#define FIFO_MASK 0x1f /* at shift left 0xb */
  148. //#define FIFO_SIZE 0x20
  149. #define FIFO_BITS 0x03880000
  150. #define VORTEX_FIFO_ADBDATA 0x14000
  151. #define VORTEX_FIFO_WTDATA 0x10000
  152. /* CODEC */
  153. #define VORTEX_CODEC_CTRL 0x29184
  154. #define VORTEX_CODEC_EN 0x29190
  155. #define EN_CODEC0 0x00000300
  156. #define EN_AC98 0x00000c00 /* Modem AC98 slots. */
  157. #define EN_CODEC1 0x00003000
  158. #define EN_CODEC (EN_CODEC0 | EN_CODEC1)
  159. #define EN_SPORT 0x00030000
  160. #define EN_SPDIF 0x000c0000
  161. #define VORTEX_CODEC_CHN 0x29080
  162. #define VORTEX_CODEC_IO 0x29188
  163. /* SPDIF */
  164. #define VORTEX_SPDIF_FLAGS 0x2205c
  165. #define VORTEX_SPDIF_CFG0 0x291D0
  166. #define VORTEX_SPDIF_CFG1 0x291D4
  167. #define VORTEX_SPDIF_SMPRATE 0x29194
  168. /* Sample timer */
  169. #define VORTEX_SMP_TIME 0x29198
  170. #define VORTEX_MODEM_CTRL 0x291ac
  171. /* IRQ */
  172. #define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
  173. #define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
  174. #define VORTEX_STAT 0x2a008 /* Status */
  175. #define VORTEX_CTRL 0x2a00c
  176. #define CTRL_MIDI_EN 0x00000001
  177. #define CTRL_MIDI_PORT 0x00000060
  178. #define CTRL_GAME_EN 0x00000008
  179. #define CTRL_GAME_PORT 0x00000e00
  180. //#define CTRL_IRQ_ENABLE 0x01004000
  181. #define CTRL_IRQ_ENABLE 0x00004000
  182. /* write: Timer period config / read: TIMER IRQ ack. */
  183. #define VORTEX_IRQ_STAT 0x2919c
  184. /* DMA */
  185. #define VORTEX_ENGINE_CTRL 0x27ae8
  186. #define ENGINE_INIT 0x1380000
  187. /* MIDI *//* GAME. */
  188. #define VORTEX_MIDI_DATA 0x28800
  189. #define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */
  190. #define VORTEX_CTRL2 0x2880c
  191. #define CTRL2_GAME_ADCMODE 0x40
  192. #define VORTEX_GAME_LEGACY 0x28808
  193. #define VORTEX_GAME_AXIS 0x28810
  194. #define AXIS_SIZE 4
  195. #define AXIS_RANGE 0x1fff