swarm_cs4297a.c 87 KB

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  1. /*******************************************************************************
  2. *
  3. * "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver.
  4. *
  5. * Copyright (C) 2001 Broadcom Corporation.
  6. * Copyright (C) 2000,2001 Cirrus Logic Corp.
  7. * -- adapted from drivers by Thomas Sailer,
  8. * -- but don't bug him; Problems should go to:
  9. * -- tom woller (twoller@crystal.cirrus.com) or
  10. * (audio@crystal.cirrus.com).
  11. * -- adapted from cs4281 PCI driver for cs4297a on
  12. * BCM1250 Synchronous Serial interface
  13. * (Kip Walker, Broadcom Corp.)
  14. * Copyright (C) 2004 Maciej W. Rozycki
  15. * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
  16. *
  17. * This program is free software; you can redistribute it and/or modify
  18. * it under the terms of the GNU General Public License as published by
  19. * the Free Software Foundation; either version 2 of the License, or
  20. * (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  30. *
  31. * Module command line parameters:
  32. * none
  33. *
  34. * Supported devices:
  35. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  36. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  37. * /dev/midi simple MIDI UART interface, no ioctl
  38. *
  39. * Modification History
  40. * 08/20/00 trw - silence and no stopping DAC until release
  41. * 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  42. * 09/18/00 trw - added 16bit only record with conversion
  43. * 09/24/00 trw - added Enhanced Full duplex (separate simultaneous
  44. * capture/playback rates)
  45. * 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin
  46. * libOSSm.so)
  47. * 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  48. * 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  49. * 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  50. * 11/10/00 trw - fixed SMP and capture spinlock hang.
  51. * 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  52. * 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  53. * 12/08/00 trw - added PM support.
  54. * 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8
  55. * (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident.
  56. * 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  57. * 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use
  58. * defaultorder-100 as power of 2 for the buffer size. example:
  59. * 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  60. *
  61. *******************************************************************************/
  62. #include <linux/list.h>
  63. #include <linux/module.h>
  64. #include <linux/string.h>
  65. #include <linux/ioport.h>
  66. #include <linux/sched.h>
  67. #include <linux/delay.h>
  68. #include <linux/sound.h>
  69. #include <linux/slab.h>
  70. #include <linux/soundcard.h>
  71. #include <linux/ac97_codec.h>
  72. #include <linux/pci.h>
  73. #include <linux/bitops.h>
  74. #include <linux/interrupt.h>
  75. #include <linux/init.h>
  76. #include <linux/poll.h>
  77. #include <linux/smp_lock.h>
  78. #include <linux/mutex.h>
  79. #include <linux/kernel.h>
  80. #include <asm/byteorder.h>
  81. #include <asm/dma.h>
  82. #include <asm/io.h>
  83. #include <asm/uaccess.h>
  84. #include <asm/sibyte/sb1250_regs.h>
  85. #include <asm/sibyte/sb1250_int.h>
  86. #include <asm/sibyte/sb1250_dma.h>
  87. #include <asm/sibyte/sb1250_scd.h>
  88. #include <asm/sibyte/sb1250_syncser.h>
  89. #include <asm/sibyte/sb1250_mac.h>
  90. #include <asm/sibyte/sb1250.h>
  91. struct cs4297a_state;
  92. static void stop_dac(struct cs4297a_state *s);
  93. static void stop_adc(struct cs4297a_state *s);
  94. static void start_dac(struct cs4297a_state *s);
  95. static void start_adc(struct cs4297a_state *s);
  96. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  97. // ---------------------------------------------------------------------
  98. #define CS4297a_MAGIC 0xf00beef1
  99. // buffer order determines the size of the dma buffer for the driver.
  100. // under Linux, a smaller buffer allows more responsiveness from many of the
  101. // applications (e.g. games). A larger buffer allows some of the apps (esound)
  102. // to not underrun the dma buffer as easily. As default, use 32k (order=3)
  103. // rather than 64k as some of the games work more responsively.
  104. // log base 2( buff sz = 32k).
  105. //static unsigned long defaultorder = 3;
  106. //MODULE_PARM(defaultorder, "i");
  107. //
  108. // Turn on/off debugging compilation by commenting out "#define CSDEBUG"
  109. //
  110. #define CSDEBUG 0
  111. #if CSDEBUG
  112. #define CSDEBUG_INTERFACE 1
  113. #else
  114. #undef CSDEBUG_INTERFACE
  115. #endif
  116. //
  117. // cs_debugmask areas
  118. //
  119. #define CS_INIT 0x00000001 // initialization and probe functions
  120. #define CS_ERROR 0x00000002 // tmp debugging bit placeholder
  121. #define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other)
  122. #define CS_FUNCTION 0x00000008 // enter/leave functions
  123. #define CS_WAVE_WRITE 0x00000010 // write information for wave
  124. #define CS_WAVE_READ 0x00000020 // read information for wave
  125. #define CS_AC97 0x00000040 // AC97 register access
  126. #define CS_DESCR 0x00000080 // descriptor management
  127. #define CS_OPEN 0x00000400 // all open functions in the driver
  128. #define CS_RELEASE 0x00000800 // all release functions in the driver
  129. #define CS_PARMS 0x00001000 // functional and operational parameters
  130. #define CS_IOCTL 0x00002000 // ioctl (non-mixer)
  131. #define CS_TMP 0x10000000 // tmp debug mask bit
  132. //
  133. // CSDEBUG is usual mode is set to 1, then use the
  134. // cs_debuglevel and cs_debugmask to turn on or off debugging.
  135. // Debug level of 1 has been defined to be kernel errors and info
  136. // that should be printed on any released driver.
  137. //
  138. #if CSDEBUG
  139. #define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
  140. #else
  141. #define CS_DBGOUT(mask,level,x)
  142. #endif
  143. #if CSDEBUG
  144. static unsigned long cs_debuglevel = 4; // levels range from 1-9
  145. static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
  146. module_param(cs_debuglevel, int, 0);
  147. module_param(cs_debugmask, int, 0);
  148. #endif
  149. #define CS_TRUE 1
  150. #define CS_FALSE 0
  151. #define CS_TYPE_ADC 0
  152. #define CS_TYPE_DAC 1
  153. #define SER_BASE (A_SER_BASE_1 + KSEG1)
  154. #define SS_CSR(t) (SER_BASE+t)
  155. #define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
  156. #define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
  157. #define FRAME_BYTES 32
  158. #define FRAME_SAMPLE_BYTES 4
  159. /* Should this be variable? */
  160. #define SAMPLE_BUF_SIZE (16*1024)
  161. #define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
  162. /* The driver can explode/shrink the frames to/from a smaller sample
  163. buffer */
  164. #define DMA_BLOAT_FACTOR 1
  165. #define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
  166. #define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES)
  167. /* Use the maxmium count (255 == 5.1 ms between interrupts) */
  168. #define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1)
  169. /* Figure this out: how many TX DMAs ahead to schedule a reg access */
  170. #define REG_LATENCY 150
  171. #define FRAME_TX_US 20
  172. #define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
  173. static const char invalid_magic[] =
  174. KERN_CRIT "cs4297a: invalid magic value\n";
  175. #define VALIDATE_STATE(s) \
  176. ({ \
  177. if (!(s) || (s)->magic != CS4297a_MAGIC) { \
  178. printk(invalid_magic); \
  179. return -ENXIO; \
  180. } \
  181. })
  182. struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
  183. typedef struct serdma_descr_s {
  184. u64 descr_a;
  185. u64 descr_b;
  186. } serdma_descr_t;
  187. typedef unsigned long paddr_t;
  188. typedef struct serdma_s {
  189. unsigned ringsz;
  190. serdma_descr_t *descrtab;
  191. serdma_descr_t *descrtab_end;
  192. paddr_t descrtab_phys;
  193. serdma_descr_t *descr_add;
  194. serdma_descr_t *descr_rem;
  195. u64 *dma_buf; // buffer for DMA contents (frames)
  196. paddr_t dma_buf_phys;
  197. u16 *sample_buf; // tmp buffer for sample conversions
  198. u16 *sb_swptr;
  199. u16 *sb_hwptr;
  200. u16 *sb_end;
  201. dma_addr_t dmaaddr;
  202. // unsigned buforder; // Log base 2 of 'dma_buf' size in bytes..
  203. unsigned numfrag; // # of 'fragments' in the buffer.
  204. unsigned fragshift; // Log base 2 of fragment size.
  205. unsigned hwptr, swptr;
  206. unsigned total_bytes; // # bytes process since open.
  207. unsigned blocks; // last returned blocks value GETOPTR
  208. unsigned wakeup; // interrupt occurred on block
  209. int count;
  210. unsigned underrun; // underrun flag
  211. unsigned error; // over/underrun
  212. wait_queue_head_t wait;
  213. wait_queue_head_t reg_wait;
  214. // redundant, but makes calculations easier
  215. unsigned fragsize; // 2**fragshift..
  216. unsigned sbufsz; // 2**buforder.
  217. unsigned fragsamples;
  218. // OSS stuff
  219. unsigned mapped:1; // Buffer mapped in cs4297a_mmap()?
  220. unsigned ready:1; // prog_dmabuf_dac()/adc() successful?
  221. unsigned endcleared:1;
  222. unsigned type:1; // adc or dac buffer (CS_TYPE_XXX)
  223. unsigned ossfragshift;
  224. int ossmaxfrags;
  225. unsigned subdivision;
  226. } serdma_t;
  227. struct cs4297a_state {
  228. // magic
  229. unsigned int magic;
  230. struct list_head list;
  231. // soundcore stuff
  232. int dev_audio;
  233. int dev_mixer;
  234. // hardware resources
  235. unsigned int irq;
  236. struct {
  237. unsigned int rx_ovrrn; /* FIFO */
  238. unsigned int rx_overflow; /* staging buffer */
  239. unsigned int tx_underrun;
  240. unsigned int rx_bad;
  241. unsigned int rx_good;
  242. } stats;
  243. // mixer registers
  244. struct {
  245. unsigned short vol[10];
  246. unsigned int recsrc;
  247. unsigned int modcnt;
  248. unsigned short micpreamp;
  249. } mix;
  250. // wave stuff
  251. struct properties {
  252. unsigned fmt;
  253. unsigned fmt_original; // original requested format
  254. unsigned channels;
  255. unsigned rate;
  256. } prop_dac, prop_adc;
  257. unsigned conversion:1; // conversion from 16 to 8 bit in progress
  258. unsigned ena;
  259. spinlock_t lock;
  260. struct mutex open_mutex;
  261. struct mutex open_sem_adc;
  262. struct mutex open_sem_dac;
  263. mode_t open_mode;
  264. wait_queue_head_t open_wait;
  265. wait_queue_head_t open_wait_adc;
  266. wait_queue_head_t open_wait_dac;
  267. dma_addr_t dmaaddr_sample_buf;
  268. unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes..
  269. serdma_t dma_dac, dma_adc;
  270. volatile u16 read_value;
  271. volatile u16 read_reg;
  272. volatile u64 reg_request;
  273. };
  274. #if 1
  275. #define prog_codec(a,b)
  276. #define dealloc_dmabuf(a,b);
  277. #endif
  278. static int prog_dmabuf_adc(struct cs4297a_state *s)
  279. {
  280. s->dma_adc.ready = 1;
  281. return 0;
  282. }
  283. static int prog_dmabuf_dac(struct cs4297a_state *s)
  284. {
  285. s->dma_dac.ready = 1;
  286. return 0;
  287. }
  288. static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
  289. unsigned len, unsigned char c)
  290. {
  291. if (bptr + len > bsize) {
  292. unsigned x = bsize - bptr;
  293. memset(((char *) buf) + bptr, c, x);
  294. bptr = 0;
  295. len -= x;
  296. }
  297. CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
  298. "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
  299. (unsigned)c, (unsigned)((char *) buf) + bptr, len));
  300. memset(((char *) buf) + bptr, c, len);
  301. }
  302. #if CSDEBUG
  303. // DEBUG ROUTINES
  304. #define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int)
  305. #define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int)
  306. #define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int)
  307. #define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int)
  308. static void cs_printioctl(unsigned int x)
  309. {
  310. unsigned int i;
  311. unsigned char vidx;
  312. // Index of mixtable1[] member is Device ID
  313. // and must be <= SOUND_MIXER_NRDEVICES.
  314. // Value of array member is index into s->mix.vol[]
  315. static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
  316. [SOUND_MIXER_PCM] = 1, // voice
  317. [SOUND_MIXER_LINE1] = 2, // AUX
  318. [SOUND_MIXER_CD] = 3, // CD
  319. [SOUND_MIXER_LINE] = 4, // Line
  320. [SOUND_MIXER_SYNTH] = 5, // FM
  321. [SOUND_MIXER_MIC] = 6, // Mic
  322. [SOUND_MIXER_SPEAKER] = 7, // Speaker
  323. [SOUND_MIXER_RECLEV] = 8, // Recording level
  324. [SOUND_MIXER_VOLUME] = 9 // Master Volume
  325. };
  326. switch (x) {
  327. case SOUND_MIXER_CS_GETDBGMASK:
  328. CS_DBGOUT(CS_IOCTL, 4,
  329. printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
  330. break;
  331. case SOUND_MIXER_CS_GETDBGLEVEL:
  332. CS_DBGOUT(CS_IOCTL, 4,
  333. printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
  334. break;
  335. case SOUND_MIXER_CS_SETDBGMASK:
  336. CS_DBGOUT(CS_IOCTL, 4,
  337. printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
  338. break;
  339. case SOUND_MIXER_CS_SETDBGLEVEL:
  340. CS_DBGOUT(CS_IOCTL, 4,
  341. printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
  342. break;
  343. case OSS_GETVERSION:
  344. CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
  345. break;
  346. case SNDCTL_DSP_SYNC:
  347. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
  348. break;
  349. case SNDCTL_DSP_SETDUPLEX:
  350. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
  351. break;
  352. case SNDCTL_DSP_GETCAPS:
  353. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
  354. break;
  355. case SNDCTL_DSP_RESET:
  356. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
  357. break;
  358. case SNDCTL_DSP_SPEED:
  359. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
  360. break;
  361. case SNDCTL_DSP_STEREO:
  362. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
  363. break;
  364. case SNDCTL_DSP_CHANNELS:
  365. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
  366. break;
  367. case SNDCTL_DSP_GETFMTS:
  368. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
  369. break;
  370. case SNDCTL_DSP_SETFMT:
  371. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
  372. break;
  373. case SNDCTL_DSP_POST:
  374. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
  375. break;
  376. case SNDCTL_DSP_GETTRIGGER:
  377. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
  378. break;
  379. case SNDCTL_DSP_SETTRIGGER:
  380. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
  381. break;
  382. case SNDCTL_DSP_GETOSPACE:
  383. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
  384. break;
  385. case SNDCTL_DSP_GETISPACE:
  386. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
  387. break;
  388. case SNDCTL_DSP_NONBLOCK:
  389. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
  390. break;
  391. case SNDCTL_DSP_GETODELAY:
  392. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
  393. break;
  394. case SNDCTL_DSP_GETIPTR:
  395. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
  396. break;
  397. case SNDCTL_DSP_GETOPTR:
  398. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
  399. break;
  400. case SNDCTL_DSP_GETBLKSIZE:
  401. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
  402. break;
  403. case SNDCTL_DSP_SETFRAGMENT:
  404. CS_DBGOUT(CS_IOCTL, 4,
  405. printk("SNDCTL_DSP_SETFRAGMENT:\n"));
  406. break;
  407. case SNDCTL_DSP_SUBDIVIDE:
  408. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
  409. break;
  410. case SOUND_PCM_READ_RATE:
  411. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
  412. break;
  413. case SOUND_PCM_READ_CHANNELS:
  414. CS_DBGOUT(CS_IOCTL, 4,
  415. printk("SOUND_PCM_READ_CHANNELS:\n"));
  416. break;
  417. case SOUND_PCM_READ_BITS:
  418. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
  419. break;
  420. case SOUND_PCM_WRITE_FILTER:
  421. CS_DBGOUT(CS_IOCTL, 4,
  422. printk("SOUND_PCM_WRITE_FILTER:\n"));
  423. break;
  424. case SNDCTL_DSP_SETSYNCRO:
  425. CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
  426. break;
  427. case SOUND_PCM_READ_FILTER:
  428. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
  429. break;
  430. case SOUND_MIXER_PRIVATE1:
  431. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
  432. break;
  433. case SOUND_MIXER_PRIVATE2:
  434. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
  435. break;
  436. case SOUND_MIXER_PRIVATE3:
  437. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
  438. break;
  439. case SOUND_MIXER_PRIVATE4:
  440. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
  441. break;
  442. case SOUND_MIXER_PRIVATE5:
  443. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
  444. break;
  445. case SOUND_MIXER_INFO:
  446. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
  447. break;
  448. case SOUND_OLD_MIXER_INFO:
  449. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
  450. break;
  451. default:
  452. switch (_IOC_NR(x)) {
  453. case SOUND_MIXER_VOLUME:
  454. CS_DBGOUT(CS_IOCTL, 4,
  455. printk("SOUND_MIXER_VOLUME:\n"));
  456. break;
  457. case SOUND_MIXER_SPEAKER:
  458. CS_DBGOUT(CS_IOCTL, 4,
  459. printk("SOUND_MIXER_SPEAKER:\n"));
  460. break;
  461. case SOUND_MIXER_RECLEV:
  462. CS_DBGOUT(CS_IOCTL, 4,
  463. printk("SOUND_MIXER_RECLEV:\n"));
  464. break;
  465. case SOUND_MIXER_MIC:
  466. CS_DBGOUT(CS_IOCTL, 4,
  467. printk("SOUND_MIXER_MIC:\n"));
  468. break;
  469. case SOUND_MIXER_SYNTH:
  470. CS_DBGOUT(CS_IOCTL, 4,
  471. printk("SOUND_MIXER_SYNTH:\n"));
  472. break;
  473. case SOUND_MIXER_RECSRC:
  474. CS_DBGOUT(CS_IOCTL, 4,
  475. printk("SOUND_MIXER_RECSRC:\n"));
  476. break;
  477. case SOUND_MIXER_DEVMASK:
  478. CS_DBGOUT(CS_IOCTL, 4,
  479. printk("SOUND_MIXER_DEVMASK:\n"));
  480. break;
  481. case SOUND_MIXER_RECMASK:
  482. CS_DBGOUT(CS_IOCTL, 4,
  483. printk("SOUND_MIXER_RECMASK:\n"));
  484. break;
  485. case SOUND_MIXER_STEREODEVS:
  486. CS_DBGOUT(CS_IOCTL, 4,
  487. printk("SOUND_MIXER_STEREODEVS:\n"));
  488. break;
  489. case SOUND_MIXER_CAPS:
  490. CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
  491. break;
  492. default:
  493. i = _IOC_NR(x);
  494. if (i >= SOUND_MIXER_NRDEVICES
  495. || !(vidx = mixtable1[i])) {
  496. CS_DBGOUT(CS_IOCTL, 4, printk
  497. ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
  498. x, i));
  499. } else {
  500. CS_DBGOUT(CS_IOCTL, 4, printk
  501. ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
  502. x, i));
  503. }
  504. break;
  505. }
  506. }
  507. }
  508. #endif
  509. static int ser_init(struct cs4297a_state *s)
  510. {
  511. int i;
  512. CS_DBGOUT(CS_INIT, 2,
  513. printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
  514. __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
  515. __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
  516. __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ));
  517. __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ));
  518. __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH));
  519. __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH));
  520. __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH));
  521. /* This looks good from experimentation */
  522. __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
  523. M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
  524. SS_CSR(R_SER_LINE_MODE));
  525. /* This looks good from experimentation */
  526. __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
  527. SS_TXTBL(0));
  528. __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
  529. SS_TXTBL(1));
  530. __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
  531. SS_TXTBL(2));
  532. __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
  533. M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
  534. __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
  535. SS_RXTBL(0));
  536. __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
  537. SS_RXTBL(1));
  538. __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
  539. SS_RXTBL(2));
  540. __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
  541. M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
  542. for (i=4; i<16; i++) {
  543. /* Just in case... */
  544. __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
  545. __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
  546. }
  547. return 0;
  548. }
  549. static int init_serdma(serdma_t *dma)
  550. {
  551. CS_DBGOUT(CS_INIT, 2,
  552. printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
  553. DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
  554. /* Descriptors */
  555. dma->ringsz = DMA_DESCR;
  556. dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
  557. if (!dma->descrtab) {
  558. printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n");
  559. return -1;
  560. }
  561. dma->descrtab_end = dma->descrtab + dma->ringsz;
  562. /* XXX bloddy mess, use proper DMA API here ... */
  563. dma->descrtab_phys = CPHYSADDR((long)dma->descrtab);
  564. dma->descr_add = dma->descr_rem = dma->descrtab;
  565. /* Frame buffer area */
  566. dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL);
  567. if (!dma->dma_buf) {
  568. printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n");
  569. kfree(dma->descrtab);
  570. return -1;
  571. }
  572. dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf);
  573. /* Samples buffer area */
  574. dma->sbufsz = SAMPLE_BUF_SIZE;
  575. dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
  576. if (!dma->sample_buf) {
  577. printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
  578. kfree(dma->descrtab);
  579. kfree(dma->dma_buf);
  580. return -1;
  581. }
  582. dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
  583. dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
  584. dma->fragsize = dma->sbufsz >> 1;
  585. CS_DBGOUT(CS_INIT, 4,
  586. printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
  587. (int)dma->descrtab, (int)dma->dma_buf,
  588. (int)dma->sample_buf));
  589. return 0;
  590. }
  591. static int dma_init(struct cs4297a_state *s)
  592. {
  593. int i;
  594. CS_DBGOUT(CS_INIT, 2,
  595. printk(KERN_INFO "cs4297a: Setting up DMA\n"));
  596. if (init_serdma(&s->dma_adc) ||
  597. init_serdma(&s->dma_dac))
  598. return -1;
  599. if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
  600. __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
  601. panic("DMA state corrupted?!");
  602. }
  603. /* Initialize now - the descr/buffer pairings will never
  604. change... */
  605. for (i=0; i<DMA_DESCR; i++) {
  606. s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) |
  607. (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
  608. s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
  609. s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
  610. (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
  611. s->dma_adc.descrtab[i].descr_b = 0;
  612. }
  613. __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
  614. V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
  615. SS_CSR(R_SER_DMA_CONFIG0_RX));
  616. __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
  617. __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
  618. __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
  619. __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
  620. __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
  621. /* Prep the receive DMA descriptor ring */
  622. __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
  623. __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
  624. __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
  625. SS_CSR(R_SER_INT_MASK));
  626. /* Enable the rx/tx; let the codec warm up to the sync and
  627. start sending good frames before the receive FIFO is
  628. enabled */
  629. __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
  630. udelay(1000);
  631. __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
  632. /* XXXKW is this magic? (the "1" part) */
  633. while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
  634. ;
  635. CS_DBGOUT(CS_INIT, 4,
  636. printk(KERN_INFO "cs4297a: status: %08x\n",
  637. (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
  638. return 0;
  639. }
  640. static int serdma_reg_access(struct cs4297a_state *s, u64 data)
  641. {
  642. serdma_t *d = &s->dma_dac;
  643. u64 *data_p;
  644. unsigned swptr;
  645. unsigned long flags;
  646. serdma_descr_t *descr;
  647. if (s->reg_request) {
  648. printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
  649. return -1;
  650. }
  651. if (s->ena & FMODE_WRITE) {
  652. /* Since a writer has the DSP open, we have to mux the
  653. request in */
  654. s->reg_request = data;
  655. interruptible_sleep_on(&s->dma_dac.reg_wait);
  656. /* XXXKW how can I deal with the starvation case where
  657. the opener isn't writing? */
  658. } else {
  659. /* Be safe when changing ring pointers */
  660. spin_lock_irqsave(&s->lock, flags);
  661. if (d->hwptr != d->swptr) {
  662. printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
  663. d->hwptr, d->swptr);
  664. spin_unlock_irqrestore(&s->lock, flags);
  665. return -1;
  666. }
  667. swptr = d->swptr;
  668. d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
  669. spin_unlock_irqrestore(&s->lock, flags);
  670. descr = &d->descrtab[swptr];
  671. data_p = &d->dma_buf[swptr * 4];
  672. *data_p = cpu_to_be64(data);
  673. __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
  674. CS_DBGOUT(CS_DESCR, 4,
  675. printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n",
  676. data_p, swptr, d->hwptr));
  677. }
  678. CS_DBGOUT(CS_FUNCTION, 6,
  679. printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
  680. return 0;
  681. }
  682. //****************************************************************************
  683. // "cs4297a_read_ac97" -- Reads an AC97 register
  684. //****************************************************************************
  685. static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
  686. u32 * value)
  687. {
  688. CS_DBGOUT(CS_AC97, 1,
  689. printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
  690. if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
  691. return -1;
  692. interruptible_sleep_on(&s->dma_adc.reg_wait);
  693. *value = s->read_value;
  694. CS_DBGOUT(CS_AC97, 2,
  695. printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
  696. return 0;
  697. }
  698. //****************************************************************************
  699. // "cs4297a_write_ac97()"-- writes an AC97 register
  700. //****************************************************************************
  701. static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
  702. u32 value)
  703. {
  704. CS_DBGOUT(CS_AC97, 1,
  705. printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
  706. return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
  707. }
  708. static void stop_dac(struct cs4297a_state *s)
  709. {
  710. unsigned long flags;
  711. CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
  712. spin_lock_irqsave(&s->lock, flags);
  713. s->ena &= ~FMODE_WRITE;
  714. #if 0
  715. /* XXXKW what do I really want here? My theory for now is
  716. that I just flip the "ena" bit, and the interrupt handler
  717. will stop processing the xmit channel */
  718. __raw_writeq((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
  719. SS_CSR(R_SER_DMA_ENABLE));
  720. #endif
  721. spin_unlock_irqrestore(&s->lock, flags);
  722. }
  723. static void start_dac(struct cs4297a_state *s)
  724. {
  725. unsigned long flags;
  726. CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
  727. spin_lock_irqsave(&s->lock, flags);
  728. if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
  729. (s->dma_dac.count > 0
  730. && s->dma_dac.ready))) {
  731. s->ena |= FMODE_WRITE;
  732. /* XXXKW what do I really want here? My theory for
  733. now is that I just flip the "ena" bit, and the
  734. interrupt handler will start processing the xmit
  735. channel */
  736. CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
  737. "cs4297a: start_dac(): start dma\n"));
  738. }
  739. spin_unlock_irqrestore(&s->lock, flags);
  740. CS_DBGOUT(CS_FUNCTION, 3,
  741. printk(KERN_INFO "cs4297a: start_dac()-\n"));
  742. }
  743. static void stop_adc(struct cs4297a_state *s)
  744. {
  745. unsigned long flags;
  746. CS_DBGOUT(CS_FUNCTION, 3,
  747. printk(KERN_INFO "cs4297a: stop_adc()+\n"));
  748. spin_lock_irqsave(&s->lock, flags);
  749. s->ena &= ~FMODE_READ;
  750. if (s->conversion == 1) {
  751. s->conversion = 0;
  752. s->prop_adc.fmt = s->prop_adc.fmt_original;
  753. }
  754. /* Nothing to do really, I need to keep the DMA going
  755. XXXKW when do I get here, and is there more I should do? */
  756. spin_unlock_irqrestore(&s->lock, flags);
  757. CS_DBGOUT(CS_FUNCTION, 3,
  758. printk(KERN_INFO "cs4297a: stop_adc()-\n"));
  759. }
  760. static void start_adc(struct cs4297a_state *s)
  761. {
  762. unsigned long flags;
  763. CS_DBGOUT(CS_FUNCTION, 2,
  764. printk(KERN_INFO "cs4297a: start_adc()+\n"));
  765. if (!(s->ena & FMODE_READ) &&
  766. (s->dma_adc.mapped || s->dma_adc.count <=
  767. (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
  768. && s->dma_adc.ready) {
  769. if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
  770. //
  771. // now only use 16 bit capture, due to truncation issue
  772. // in the chip, noticable distortion occurs.
  773. // allocate buffer and then convert from 16 bit to
  774. // 8 bit for the user buffer.
  775. //
  776. s->prop_adc.fmt_original = s->prop_adc.fmt;
  777. if (s->prop_adc.fmt & AFMT_S8) {
  778. s->prop_adc.fmt &= ~AFMT_S8;
  779. s->prop_adc.fmt |= AFMT_S16_LE;
  780. }
  781. if (s->prop_adc.fmt & AFMT_U8) {
  782. s->prop_adc.fmt &= ~AFMT_U8;
  783. s->prop_adc.fmt |= AFMT_U16_LE;
  784. }
  785. //
  786. // prog_dmabuf_adc performs a stop_adc() but that is
  787. // ok since we really haven't started the DMA yet.
  788. //
  789. prog_codec(s, CS_TYPE_ADC);
  790. prog_dmabuf_adc(s);
  791. s->conversion = 1;
  792. }
  793. spin_lock_irqsave(&s->lock, flags);
  794. s->ena |= FMODE_READ;
  795. /* Nothing to do really, I am probably already
  796. DMAing... XXXKW when do I get here, and is there
  797. more I should do? */
  798. spin_unlock_irqrestore(&s->lock, flags);
  799. CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
  800. "cs4297a: start_adc(): start adc\n"));
  801. }
  802. CS_DBGOUT(CS_FUNCTION, 2,
  803. printk(KERN_INFO "cs4297a: start_adc()-\n"));
  804. }
  805. // call with spinlock held!
  806. static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
  807. {
  808. int good_diff, diff, diff2;
  809. u64 *data_p, data;
  810. u32 *s_ptr;
  811. unsigned hwptr;
  812. u32 status;
  813. serdma_t *d;
  814. serdma_descr_t *descr;
  815. // update ADC pointer
  816. status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0;
  817. if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
  818. d = &s->dma_adc;
  819. hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
  820. d->descrtab_phys) / sizeof(serdma_descr_t));
  821. if (s->ena & FMODE_READ) {
  822. CS_DBGOUT(CS_FUNCTION, 2,
  823. printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
  824. d->swptr, d->hwptr, hwptr, intflag));
  825. /* Number of DMA buffers available for software: */
  826. diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
  827. d->hwptr = hwptr;
  828. good_diff = 0;
  829. s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
  830. descr = &d->descrtab[d->swptr];
  831. while (diff2--) {
  832. u64 data = be64_to_cpu(*(u64 *)s_ptr);
  833. u64 descr_a;
  834. u16 left, right;
  835. descr_a = descr->descr_a;
  836. descr->descr_a &= ~M_DMA_SERRX_SOP;
  837. if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) {
  838. printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
  839. }
  840. if (((data & 0x9800000000000000) != 0x9800000000000000) ||
  841. (!(descr_a & M_DMA_SERRX_SOP)) ||
  842. (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
  843. s->stats.rx_bad++;
  844. printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
  845. continue;
  846. }
  847. s->stats.rx_good++;
  848. if ((data >> 61) == 7) {
  849. s->read_value = (data >> 12) & 0xffff;
  850. s->read_reg = (data >> 40) & 0x7f;
  851. wake_up(&d->reg_wait);
  852. }
  853. if (d->count && (d->sb_hwptr == d->sb_swptr)) {
  854. s->stats.rx_overflow++;
  855. printk(KERN_DEBUG "cs4297a: RX overflow\n");
  856. continue;
  857. }
  858. good_diff++;
  859. left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
  860. ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
  861. right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
  862. *d->sb_hwptr++ = cpu_to_be16(left);
  863. *d->sb_hwptr++ = cpu_to_be16(right);
  864. if (d->sb_hwptr == d->sb_end)
  865. d->sb_hwptr = d->sample_buf;
  866. descr++;
  867. if (descr == d->descrtab_end) {
  868. descr = d->descrtab;
  869. s_ptr = (u32 *)s->dma_adc.dma_buf;
  870. } else {
  871. s_ptr += 8;
  872. }
  873. }
  874. d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
  875. d->count += good_diff * FRAME_SAMPLE_BYTES;
  876. if (d->count > d->sbufsz) {
  877. printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
  878. }
  879. d->swptr = (d->swptr + diff) % d->ringsz;
  880. __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
  881. if (d->mapped) {
  882. if (d->count >= (signed) d->fragsize)
  883. wake_up(&d->wait);
  884. } else {
  885. if (d->count > 0) {
  886. CS_DBGOUT(CS_WAVE_READ, 4,
  887. printk(KERN_INFO
  888. "cs4297a: update count -> %d\n", d->count));
  889. wake_up(&d->wait);
  890. }
  891. }
  892. } else {
  893. /* Receive is going even if no one is
  894. listening (for register accesses and to
  895. avoid FIFO overrun) */
  896. diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
  897. if (!diff) {
  898. printk(KERN_ERR "cs4297a: RX full or empty?\n");
  899. }
  900. descr = &d->descrtab[d->swptr];
  901. data_p = &d->dma_buf[d->swptr*4];
  902. /* Force this to happen at least once; I got
  903. here because of an interrupt, so there must
  904. be a buffer to process. */
  905. do {
  906. data = be64_to_cpu(*data_p);
  907. if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) {
  908. printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
  909. (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
  910. (long)CPHYSADDR((long)data_p));
  911. }
  912. if (!(data & (1LL << 63)) ||
  913. !(descr->descr_a & M_DMA_SERRX_SOP) ||
  914. (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
  915. s->stats.rx_bad++;
  916. printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
  917. } else {
  918. s->stats.rx_good++;
  919. if ((data >> 61) == 7) {
  920. s->read_value = (data >> 12) & 0xffff;
  921. s->read_reg = (data >> 40) & 0x7f;
  922. wake_up(&d->reg_wait);
  923. }
  924. }
  925. descr->descr_a &= ~M_DMA_SERRX_SOP;
  926. descr++;
  927. d->swptr++;
  928. data_p += 4;
  929. if (descr == d->descrtab_end) {
  930. descr = d->descrtab;
  931. d->swptr = 0;
  932. data_p = d->dma_buf;
  933. }
  934. __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
  935. } while (--diff);
  936. d->hwptr = hwptr;
  937. CS_DBGOUT(CS_DESCR, 6,
  938. printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
  939. }
  940. CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
  941. "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
  942. (unsigned)s, d->hwptr,
  943. d->total_bytes, d->count));
  944. }
  945. /* XXXKW worry about s->reg_request -- there is a starvation
  946. case if s->ena has FMODE_WRITE on, but the client isn't
  947. doing writes */
  948. // update DAC pointer
  949. //
  950. // check for end of buffer, means that we are going to wait for another interrupt
  951. // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
  952. //
  953. if (s->ena & FMODE_WRITE) {
  954. serdma_t *d = &s->dma_dac;
  955. hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
  956. d->descrtab_phys) / sizeof(serdma_descr_t));
  957. diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
  958. CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
  959. "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
  960. d->hwptr, hwptr, d->swptr, diff, d->count));
  961. d->hwptr = hwptr;
  962. /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
  963. d->total_bytes += diff * FRAME_SAMPLE_BYTES;
  964. if (d->mapped) {
  965. d->count += diff * FRAME_SAMPLE_BYTES;
  966. if (d->count >= d->fragsize) {
  967. d->wakeup = 1;
  968. wake_up(&d->wait);
  969. if (d->count > d->sbufsz)
  970. d->count &= d->sbufsz - 1;
  971. }
  972. } else {
  973. d->count -= diff * FRAME_SAMPLE_BYTES;
  974. if (d->count <= 0) {
  975. //
  976. // fill with silence, and do not shut down the DAC.
  977. // Continue to play silence until the _release.
  978. //
  979. CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
  980. "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
  981. (unsigned)(s->prop_dac.fmt &
  982. (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
  983. (unsigned)d->dma_buf,
  984. d->ringsz));
  985. memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
  986. if (d->count < 0) {
  987. d->underrun = 1;
  988. s->stats.tx_underrun++;
  989. d->count = 0;
  990. CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
  991. "cs4297a: cs4297a_update_ptr(): underrun\n"));
  992. }
  993. } else if (d->count <=
  994. (signed) d->fragsize
  995. && !d->endcleared) {
  996. /* XXXKW what is this for? */
  997. clear_advance(d->dma_buf,
  998. d->sbufsz,
  999. d->swptr,
  1000. d->fragsize,
  1001. 0);
  1002. d->endcleared = 1;
  1003. }
  1004. if ( (d->count <= (signed) d->sbufsz/2) || intflag)
  1005. {
  1006. CS_DBGOUT(CS_WAVE_WRITE, 4,
  1007. printk(KERN_INFO
  1008. "cs4297a: update count -> %d\n", d->count));
  1009. wake_up(&d->wait);
  1010. }
  1011. }
  1012. CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
  1013. "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
  1014. (unsigned) s, d->hwptr,
  1015. d->total_bytes, d->count));
  1016. }
  1017. }
  1018. static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
  1019. unsigned long arg)
  1020. {
  1021. // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
  1022. // Value of array member is recording source Device ID Mask.
  1023. static const unsigned int mixer_src[8] = {
  1024. SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
  1025. SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
  1026. };
  1027. // Index of mixtable1[] member is Device ID
  1028. // and must be <= SOUND_MIXER_NRDEVICES.
  1029. // Value of array member is index into s->mix.vol[]
  1030. static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
  1031. [SOUND_MIXER_PCM] = 1, // voice
  1032. [SOUND_MIXER_LINE1] = 2, // AUX
  1033. [SOUND_MIXER_CD] = 3, // CD
  1034. [SOUND_MIXER_LINE] = 4, // Line
  1035. [SOUND_MIXER_SYNTH] = 5, // FM
  1036. [SOUND_MIXER_MIC] = 6, // Mic
  1037. [SOUND_MIXER_SPEAKER] = 7, // Speaker
  1038. [SOUND_MIXER_RECLEV] = 8, // Recording level
  1039. [SOUND_MIXER_VOLUME] = 9 // Master Volume
  1040. };
  1041. static const unsigned mixreg[] = {
  1042. AC97_PCMOUT_VOL,
  1043. AC97_AUX_VOL,
  1044. AC97_CD_VOL,
  1045. AC97_LINEIN_VOL
  1046. };
  1047. unsigned char l, r, rl, rr, vidx;
  1048. unsigned char attentbl[11] =
  1049. { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
  1050. unsigned temp1;
  1051. int i, val;
  1052. VALIDATE_STATE(s);
  1053. CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
  1054. "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
  1055. (unsigned) s, cmd));
  1056. #if CSDEBUG
  1057. cs_printioctl(cmd);
  1058. #endif
  1059. #if CSDEBUG_INTERFACE
  1060. if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
  1061. (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
  1062. (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
  1063. (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
  1064. {
  1065. switch (cmd) {
  1066. case SOUND_MIXER_CS_GETDBGMASK:
  1067. return put_user(cs_debugmask,
  1068. (unsigned long *) arg);
  1069. case SOUND_MIXER_CS_GETDBGLEVEL:
  1070. return put_user(cs_debuglevel,
  1071. (unsigned long *) arg);
  1072. case SOUND_MIXER_CS_SETDBGMASK:
  1073. if (get_user(val, (unsigned long *) arg))
  1074. return -EFAULT;
  1075. cs_debugmask = val;
  1076. return 0;
  1077. case SOUND_MIXER_CS_SETDBGLEVEL:
  1078. if (get_user(val, (unsigned long *) arg))
  1079. return -EFAULT;
  1080. cs_debuglevel = val;
  1081. return 0;
  1082. default:
  1083. CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
  1084. "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
  1085. return 0;
  1086. }
  1087. }
  1088. #endif
  1089. if (cmd == SOUND_MIXER_PRIVATE1) {
  1090. return -EINVAL;
  1091. }
  1092. if (cmd == SOUND_MIXER_PRIVATE2) {
  1093. // enable/disable/query spatializer
  1094. if (get_user(val, (int *) arg))
  1095. return -EFAULT;
  1096. if (val != -1) {
  1097. temp1 = (val & 0x3f) >> 2;
  1098. cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
  1099. cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
  1100. &temp1);
  1101. cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
  1102. temp1 | 0x2000);
  1103. }
  1104. cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
  1105. return put_user((temp1 << 2) | 3, (int *) arg);
  1106. }
  1107. if (cmd == SOUND_MIXER_INFO) {
  1108. mixer_info info;
  1109. memset(&info, 0, sizeof(info));
  1110. strlcpy(info.id, "CS4297a", sizeof(info.id));
  1111. strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
  1112. info.modify_counter = s->mix.modcnt;
  1113. if (copy_to_user((void *) arg, &info, sizeof(info)))
  1114. return -EFAULT;
  1115. return 0;
  1116. }
  1117. if (cmd == SOUND_OLD_MIXER_INFO) {
  1118. _old_mixer_info info;
  1119. memset(&info, 0, sizeof(info));
  1120. strlcpy(info.id, "CS4297a", sizeof(info.id));
  1121. strlcpy(info.name, "Crystal CS4297a", sizeof(info.name));
  1122. if (copy_to_user((void *) arg, &info, sizeof(info)))
  1123. return -EFAULT;
  1124. return 0;
  1125. }
  1126. if (cmd == OSS_GETVERSION)
  1127. return put_user(SOUND_VERSION, (int *) arg);
  1128. if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
  1129. return -EINVAL;
  1130. // If ioctl has only the SIOC_READ bit(bit 31)
  1131. // on, process the only-read commands.
  1132. if (_SIOC_DIR(cmd) == _SIOC_READ) {
  1133. switch (_IOC_NR(cmd)) {
  1134. case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
  1135. cs4297a_read_ac97(s, AC97_RECORD_SELECT,
  1136. &temp1);
  1137. return put_user(mixer_src[temp1 & 7], (int *) arg);
  1138. case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device
  1139. return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
  1140. SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
  1141. (int *) arg);
  1142. case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source
  1143. return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
  1144. (int *) arg);
  1145. case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo
  1146. return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
  1147. SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
  1148. (int *) arg);
  1149. case SOUND_MIXER_CAPS:
  1150. return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
  1151. default:
  1152. i = _IOC_NR(cmd);
  1153. if (i >= SOUND_MIXER_NRDEVICES
  1154. || !(vidx = mixtable1[i]))
  1155. return -EINVAL;
  1156. return put_user(s->mix.vol[vidx - 1], (int *) arg);
  1157. }
  1158. }
  1159. // If ioctl doesn't have both the SIOC_READ and
  1160. // the SIOC_WRITE bit set, return invalid.
  1161. if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
  1162. return -EINVAL;
  1163. // Increment the count of volume writes.
  1164. s->mix.modcnt++;
  1165. // Isolate the command; it must be a write.
  1166. switch (_IOC_NR(cmd)) {
  1167. case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source
  1168. if (get_user(val, (int *) arg))
  1169. return -EFAULT;
  1170. i = hweight32(val); // i = # bits on in val.
  1171. if (i != 1) // One & only 1 bit must be on.
  1172. return 0;
  1173. for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
  1174. if (val == mixer_src[i]) {
  1175. temp1 = (i << 8) | i;
  1176. cs4297a_write_ac97(s,
  1177. AC97_RECORD_SELECT,
  1178. temp1);
  1179. return 0;
  1180. }
  1181. }
  1182. return 0;
  1183. case SOUND_MIXER_VOLUME:
  1184. if (get_user(val, (int *) arg))
  1185. return -EFAULT;
  1186. l = val & 0xff;
  1187. if (l > 100)
  1188. l = 100; // Max soundcard.h vol is 100.
  1189. if (l < 6) {
  1190. rl = 63;
  1191. l = 0;
  1192. } else
  1193. rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten.
  1194. r = (val >> 8) & 0xff;
  1195. if (r > 100)
  1196. r = 100; // Max right volume is 100, too
  1197. if (r < 6) {
  1198. rr = 63;
  1199. r = 0;
  1200. } else
  1201. rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation.
  1202. if ((rl > 60) && (rr > 60)) // If both l & r are 'low',
  1203. temp1 = 0x8000; // turn on the mute bit.
  1204. else
  1205. temp1 = 0;
  1206. temp1 |= (rl << 8) | rr;
  1207. cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
  1208. cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
  1209. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1210. s->mix.vol[8] = ((unsigned int) r << 8) | l;
  1211. #else
  1212. s->mix.vol[8] = val;
  1213. #endif
  1214. return put_user(s->mix.vol[8], (int *) arg);
  1215. case SOUND_MIXER_SPEAKER:
  1216. if (get_user(val, (int *) arg))
  1217. return -EFAULT;
  1218. l = val & 0xff;
  1219. if (l > 100)
  1220. l = 100;
  1221. if (l < 3) {
  1222. rl = 0;
  1223. l = 0;
  1224. } else {
  1225. rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15.
  1226. l = (rl * 13 + 5) / 2;
  1227. }
  1228. if (rl < 3) {
  1229. temp1 = 0x8000;
  1230. rl = 0;
  1231. } else
  1232. temp1 = 0;
  1233. rl = 15 - rl; // Convert volume to attenuation.
  1234. temp1 |= rl << 1;
  1235. cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
  1236. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1237. s->mix.vol[6] = l << 8;
  1238. #else
  1239. s->mix.vol[6] = val;
  1240. #endif
  1241. return put_user(s->mix.vol[6], (int *) arg);
  1242. case SOUND_MIXER_RECLEV:
  1243. if (get_user(val, (int *) arg))
  1244. return -EFAULT;
  1245. l = val & 0xff;
  1246. if (l > 100)
  1247. l = 100;
  1248. r = (val >> 8) & 0xff;
  1249. if (r > 100)
  1250. r = 100;
  1251. rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15.
  1252. rr = (r * 2 - 5) / 13;
  1253. if (rl < 3 && rr < 3)
  1254. temp1 = 0x8000;
  1255. else
  1256. temp1 = 0;
  1257. temp1 = temp1 | (rl << 8) | rr;
  1258. cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
  1259. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1260. s->mix.vol[7] = ((unsigned int) r << 8) | l;
  1261. #else
  1262. s->mix.vol[7] = val;
  1263. #endif
  1264. return put_user(s->mix.vol[7], (int *) arg);
  1265. case SOUND_MIXER_MIC:
  1266. if (get_user(val, (int *) arg))
  1267. return -EFAULT;
  1268. l = val & 0xff;
  1269. if (l > 100)
  1270. l = 100;
  1271. if (l < 1) {
  1272. l = 0;
  1273. rl = 0;
  1274. } else {
  1275. rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31.
  1276. l = (rl * 16 + 4) / 5;
  1277. }
  1278. cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
  1279. temp1 &= 0x40; // Isolate 20db gain bit.
  1280. if (rl < 3) {
  1281. temp1 |= 0x8000;
  1282. rl = 0;
  1283. }
  1284. rl = 31 - rl; // Convert volume to attenuation.
  1285. temp1 |= rl;
  1286. cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
  1287. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1288. s->mix.vol[5] = val << 8;
  1289. #else
  1290. s->mix.vol[5] = val;
  1291. #endif
  1292. return put_user(s->mix.vol[5], (int *) arg);
  1293. case SOUND_MIXER_SYNTH:
  1294. if (get_user(val, (int *) arg))
  1295. return -EFAULT;
  1296. l = val & 0xff;
  1297. if (l > 100)
  1298. l = 100;
  1299. if (get_user(val, (int *) arg))
  1300. return -EFAULT;
  1301. r = (val >> 8) & 0xff;
  1302. if (r > 100)
  1303. r = 100;
  1304. rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63.
  1305. rr = (r * 2 - 11) / 3;
  1306. if (rl < 3) // If l is low, turn on
  1307. temp1 = 0x0080; // the mute bit.
  1308. else
  1309. temp1 = 0;
  1310. rl = 63 - rl; // Convert vol to attenuation.
  1311. // writel(temp1 | rl, s->pBA0 + FMLVC);
  1312. if (rr < 3) // If rr is low, turn on
  1313. temp1 = 0x0080; // the mute bit.
  1314. else
  1315. temp1 = 0;
  1316. rr = 63 - rr; // Convert vol to attenuation.
  1317. // writel(temp1 | rr, s->pBA0 + FMRVC);
  1318. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1319. s->mix.vol[4] = (r << 8) | l;
  1320. #else
  1321. s->mix.vol[4] = val;
  1322. #endif
  1323. return put_user(s->mix.vol[4], (int *) arg);
  1324. default:
  1325. CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
  1326. "cs4297a: mixer_ioctl(): default\n"));
  1327. i = _IOC_NR(cmd);
  1328. if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
  1329. return -EINVAL;
  1330. if (get_user(val, (int *) arg))
  1331. return -EFAULT;
  1332. l = val & 0xff;
  1333. if (l > 100)
  1334. l = 100;
  1335. if (l < 1) {
  1336. l = 0;
  1337. rl = 31;
  1338. } else
  1339. rl = (attentbl[(l * 10) / 100]) >> 1;
  1340. r = (val >> 8) & 0xff;
  1341. if (r > 100)
  1342. r = 100;
  1343. if (r < 1) {
  1344. r = 0;
  1345. rr = 31;
  1346. } else
  1347. rr = (attentbl[(r * 10) / 100]) >> 1;
  1348. if ((rl > 30) && (rr > 30))
  1349. temp1 = 0x8000;
  1350. else
  1351. temp1 = 0;
  1352. temp1 = temp1 | (rl << 8) | rr;
  1353. cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
  1354. #ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
  1355. s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
  1356. #else
  1357. s->mix.vol[vidx - 1] = val;
  1358. #endif
  1359. return put_user(s->mix.vol[vidx - 1], (int *) arg);
  1360. }
  1361. }
  1362. // ---------------------------------------------------------------------
  1363. static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
  1364. {
  1365. int minor = iminor(inode);
  1366. struct cs4297a_state *s=NULL;
  1367. struct list_head *entry;
  1368. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
  1369. printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
  1370. list_for_each(entry, &cs4297a_devs)
  1371. {
  1372. s = list_entry(entry, struct cs4297a_state, list);
  1373. if(s->dev_mixer == minor)
  1374. break;
  1375. }
  1376. if (!s)
  1377. {
  1378. CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
  1379. printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
  1380. return -ENODEV;
  1381. }
  1382. VALIDATE_STATE(s);
  1383. file->private_data = s;
  1384. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
  1385. printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
  1386. return nonseekable_open(inode, file);
  1387. }
  1388. static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
  1389. {
  1390. struct cs4297a_state *s =
  1391. (struct cs4297a_state *) file->private_data;
  1392. VALIDATE_STATE(s);
  1393. return 0;
  1394. }
  1395. static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
  1396. unsigned int cmd, unsigned long arg)
  1397. {
  1398. return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
  1399. arg);
  1400. }
  1401. // ******************************************************************************************
  1402. // Mixer file operations struct.
  1403. // ******************************************************************************************
  1404. static /*const */ struct file_operations cs4297a_mixer_fops = {
  1405. .owner = THIS_MODULE,
  1406. .llseek = no_llseek,
  1407. .ioctl = cs4297a_ioctl_mixdev,
  1408. .open = cs4297a_open_mixdev,
  1409. .release = cs4297a_release_mixdev,
  1410. };
  1411. // ---------------------------------------------------------------------
  1412. static int drain_adc(struct cs4297a_state *s, int nonblock)
  1413. {
  1414. /* This routine serves no purpose currently - any samples
  1415. sitting in the receive queue will just be processed by the
  1416. background consumer. This would be different if DMA
  1417. actually stopped when there were no clients. */
  1418. return 0;
  1419. }
  1420. static int drain_dac(struct cs4297a_state *s, int nonblock)
  1421. {
  1422. DECLARE_WAITQUEUE(wait, current);
  1423. unsigned long flags;
  1424. unsigned hwptr;
  1425. unsigned tmo;
  1426. int count;
  1427. if (s->dma_dac.mapped)
  1428. return 0;
  1429. if (nonblock)
  1430. return -EBUSY;
  1431. add_wait_queue(&s->dma_dac.wait, &wait);
  1432. while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
  1433. (s->dma_dac.count > 0)) {
  1434. if (!signal_pending(current)) {
  1435. set_current_state(TASK_INTERRUPTIBLE);
  1436. /* XXXKW is this calculation working? */
  1437. tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
  1438. schedule_timeout(tmo + 1);
  1439. } else {
  1440. /* XXXKW do I care if there is a signal pending? */
  1441. }
  1442. }
  1443. spin_lock_irqsave(&s->lock, flags);
  1444. /* Reset the bookkeeping */
  1445. hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
  1446. s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
  1447. s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
  1448. spin_unlock_irqrestore(&s->lock, flags);
  1449. remove_wait_queue(&s->dma_dac.wait, &wait);
  1450. current->state = TASK_RUNNING;
  1451. return 0;
  1452. }
  1453. // ---------------------------------------------------------------------
  1454. static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
  1455. loff_t * ppos)
  1456. {
  1457. struct cs4297a_state *s =
  1458. (struct cs4297a_state *) file->private_data;
  1459. ssize_t ret;
  1460. unsigned long flags;
  1461. int cnt, count_fr, cnt_by;
  1462. unsigned copied = 0;
  1463. CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
  1464. printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
  1465. VALIDATE_STATE(s);
  1466. if (s->dma_adc.mapped)
  1467. return -ENXIO;
  1468. if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
  1469. return ret;
  1470. if (!access_ok(VERIFY_WRITE, buffer, count))
  1471. return -EFAULT;
  1472. ret = 0;
  1473. //
  1474. // "count" is the amount of bytes to read (from app), is decremented each loop
  1475. // by the amount of bytes that have been returned to the user buffer.
  1476. // "cnt" is the running total of each read from the buffer (changes each loop)
  1477. // "buffer" points to the app's buffer
  1478. // "ret" keeps a running total of the amount of bytes that have been copied
  1479. // to the user buffer.
  1480. // "copied" is the total bytes copied into the user buffer for each loop.
  1481. //
  1482. while (count > 0) {
  1483. CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
  1484. "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
  1485. count, s->dma_adc.count,
  1486. s->dma_adc.swptr, s->dma_adc.hwptr));
  1487. spin_lock_irqsave(&s->lock, flags);
  1488. /* cnt will be the number of available samples (16-bit
  1489. stereo); it starts out as the maxmimum consequetive
  1490. samples */
  1491. cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
  1492. count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
  1493. // dma_adc.count is the current total bytes that have not been read.
  1494. // if the amount of unread bytes from the current sw pointer to the
  1495. // end of the buffer is greater than the current total bytes that
  1496. // have not been read, then set the "cnt" (unread bytes) to the
  1497. // amount of unread bytes.
  1498. if (count_fr < cnt)
  1499. cnt = count_fr;
  1500. cnt_by = cnt * FRAME_SAMPLE_BYTES;
  1501. spin_unlock_irqrestore(&s->lock, flags);
  1502. //
  1503. // if we are converting from 8/16 then we need to copy
  1504. // twice the number of 16 bit bytes then 8 bit bytes.
  1505. //
  1506. if (s->conversion) {
  1507. if (cnt_by > (count * 2)) {
  1508. cnt = (count * 2) / FRAME_SAMPLE_BYTES;
  1509. cnt_by = count * 2;
  1510. }
  1511. } else {
  1512. if (cnt_by > count) {
  1513. cnt = count / FRAME_SAMPLE_BYTES;
  1514. cnt_by = count;
  1515. }
  1516. }
  1517. //
  1518. // "cnt" NOW is the smaller of the amount that will be read,
  1519. // and the amount that is requested in this read (or partial).
  1520. // if there are no bytes in the buffer to read, then start the
  1521. // ADC and wait for the interrupt handler to wake us up.
  1522. //
  1523. if (cnt <= 0) {
  1524. // start up the dma engine and then continue back to the top of
  1525. // the loop when wake up occurs.
  1526. start_adc(s);
  1527. if (file->f_flags & O_NONBLOCK)
  1528. return ret ? ret : -EAGAIN;
  1529. interruptible_sleep_on(&s->dma_adc.wait);
  1530. if (signal_pending(current))
  1531. return ret ? ret : -ERESTARTSYS;
  1532. continue;
  1533. }
  1534. // there are bytes in the buffer to read.
  1535. // copy from the hw buffer over to the user buffer.
  1536. // user buffer is designated by "buffer"
  1537. // virtual address to copy from is dma_buf+swptr
  1538. // the "cnt" is the number of bytes to read.
  1539. CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
  1540. "_read() copy_to cnt=%d count=%d ", cnt_by, count));
  1541. CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
  1542. " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
  1543. s->dma_adc.sbufsz, s->dma_adc.count,
  1544. (unsigned) buffer, ret));
  1545. if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
  1546. return ret ? ret : -EFAULT;
  1547. copied = cnt_by;
  1548. /* Return the descriptors */
  1549. spin_lock_irqsave(&s->lock, flags);
  1550. CS_DBGOUT(CS_FUNCTION, 2,
  1551. printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
  1552. s->dma_adc.count -= cnt_by;
  1553. s->dma_adc.sb_swptr += cnt * 2;
  1554. if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
  1555. s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
  1556. spin_unlock_irqrestore(&s->lock, flags);
  1557. count -= copied;
  1558. buffer += copied;
  1559. ret += copied;
  1560. start_adc(s);
  1561. }
  1562. CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
  1563. printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
  1564. return ret;
  1565. }
  1566. static ssize_t cs4297a_write(struct file *file, const char *buffer,
  1567. size_t count, loff_t * ppos)
  1568. {
  1569. struct cs4297a_state *s =
  1570. (struct cs4297a_state *) file->private_data;
  1571. ssize_t ret;
  1572. unsigned long flags;
  1573. unsigned swptr, hwptr;
  1574. int cnt;
  1575. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
  1576. printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
  1577. count));
  1578. VALIDATE_STATE(s);
  1579. if (s->dma_dac.mapped)
  1580. return -ENXIO;
  1581. if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
  1582. return ret;
  1583. if (!access_ok(VERIFY_READ, buffer, count))
  1584. return -EFAULT;
  1585. ret = 0;
  1586. while (count > 0) {
  1587. serdma_t *d = &s->dma_dac;
  1588. int copy_cnt;
  1589. u32 *s_tmpl;
  1590. u32 *t_tmpl;
  1591. u32 left, right;
  1592. int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
  1593. /* XXXXXX this is broken for BLOAT_FACTOR */
  1594. spin_lock_irqsave(&s->lock, flags);
  1595. if (d->count < 0) {
  1596. d->count = 0;
  1597. d->swptr = d->hwptr;
  1598. }
  1599. if (d->underrun) {
  1600. d->underrun = 0;
  1601. hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
  1602. d->descrtab_phys) / sizeof(serdma_descr_t));
  1603. d->swptr = d->hwptr = hwptr;
  1604. }
  1605. swptr = d->swptr;
  1606. cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
  1607. /* Will this write fill up the buffer? */
  1608. if (d->count + cnt > d->sbufsz)
  1609. cnt = d->sbufsz - d->count;
  1610. spin_unlock_irqrestore(&s->lock, flags);
  1611. if (cnt > count)
  1612. cnt = count;
  1613. if (cnt <= 0) {
  1614. start_dac(s);
  1615. if (file->f_flags & O_NONBLOCK)
  1616. return ret ? ret : -EAGAIN;
  1617. interruptible_sleep_on(&d->wait);
  1618. if (signal_pending(current))
  1619. return ret ? ret : -ERESTARTSYS;
  1620. continue;
  1621. }
  1622. if (copy_from_user(d->sample_buf, buffer, cnt))
  1623. return ret ? ret : -EFAULT;
  1624. copy_cnt = cnt;
  1625. s_tmpl = (u32 *)d->sample_buf;
  1626. t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
  1627. /* XXXKW assuming 16-bit stereo! */
  1628. do {
  1629. u32 tmp;
  1630. t_tmpl[0] = cpu_to_be32(0x98000000);
  1631. tmp = be32_to_cpu(s_tmpl[0]);
  1632. left = tmp & 0xffff;
  1633. right = tmp >> 16;
  1634. if (swap) {
  1635. left = swab16(left);
  1636. right = swab16(right);
  1637. }
  1638. t_tmpl[1] = cpu_to_be32(left >> 8);
  1639. t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
  1640. (right << 4));
  1641. s_tmpl++;
  1642. t_tmpl += 8;
  1643. copy_cnt -= 4;
  1644. } while (copy_cnt);
  1645. /* Mux in any pending read/write accesses */
  1646. if (s->reg_request) {
  1647. *(u64 *)(d->dma_buf + (swptr * 4)) |=
  1648. cpu_to_be64(s->reg_request);
  1649. s->reg_request = 0;
  1650. wake_up(&s->dma_dac.reg_wait);
  1651. }
  1652. CS_DBGOUT(CS_WAVE_WRITE, 4,
  1653. printk(KERN_INFO
  1654. "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
  1655. swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
  1656. __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
  1657. spin_lock_irqsave(&s->lock, flags);
  1658. d->swptr = swptr;
  1659. d->count += cnt;
  1660. d->endcleared = 0;
  1661. spin_unlock_irqrestore(&s->lock, flags);
  1662. count -= cnt;
  1663. buffer += cnt;
  1664. ret += cnt;
  1665. start_dac(s);
  1666. }
  1667. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
  1668. printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
  1669. return ret;
  1670. }
  1671. static unsigned int cs4297a_poll(struct file *file,
  1672. struct poll_table_struct *wait)
  1673. {
  1674. struct cs4297a_state *s =
  1675. (struct cs4297a_state *) file->private_data;
  1676. unsigned long flags;
  1677. unsigned int mask = 0;
  1678. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
  1679. printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
  1680. VALIDATE_STATE(s);
  1681. if (file->f_mode & FMODE_WRITE) {
  1682. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
  1683. printk(KERN_INFO
  1684. "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
  1685. if(!s->dma_dac.ready && prog_dmabuf_dac(s))
  1686. return 0;
  1687. poll_wait(file, &s->dma_dac.wait, wait);
  1688. }
  1689. if (file->f_mode & FMODE_READ) {
  1690. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
  1691. printk(KERN_INFO
  1692. "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
  1693. if(!s->dma_dac.ready && prog_dmabuf_adc(s))
  1694. return 0;
  1695. poll_wait(file, &s->dma_adc.wait, wait);
  1696. }
  1697. spin_lock_irqsave(&s->lock, flags);
  1698. cs4297a_update_ptr(s,CS_FALSE);
  1699. if (file->f_mode & FMODE_WRITE) {
  1700. if (s->dma_dac.mapped) {
  1701. if (s->dma_dac.count >=
  1702. (signed) s->dma_dac.fragsize) {
  1703. if (s->dma_dac.wakeup)
  1704. mask |= POLLOUT | POLLWRNORM;
  1705. else
  1706. mask = 0;
  1707. s->dma_dac.wakeup = 0;
  1708. }
  1709. } else {
  1710. if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
  1711. mask |= POLLOUT | POLLWRNORM;
  1712. }
  1713. } else if (file->f_mode & FMODE_READ) {
  1714. if (s->dma_adc.mapped) {
  1715. if (s->dma_adc.count >= (signed) s->dma_adc.fragsize)
  1716. mask |= POLLIN | POLLRDNORM;
  1717. } else {
  1718. if (s->dma_adc.count > 0)
  1719. mask |= POLLIN | POLLRDNORM;
  1720. }
  1721. }
  1722. spin_unlock_irqrestore(&s->lock, flags);
  1723. CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
  1724. printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
  1725. mask));
  1726. return mask;
  1727. }
  1728. static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
  1729. {
  1730. /* XXXKW currently no mmap support */
  1731. return -EINVAL;
  1732. return 0;
  1733. }
  1734. static int cs4297a_ioctl(struct inode *inode, struct file *file,
  1735. unsigned int cmd, unsigned long arg)
  1736. {
  1737. struct cs4297a_state *s =
  1738. (struct cs4297a_state *) file->private_data;
  1739. unsigned long flags;
  1740. audio_buf_info abinfo;
  1741. count_info cinfo;
  1742. int val, mapped, ret;
  1743. CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
  1744. "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
  1745. (unsigned) file, cmd));
  1746. #if CSDEBUG
  1747. cs_printioctl(cmd);
  1748. #endif
  1749. VALIDATE_STATE(s);
  1750. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1751. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1752. switch (cmd) {
  1753. case OSS_GETVERSION:
  1754. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1755. "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
  1756. SOUND_VERSION));
  1757. return put_user(SOUND_VERSION, (int *) arg);
  1758. case SNDCTL_DSP_SYNC:
  1759. CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
  1760. "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
  1761. if (file->f_mode & FMODE_WRITE)
  1762. return drain_dac(s,
  1763. 0 /*file->f_flags & O_NONBLOCK */
  1764. );
  1765. return 0;
  1766. case SNDCTL_DSP_SETDUPLEX:
  1767. return 0;
  1768. case SNDCTL_DSP_GETCAPS:
  1769. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1770. DSP_CAP_TRIGGER | DSP_CAP_MMAP,
  1771. (int *) arg);
  1772. case SNDCTL_DSP_RESET:
  1773. CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
  1774. "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
  1775. if (file->f_mode & FMODE_WRITE) {
  1776. stop_dac(s);
  1777. synchronize_irq(s->irq);
  1778. s->dma_dac.count = s->dma_dac.total_bytes =
  1779. s->dma_dac.blocks = s->dma_dac.wakeup = 0;
  1780. s->dma_dac.swptr = s->dma_dac.hwptr =
  1781. (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
  1782. s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
  1783. }
  1784. if (file->f_mode & FMODE_READ) {
  1785. stop_adc(s);
  1786. synchronize_irq(s->irq);
  1787. s->dma_adc.count = s->dma_adc.total_bytes =
  1788. s->dma_adc.blocks = s->dma_dac.wakeup = 0;
  1789. s->dma_adc.swptr = s->dma_adc.hwptr =
  1790. (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
  1791. s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
  1792. }
  1793. return 0;
  1794. case SNDCTL_DSP_SPEED:
  1795. if (get_user(val, (int *) arg))
  1796. return -EFAULT;
  1797. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1798. "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
  1799. val = 48000;
  1800. return put_user(val, (int *) arg);
  1801. case SNDCTL_DSP_STEREO:
  1802. if (get_user(val, (int *) arg))
  1803. return -EFAULT;
  1804. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1805. "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
  1806. if (file->f_mode & FMODE_READ) {
  1807. stop_adc(s);
  1808. s->dma_adc.ready = 0;
  1809. s->prop_adc.channels = val ? 2 : 1;
  1810. }
  1811. if (file->f_mode & FMODE_WRITE) {
  1812. stop_dac(s);
  1813. s->dma_dac.ready = 0;
  1814. s->prop_dac.channels = val ? 2 : 1;
  1815. }
  1816. return 0;
  1817. case SNDCTL_DSP_CHANNELS:
  1818. if (get_user(val, (int *) arg))
  1819. return -EFAULT;
  1820. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1821. "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
  1822. val));
  1823. if (val != 0) {
  1824. if (file->f_mode & FMODE_READ) {
  1825. stop_adc(s);
  1826. s->dma_adc.ready = 0;
  1827. if (val >= 2)
  1828. s->prop_adc.channels = 2;
  1829. else
  1830. s->prop_adc.channels = 1;
  1831. }
  1832. if (file->f_mode & FMODE_WRITE) {
  1833. stop_dac(s);
  1834. s->dma_dac.ready = 0;
  1835. if (val >= 2)
  1836. s->prop_dac.channels = 2;
  1837. else
  1838. s->prop_dac.channels = 1;
  1839. }
  1840. }
  1841. if (file->f_mode & FMODE_WRITE)
  1842. val = s->prop_dac.channels;
  1843. else if (file->f_mode & FMODE_READ)
  1844. val = s->prop_adc.channels;
  1845. return put_user(val, (int *) arg);
  1846. case SNDCTL_DSP_GETFMTS: // Returns a mask
  1847. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1848. "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
  1849. AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
  1850. AFMT_U8));
  1851. return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
  1852. AFMT_U8, (int *) arg);
  1853. case SNDCTL_DSP_SETFMT:
  1854. if (get_user(val, (int *) arg))
  1855. return -EFAULT;
  1856. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1857. "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
  1858. val));
  1859. if (val != AFMT_QUERY) {
  1860. if (file->f_mode & FMODE_READ) {
  1861. stop_adc(s);
  1862. s->dma_adc.ready = 0;
  1863. if (val != AFMT_S16_LE
  1864. && val != AFMT_U16_LE && val != AFMT_S8
  1865. && val != AFMT_U8)
  1866. val = AFMT_U8;
  1867. s->prop_adc.fmt = val;
  1868. s->prop_adc.fmt_original = s->prop_adc.fmt;
  1869. }
  1870. if (file->f_mode & FMODE_WRITE) {
  1871. stop_dac(s);
  1872. s->dma_dac.ready = 0;
  1873. if (val != AFMT_S16_LE
  1874. && val != AFMT_U16_LE && val != AFMT_S8
  1875. && val != AFMT_U8)
  1876. val = AFMT_U8;
  1877. s->prop_dac.fmt = val;
  1878. s->prop_dac.fmt_original = s->prop_dac.fmt;
  1879. }
  1880. } else {
  1881. if (file->f_mode & FMODE_WRITE)
  1882. val = s->prop_dac.fmt_original;
  1883. else if (file->f_mode & FMODE_READ)
  1884. val = s->prop_adc.fmt_original;
  1885. }
  1886. CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
  1887. "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n",
  1888. val));
  1889. return put_user(val, (int *) arg);
  1890. case SNDCTL_DSP_POST:
  1891. CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
  1892. "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
  1893. return 0;
  1894. case SNDCTL_DSP_GETTRIGGER:
  1895. val = 0;
  1896. if (file->f_mode & s->ena & FMODE_READ)
  1897. val |= PCM_ENABLE_INPUT;
  1898. if (file->f_mode & s->ena & FMODE_WRITE)
  1899. val |= PCM_ENABLE_OUTPUT;
  1900. return put_user(val, (int *) arg);
  1901. case SNDCTL_DSP_SETTRIGGER:
  1902. if (get_user(val, (int *) arg))
  1903. return -EFAULT;
  1904. if (file->f_mode & FMODE_READ) {
  1905. if (val & PCM_ENABLE_INPUT) {
  1906. if (!s->dma_adc.ready
  1907. && (ret = prog_dmabuf_adc(s)))
  1908. return ret;
  1909. start_adc(s);
  1910. } else
  1911. stop_adc(s);
  1912. }
  1913. if (file->f_mode & FMODE_WRITE) {
  1914. if (val & PCM_ENABLE_OUTPUT) {
  1915. if (!s->dma_dac.ready
  1916. && (ret = prog_dmabuf_dac(s)))
  1917. return ret;
  1918. start_dac(s);
  1919. } else
  1920. stop_dac(s);
  1921. }
  1922. return 0;
  1923. case SNDCTL_DSP_GETOSPACE:
  1924. if (!(file->f_mode & FMODE_WRITE))
  1925. return -EINVAL;
  1926. if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
  1927. return val;
  1928. spin_lock_irqsave(&s->lock, flags);
  1929. cs4297a_update_ptr(s,CS_FALSE);
  1930. abinfo.fragsize = s->dma_dac.fragsize;
  1931. if (s->dma_dac.mapped)
  1932. abinfo.bytes = s->dma_dac.sbufsz;
  1933. else
  1934. abinfo.bytes =
  1935. s->dma_dac.sbufsz - s->dma_dac.count;
  1936. abinfo.fragstotal = s->dma_dac.numfrag;
  1937. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1938. CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
  1939. "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
  1940. abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
  1941. abinfo.fragments));
  1942. spin_unlock_irqrestore(&s->lock, flags);
  1943. return copy_to_user((void *) arg, &abinfo,
  1944. sizeof(abinfo)) ? -EFAULT : 0;
  1945. case SNDCTL_DSP_GETISPACE:
  1946. if (!(file->f_mode & FMODE_READ))
  1947. return -EINVAL;
  1948. if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
  1949. return val;
  1950. spin_lock_irqsave(&s->lock, flags);
  1951. cs4297a_update_ptr(s,CS_FALSE);
  1952. if (s->conversion) {
  1953. abinfo.fragsize = s->dma_adc.fragsize / 2;
  1954. abinfo.bytes = s->dma_adc.count / 2;
  1955. abinfo.fragstotal = s->dma_adc.numfrag;
  1956. abinfo.fragments =
  1957. abinfo.bytes >> (s->dma_adc.fragshift - 1);
  1958. } else {
  1959. abinfo.fragsize = s->dma_adc.fragsize;
  1960. abinfo.bytes = s->dma_adc.count;
  1961. abinfo.fragstotal = s->dma_adc.numfrag;
  1962. abinfo.fragments =
  1963. abinfo.bytes >> s->dma_adc.fragshift;
  1964. }
  1965. spin_unlock_irqrestore(&s->lock, flags);
  1966. return copy_to_user((void *) arg, &abinfo,
  1967. sizeof(abinfo)) ? -EFAULT : 0;
  1968. case SNDCTL_DSP_NONBLOCK:
  1969. file->f_flags |= O_NONBLOCK;
  1970. return 0;
  1971. case SNDCTL_DSP_GETODELAY:
  1972. if (!(file->f_mode & FMODE_WRITE))
  1973. return -EINVAL;
  1974. if(!s->dma_dac.ready && prog_dmabuf_dac(s))
  1975. return 0;
  1976. spin_lock_irqsave(&s->lock, flags);
  1977. cs4297a_update_ptr(s,CS_FALSE);
  1978. val = s->dma_dac.count;
  1979. spin_unlock_irqrestore(&s->lock, flags);
  1980. return put_user(val, (int *) arg);
  1981. case SNDCTL_DSP_GETIPTR:
  1982. if (!(file->f_mode & FMODE_READ))
  1983. return -EINVAL;
  1984. if(!s->dma_adc.ready && prog_dmabuf_adc(s))
  1985. return 0;
  1986. spin_lock_irqsave(&s->lock, flags);
  1987. cs4297a_update_ptr(s,CS_FALSE);
  1988. cinfo.bytes = s->dma_adc.total_bytes;
  1989. if (s->dma_adc.mapped) {
  1990. cinfo.blocks =
  1991. (cinfo.bytes >> s->dma_adc.fragshift) -
  1992. s->dma_adc.blocks;
  1993. s->dma_adc.blocks =
  1994. cinfo.bytes >> s->dma_adc.fragshift;
  1995. } else {
  1996. if (s->conversion) {
  1997. cinfo.blocks =
  1998. s->dma_adc.count /
  1999. 2 >> (s->dma_adc.fragshift - 1);
  2000. } else
  2001. cinfo.blocks =
  2002. s->dma_adc.count >> s->dma_adc.
  2003. fragshift;
  2004. }
  2005. if (s->conversion)
  2006. cinfo.ptr = s->dma_adc.hwptr / 2;
  2007. else
  2008. cinfo.ptr = s->dma_adc.hwptr;
  2009. if (s->dma_adc.mapped)
  2010. s->dma_adc.count &= s->dma_adc.fragsize - 1;
  2011. spin_unlock_irqrestore(&s->lock, flags);
  2012. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  2013. case SNDCTL_DSP_GETOPTR:
  2014. if (!(file->f_mode & FMODE_WRITE))
  2015. return -EINVAL;
  2016. if(!s->dma_dac.ready && prog_dmabuf_dac(s))
  2017. return 0;
  2018. spin_lock_irqsave(&s->lock, flags);
  2019. cs4297a_update_ptr(s,CS_FALSE);
  2020. cinfo.bytes = s->dma_dac.total_bytes;
  2021. if (s->dma_dac.mapped) {
  2022. cinfo.blocks =
  2023. (cinfo.bytes >> s->dma_dac.fragshift) -
  2024. s->dma_dac.blocks;
  2025. s->dma_dac.blocks =
  2026. cinfo.bytes >> s->dma_dac.fragshift;
  2027. } else {
  2028. cinfo.blocks =
  2029. s->dma_dac.count >> s->dma_dac.fragshift;
  2030. }
  2031. cinfo.ptr = s->dma_dac.hwptr;
  2032. if (s->dma_dac.mapped)
  2033. s->dma_dac.count &= s->dma_dac.fragsize - 1;
  2034. spin_unlock_irqrestore(&s->lock, flags);
  2035. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
  2036. case SNDCTL_DSP_GETBLKSIZE:
  2037. if (file->f_mode & FMODE_WRITE) {
  2038. if ((val = prog_dmabuf_dac(s)))
  2039. return val;
  2040. return put_user(s->dma_dac.fragsize, (int *) arg);
  2041. }
  2042. if ((val = prog_dmabuf_adc(s)))
  2043. return val;
  2044. if (s->conversion)
  2045. return put_user(s->dma_adc.fragsize / 2,
  2046. (int *) arg);
  2047. else
  2048. return put_user(s->dma_adc.fragsize, (int *) arg);
  2049. case SNDCTL_DSP_SETFRAGMENT:
  2050. if (get_user(val, (int *) arg))
  2051. return -EFAULT;
  2052. return 0; // Say OK, but do nothing.
  2053. case SNDCTL_DSP_SUBDIVIDE:
  2054. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
  2055. || (file->f_mode & FMODE_WRITE
  2056. && s->dma_dac.subdivision)) return -EINVAL;
  2057. if (get_user(val, (int *) arg))
  2058. return -EFAULT;
  2059. if (val != 1 && val != 2 && val != 4)
  2060. return -EINVAL;
  2061. if (file->f_mode & FMODE_READ)
  2062. s->dma_adc.subdivision = val;
  2063. else if (file->f_mode & FMODE_WRITE)
  2064. s->dma_dac.subdivision = val;
  2065. return 0;
  2066. case SOUND_PCM_READ_RATE:
  2067. if (file->f_mode & FMODE_READ)
  2068. return put_user(s->prop_adc.rate, (int *) arg);
  2069. else if (file->f_mode & FMODE_WRITE)
  2070. return put_user(s->prop_dac.rate, (int *) arg);
  2071. case SOUND_PCM_READ_CHANNELS:
  2072. if (file->f_mode & FMODE_READ)
  2073. return put_user(s->prop_adc.channels, (int *) arg);
  2074. else if (file->f_mode & FMODE_WRITE)
  2075. return put_user(s->prop_dac.channels, (int *) arg);
  2076. case SOUND_PCM_READ_BITS:
  2077. if (file->f_mode & FMODE_READ)
  2078. return
  2079. put_user(
  2080. (s->prop_adc.
  2081. fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
  2082. (int *) arg);
  2083. else if (file->f_mode & FMODE_WRITE)
  2084. return
  2085. put_user(
  2086. (s->prop_dac.
  2087. fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
  2088. (int *) arg);
  2089. case SOUND_PCM_WRITE_FILTER:
  2090. case SNDCTL_DSP_SETSYNCRO:
  2091. case SOUND_PCM_READ_FILTER:
  2092. return -EINVAL;
  2093. }
  2094. return mixer_ioctl(s, cmd, arg);
  2095. }
  2096. static int cs4297a_release(struct inode *inode, struct file *file)
  2097. {
  2098. struct cs4297a_state *s =
  2099. (struct cs4297a_state *) file->private_data;
  2100. CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
  2101. "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
  2102. (unsigned) inode, (unsigned) file, file->f_mode));
  2103. VALIDATE_STATE(s);
  2104. if (file->f_mode & FMODE_WRITE) {
  2105. drain_dac(s, file->f_flags & O_NONBLOCK);
  2106. mutex_lock(&s->open_sem_dac);
  2107. stop_dac(s);
  2108. dealloc_dmabuf(s, &s->dma_dac);
  2109. s->open_mode &= ~FMODE_WRITE;
  2110. mutex_unlock(&s->open_sem_dac);
  2111. wake_up(&s->open_wait_dac);
  2112. }
  2113. if (file->f_mode & FMODE_READ) {
  2114. drain_adc(s, file->f_flags & O_NONBLOCK);
  2115. mutex_lock(&s->open_sem_adc);
  2116. stop_adc(s);
  2117. dealloc_dmabuf(s, &s->dma_adc);
  2118. s->open_mode &= ~FMODE_READ;
  2119. mutex_unlock(&s->open_sem_adc);
  2120. wake_up(&s->open_wait_adc);
  2121. }
  2122. return 0;
  2123. }
  2124. static int cs4297a_open(struct inode *inode, struct file *file)
  2125. {
  2126. int minor = iminor(inode);
  2127. struct cs4297a_state *s=NULL;
  2128. struct list_head *entry;
  2129. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
  2130. "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
  2131. (unsigned) inode, (unsigned) file, file->f_mode));
  2132. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
  2133. "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG))));
  2134. list_for_each(entry, &cs4297a_devs)
  2135. {
  2136. s = list_entry(entry, struct cs4297a_state, list);
  2137. if (!((s->dev_audio ^ minor) & ~0xf))
  2138. break;
  2139. }
  2140. if (entry == &cs4297a_devs)
  2141. return -ENODEV;
  2142. if (!s) {
  2143. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
  2144. "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
  2145. return -ENODEV;
  2146. }
  2147. VALIDATE_STATE(s);
  2148. file->private_data = s;
  2149. // wait for device to become free
  2150. if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
  2151. CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
  2152. "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
  2153. return -ENODEV;
  2154. }
  2155. if (file->f_mode & FMODE_WRITE) {
  2156. if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
  2157. printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
  2158. while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
  2159. ;
  2160. }
  2161. mutex_lock(&s->open_sem_dac);
  2162. while (s->open_mode & FMODE_WRITE) {
  2163. if (file->f_flags & O_NONBLOCK) {
  2164. mutex_unlock(&s->open_sem_dac);
  2165. return -EBUSY;
  2166. }
  2167. mutex_unlock(&s->open_sem_dac);
  2168. interruptible_sleep_on(&s->open_wait_dac);
  2169. if (signal_pending(current)) {
  2170. printk("open - sig pending\n");
  2171. return -ERESTARTSYS;
  2172. }
  2173. mutex_lock(&s->open_sem_dac);
  2174. }
  2175. }
  2176. if (file->f_mode & FMODE_READ) {
  2177. mutex_lock(&s->open_sem_adc);
  2178. while (s->open_mode & FMODE_READ) {
  2179. if (file->f_flags & O_NONBLOCK) {
  2180. mutex_unlock(&s->open_sem_adc);
  2181. return -EBUSY;
  2182. }
  2183. mutex_unlock(&s->open_sem_adc);
  2184. interruptible_sleep_on(&s->open_wait_adc);
  2185. if (signal_pending(current)) {
  2186. printk("open - sig pending\n");
  2187. return -ERESTARTSYS;
  2188. }
  2189. mutex_lock(&s->open_sem_adc);
  2190. }
  2191. }
  2192. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  2193. if (file->f_mode & FMODE_READ) {
  2194. s->prop_adc.fmt = AFMT_S16_BE;
  2195. s->prop_adc.fmt_original = s->prop_adc.fmt;
  2196. s->prop_adc.channels = 2;
  2197. s->prop_adc.rate = 48000;
  2198. s->conversion = 0;
  2199. s->ena &= ~FMODE_READ;
  2200. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  2201. s->dma_adc.subdivision = 0;
  2202. mutex_unlock(&s->open_sem_adc);
  2203. if (prog_dmabuf_adc(s)) {
  2204. CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
  2205. "cs4297a: adc Program dmabufs failed.\n"));
  2206. cs4297a_release(inode, file);
  2207. return -ENOMEM;
  2208. }
  2209. }
  2210. if (file->f_mode & FMODE_WRITE) {
  2211. s->prop_dac.fmt = AFMT_S16_BE;
  2212. s->prop_dac.fmt_original = s->prop_dac.fmt;
  2213. s->prop_dac.channels = 2;
  2214. s->prop_dac.rate = 48000;
  2215. s->conversion = 0;
  2216. s->ena &= ~FMODE_WRITE;
  2217. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  2218. s->dma_dac.subdivision = 0;
  2219. mutex_unlock(&s->open_sem_dac);
  2220. if (prog_dmabuf_dac(s)) {
  2221. CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
  2222. "cs4297a: dac Program dmabufs failed.\n"));
  2223. cs4297a_release(inode, file);
  2224. return -ENOMEM;
  2225. }
  2226. }
  2227. CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
  2228. printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
  2229. return nonseekable_open(inode, file);
  2230. }
  2231. // ******************************************************************************************
  2232. // Wave (audio) file operations struct.
  2233. // ******************************************************************************************
  2234. static /*const */ struct file_operations cs4297a_audio_fops = {
  2235. .owner = THIS_MODULE,
  2236. .llseek = no_llseek,
  2237. .read = cs4297a_read,
  2238. .write = cs4297a_write,
  2239. .poll = cs4297a_poll,
  2240. .ioctl = cs4297a_ioctl,
  2241. .mmap = cs4297a_mmap,
  2242. .open = cs4297a_open,
  2243. .release = cs4297a_release,
  2244. };
  2245. static void cs4297a_interrupt(int irq, void *dev_id)
  2246. {
  2247. struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
  2248. u32 status;
  2249. status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG));
  2250. CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
  2251. "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
  2252. #if 0
  2253. /* XXXKW what check *should* be done here? */
  2254. if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
  2255. status = __raw_readq(SS_CSR(R_SER_STATUS));
  2256. printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
  2257. return;
  2258. }
  2259. #endif
  2260. if (status & M_SYNCSER_RX_SYNC_ERR) {
  2261. status = __raw_readq(SS_CSR(R_SER_STATUS));
  2262. printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
  2263. return;
  2264. }
  2265. if (status & M_SYNCSER_RX_OVERRUN) {
  2266. int newptr, i;
  2267. s->stats.rx_ovrrn++;
  2268. printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
  2269. /* Fix things up: get the receive descriptor pool
  2270. clean and give them back to the hardware */
  2271. while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
  2272. ;
  2273. newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
  2274. s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
  2275. for (i=0; i<DMA_DESCR; i++) {
  2276. s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
  2277. }
  2278. s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
  2279. s->dma_adc.count = 0;
  2280. s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
  2281. __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
  2282. }
  2283. spin_lock(&s->lock);
  2284. cs4297a_update_ptr(s,CS_TRUE);
  2285. spin_unlock(&s->lock);
  2286. CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
  2287. "cs4297a: cs4297a_interrupt()-\n"));
  2288. }
  2289. #if 0
  2290. static struct initvol {
  2291. int mixch;
  2292. int vol;
  2293. } initvol[] __initdata = {
  2294. {SOUND_MIXER_WRITE_VOLUME, 0x4040},
  2295. {SOUND_MIXER_WRITE_PCM, 0x4040},
  2296. {SOUND_MIXER_WRITE_SYNTH, 0x4040},
  2297. {SOUND_MIXER_WRITE_CD, 0x4040},
  2298. {SOUND_MIXER_WRITE_LINE, 0x4040},
  2299. {SOUND_MIXER_WRITE_LINE1, 0x4040},
  2300. {SOUND_MIXER_WRITE_RECLEV, 0x0000},
  2301. {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
  2302. {SOUND_MIXER_WRITE_MIC, 0x0000}
  2303. };
  2304. #endif
  2305. static int __init cs4297a_init(void)
  2306. {
  2307. struct cs4297a_state *s;
  2308. u32 pwr, id;
  2309. mm_segment_t fs;
  2310. int rval;
  2311. #ifndef CONFIG_BCM_CS4297A_CSWARM
  2312. u64 cfg;
  2313. int mdio_val;
  2314. #endif
  2315. CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
  2316. "cs4297a: cs4297a_init_module()+ \n"));
  2317. #ifndef CONFIG_BCM_CS4297A_CSWARM
  2318. mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
  2319. (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
  2320. /* Check syscfg for synchronous serial on port 1 */
  2321. cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
  2322. if (!(cfg & M_SYS_SER1_ENABLE)) {
  2323. __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
  2324. cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG);
  2325. if (!(cfg & M_SYS_SER1_ENABLE)) {
  2326. printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
  2327. return -1;
  2328. }
  2329. printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
  2330. /* Force the codec (on SWARM) to reset by clearing
  2331. GENO, preserving MDIO (no effect on CSWARM) */
  2332. __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
  2333. udelay(10);
  2334. }
  2335. /* Now set GENO */
  2336. __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
  2337. /* Give the codec some time to finish resetting (start the bit clock) */
  2338. udelay(100);
  2339. #endif
  2340. if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
  2341. CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
  2342. "cs4297a: probe() no memory for state struct.\n"));
  2343. return -1;
  2344. }
  2345. s->magic = CS4297a_MAGIC;
  2346. init_waitqueue_head(&s->dma_adc.wait);
  2347. init_waitqueue_head(&s->dma_dac.wait);
  2348. init_waitqueue_head(&s->dma_adc.reg_wait);
  2349. init_waitqueue_head(&s->dma_dac.reg_wait);
  2350. init_waitqueue_head(&s->open_wait);
  2351. init_waitqueue_head(&s->open_wait_adc);
  2352. init_waitqueue_head(&s->open_wait_dac);
  2353. mutex_init(&s->open_sem_adc);
  2354. mutex_init(&s->open_sem_dac);
  2355. spin_lock_init(&s->lock);
  2356. s->irq = K_INT_SER_1;
  2357. if (request_irq
  2358. (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
  2359. CS_DBGOUT(CS_INIT | CS_ERROR, 1,
  2360. printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
  2361. goto err_irq;
  2362. }
  2363. if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
  2364. 0) {
  2365. CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
  2366. "cs4297a: probe() register_sound_dsp() failed.\n"));
  2367. goto err_dev1;
  2368. }
  2369. if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
  2370. 0) {
  2371. CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
  2372. "cs4297a: probe() register_sound_mixer() failed.\n"));
  2373. goto err_dev2;
  2374. }
  2375. if (ser_init(s) || dma_init(s)) {
  2376. CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
  2377. "cs4297a: ser_init failed.\n"));
  2378. goto err_dev3;
  2379. }
  2380. do {
  2381. udelay(4000);
  2382. rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
  2383. } while (!rval && (pwr != 0xf));
  2384. if (!rval) {
  2385. char *sb1250_duart_present;
  2386. fs = get_fs();
  2387. set_fs(KERNEL_DS);
  2388. #if 0
  2389. val = SOUND_MASK_LINE;
  2390. mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
  2391. for (i = 0; i < ARRAY_SIZE(initvol); i++) {
  2392. val = initvol[i].vol;
  2393. mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
  2394. }
  2395. // cs4297a_write_ac97(s, 0x18, 0x0808);
  2396. #else
  2397. // cs4297a_write_ac97(s, 0x5e, 0x180);
  2398. cs4297a_write_ac97(s, 0x02, 0x0808);
  2399. cs4297a_write_ac97(s, 0x18, 0x0808);
  2400. #endif
  2401. set_fs(fs);
  2402. list_add(&s->list, &cs4297a_devs);
  2403. cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
  2404. sb1250_duart_present = symbol_get(sb1250_duart_present);
  2405. if (sb1250_duart_present)
  2406. sb1250_duart_present[1] = 0;
  2407. printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
  2408. CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
  2409. printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
  2410. return 0;
  2411. }
  2412. err_dev3:
  2413. unregister_sound_mixer(s->dev_mixer);
  2414. err_dev2:
  2415. unregister_sound_dsp(s->dev_audio);
  2416. err_dev1:
  2417. free_irq(s->irq, s);
  2418. err_irq:
  2419. kfree(s);
  2420. printk(KERN_INFO "cs4297a: initialization failed\n");
  2421. return -1;
  2422. }
  2423. static void __exit cs4297a_cleanup(void)
  2424. {
  2425. /*
  2426. XXXKW
  2427. disable_irq, free_irq
  2428. drain DMA queue
  2429. disable DMA
  2430. disable TX/RX
  2431. free memory
  2432. */
  2433. CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
  2434. printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
  2435. }
  2436. // ---------------------------------------------------------------------
  2437. MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
  2438. MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
  2439. // ---------------------------------------------------------------------
  2440. module_init(cs4297a_init);
  2441. module_exit(cs4297a_cleanup);