hal2.c 40 KB

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  1. /*
  2. * Driver for A2 audio system used in SGI machines
  3. * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
  4. *
  5. * Based on Ulf Carlsson's code.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. *
  20. * Supported devices:
  21. * /dev/dsp standard dsp device, (mostly) OSS compatible
  22. * /dev/mixer standard mixer device, (mostly) OSS compatible
  23. *
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/sched.h>
  28. #include <linux/init.h>
  29. #include <linux/slab.h>
  30. #include <linux/poll.h>
  31. #include <linux/interrupt.h>
  32. #include <linux/dma-mapping.h>
  33. #include <linux/sound.h>
  34. #include <linux/soundcard.h>
  35. #include <linux/mutex.h>
  36. #include <asm/io.h>
  37. #include <asm/sgi/hpc3.h>
  38. #include <asm/sgi/ip22.h>
  39. #include "hal2.h"
  40. #if 0
  41. #define DEBUG(args...) printk(args)
  42. #else
  43. #define DEBUG(args...)
  44. #endif
  45. #if 0
  46. #define DEBUG_MIX(args...) printk(args)
  47. #else
  48. #define DEBUG_MIX(args...)
  49. #endif
  50. /*
  51. * Before touching these look how it works. It is a bit unusual I know,
  52. * but it helps to keep things simple. This driver is considered complete
  53. * and I won't add any new features although hardware has many cool
  54. * capabilities.
  55. * (Historical note: HAL2 driver was first written by Ulf Carlsson - ALSA
  56. * 0.3 running with 2.2.x kernel. Then ALSA changed completely and it
  57. * seemed easier to me to write OSS driver from scratch - this one. Now
  58. * when ALSA is official part of 2.6 kernel it's time to write ALSA driver
  59. * using (hopefully) final version of ALSA interface)
  60. */
  61. #define H2_BLOCK_SIZE 1024
  62. #define H2_ADC_BUFSIZE 8192
  63. #define H2_DAC_BUFSIZE 16834
  64. struct hal2_pbus {
  65. struct hpc3_pbus_dmacregs *pbus;
  66. int pbusnr;
  67. unsigned int ctrl; /* Current state of pbus->pbdma_ctrl */
  68. };
  69. struct hal2_desc {
  70. struct hpc_dma_desc desc;
  71. u32 cnt; /* don't touch, it is also padding */
  72. };
  73. struct hal2_codec {
  74. unsigned char *buffer;
  75. struct hal2_desc *desc;
  76. int desc_count;
  77. int tail, head; /* tail index, head index */
  78. struct hal2_pbus pbus;
  79. unsigned int format; /* Audio data format */
  80. int voices; /* mono/stereo */
  81. unsigned int sample_rate;
  82. unsigned int master; /* Master frequency */
  83. unsigned short mod; /* MOD value */
  84. unsigned short inc; /* INC value */
  85. wait_queue_head_t dma_wait;
  86. spinlock_t lock;
  87. struct mutex sem;
  88. int usecount; /* recording and playback are
  89. * independent */
  90. };
  91. #define H2_MIX_OUTPUT_ATT 0
  92. #define H2_MIX_INPUT_GAIN 1
  93. #define H2_MIXERS 2
  94. struct hal2_mixer {
  95. int modcnt;
  96. unsigned int master;
  97. unsigned int volume[H2_MIXERS];
  98. };
  99. struct hal2_card {
  100. int dev_dsp; /* audio device */
  101. int dev_mixer; /* mixer device */
  102. int dev_midi; /* midi device */
  103. struct hal2_ctl_regs *ctl_regs; /* HAL2 ctl registers */
  104. struct hal2_aes_regs *aes_regs; /* HAL2 aes registers */
  105. struct hal2_vol_regs *vol_regs; /* HAL2 vol registers */
  106. struct hal2_syn_regs *syn_regs; /* HAL2 syn registers */
  107. struct hal2_codec dac;
  108. struct hal2_codec adc;
  109. struct hal2_mixer mixer;
  110. };
  111. #define H2_INDIRECT_WAIT(regs) while (regs->isr & H2_ISR_TSTATUS);
  112. #define H2_READ_ADDR(addr) (addr | (1<<7))
  113. #define H2_WRITE_ADDR(addr) (addr)
  114. static char *hal2str = "HAL2";
  115. /*
  116. * I doubt anyone has a machine with two HAL2 cards. It's possible to
  117. * have two HPC's, so it is probably possible to have two HAL2 cards.
  118. * Try to deal with it, but note that it is not tested.
  119. */
  120. #define MAXCARDS 2
  121. static struct hal2_card* hal2_card[MAXCARDS];
  122. static const struct {
  123. unsigned char idx:4, avail:1;
  124. } mixtable[SOUND_MIXER_NRDEVICES] = {
  125. [SOUND_MIXER_PCM] = { H2_MIX_OUTPUT_ATT, 1 }, /* voice */
  126. [SOUND_MIXER_MIC] = { H2_MIX_INPUT_GAIN, 1 }, /* mic */
  127. };
  128. #define H2_SUPPORTED_FORMATS (AFMT_S16_LE | AFMT_S16_BE)
  129. static inline void hal2_isr_write(struct hal2_card *hal2, u16 val)
  130. {
  131. hal2->ctl_regs->isr = val;
  132. }
  133. static inline u16 hal2_isr_look(struct hal2_card *hal2)
  134. {
  135. return hal2->ctl_regs->isr;
  136. }
  137. static inline u16 hal2_rev_look(struct hal2_card *hal2)
  138. {
  139. return hal2->ctl_regs->rev;
  140. }
  141. #ifdef HAL2_DUMP_REGS
  142. static u16 hal2_i_look16(struct hal2_card *hal2, u16 addr)
  143. {
  144. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  145. regs->iar = H2_READ_ADDR(addr);
  146. H2_INDIRECT_WAIT(regs);
  147. return regs->idr0;
  148. }
  149. #endif
  150. static u32 hal2_i_look32(struct hal2_card *hal2, u16 addr)
  151. {
  152. u32 ret;
  153. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  154. regs->iar = H2_READ_ADDR(addr);
  155. H2_INDIRECT_WAIT(regs);
  156. ret = regs->idr0 & 0xffff;
  157. regs->iar = H2_READ_ADDR(addr | 0x1);
  158. H2_INDIRECT_WAIT(regs);
  159. ret |= (regs->idr0 & 0xffff) << 16;
  160. return ret;
  161. }
  162. static void hal2_i_write16(struct hal2_card *hal2, u16 addr, u16 val)
  163. {
  164. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  165. regs->idr0 = val;
  166. regs->idr1 = 0;
  167. regs->idr2 = 0;
  168. regs->idr3 = 0;
  169. regs->iar = H2_WRITE_ADDR(addr);
  170. H2_INDIRECT_WAIT(regs);
  171. }
  172. static void hal2_i_write32(struct hal2_card *hal2, u16 addr, u32 val)
  173. {
  174. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  175. regs->idr0 = val & 0xffff;
  176. regs->idr1 = val >> 16;
  177. regs->idr2 = 0;
  178. regs->idr3 = 0;
  179. regs->iar = H2_WRITE_ADDR(addr);
  180. H2_INDIRECT_WAIT(regs);
  181. }
  182. static void hal2_i_setbit16(struct hal2_card *hal2, u16 addr, u16 bit)
  183. {
  184. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  185. regs->iar = H2_READ_ADDR(addr);
  186. H2_INDIRECT_WAIT(regs);
  187. regs->idr0 = (regs->idr0 & 0xffff) | bit;
  188. regs->idr1 = 0;
  189. regs->idr2 = 0;
  190. regs->idr3 = 0;
  191. regs->iar = H2_WRITE_ADDR(addr);
  192. H2_INDIRECT_WAIT(regs);
  193. }
  194. static void hal2_i_setbit32(struct hal2_card *hal2, u16 addr, u32 bit)
  195. {
  196. u32 tmp;
  197. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  198. regs->iar = H2_READ_ADDR(addr);
  199. H2_INDIRECT_WAIT(regs);
  200. tmp = (regs->idr0 & 0xffff) | (regs->idr1 << 16) | bit;
  201. regs->idr0 = tmp & 0xffff;
  202. regs->idr1 = tmp >> 16;
  203. regs->idr2 = 0;
  204. regs->idr3 = 0;
  205. regs->iar = H2_WRITE_ADDR(addr);
  206. H2_INDIRECT_WAIT(regs);
  207. }
  208. static void hal2_i_clearbit16(struct hal2_card *hal2, u16 addr, u16 bit)
  209. {
  210. struct hal2_ctl_regs *regs = hal2->ctl_regs;
  211. regs->iar = H2_READ_ADDR(addr);
  212. H2_INDIRECT_WAIT(regs);
  213. regs->idr0 = (regs->idr0 & 0xffff) & ~bit;
  214. regs->idr1 = 0;
  215. regs->idr2 = 0;
  216. regs->idr3 = 0;
  217. regs->iar = H2_WRITE_ADDR(addr);
  218. H2_INDIRECT_WAIT(regs);
  219. }
  220. #if 0
  221. static void hal2_i_clearbit32(struct hal2_card *hal2, u16 addr, u32 bit)
  222. {
  223. u32 tmp;
  224. hal2_ctl_regs_t *regs = hal2->ctl_regs;
  225. regs->iar = H2_READ_ADDR(addr);
  226. H2_INDIRECT_WAIT(regs);
  227. tmp = ((regs->idr0 & 0xffff) | (regs->idr1 << 16)) & ~bit;
  228. regs->idr0 = tmp & 0xffff;
  229. regs->idr1 = tmp >> 16;
  230. regs->idr2 = 0;
  231. regs->idr3 = 0;
  232. regs->iar = H2_WRITE_ADDR(addr);
  233. H2_INDIRECT_WAIT(regs);
  234. }
  235. #endif
  236. #ifdef HAL2_DUMP_REGS
  237. static void hal2_dump_regs(struct hal2_card *hal2)
  238. {
  239. DEBUG("isr: %08hx ", hal2_isr_look(hal2));
  240. DEBUG("rev: %08hx\n", hal2_rev_look(hal2));
  241. DEBUG("relay: %04hx\n", hal2_i_look16(hal2, H2I_RELAY_C));
  242. DEBUG("port en: %04hx ", hal2_i_look16(hal2, H2I_DMA_PORT_EN));
  243. DEBUG("dma end: %04hx ", hal2_i_look16(hal2, H2I_DMA_END));
  244. DEBUG("dma drv: %04hx\n", hal2_i_look16(hal2, H2I_DMA_DRV));
  245. DEBUG("syn ctl: %04hx ", hal2_i_look16(hal2, H2I_SYNTH_C));
  246. DEBUG("aesrx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESRX_C));
  247. DEBUG("aestx ctl: %04hx ", hal2_i_look16(hal2, H2I_AESTX_C));
  248. DEBUG("dac ctl1: %04hx ", hal2_i_look16(hal2, H2I_ADC_C1));
  249. DEBUG("dac ctl2: %08x ", hal2_i_look32(hal2, H2I_ADC_C2));
  250. DEBUG("adc ctl1: %04hx ", hal2_i_look16(hal2, H2I_DAC_C1));
  251. DEBUG("adc ctl2: %08x ", hal2_i_look32(hal2, H2I_DAC_C2));
  252. DEBUG("syn map: %04hx\n", hal2_i_look16(hal2, H2I_SYNTH_MAP_C));
  253. DEBUG("bres1 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES1_C1));
  254. DEBUG("bres1 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES1_C2));
  255. DEBUG("bres2 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES2_C1));
  256. DEBUG("bres2 ctl2: %04x ", hal2_i_look32(hal2, H2I_BRES2_C2));
  257. DEBUG("bres3 ctl1: %04hx ", hal2_i_look16(hal2, H2I_BRES3_C1));
  258. DEBUG("bres3 ctl2: %04x\n", hal2_i_look32(hal2, H2I_BRES3_C2));
  259. }
  260. #endif
  261. static struct hal2_card* hal2_dsp_find_card(int minor)
  262. {
  263. int i;
  264. for (i = 0; i < MAXCARDS; i++)
  265. if (hal2_card[i] != NULL && hal2_card[i]->dev_dsp == minor)
  266. return hal2_card[i];
  267. return NULL;
  268. }
  269. static struct hal2_card* hal2_mixer_find_card(int minor)
  270. {
  271. int i;
  272. for (i = 0; i < MAXCARDS; i++)
  273. if (hal2_card[i] != NULL && hal2_card[i]->dev_mixer == minor)
  274. return hal2_card[i];
  275. return NULL;
  276. }
  277. static void hal2_inc_head(struct hal2_codec *codec)
  278. {
  279. codec->head++;
  280. if (codec->head == codec->desc_count)
  281. codec->head = 0;
  282. }
  283. static void hal2_inc_tail(struct hal2_codec *codec)
  284. {
  285. codec->tail++;
  286. if (codec->tail == codec->desc_count)
  287. codec->tail = 0;
  288. }
  289. static void hal2_dac_interrupt(struct hal2_codec *dac)
  290. {
  291. int running;
  292. spin_lock(&dac->lock);
  293. /* if tail buffer contains zero samples DMA stream was already
  294. * stopped */
  295. running = dac->desc[dac->tail].cnt;
  296. dac->desc[dac->tail].cnt = 0;
  297. dac->desc[dac->tail].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOX;
  298. /* we just proccessed empty buffer, don't update tail pointer */
  299. if (running)
  300. hal2_inc_tail(dac);
  301. spin_unlock(&dac->lock);
  302. wake_up(&dac->dma_wait);
  303. }
  304. static void hal2_adc_interrupt(struct hal2_codec *adc)
  305. {
  306. int running;
  307. spin_lock(&adc->lock);
  308. /* if head buffer contains nonzero samples DMA stream was already
  309. * stopped */
  310. running = !adc->desc[adc->head].cnt;
  311. adc->desc[adc->head].cnt = H2_BLOCK_SIZE;
  312. adc->desc[adc->head].desc.cntinfo = HPCDMA_XIE | HPCDMA_EOR;
  313. /* we just proccessed empty buffer, don't update head pointer */
  314. if (running)
  315. hal2_inc_head(adc);
  316. spin_unlock(&adc->lock);
  317. wake_up(&adc->dma_wait);
  318. }
  319. static irqreturn_t hal2_interrupt(int irq, void *dev_id)
  320. {
  321. struct hal2_card *hal2 = dev_id;
  322. irqreturn_t ret = IRQ_NONE;
  323. /* decide what caused this interrupt */
  324. if (hal2->dac.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
  325. hal2_dac_interrupt(&hal2->dac);
  326. ret = IRQ_HANDLED;
  327. }
  328. if (hal2->adc.pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_INT) {
  329. hal2_adc_interrupt(&hal2->adc);
  330. ret = IRQ_HANDLED;
  331. }
  332. return ret;
  333. }
  334. static int hal2_compute_rate(struct hal2_codec *codec, unsigned int rate)
  335. {
  336. unsigned short mod;
  337. DEBUG("rate: %d\n", rate);
  338. if (rate < 4000) rate = 4000;
  339. else if (rate > 48000) rate = 48000;
  340. if (44100 % rate < 48000 % rate) {
  341. mod = 4 * 44100 / rate;
  342. codec->master = 44100;
  343. } else {
  344. mod = 4 * 48000 / rate;
  345. codec->master = 48000;
  346. }
  347. codec->inc = 4;
  348. codec->mod = mod;
  349. rate = 4 * codec->master / mod;
  350. DEBUG("real_rate: %d\n", rate);
  351. return rate;
  352. }
  353. static void hal2_set_dac_rate(struct hal2_card *hal2)
  354. {
  355. unsigned int master = hal2->dac.master;
  356. int inc = hal2->dac.inc;
  357. int mod = hal2->dac.mod;
  358. DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
  359. hal2_i_write16(hal2, H2I_BRES1_C1, (master == 44100) ? 1 : 0);
  360. hal2_i_write32(hal2, H2I_BRES1_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
  361. }
  362. static void hal2_set_adc_rate(struct hal2_card *hal2)
  363. {
  364. unsigned int master = hal2->adc.master;
  365. int inc = hal2->adc.inc;
  366. int mod = hal2->adc.mod;
  367. DEBUG("master: %d inc: %d mod: %d\n", master, inc, mod);
  368. hal2_i_write16(hal2, H2I_BRES2_C1, (master == 44100) ? 1 : 0);
  369. hal2_i_write32(hal2, H2I_BRES2_C2, ((0xffff & (inc - mod - 1)) << 16) | inc);
  370. }
  371. static void hal2_setup_dac(struct hal2_card *hal2)
  372. {
  373. unsigned int fifobeg, fifoend, highwater, sample_size;
  374. struct hal2_pbus *pbus = &hal2->dac.pbus;
  375. DEBUG("hal2_setup_dac\n");
  376. /* Now we set up some PBUS information. The PBUS needs information about
  377. * what portion of the fifo it will use. If it's receiving or
  378. * transmitting, and finally whether the stream is little endian or big
  379. * endian. The information is written later, on the start call.
  380. */
  381. sample_size = 2 * hal2->dac.voices;
  382. /* Fifo should be set to hold exactly four samples. Highwater mark
  383. * should be set to two samples. */
  384. highwater = (sample_size * 2) >> 1; /* halfwords */
  385. fifobeg = 0; /* playback is first */
  386. fifoend = (sample_size * 4) >> 3; /* doublewords */
  387. pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_LD |
  388. (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
  389. (hal2->dac.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
  390. /* We disable everything before we do anything at all */
  391. pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
  392. hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
  393. /* Setup the HAL2 for playback */
  394. hal2_set_dac_rate(hal2);
  395. /* Set endianess */
  396. if (hal2->dac.format & AFMT_S16_LE)
  397. hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
  398. else
  399. hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECTX);
  400. /* Set DMA bus */
  401. hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
  402. /* We are using 1st Bresenham clock generator for playback */
  403. hal2_i_write16(hal2, H2I_DAC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
  404. | (1 << H2I_C1_CLKID_SHIFT)
  405. | (hal2->dac.voices << H2I_C1_DATAT_SHIFT));
  406. }
  407. static void hal2_setup_adc(struct hal2_card *hal2)
  408. {
  409. unsigned int fifobeg, fifoend, highwater, sample_size;
  410. struct hal2_pbus *pbus = &hal2->adc.pbus;
  411. DEBUG("hal2_setup_adc\n");
  412. sample_size = 2 * hal2->adc.voices;
  413. highwater = (sample_size * 2) >> 1; /* halfwords */
  414. fifobeg = (4 * 4) >> 3; /* record is second */
  415. fifoend = (4 * 4 + sample_size * 4) >> 3; /* doublewords */
  416. pbus->ctrl = HPC3_PDMACTRL_RT | HPC3_PDMACTRL_RCV | HPC3_PDMACTRL_LD |
  417. (highwater << 8) | (fifobeg << 16) | (fifoend << 24) |
  418. (hal2->adc.format & AFMT_S16_LE ? HPC3_PDMACTRL_SEL : 0);
  419. pbus->pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
  420. hal2_i_clearbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
  421. /* Setup the HAL2 for record */
  422. hal2_set_adc_rate(hal2);
  423. /* Set endianess */
  424. if (hal2->adc.format & AFMT_S16_LE)
  425. hal2_i_setbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
  426. else
  427. hal2_i_clearbit16(hal2, H2I_DMA_END, H2I_DMA_END_CODECR);
  428. /* Set DMA bus */
  429. hal2_i_setbit16(hal2, H2I_DMA_DRV, (1 << pbus->pbusnr));
  430. /* We are using 2nd Bresenham clock generator for record */
  431. hal2_i_write16(hal2, H2I_ADC_C1, (pbus->pbusnr << H2I_C1_DMA_SHIFT)
  432. | (2 << H2I_C1_CLKID_SHIFT)
  433. | (hal2->adc.voices << H2I_C1_DATAT_SHIFT));
  434. }
  435. static dma_addr_t hal2_desc_addr(struct hal2_codec *codec, int i)
  436. {
  437. if (--i < 0)
  438. i = codec->desc_count - 1;
  439. return codec->desc[i].desc.pnext;
  440. }
  441. static void hal2_start_dac(struct hal2_card *hal2)
  442. {
  443. struct hal2_codec *dac = &hal2->dac;
  444. struct hal2_pbus *pbus = &dac->pbus;
  445. pbus->pbus->pbdma_dptr = hal2_desc_addr(dac, dac->tail);
  446. pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
  447. /* enable DAC */
  448. hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECTX);
  449. }
  450. static void hal2_start_adc(struct hal2_card *hal2)
  451. {
  452. struct hal2_codec *adc = &hal2->adc;
  453. struct hal2_pbus *pbus = &adc->pbus;
  454. pbus->pbus->pbdma_dptr = hal2_desc_addr(adc, adc->head);
  455. pbus->pbus->pbdma_ctrl = pbus->ctrl | HPC3_PDMACTRL_ACT;
  456. /* enable ADC */
  457. hal2_i_setbit16(hal2, H2I_DMA_PORT_EN, H2I_DMA_PORT_EN_CODECR);
  458. }
  459. static inline void hal2_stop_dac(struct hal2_card *hal2)
  460. {
  461. hal2->dac.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
  462. /* The HAL2 itself may remain enabled safely */
  463. }
  464. static inline void hal2_stop_adc(struct hal2_card *hal2)
  465. {
  466. hal2->adc.pbus.pbus->pbdma_ctrl = HPC3_PDMACTRL_LD;
  467. }
  468. static int hal2_alloc_dmabuf(struct hal2_codec *codec, int size,
  469. int count, int cntinfo, int dir)
  470. {
  471. struct hal2_desc *desc, *dma_addr;
  472. int i;
  473. DEBUG("allocating %dk DMA buffer.\n", size / 1024);
  474. codec->buffer = (unsigned char *)__get_free_pages(GFP_KERNEL | GFP_DMA,
  475. get_order(size));
  476. if (!codec->buffer)
  477. return -ENOMEM;
  478. desc = dma_alloc_coherent(NULL, count * sizeof(struct hal2_desc),
  479. (dma_addr_t *)&dma_addr, GFP_KERNEL);
  480. if (!desc) {
  481. free_pages((unsigned long)codec->buffer, get_order(size));
  482. return -ENOMEM;
  483. }
  484. codec->desc = desc;
  485. for (i = 0; i < count; i++) {
  486. desc->desc.pbuf = dma_map_single(NULL,
  487. (void *)(codec->buffer + i * H2_BLOCK_SIZE),
  488. H2_BLOCK_SIZE, dir);
  489. desc->desc.cntinfo = cntinfo;
  490. desc->desc.pnext = (i == count - 1) ?
  491. (u32)dma_addr : (u32)(dma_addr + i + 1);
  492. desc->cnt = 0;
  493. desc++;
  494. }
  495. codec->desc_count = count;
  496. codec->head = codec->tail = 0;
  497. return 0;
  498. }
  499. static int hal2_alloc_dac_dmabuf(struct hal2_codec *codec)
  500. {
  501. return hal2_alloc_dmabuf(codec, H2_DAC_BUFSIZE,
  502. H2_DAC_BUFSIZE / H2_BLOCK_SIZE,
  503. HPCDMA_XIE | HPCDMA_EOX,
  504. DMA_TO_DEVICE);
  505. }
  506. static int hal2_alloc_adc_dmabuf(struct hal2_codec *codec)
  507. {
  508. return hal2_alloc_dmabuf(codec, H2_ADC_BUFSIZE,
  509. H2_ADC_BUFSIZE / H2_BLOCK_SIZE,
  510. HPCDMA_XIE | H2_BLOCK_SIZE,
  511. DMA_TO_DEVICE);
  512. }
  513. static void hal2_free_dmabuf(struct hal2_codec *codec, int size, int dir)
  514. {
  515. dma_addr_t dma_addr;
  516. int i;
  517. dma_addr = codec->desc[codec->desc_count - 1].desc.pnext;
  518. for (i = 0; i < codec->desc_count; i++)
  519. dma_unmap_single(NULL, codec->desc[i].desc.pbuf,
  520. H2_BLOCK_SIZE, dir);
  521. dma_free_coherent(NULL, codec->desc_count * sizeof(struct hal2_desc),
  522. (void *)codec->desc, dma_addr);
  523. free_pages((unsigned long)codec->buffer, get_order(size));
  524. }
  525. static void hal2_free_dac_dmabuf(struct hal2_codec *codec)
  526. {
  527. return hal2_free_dmabuf(codec, H2_DAC_BUFSIZE, DMA_TO_DEVICE);
  528. }
  529. static void hal2_free_adc_dmabuf(struct hal2_codec *codec)
  530. {
  531. return hal2_free_dmabuf(codec, H2_ADC_BUFSIZE, DMA_FROM_DEVICE);
  532. }
  533. /*
  534. * Add 'count' bytes to 'buffer' from DMA ring buffers. Return number of
  535. * bytes added or -EFAULT if copy_from_user failed.
  536. */
  537. static int hal2_get_buffer(struct hal2_card *hal2, char *buffer, int count)
  538. {
  539. unsigned long flags;
  540. int size, ret = 0;
  541. unsigned char *buf;
  542. struct hal2_desc *tail;
  543. struct hal2_codec *adc = &hal2->adc;
  544. DEBUG("getting %d bytes ", count);
  545. spin_lock_irqsave(&adc->lock, flags);
  546. tail = &adc->desc[adc->tail];
  547. /* enable DMA stream if there are no data */
  548. if (!tail->cnt && !(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
  549. hal2_start_adc(hal2);
  550. while (tail->cnt > 0 && count > 0) {
  551. size = min((int)tail->cnt, count);
  552. buf = &adc->buffer[(adc->tail + 1) * H2_BLOCK_SIZE - tail->cnt];
  553. spin_unlock_irqrestore(&adc->lock, flags);
  554. dma_sync_single(NULL, tail->desc.pbuf, size, DMA_FROM_DEVICE);
  555. if (copy_to_user(buffer, buf, size)) {
  556. ret = -EFAULT;
  557. goto out;
  558. }
  559. spin_lock_irqsave(&adc->lock, flags);
  560. tail->cnt -= size;
  561. /* buffer is empty, update tail pointer */
  562. if (tail->cnt == 0) {
  563. tail->desc.cntinfo = HPCDMA_XIE | H2_BLOCK_SIZE;
  564. hal2_inc_tail(adc);
  565. tail = &adc->desc[adc->tail];
  566. /* enable DMA stream again if needed */
  567. if (!(adc->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT))
  568. hal2_start_adc(hal2);
  569. }
  570. buffer += size;
  571. ret += size;
  572. count -= size;
  573. DEBUG("(%d) ", size);
  574. }
  575. spin_unlock_irqrestore(&adc->lock, flags);
  576. out:
  577. DEBUG("\n");
  578. return ret;
  579. }
  580. /*
  581. * Add 'count' bytes from 'buffer' to DMA ring buffers. Return number of
  582. * bytes added or -EFAULT if copy_from_user failed.
  583. */
  584. static int hal2_add_buffer(struct hal2_card *hal2, char *buffer, int count)
  585. {
  586. unsigned long flags;
  587. unsigned char *buf;
  588. int size, ret = 0;
  589. struct hal2_desc *head;
  590. struct hal2_codec *dac = &hal2->dac;
  591. DEBUG("adding %d bytes ", count);
  592. spin_lock_irqsave(&dac->lock, flags);
  593. head = &dac->desc[dac->head];
  594. while (head->cnt == 0 && count > 0) {
  595. size = min((int)H2_BLOCK_SIZE, count);
  596. buf = &dac->buffer[dac->head * H2_BLOCK_SIZE];
  597. spin_unlock_irqrestore(&dac->lock, flags);
  598. if (copy_from_user(buf, buffer, size)) {
  599. ret = -EFAULT;
  600. goto out;
  601. }
  602. dma_sync_single(NULL, head->desc.pbuf, size, DMA_TO_DEVICE);
  603. spin_lock_irqsave(&dac->lock, flags);
  604. head->desc.cntinfo = size | HPCDMA_XIE;
  605. head->cnt = size;
  606. buffer += size;
  607. ret += size;
  608. count -= size;
  609. hal2_inc_head(dac);
  610. head = &dac->desc[dac->head];
  611. DEBUG("(%d) ", size);
  612. }
  613. if (!(dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) && ret > 0)
  614. hal2_start_dac(hal2);
  615. spin_unlock_irqrestore(&dac->lock, flags);
  616. out:
  617. DEBUG("\n");
  618. return ret;
  619. }
  620. #define hal2_reset_dac_pointer(hal2) hal2_reset_pointer(hal2, 1)
  621. #define hal2_reset_adc_pointer(hal2) hal2_reset_pointer(hal2, 0)
  622. static void hal2_reset_pointer(struct hal2_card *hal2, int is_dac)
  623. {
  624. int i;
  625. struct hal2_codec *codec = (is_dac) ? &hal2->dac : &hal2->adc;
  626. DEBUG("hal2_reset_pointer\n");
  627. for (i = 0; i < codec->desc_count; i++) {
  628. codec->desc[i].cnt = 0;
  629. codec->desc[i].desc.cntinfo = HPCDMA_XIE | (is_dac) ?
  630. HPCDMA_EOX : H2_BLOCK_SIZE;
  631. }
  632. codec->head = codec->tail = 0;
  633. }
  634. static int hal2_sync_dac(struct hal2_card *hal2)
  635. {
  636. DECLARE_WAITQUEUE(wait, current);
  637. struct hal2_codec *dac = &hal2->dac;
  638. int ret = 0;
  639. unsigned long flags;
  640. signed long timeout = 1000 * H2_BLOCK_SIZE * 2 * dac->voices *
  641. HZ / dac->sample_rate / 900;
  642. while (dac->pbus.pbus->pbdma_ctrl & HPC3_PDMACTRL_ISACT) {
  643. add_wait_queue(&dac->dma_wait, &wait);
  644. set_current_state(TASK_INTERRUPTIBLE);
  645. schedule_timeout(timeout);
  646. spin_lock_irqsave(&dac->lock, flags);
  647. if (dac->desc[dac->tail].cnt)
  648. ret = -ETIME;
  649. spin_unlock_irqrestore(&dac->lock, flags);
  650. if (signal_pending(current))
  651. ret = -ERESTARTSYS;
  652. if (ret) {
  653. hal2_stop_dac(hal2);
  654. hal2_reset_dac_pointer(hal2);
  655. }
  656. remove_wait_queue(&dac->dma_wait, &wait);
  657. }
  658. return ret;
  659. }
  660. static int hal2_write_mixer(struct hal2_card *hal2, int index, int vol)
  661. {
  662. unsigned int l, r, tmp;
  663. DEBUG_MIX("mixer %d write\n", index);
  664. if (index >= SOUND_MIXER_NRDEVICES || !mixtable[index].avail)
  665. return -EINVAL;
  666. r = (vol >> 8) & 0xff;
  667. if (r > 100)
  668. r = 100;
  669. l = vol & 0xff;
  670. if (l > 100)
  671. l = 100;
  672. hal2->mixer.volume[mixtable[index].idx] = l | (r << 8);
  673. switch (mixtable[index].idx) {
  674. case H2_MIX_OUTPUT_ATT:
  675. DEBUG_MIX("output attenuator %d,%d\n", l, r);
  676. if (r | l) {
  677. tmp = hal2_i_look32(hal2, H2I_DAC_C2);
  678. tmp &= ~(H2I_C2_L_ATT_M | H2I_C2_R_ATT_M | H2I_C2_MUTE);
  679. /* Attenuator has five bits */
  680. l = 31 * (100 - l) / 99;
  681. r = 31 * (100 - r) / 99;
  682. DEBUG_MIX("left: %d, right %d\n", l, r);
  683. tmp |= (l << H2I_C2_L_ATT_SHIFT) & H2I_C2_L_ATT_M;
  684. tmp |= (r << H2I_C2_R_ATT_SHIFT) & H2I_C2_R_ATT_M;
  685. hal2_i_write32(hal2, H2I_DAC_C2, tmp);
  686. } else
  687. hal2_i_setbit32(hal2, H2I_DAC_C2, H2I_C2_MUTE);
  688. break;
  689. case H2_MIX_INPUT_GAIN:
  690. DEBUG_MIX("input gain %d,%d\n", l, r);
  691. tmp = hal2_i_look32(hal2, H2I_ADC_C2);
  692. tmp &= ~(H2I_C2_L_GAIN_M | H2I_C2_R_GAIN_M);
  693. /* Gain control has four bits */
  694. l = 16 * l / 100;
  695. r = 16 * r / 100;
  696. DEBUG_MIX("left: %d, right %d\n", l, r);
  697. tmp |= (l << H2I_C2_L_GAIN_SHIFT) & H2I_C2_L_GAIN_M;
  698. tmp |= (r << H2I_C2_R_GAIN_SHIFT) & H2I_C2_R_GAIN_M;
  699. hal2_i_write32(hal2, H2I_ADC_C2, tmp);
  700. break;
  701. }
  702. return 0;
  703. }
  704. static void hal2_init_mixer(struct hal2_card *hal2)
  705. {
  706. int i;
  707. for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  708. if (mixtable[i].avail)
  709. hal2->mixer.volume[mixtable[i].idx] = 100 | (100 << 8);
  710. /* disable attenuator */
  711. hal2_i_write32(hal2, H2I_DAC_C2, 0);
  712. /* set max input gain */
  713. hal2_i_write32(hal2, H2I_ADC_C2, H2I_C2_MUTE |
  714. (H2I_C2_L_GAIN_M << H2I_C2_L_GAIN_SHIFT) |
  715. (H2I_C2_R_GAIN_M << H2I_C2_R_GAIN_SHIFT));
  716. /* set max volume */
  717. hal2->mixer.master = 0xff;
  718. hal2->vol_regs->left = 0xff;
  719. hal2->vol_regs->right = 0xff;
  720. }
  721. /*
  722. * XXX: later i'll implement mixer for main volume which will be disabled
  723. * by default. enabling it users will be allowed to have master volume level
  724. * control on panel in their favourite X desktop
  725. */
  726. static void hal2_volume_control(int direction)
  727. {
  728. unsigned int master = hal2_card[0]->mixer.master;
  729. struct hal2_vol_regs *vol = hal2_card[0]->vol_regs;
  730. /* volume up */
  731. if (direction > 0 && master < 0xff)
  732. master++;
  733. /* volume down */
  734. else if (direction < 0 && master > 0)
  735. master--;
  736. /* TODO: mute/unmute */
  737. vol->left = master;
  738. vol->right = master;
  739. hal2_card[0]->mixer.master = master;
  740. }
  741. static int hal2_mixer_ioctl(struct hal2_card *hal2, unsigned int cmd,
  742. unsigned long arg)
  743. {
  744. int val;
  745. if (cmd == SOUND_MIXER_INFO) {
  746. mixer_info info;
  747. memset(&info, 0, sizeof(info));
  748. strlcpy(info.id, hal2str, sizeof(info.id));
  749. strlcpy(info.name, hal2str, sizeof(info.name));
  750. info.modify_counter = hal2->mixer.modcnt;
  751. if (copy_to_user((void *)arg, &info, sizeof(info)))
  752. return -EFAULT;
  753. return 0;
  754. }
  755. if (cmd == SOUND_OLD_MIXER_INFO) {
  756. _old_mixer_info info;
  757. memset(&info, 0, sizeof(info));
  758. strlcpy(info.id, hal2str, sizeof(info.id));
  759. strlcpy(info.name, hal2str, sizeof(info.name));
  760. if (copy_to_user((void *)arg, &info, sizeof(info)))
  761. return -EFAULT;
  762. return 0;
  763. }
  764. if (cmd == OSS_GETVERSION)
  765. return put_user(SOUND_VERSION, (int *)arg);
  766. if (_IOC_TYPE(cmd) != 'M' || _IOC_SIZE(cmd) != sizeof(int))
  767. return -EINVAL;
  768. if (_IOC_DIR(cmd) == _IOC_READ) {
  769. switch (_IOC_NR(cmd)) {
  770. /* Give the current record source */
  771. case SOUND_MIXER_RECSRC:
  772. val = 0; /* FIXME */
  773. break;
  774. /* Give the supported mixers, all of them support stereo */
  775. case SOUND_MIXER_DEVMASK:
  776. case SOUND_MIXER_STEREODEVS: {
  777. int i;
  778. for (val = i = 0; i < SOUND_MIXER_NRDEVICES; i++)
  779. if (mixtable[i].avail)
  780. val |= 1 << i;
  781. break;
  782. }
  783. /* Arg contains a bit for each supported recording source */
  784. case SOUND_MIXER_RECMASK:
  785. val = 0;
  786. break;
  787. case SOUND_MIXER_CAPS:
  788. val = 0;
  789. break;
  790. /* Read a specific mixer */
  791. default: {
  792. int i = _IOC_NR(cmd);
  793. if (i >= SOUND_MIXER_NRDEVICES || !mixtable[i].avail)
  794. return -EINVAL;
  795. val = hal2->mixer.volume[mixtable[i].idx];
  796. break;
  797. }
  798. }
  799. return put_user(val, (int *)arg);
  800. }
  801. if (_IOC_DIR(cmd) != (_IOC_WRITE|_IOC_READ))
  802. return -EINVAL;
  803. hal2->mixer.modcnt++;
  804. if (get_user(val, (int *)arg))
  805. return -EFAULT;
  806. switch (_IOC_NR(cmd)) {
  807. /* Arg contains a bit for each recording source */
  808. case SOUND_MIXER_RECSRC:
  809. return 0; /* FIXME */
  810. default:
  811. return hal2_write_mixer(hal2, _IOC_NR(cmd), val);
  812. }
  813. return 0;
  814. }
  815. static int hal2_open_mixdev(struct inode *inode, struct file *file)
  816. {
  817. struct hal2_card *hal2 = hal2_mixer_find_card(iminor(inode));
  818. if (hal2) {
  819. file->private_data = hal2;
  820. return nonseekable_open(inode, file);
  821. }
  822. return -ENODEV;
  823. }
  824. static int hal2_release_mixdev(struct inode *inode, struct file *file)
  825. {
  826. return 0;
  827. }
  828. static int hal2_ioctl_mixdev(struct inode *inode, struct file *file,
  829. unsigned int cmd, unsigned long arg)
  830. {
  831. return hal2_mixer_ioctl((struct hal2_card *)file->private_data, cmd, arg);
  832. }
  833. static int hal2_ioctl(struct inode *inode, struct file *file,
  834. unsigned int cmd, unsigned long arg)
  835. {
  836. int val;
  837. struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
  838. switch (cmd) {
  839. case OSS_GETVERSION:
  840. return put_user(SOUND_VERSION, (int *)arg);
  841. case SNDCTL_DSP_SYNC:
  842. if (file->f_mode & FMODE_WRITE)
  843. return hal2_sync_dac(hal2);
  844. return 0;
  845. case SNDCTL_DSP_SETDUPLEX:
  846. return 0;
  847. case SNDCTL_DSP_GETCAPS:
  848. return put_user(DSP_CAP_DUPLEX | DSP_CAP_MULTI, (int *)arg);
  849. case SNDCTL_DSP_RESET:
  850. if (file->f_mode & FMODE_READ) {
  851. hal2_stop_adc(hal2);
  852. hal2_reset_adc_pointer(hal2);
  853. }
  854. if (file->f_mode & FMODE_WRITE) {
  855. hal2_stop_dac(hal2);
  856. hal2_reset_dac_pointer(hal2);
  857. }
  858. return 0;
  859. case SNDCTL_DSP_SPEED:
  860. if (get_user(val, (int *)arg))
  861. return -EFAULT;
  862. if (file->f_mode & FMODE_READ) {
  863. hal2_stop_adc(hal2);
  864. val = hal2_compute_rate(&hal2->adc, val);
  865. hal2->adc.sample_rate = val;
  866. hal2_set_adc_rate(hal2);
  867. }
  868. if (file->f_mode & FMODE_WRITE) {
  869. hal2_stop_dac(hal2);
  870. val = hal2_compute_rate(&hal2->dac, val);
  871. hal2->dac.sample_rate = val;
  872. hal2_set_dac_rate(hal2);
  873. }
  874. return put_user(val, (int *)arg);
  875. case SNDCTL_DSP_STEREO:
  876. if (get_user(val, (int *)arg))
  877. return -EFAULT;
  878. if (file->f_mode & FMODE_READ) {
  879. hal2_stop_adc(hal2);
  880. hal2->adc.voices = (val) ? 2 : 1;
  881. hal2_setup_adc(hal2);
  882. }
  883. if (file->f_mode & FMODE_WRITE) {
  884. hal2_stop_dac(hal2);
  885. hal2->dac.voices = (val) ? 2 : 1;
  886. hal2_setup_dac(hal2);
  887. }
  888. return 0;
  889. case SNDCTL_DSP_CHANNELS:
  890. if (get_user(val, (int *)arg))
  891. return -EFAULT;
  892. if (val != 0) {
  893. if (file->f_mode & FMODE_READ) {
  894. hal2_stop_adc(hal2);
  895. hal2->adc.voices = (val == 1) ? 1 : 2;
  896. hal2_setup_adc(hal2);
  897. }
  898. if (file->f_mode & FMODE_WRITE) {
  899. hal2_stop_dac(hal2);
  900. hal2->dac.voices = (val == 1) ? 1 : 2;
  901. hal2_setup_dac(hal2);
  902. }
  903. }
  904. val = -EINVAL;
  905. if (file->f_mode & FMODE_READ)
  906. val = hal2->adc.voices;
  907. if (file->f_mode & FMODE_WRITE)
  908. val = hal2->dac.voices;
  909. return put_user(val, (int *)arg);
  910. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  911. return put_user(H2_SUPPORTED_FORMATS, (int *)arg);
  912. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  913. if (get_user(val, (int *)arg))
  914. return -EFAULT;
  915. if (val != AFMT_QUERY) {
  916. if (!(val & H2_SUPPORTED_FORMATS))
  917. return -EINVAL;
  918. if (file->f_mode & FMODE_READ) {
  919. hal2_stop_adc(hal2);
  920. hal2->adc.format = val;
  921. hal2_setup_adc(hal2);
  922. }
  923. if (file->f_mode & FMODE_WRITE) {
  924. hal2_stop_dac(hal2);
  925. hal2->dac.format = val;
  926. hal2_setup_dac(hal2);
  927. }
  928. } else {
  929. val = -EINVAL;
  930. if (file->f_mode & FMODE_READ)
  931. val = hal2->adc.format;
  932. if (file->f_mode & FMODE_WRITE)
  933. val = hal2->dac.format;
  934. }
  935. return put_user(val, (int *)arg);
  936. case SNDCTL_DSP_POST:
  937. return 0;
  938. case SNDCTL_DSP_GETOSPACE: {
  939. audio_buf_info info;
  940. int i;
  941. unsigned long flags;
  942. struct hal2_codec *dac = &hal2->dac;
  943. if (!(file->f_mode & FMODE_WRITE))
  944. return -EINVAL;
  945. info.fragments = 0;
  946. spin_lock_irqsave(&dac->lock, flags);
  947. for (i = 0; i < dac->desc_count; i++)
  948. if (dac->desc[i].cnt == 0)
  949. info.fragments++;
  950. spin_unlock_irqrestore(&dac->lock, flags);
  951. info.fragstotal = dac->desc_count;
  952. info.fragsize = H2_BLOCK_SIZE;
  953. info.bytes = info.fragsize * info.fragments;
  954. return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
  955. }
  956. case SNDCTL_DSP_GETISPACE: {
  957. audio_buf_info info;
  958. int i;
  959. unsigned long flags;
  960. struct hal2_codec *adc = &hal2->adc;
  961. if (!(file->f_mode & FMODE_READ))
  962. return -EINVAL;
  963. info.fragments = 0;
  964. info.bytes = 0;
  965. spin_lock_irqsave(&adc->lock, flags);
  966. for (i = 0; i < adc->desc_count; i++)
  967. if (adc->desc[i].cnt > 0) {
  968. info.fragments++;
  969. info.bytes += adc->desc[i].cnt;
  970. }
  971. spin_unlock_irqrestore(&adc->lock, flags);
  972. info.fragstotal = adc->desc_count;
  973. info.fragsize = H2_BLOCK_SIZE;
  974. return copy_to_user((void *)arg, &info, sizeof(info)) ? -EFAULT : 0;
  975. }
  976. case SNDCTL_DSP_NONBLOCK:
  977. file->f_flags |= O_NONBLOCK;
  978. return 0;
  979. case SNDCTL_DSP_GETBLKSIZE:
  980. return put_user(H2_BLOCK_SIZE, (int *)arg);
  981. case SNDCTL_DSP_SETFRAGMENT:
  982. return 0;
  983. case SOUND_PCM_READ_RATE:
  984. val = -EINVAL;
  985. if (file->f_mode & FMODE_READ)
  986. val = hal2->adc.sample_rate;
  987. if (file->f_mode & FMODE_WRITE)
  988. val = hal2->dac.sample_rate;
  989. return put_user(val, (int *)arg);
  990. case SOUND_PCM_READ_CHANNELS:
  991. val = -EINVAL;
  992. if (file->f_mode & FMODE_READ)
  993. val = hal2->adc.voices;
  994. if (file->f_mode & FMODE_WRITE)
  995. val = hal2->dac.voices;
  996. return put_user(val, (int *)arg);
  997. case SOUND_PCM_READ_BITS:
  998. return put_user(16, (int *)arg);
  999. }
  1000. return hal2_mixer_ioctl(hal2, cmd, arg);
  1001. }
  1002. static ssize_t hal2_read(struct file *file, char *buffer,
  1003. size_t count, loff_t *ppos)
  1004. {
  1005. ssize_t err;
  1006. struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
  1007. struct hal2_codec *adc = &hal2->adc;
  1008. if (!count)
  1009. return 0;
  1010. if (mutex_lock_interruptible(&adc->sem))
  1011. return -EINTR;
  1012. if (file->f_flags & O_NONBLOCK) {
  1013. err = hal2_get_buffer(hal2, buffer, count);
  1014. err = err == 0 ? -EAGAIN : err;
  1015. } else {
  1016. do {
  1017. /* ~10% longer */
  1018. signed long timeout = 1000 * H2_BLOCK_SIZE *
  1019. 2 * adc->voices * HZ / adc->sample_rate / 900;
  1020. unsigned long flags;
  1021. DECLARE_WAITQUEUE(wait, current);
  1022. ssize_t cnt = 0;
  1023. err = hal2_get_buffer(hal2, buffer, count);
  1024. if (err > 0) {
  1025. count -= err;
  1026. cnt += err;
  1027. buffer += err;
  1028. err = cnt;
  1029. }
  1030. if (count > 0 && err >= 0) {
  1031. add_wait_queue(&adc->dma_wait, &wait);
  1032. set_current_state(TASK_INTERRUPTIBLE);
  1033. schedule_timeout(timeout);
  1034. spin_lock_irqsave(&adc->lock, flags);
  1035. if (!adc->desc[adc->tail].cnt)
  1036. err = -EAGAIN;
  1037. spin_unlock_irqrestore(&adc->lock, flags);
  1038. if (signal_pending(current))
  1039. err = -ERESTARTSYS;
  1040. remove_wait_queue(&adc->dma_wait, &wait);
  1041. if (err < 0) {
  1042. hal2_stop_adc(hal2);
  1043. hal2_reset_adc_pointer(hal2);
  1044. }
  1045. }
  1046. } while (count > 0 && err >= 0);
  1047. }
  1048. mutex_unlock(&adc->sem);
  1049. return err;
  1050. }
  1051. static ssize_t hal2_write(struct file *file, const char *buffer,
  1052. size_t count, loff_t *ppos)
  1053. {
  1054. ssize_t err;
  1055. char *buf = (char*) buffer;
  1056. struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
  1057. struct hal2_codec *dac = &hal2->dac;
  1058. if (!count)
  1059. return 0;
  1060. if (mutex_lock_interruptible(&dac->sem))
  1061. return -EINTR;
  1062. if (file->f_flags & O_NONBLOCK) {
  1063. err = hal2_add_buffer(hal2, buf, count);
  1064. err = err == 0 ? -EAGAIN : err;
  1065. } else {
  1066. do {
  1067. /* ~10% longer */
  1068. signed long timeout = 1000 * H2_BLOCK_SIZE *
  1069. 2 * dac->voices * HZ / dac->sample_rate / 900;
  1070. unsigned long flags;
  1071. DECLARE_WAITQUEUE(wait, current);
  1072. ssize_t cnt = 0;
  1073. err = hal2_add_buffer(hal2, buf, count);
  1074. if (err > 0) {
  1075. count -= err;
  1076. cnt += err;
  1077. buf += err;
  1078. err = cnt;
  1079. }
  1080. if (count > 0 && err >= 0) {
  1081. add_wait_queue(&dac->dma_wait, &wait);
  1082. set_current_state(TASK_INTERRUPTIBLE);
  1083. schedule_timeout(timeout);
  1084. spin_lock_irqsave(&dac->lock, flags);
  1085. if (dac->desc[dac->head].cnt)
  1086. err = -EAGAIN;
  1087. spin_unlock_irqrestore(&dac->lock, flags);
  1088. if (signal_pending(current))
  1089. err = -ERESTARTSYS;
  1090. remove_wait_queue(&dac->dma_wait, &wait);
  1091. if (err < 0) {
  1092. hal2_stop_dac(hal2);
  1093. hal2_reset_dac_pointer(hal2);
  1094. }
  1095. }
  1096. } while (count > 0 && err >= 0);
  1097. }
  1098. mutex_unlock(&dac->sem);
  1099. return err;
  1100. }
  1101. static unsigned int hal2_poll(struct file *file, struct poll_table_struct *wait)
  1102. {
  1103. unsigned long flags;
  1104. unsigned int mask = 0;
  1105. struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
  1106. if (file->f_mode & FMODE_READ) {
  1107. struct hal2_codec *adc = &hal2->adc;
  1108. poll_wait(file, &adc->dma_wait, wait);
  1109. spin_lock_irqsave(&adc->lock, flags);
  1110. if (adc->desc[adc->tail].cnt > 0)
  1111. mask |= POLLIN;
  1112. spin_unlock_irqrestore(&adc->lock, flags);
  1113. }
  1114. if (file->f_mode & FMODE_WRITE) {
  1115. struct hal2_codec *dac = &hal2->dac;
  1116. poll_wait(file, &dac->dma_wait, wait);
  1117. spin_lock_irqsave(&dac->lock, flags);
  1118. if (dac->desc[dac->head].cnt == 0)
  1119. mask |= POLLOUT;
  1120. spin_unlock_irqrestore(&dac->lock, flags);
  1121. }
  1122. return mask;
  1123. }
  1124. static int hal2_open(struct inode *inode, struct file *file)
  1125. {
  1126. int err;
  1127. struct hal2_card *hal2 = hal2_dsp_find_card(iminor(inode));
  1128. if (!hal2)
  1129. return -ENODEV;
  1130. file->private_data = hal2;
  1131. if (file->f_mode & FMODE_READ) {
  1132. struct hal2_codec *adc = &hal2->adc;
  1133. if (adc->usecount)
  1134. return -EBUSY;
  1135. /* OSS spec wanted us to use 8 bit, 8 kHz mono by default,
  1136. * but HAL2 can't do 8bit audio */
  1137. adc->format = AFMT_S16_BE;
  1138. adc->voices = 1;
  1139. adc->sample_rate = hal2_compute_rate(adc, 8000);
  1140. hal2_set_adc_rate(hal2);
  1141. err = hal2_alloc_adc_dmabuf(adc);
  1142. if (err)
  1143. return err;
  1144. hal2_setup_adc(hal2);
  1145. adc->usecount++;
  1146. }
  1147. if (file->f_mode & FMODE_WRITE) {
  1148. struct hal2_codec *dac = &hal2->dac;
  1149. if (dac->usecount)
  1150. return -EBUSY;
  1151. dac->format = AFMT_S16_BE;
  1152. dac->voices = 1;
  1153. dac->sample_rate = hal2_compute_rate(dac, 8000);
  1154. hal2_set_dac_rate(hal2);
  1155. err = hal2_alloc_dac_dmabuf(dac);
  1156. if (err)
  1157. return err;
  1158. hal2_setup_dac(hal2);
  1159. dac->usecount++;
  1160. }
  1161. return nonseekable_open(inode, file);
  1162. }
  1163. static int hal2_release(struct inode *inode, struct file *file)
  1164. {
  1165. struct hal2_card *hal2 = (struct hal2_card *) file->private_data;
  1166. if (file->f_mode & FMODE_READ) {
  1167. struct hal2_codec *adc = &hal2->adc;
  1168. mutex_lock(&adc->sem);
  1169. hal2_stop_adc(hal2);
  1170. hal2_free_adc_dmabuf(adc);
  1171. adc->usecount--;
  1172. mutex_unlock(&adc->sem);
  1173. }
  1174. if (file->f_mode & FMODE_WRITE) {
  1175. struct hal2_codec *dac = &hal2->dac;
  1176. mutex_lock(&dac->sem);
  1177. hal2_sync_dac(hal2);
  1178. hal2_free_dac_dmabuf(dac);
  1179. dac->usecount--;
  1180. mutex_unlock(&dac->sem);
  1181. }
  1182. return 0;
  1183. }
  1184. static const struct file_operations hal2_audio_fops = {
  1185. .owner = THIS_MODULE,
  1186. .llseek = no_llseek,
  1187. .read = hal2_read,
  1188. .write = hal2_write,
  1189. .poll = hal2_poll,
  1190. .ioctl = hal2_ioctl,
  1191. .open = hal2_open,
  1192. .release = hal2_release,
  1193. };
  1194. static const struct file_operations hal2_mixer_fops = {
  1195. .owner = THIS_MODULE,
  1196. .llseek = no_llseek,
  1197. .ioctl = hal2_ioctl_mixdev,
  1198. .open = hal2_open_mixdev,
  1199. .release = hal2_release_mixdev,
  1200. };
  1201. static void hal2_init_codec(struct hal2_codec *codec, struct hpc3_regs *hpc3,
  1202. int index)
  1203. {
  1204. codec->pbus.pbusnr = index;
  1205. codec->pbus.pbus = &hpc3->pbdma[index];
  1206. init_waitqueue_head(&codec->dma_wait);
  1207. mutex_init(&codec->sem);
  1208. spin_lock_init(&codec->lock);
  1209. }
  1210. static int hal2_detect(struct hal2_card *hal2)
  1211. {
  1212. unsigned short board, major, minor;
  1213. unsigned short rev;
  1214. /* reset HAL2 */
  1215. hal2_isr_write(hal2, 0);
  1216. /* release reset */
  1217. hal2_isr_write(hal2, H2_ISR_GLOBAL_RESET_N | H2_ISR_CODEC_RESET_N);
  1218. hal2_i_write16(hal2, H2I_RELAY_C, H2I_RELAY_C_STATE);
  1219. if ((rev = hal2_rev_look(hal2)) & H2_REV_AUDIO_PRESENT)
  1220. return -ENODEV;
  1221. board = (rev & H2_REV_BOARD_M) >> 12;
  1222. major = (rev & H2_REV_MAJOR_CHIP_M) >> 4;
  1223. minor = (rev & H2_REV_MINOR_CHIP_M);
  1224. printk(KERN_INFO "SGI HAL2 revision %i.%i.%i\n",
  1225. board, major, minor);
  1226. return 0;
  1227. }
  1228. static int hal2_init_card(struct hal2_card **phal2, struct hpc3_regs *hpc3)
  1229. {
  1230. int ret = 0;
  1231. struct hal2_card *hal2;
  1232. hal2 = kzalloc(sizeof(struct hal2_card), GFP_KERNEL);
  1233. if (!hal2)
  1234. return -ENOMEM;
  1235. hal2->ctl_regs = (struct hal2_ctl_regs *)hpc3->pbus_extregs[0];
  1236. hal2->aes_regs = (struct hal2_aes_regs *)hpc3->pbus_extregs[1];
  1237. hal2->vol_regs = (struct hal2_vol_regs *)hpc3->pbus_extregs[2];
  1238. hal2->syn_regs = (struct hal2_syn_regs *)hpc3->pbus_extregs[3];
  1239. if (hal2_detect(hal2) < 0) {
  1240. ret = -ENODEV;
  1241. goto free_card;
  1242. }
  1243. hal2_init_codec(&hal2->dac, hpc3, 0);
  1244. hal2_init_codec(&hal2->adc, hpc3, 1);
  1245. /*
  1246. * All DMA channel interfaces in HAL2 are designed to operate with
  1247. * PBUS programmed for 2 cycles in D3, 2 cycles in D4 and 2 cycles
  1248. * in D5. HAL2 is a 16-bit device which can accept both big and little
  1249. * endian format. It assumes that even address bytes are on high
  1250. * portion of PBUS (15:8) and assumes that HPC3 is programmed to
  1251. * accept a live (unsynchronized) version of P_DREQ_N from HAL2.
  1252. */
  1253. #define HAL2_PBUS_DMACFG ((0 << HPC3_DMACFG_D3R_SHIFT) | \
  1254. (2 << HPC3_DMACFG_D4R_SHIFT) | \
  1255. (2 << HPC3_DMACFG_D5R_SHIFT) | \
  1256. (0 << HPC3_DMACFG_D3W_SHIFT) | \
  1257. (2 << HPC3_DMACFG_D4W_SHIFT) | \
  1258. (2 << HPC3_DMACFG_D5W_SHIFT) | \
  1259. HPC3_DMACFG_DS16 | \
  1260. HPC3_DMACFG_EVENHI | \
  1261. HPC3_DMACFG_RTIME | \
  1262. (8 << HPC3_DMACFG_BURST_SHIFT) | \
  1263. HPC3_DMACFG_DRQLIVE)
  1264. /*
  1265. * Ignore what's mentioned in the specification and write value which
  1266. * works in The Real World (TM)
  1267. */
  1268. hpc3->pbus_dmacfg[hal2->dac.pbus.pbusnr][0] = 0x8208844;
  1269. hpc3->pbus_dmacfg[hal2->adc.pbus.pbusnr][0] = 0x8208844;
  1270. if (request_irq(SGI_HPCDMA_IRQ, hal2_interrupt, IRQF_SHARED,
  1271. hal2str, hal2)) {
  1272. printk(KERN_ERR "HAL2: Can't get irq %d\n", SGI_HPCDMA_IRQ);
  1273. ret = -EAGAIN;
  1274. goto free_card;
  1275. }
  1276. hal2->dev_dsp = register_sound_dsp(&hal2_audio_fops, -1);
  1277. if (hal2->dev_dsp < 0) {
  1278. ret = hal2->dev_dsp;
  1279. goto free_irq;
  1280. }
  1281. hal2->dev_mixer = register_sound_mixer(&hal2_mixer_fops, -1);
  1282. if (hal2->dev_mixer < 0) {
  1283. ret = hal2->dev_mixer;
  1284. goto unregister_dsp;
  1285. }
  1286. hal2_init_mixer(hal2);
  1287. *phal2 = hal2;
  1288. return 0;
  1289. unregister_dsp:
  1290. unregister_sound_dsp(hal2->dev_dsp);
  1291. free_irq:
  1292. free_irq(SGI_HPCDMA_IRQ, hal2);
  1293. free_card:
  1294. kfree(hal2);
  1295. return ret;
  1296. }
  1297. extern void (*indy_volume_button)(int);
  1298. /*
  1299. * Assuming only one HAL2 card. Mail me if you ever meet machine with
  1300. * more than one.
  1301. */
  1302. static int __init init_hal2(void)
  1303. {
  1304. int i, error;
  1305. for (i = 0; i < MAXCARDS; i++)
  1306. hal2_card[i] = NULL;
  1307. error = hal2_init_card(&hal2_card[0], hpc3c0);
  1308. /* let Indy's volume buttons work */
  1309. if (!error && !ip22_is_fullhouse())
  1310. indy_volume_button = hal2_volume_control;
  1311. return error;
  1312. }
  1313. static void __exit exit_hal2(void)
  1314. {
  1315. int i;
  1316. /* unregister volume butons callback function */
  1317. indy_volume_button = NULL;
  1318. for (i = 0; i < MAXCARDS; i++)
  1319. if (hal2_card[i]) {
  1320. free_irq(SGI_HPCDMA_IRQ, hal2_card[i]);
  1321. unregister_sound_dsp(hal2_card[i]->dev_dsp);
  1322. unregister_sound_mixer(hal2_card[i]->dev_mixer);
  1323. kfree(hal2_card[i]);
  1324. }
  1325. }
  1326. module_init(init_hal2);
  1327. module_exit(exit_hal2);
  1328. MODULE_DESCRIPTION("OSS compatible driver for SGI HAL2 audio");
  1329. MODULE_AUTHOR("Ladislav Michl");
  1330. MODULE_LICENSE("GPL");