es1371.c 93 KB

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  1. /*****************************************************************************/
  2. /*
  3. * es1371.c -- Creative Ensoniq ES1371.
  4. *
  5. * Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. *
  21. * Special thanks to Ensoniq
  22. *
  23. * Supported devices:
  24. * /dev/dsp standard /dev/dsp device, (mostly) OSS compatible
  25. * /dev/mixer standard /dev/mixer device, (mostly) OSS compatible
  26. * /dev/dsp1 additional DAC, like /dev/dsp, but outputs to mixer "SYNTH" setting
  27. * /dev/midi simple MIDI UART interface, no ioctl
  28. *
  29. * NOTE: the card does not have any FM/Wavetable synthesizer, it is supposed
  30. * to be done in software. That is what /dev/dac is for. By now (Q2 1998)
  31. * there are several MIDI to PCM (WAV) packages, one of them is timidity.
  32. *
  33. * Revision history
  34. * 04.06.1998 0.1 Initial release
  35. * Mixer stuff should be overhauled; especially optional AC97 mixer bits
  36. * should be detected. This results in strange behaviour of some mixer
  37. * settings, like master volume and mic.
  38. * 08.06.1998 0.2 First release using Alan Cox' soundcore instead of miscdevice
  39. * 03.08.1998 0.3 Do not include modversions.h
  40. * Now mixer behaviour can basically be selected between
  41. * "OSS documented" and "OSS actual" behaviour
  42. * 31.08.1998 0.4 Fix realplayer problems - dac.count issues
  43. * 27.10.1998 0.5 Fix joystick support
  44. * -- Oliver Neukum (c188@org.chemie.uni-muenchen.de)
  45. * 10.12.1998 0.6 Fix drain_dac trying to wait on not yet initialized DMA
  46. * 23.12.1998 0.7 Fix a few f_file & FMODE_ bugs
  47. * Don't wake up app until there are fragsize bytes to read/write
  48. * 06.01.1999 0.8 remove the silly SA_INTERRUPT flag.
  49. * hopefully killed the egcs section type conflict
  50. * 12.03.1999 0.9 cinfo.blocks should be reset after GETxPTR ioctl.
  51. * reported by Johan Maes <joma@telindus.be>
  52. * 22.03.1999 0.10 return EAGAIN instead of EBUSY when O_NONBLOCK
  53. * read/write cannot be executed
  54. * 07.04.1999 0.11 implemented the following ioctl's: SOUND_PCM_READ_RATE,
  55. * SOUND_PCM_READ_CHANNELS, SOUND_PCM_READ_BITS;
  56. * Alpha fixes reported by Peter Jones <pjones@redhat.com>
  57. * Another Alpha fix (wait_src_ready in init routine)
  58. * reported by "Ivan N. Kokshaysky" <ink@jurassic.park.msu.ru>
  59. * Note: joystick address handling might still be wrong on archs
  60. * other than i386
  61. * 15.06.1999 0.12 Fix bad allocation bug.
  62. * Thanks to Deti Fliegl <fliegl@in.tum.de>
  63. * 28.06.1999 0.13 Add pci_set_master
  64. * 03.08.1999 0.14 adapt to Linus' new __setup/__initcall
  65. * added kernel command line option "es1371=joystickaddr"
  66. * removed CONFIG_SOUND_ES1371_JOYPORT_BOOT kludge
  67. * 10.08.1999 0.15 (Re)added S/PDIF module option for cards revision >= 4.
  68. * Initial version by Dave Platt <dplatt@snulbug.mtview.ca.us>.
  69. * module_init/__setup fixes
  70. * 08.16.1999 0.16 Joe Cotellese <joec@ensoniq.com>
  71. * Added detection for ES1371 revision ID so that we can
  72. * detect the ES1373 and later parts.
  73. * added AC97 #defines for readability
  74. * added a /proc file system for dumping hardware state
  75. * updated SRC and CODEC w/r functions to accommodate bugs
  76. * in some versions of the ES137x chips.
  77. * 31.08.1999 0.17 add spin_lock_init
  78. * replaced current->state = x with set_current_state(x)
  79. * 03.09.1999 0.18 change read semantics for MIDI to match
  80. * OSS more closely; remove possible wakeup race
  81. * 21.10.1999 0.19 Round sampling rates, requested by
  82. * Kasamatsu Kenichi <t29w0267@ip.media.kyoto-u.ac.jp>
  83. * 27.10.1999 0.20 Added SigmaTel 3D enhancement string
  84. * Codec ID printing changes
  85. * 28.10.1999 0.21 More waitqueue races fixed
  86. * Joe Cotellese <joec@ensoniq.com>
  87. * Changed PCI detection routine so we can more easily
  88. * detect ES137x chip and derivatives.
  89. * 05.01.2000 0.22 Should now work with rev7 boards; patch by
  90. * Eric Lemar, elemar@cs.washington.edu
  91. * 08.01.2000 0.23 Prevent some ioctl's from returning bad count values on underrun/overrun;
  92. * Tim Janik's BSE (Bedevilled Sound Engine) found this
  93. * 07.02.2000 0.24 Use pci_alloc_consistent and pci_register_driver
  94. * 07.02.2000 0.25 Use ac97_codec
  95. * 01.03.2000 0.26 SPDIF patch by Mikael Bouillot <mikael.bouillot@bigfoot.com>
  96. * Use pci_module_init
  97. * 21.11.2000 0.27 Initialize dma buffers in poll, otherwise poll may return a bogus mask
  98. * 12.12.2000 0.28 More dma buffer initializations, patch from
  99. * Tjeerd Mulder <tjeerd.mulder@fujitsu-siemens.com>
  100. * 05.01.2001 0.29 Hopefully updates will not be required anymore when Creative bumps
  101. * the CT5880 revision.
  102. * suggested by Stephan Müller <smueller@chronox.de>
  103. * 31.01.2001 0.30 Register/Unregister gameport
  104. * Fix SETTRIGGER non OSS API conformity
  105. * 14.07.2001 0.31 Add list of laptops needing amplifier control
  106. * 03.01.2003 0.32 open_mode fixes from Georg Acher <acher@in.tum.de>
  107. */
  108. /*****************************************************************************/
  109. #include <linux/interrupt.h>
  110. #include <linux/module.h>
  111. #include <linux/string.h>
  112. #include <linux/ioport.h>
  113. #include <linux/sched.h>
  114. #include <linux/delay.h>
  115. #include <linux/sound.h>
  116. #include <linux/slab.h>
  117. #include <linux/soundcard.h>
  118. #include <linux/pci.h>
  119. #include <linux/init.h>
  120. #include <linux/poll.h>
  121. #include <linux/bitops.h>
  122. #include <linux/proc_fs.h>
  123. #include <linux/spinlock.h>
  124. #include <linux/smp_lock.h>
  125. #include <linux/ac97_codec.h>
  126. #include <linux/gameport.h>
  127. #include <linux/wait.h>
  128. #include <linux/dma-mapping.h>
  129. #include <linux/mutex.h>
  130. #include <linux/mm.h>
  131. #include <linux/kernel.h>
  132. #include <asm/io.h>
  133. #include <asm/page.h>
  134. #include <asm/uaccess.h>
  135. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  136. #define SUPPORT_JOYSTICK
  137. #endif
  138. /* --------------------------------------------------------------------- */
  139. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  140. #define ES1371_DEBUG
  141. #define DBG(x) {}
  142. /*#define DBG(x) {x}*/
  143. /* --------------------------------------------------------------------- */
  144. #ifndef PCI_VENDOR_ID_ENSONIQ
  145. #define PCI_VENDOR_ID_ENSONIQ 0x1274
  146. #endif
  147. #ifndef PCI_VENDOR_ID_ECTIVA
  148. #define PCI_VENDOR_ID_ECTIVA 0x1102
  149. #endif
  150. #ifndef PCI_DEVICE_ID_ENSONIQ_ES1371
  151. #define PCI_DEVICE_ID_ENSONIQ_ES1371 0x1371
  152. #endif
  153. #ifndef PCI_DEVICE_ID_ENSONIQ_CT5880
  154. #define PCI_DEVICE_ID_ENSONIQ_CT5880 0x5880
  155. #endif
  156. #ifndef PCI_DEVICE_ID_ECTIVA_EV1938
  157. #define PCI_DEVICE_ID_ECTIVA_EV1938 0x8938
  158. #endif
  159. /* ES1371 chip ID */
  160. /* This is a little confusing because all ES1371 compatible chips have the
  161. same DEVICE_ID, the only thing differentiating them is the REV_ID field.
  162. This is only significant if you want to enable features on the later parts.
  163. Yes, I know it's stupid and why didn't we use the sub IDs?
  164. */
  165. #define ES1371REV_ES1373_A 0x04
  166. #define ES1371REV_ES1373_B 0x06
  167. #define ES1371REV_CT5880_A 0x07
  168. #define CT5880REV_CT5880_C 0x02
  169. #define CT5880REV_CT5880_D 0x03
  170. #define ES1371REV_ES1371_B 0x09
  171. #define EV1938REV_EV1938_A 0x00
  172. #define ES1371REV_ES1373_8 0x08
  173. #define ES1371_MAGIC ((PCI_VENDOR_ID_ENSONIQ<<16)|PCI_DEVICE_ID_ENSONIQ_ES1371)
  174. #define ES1371_EXTENT 0x40
  175. #define JOY_EXTENT 8
  176. #define ES1371_REG_CONTROL 0x00
  177. #define ES1371_REG_STATUS 0x04 /* on the 5880 it is control/status */
  178. #define ES1371_REG_UART_DATA 0x08
  179. #define ES1371_REG_UART_STATUS 0x09
  180. #define ES1371_REG_UART_CONTROL 0x09
  181. #define ES1371_REG_UART_TEST 0x0a
  182. #define ES1371_REG_MEMPAGE 0x0c
  183. #define ES1371_REG_SRCONV 0x10
  184. #define ES1371_REG_CODEC 0x14
  185. #define ES1371_REG_LEGACY 0x18
  186. #define ES1371_REG_SERIAL_CONTROL 0x20
  187. #define ES1371_REG_DAC1_SCOUNT 0x24
  188. #define ES1371_REG_DAC2_SCOUNT 0x28
  189. #define ES1371_REG_ADC_SCOUNT 0x2c
  190. #define ES1371_REG_DAC1_FRAMEADR 0xc30
  191. #define ES1371_REG_DAC1_FRAMECNT 0xc34
  192. #define ES1371_REG_DAC2_FRAMEADR 0xc38
  193. #define ES1371_REG_DAC2_FRAMECNT 0xc3c
  194. #define ES1371_REG_ADC_FRAMEADR 0xd30
  195. #define ES1371_REG_ADC_FRAMECNT 0xd34
  196. #define ES1371_FMT_U8_MONO 0
  197. #define ES1371_FMT_U8_STEREO 1
  198. #define ES1371_FMT_S16_MONO 2
  199. #define ES1371_FMT_S16_STEREO 3
  200. #define ES1371_FMT_STEREO 1
  201. #define ES1371_FMT_S16 2
  202. #define ES1371_FMT_MASK 3
  203. static const unsigned sample_size[] = { 1, 2, 2, 4 };
  204. static const unsigned sample_shift[] = { 0, 1, 1, 2 };
  205. #define CTRL_RECEN_B 0x08000000 /* 1 = don't mix analog in to digital out */
  206. #define CTRL_SPDIFEN_B 0x04000000
  207. #define CTRL_JOY_SHIFT 24
  208. #define CTRL_JOY_MASK 3
  209. #define CTRL_JOY_200 0x00000000 /* joystick base address */
  210. #define CTRL_JOY_208 0x01000000
  211. #define CTRL_JOY_210 0x02000000
  212. #define CTRL_JOY_218 0x03000000
  213. #define CTRL_GPIO_IN0 0x00100000 /* general purpose inputs/outputs */
  214. #define CTRL_GPIO_IN1 0x00200000
  215. #define CTRL_GPIO_IN2 0x00400000
  216. #define CTRL_GPIO_IN3 0x00800000
  217. #define CTRL_GPIO_OUT0 0x00010000
  218. #define CTRL_GPIO_OUT1 0x00020000
  219. #define CTRL_GPIO_OUT2 0x00040000
  220. #define CTRL_GPIO_OUT3 0x00080000
  221. #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
  222. #define CTRL_SYNCRES 0x00004000 /* AC97 warm reset */
  223. #define CTRL_ADCSTOP 0x00002000 /* stop ADC transfers */
  224. #define CTRL_PWR_INTRM 0x00001000 /* 1 = power level ints enabled */
  225. #define CTRL_M_CB 0x00000800 /* recording source: 0 = ADC, 1 = MPEG */
  226. #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
  227. #define CTRL_PDLEV0 0x00000000 /* power down level */
  228. #define CTRL_PDLEV1 0x00000100
  229. #define CTRL_PDLEV2 0x00000200
  230. #define CTRL_PDLEV3 0x00000300
  231. #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
  232. #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
  233. #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
  234. #define CTRL_ADC_EN 0x00000010 /* enable ADC */
  235. #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
  236. #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port */
  237. #define CTRL_XTALCLKDIS 0x00000002 /* 1 = disable crystal clock input */
  238. #define CTRL_PCICLKDIS 0x00000001 /* 1 = disable PCI clock distribution */
  239. #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
  240. #define CSTAT_5880_AC97_RST 0x20000000 /* CT5880 Reset bit */
  241. #define STAT_EN_SPDIF 0x00040000 /* enable S/PDIF circuitry */
  242. #define STAT_TS_SPDIF 0x00020000 /* test S/PDIF circuitry */
  243. #define STAT_TESTMODE 0x00010000 /* test ASIC */
  244. #define STAT_SYNC_ERR 0x00000100 /* 1 = codec sync error */
  245. #define STAT_VC 0x000000c0 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
  246. #define STAT_SH_VC 6
  247. #define STAT_MPWR 0x00000020 /* power level interrupt */
  248. #define STAT_MCCB 0x00000010 /* CCB int pending */
  249. #define STAT_UART 0x00000008 /* UART int pending */
  250. #define STAT_DAC1 0x00000004 /* DAC1 int pending */
  251. #define STAT_DAC2 0x00000002 /* DAC2 int pending */
  252. #define STAT_ADC 0x00000001 /* ADC int pending */
  253. #define USTAT_RXINT 0x80 /* UART rx int pending */
  254. #define USTAT_TXINT 0x04 /* UART tx int pending */
  255. #define USTAT_TXRDY 0x02 /* UART tx ready */
  256. #define USTAT_RXRDY 0x01 /* UART rx ready */
  257. #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
  258. #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
  259. #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
  260. #define UCTRL_CNTRL 0x03 /* control field */
  261. #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
  262. /* sample rate converter */
  263. #define SRC_OKSTATE 1
  264. #define SRC_RAMADDR_MASK 0xfe000000
  265. #define SRC_RAMADDR_SHIFT 25
  266. #define SRC_DAC1FREEZE (1UL << 21)
  267. #define SRC_DAC2FREEZE (1UL << 20)
  268. #define SRC_ADCFREEZE (1UL << 19)
  269. #define SRC_WE 0x01000000 /* read/write control for SRC RAM */
  270. #define SRC_BUSY 0x00800000 /* SRC busy */
  271. #define SRC_DIS 0x00400000 /* 1 = disable SRC */
  272. #define SRC_DDAC1 0x00200000 /* 1 = disable accum update for DAC1 */
  273. #define SRC_DDAC2 0x00100000 /* 1 = disable accum update for DAC2 */
  274. #define SRC_DADC 0x00080000 /* 1 = disable accum update for ADC2 */
  275. #define SRC_CTLMASK 0x00780000
  276. #define SRC_RAMDATA_MASK 0x0000ffff
  277. #define SRC_RAMDATA_SHIFT 0
  278. #define SRCREG_ADC 0x78
  279. #define SRCREG_DAC1 0x70
  280. #define SRCREG_DAC2 0x74
  281. #define SRCREG_VOL_ADC 0x6c
  282. #define SRCREG_VOL_DAC1 0x7c
  283. #define SRCREG_VOL_DAC2 0x7e
  284. #define SRCREG_TRUNC_N 0x00
  285. #define SRCREG_INT_REGS 0x01
  286. #define SRCREG_ACCUM_FRAC 0x02
  287. #define SRCREG_VFREQ_FRAC 0x03
  288. #define CODEC_PIRD 0x00800000 /* 0 = write AC97 register */
  289. #define CODEC_PIADD_MASK 0x007f0000
  290. #define CODEC_PIADD_SHIFT 16
  291. #define CODEC_PIDAT_MASK 0x0000ffff
  292. #define CODEC_PIDAT_SHIFT 0
  293. #define CODEC_RDY 0x80000000 /* AC97 read data valid */
  294. #define CODEC_WIP 0x40000000 /* AC97 write in progress */
  295. #define CODEC_PORD 0x00800000 /* 0 = write AC97 register */
  296. #define CODEC_POADD_MASK 0x007f0000
  297. #define CODEC_POADD_SHIFT 16
  298. #define CODEC_PODAT_MASK 0x0000ffff
  299. #define CODEC_PODAT_SHIFT 0
  300. #define LEGACY_JFAST 0x80000000 /* fast joystick timing */
  301. #define LEGACY_FIRQ 0x01000000 /* force IRQ */
  302. #define SCTRL_DACTEST 0x00400000 /* 1 = DAC test, test vector generation purposes */
  303. #define SCTRL_P2ENDINC 0x00380000 /* */
  304. #define SCTRL_SH_P2ENDINC 19
  305. #define SCTRL_P2STINC 0x00070000 /* */
  306. #define SCTRL_SH_P2STINC 16
  307. #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
  308. #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
  309. #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
  310. #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
  311. #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
  312. #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
  313. #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
  314. #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
  315. #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
  316. #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
  317. #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
  318. #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
  319. #define SCTRL_R1FMT 0x00000030 /* format mask */
  320. #define SCTRL_SH_R1FMT 4
  321. #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
  322. #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
  323. #define SCTRL_P2FMT 0x0000000c /* format mask */
  324. #define SCTRL_SH_P2FMT 2
  325. #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
  326. #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
  327. #define SCTRL_P1FMT 0x00000003 /* format mask */
  328. #define SCTRL_SH_P1FMT 0
  329. /* misc stuff */
  330. #define POLL_COUNT 0x1000
  331. #define FMODE_DAC 4 /* slight misuse of mode_t */
  332. /* MIDI buffer sizes */
  333. #define MIDIINBUF 256
  334. #define MIDIOUTBUF 256
  335. #define FMODE_MIDI_SHIFT 3
  336. #define FMODE_MIDI_READ (FMODE_READ << FMODE_MIDI_SHIFT)
  337. #define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
  338. #define ES1371_MODULE_NAME "es1371"
  339. #define PFX ES1371_MODULE_NAME ": "
  340. /* --------------------------------------------------------------------- */
  341. struct es1371_state {
  342. /* magic */
  343. unsigned int magic;
  344. /* list of es1371 devices */
  345. struct list_head devs;
  346. /* the corresponding pci_dev structure */
  347. struct pci_dev *dev;
  348. /* soundcore stuff */
  349. int dev_audio;
  350. int dev_dac;
  351. int dev_midi;
  352. /* hardware resources */
  353. unsigned long io; /* long for SPARC */
  354. unsigned int irq;
  355. /* PCI ID's */
  356. u16 vendor;
  357. u16 device;
  358. u8 rev; /* the chip revision */
  359. /* options */
  360. int spdif_volume; /* S/PDIF output is enabled if != -1 */
  361. #ifdef ES1371_DEBUG
  362. /* debug /proc entry */
  363. struct proc_dir_entry *ps;
  364. #endif /* ES1371_DEBUG */
  365. struct ac97_codec *codec;
  366. /* wave stuff */
  367. unsigned ctrl;
  368. unsigned sctrl;
  369. unsigned dac1rate, dac2rate, adcrate;
  370. spinlock_t lock;
  371. struct mutex open_mutex;
  372. mode_t open_mode;
  373. wait_queue_head_t open_wait;
  374. struct dmabuf {
  375. void *rawbuf;
  376. dma_addr_t dmaaddr;
  377. unsigned buforder;
  378. unsigned numfrag;
  379. unsigned fragshift;
  380. unsigned hwptr, swptr;
  381. unsigned total_bytes;
  382. int count;
  383. unsigned error; /* over/underrun */
  384. wait_queue_head_t wait;
  385. /* redundant, but makes calculations easier */
  386. unsigned fragsize;
  387. unsigned dmasize;
  388. unsigned fragsamples;
  389. /* OSS stuff */
  390. unsigned mapped:1;
  391. unsigned ready:1;
  392. unsigned endcleared:1;
  393. unsigned enabled:1;
  394. unsigned ossfragshift;
  395. int ossmaxfrags;
  396. unsigned subdivision;
  397. } dma_dac1, dma_dac2, dma_adc;
  398. /* midi stuff */
  399. struct {
  400. unsigned ird, iwr, icnt;
  401. unsigned ord, owr, ocnt;
  402. wait_queue_head_t iwait;
  403. wait_queue_head_t owait;
  404. unsigned char ibuf[MIDIINBUF];
  405. unsigned char obuf[MIDIOUTBUF];
  406. } midi;
  407. #ifdef SUPPORT_JOYSTICK
  408. struct gameport *gameport;
  409. #endif
  410. struct mutex sem;
  411. };
  412. /* --------------------------------------------------------------------- */
  413. static LIST_HEAD(devs);
  414. /* --------------------------------------------------------------------- */
  415. static inline unsigned ld2(unsigned int x)
  416. {
  417. unsigned r = 0;
  418. if (x >= 0x10000) {
  419. x >>= 16;
  420. r += 16;
  421. }
  422. if (x >= 0x100) {
  423. x >>= 8;
  424. r += 8;
  425. }
  426. if (x >= 0x10) {
  427. x >>= 4;
  428. r += 4;
  429. }
  430. if (x >= 4) {
  431. x >>= 2;
  432. r += 2;
  433. }
  434. if (x >= 2)
  435. r++;
  436. return r;
  437. }
  438. /* --------------------------------------------------------------------- */
  439. static unsigned wait_src_ready(struct es1371_state *s)
  440. {
  441. unsigned int t, r;
  442. for (t = 0; t < POLL_COUNT; t++) {
  443. if (!((r = inl(s->io + ES1371_REG_SRCONV)) & SRC_BUSY))
  444. return r;
  445. udelay(1);
  446. }
  447. printk(KERN_DEBUG PFX "sample rate converter timeout r = 0x%08x\n", r);
  448. return r;
  449. }
  450. static unsigned src_read(struct es1371_state *s, unsigned reg)
  451. {
  452. unsigned int temp,i,orig;
  453. /* wait for ready */
  454. temp = wait_src_ready (s);
  455. /* we can only access the SRC at certain times, make sure
  456. we're allowed to before we read */
  457. orig = temp;
  458. /* expose the SRC state bits */
  459. outl ( (temp & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT) | 0x10000UL,
  460. s->io + ES1371_REG_SRCONV);
  461. /* now, wait for busy and the correct time to read */
  462. temp = wait_src_ready (s);
  463. if ( (temp & 0x00870000UL ) != ( SRC_OKSTATE << 16 )){
  464. /* wait for the right state */
  465. for (i=0; i<POLL_COUNT; i++){
  466. temp = inl (s->io + ES1371_REG_SRCONV);
  467. if ( (temp & 0x00870000UL ) == ( SRC_OKSTATE << 16 ))
  468. break;
  469. }
  470. }
  471. /* hide the state bits */
  472. outl ((orig & SRC_CTLMASK) | (reg << SRC_RAMADDR_SHIFT), s->io + ES1371_REG_SRCONV);
  473. return temp;
  474. }
  475. static void src_write(struct es1371_state *s, unsigned reg, unsigned data)
  476. {
  477. unsigned int r;
  478. r = wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC);
  479. r |= (reg << SRC_RAMADDR_SHIFT) & SRC_RAMADDR_MASK;
  480. r |= (data << SRC_RAMDATA_SHIFT) & SRC_RAMDATA_MASK;
  481. outl(r | SRC_WE, s->io + ES1371_REG_SRCONV);
  482. }
  483. /* --------------------------------------------------------------------- */
  484. /* most of the following here is black magic */
  485. static void set_adc_rate(struct es1371_state *s, unsigned rate)
  486. {
  487. unsigned long flags;
  488. unsigned int n, truncm, freq;
  489. if (rate > 48000)
  490. rate = 48000;
  491. if (rate < 4000)
  492. rate = 4000;
  493. n = rate / 3000;
  494. if ((1 << n) & ((1 << 15) | (1 << 13) | (1 << 11) | (1 << 9)))
  495. n--;
  496. truncm = (21 * n - 1) | 1;
  497. freq = ((48000UL << 15) / rate) * n;
  498. s->adcrate = (48000UL << 15) / (freq / n);
  499. spin_lock_irqsave(&s->lock, flags);
  500. if (rate >= 24000) {
  501. if (truncm > 239)
  502. truncm = 239;
  503. src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
  504. (((239 - truncm) >> 1) << 9) | (n << 4));
  505. } else {
  506. if (truncm > 119)
  507. truncm = 119;
  508. src_write(s, SRCREG_ADC+SRCREG_TRUNC_N,
  509. 0x8000 | (((119 - truncm) >> 1) << 9) | (n << 4));
  510. }
  511. src_write(s, SRCREG_ADC+SRCREG_INT_REGS,
  512. (src_read(s, SRCREG_ADC+SRCREG_INT_REGS) & 0x00ff) |
  513. ((freq >> 5) & 0xfc00));
  514. src_write(s, SRCREG_ADC+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  515. src_write(s, SRCREG_VOL_ADC, n << 8);
  516. src_write(s, SRCREG_VOL_ADC+1, n << 8);
  517. spin_unlock_irqrestore(&s->lock, flags);
  518. }
  519. static void set_dac1_rate(struct es1371_state *s, unsigned rate)
  520. {
  521. unsigned long flags;
  522. unsigned int freq, r;
  523. if (rate > 48000)
  524. rate = 48000;
  525. if (rate < 4000)
  526. rate = 4000;
  527. freq = ((rate << 15) + 1500) / 3000;
  528. s->dac1rate = (freq * 3000 + 16384) >> 15;
  529. spin_lock_irqsave(&s->lock, flags);
  530. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC)) | SRC_DDAC1;
  531. outl(r, s->io + ES1371_REG_SRCONV);
  532. src_write(s, SRCREG_DAC1+SRCREG_INT_REGS,
  533. (src_read(s, SRCREG_DAC1+SRCREG_INT_REGS) & 0x00ff) |
  534. ((freq >> 5) & 0xfc00));
  535. src_write(s, SRCREG_DAC1+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  536. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC2 | SRC_DADC));
  537. outl(r, s->io + ES1371_REG_SRCONV);
  538. spin_unlock_irqrestore(&s->lock, flags);
  539. }
  540. static void set_dac2_rate(struct es1371_state *s, unsigned rate)
  541. {
  542. unsigned long flags;
  543. unsigned int freq, r;
  544. if (rate > 48000)
  545. rate = 48000;
  546. if (rate < 4000)
  547. rate = 4000;
  548. freq = ((rate << 15) + 1500) / 3000;
  549. s->dac2rate = (freq * 3000 + 16384) >> 15;
  550. spin_lock_irqsave(&s->lock, flags);
  551. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC)) | SRC_DDAC2;
  552. outl(r, s->io + ES1371_REG_SRCONV);
  553. src_write(s, SRCREG_DAC2+SRCREG_INT_REGS,
  554. (src_read(s, SRCREG_DAC2+SRCREG_INT_REGS) & 0x00ff) |
  555. ((freq >> 5) & 0xfc00));
  556. src_write(s, SRCREG_DAC2+SRCREG_VFREQ_FRAC, freq & 0x7fff);
  557. r = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DADC));
  558. outl(r, s->io + ES1371_REG_SRCONV);
  559. spin_unlock_irqrestore(&s->lock, flags);
  560. }
  561. /* --------------------------------------------------------------------- */
  562. static void __devinit src_init(struct es1371_state *s)
  563. {
  564. unsigned int i;
  565. /* before we enable or disable the SRC we need
  566. to wait for it to become ready */
  567. wait_src_ready(s);
  568. outl(SRC_DIS, s->io + ES1371_REG_SRCONV);
  569. for (i = 0; i < 0x80; i++)
  570. src_write(s, i, 0);
  571. src_write(s, SRCREG_DAC1+SRCREG_TRUNC_N, 16 << 4);
  572. src_write(s, SRCREG_DAC1+SRCREG_INT_REGS, 16 << 10);
  573. src_write(s, SRCREG_DAC2+SRCREG_TRUNC_N, 16 << 4);
  574. src_write(s, SRCREG_DAC2+SRCREG_INT_REGS, 16 << 10);
  575. src_write(s, SRCREG_VOL_ADC, 1 << 12);
  576. src_write(s, SRCREG_VOL_ADC+1, 1 << 12);
  577. src_write(s, SRCREG_VOL_DAC1, 1 << 12);
  578. src_write(s, SRCREG_VOL_DAC1+1, 1 << 12);
  579. src_write(s, SRCREG_VOL_DAC2, 1 << 12);
  580. src_write(s, SRCREG_VOL_DAC2+1, 1 << 12);
  581. set_adc_rate(s, 22050);
  582. set_dac1_rate(s, 22050);
  583. set_dac2_rate(s, 22050);
  584. /* WARNING:
  585. * enabling the sample rate converter without properly programming
  586. * its parameters causes the chip to lock up (the SRC busy bit will
  587. * be stuck high, and I've found no way to rectify this other than
  588. * power cycle)
  589. */
  590. wait_src_ready(s);
  591. outl(0, s->io+ES1371_REG_SRCONV);
  592. }
  593. /* --------------------------------------------------------------------- */
  594. static void wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  595. {
  596. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  597. unsigned long flags;
  598. unsigned t, x;
  599. spin_lock_irqsave(&s->lock, flags);
  600. for (t = 0; t < POLL_COUNT; t++)
  601. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  602. break;
  603. /* save the current state for later */
  604. x = wait_src_ready(s);
  605. /* enable SRC state data in SRC mux */
  606. outl((x & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC)) | 0x00010000,
  607. s->io+ES1371_REG_SRCONV);
  608. /* wait for not busy (state 0) first to avoid
  609. transition states */
  610. for (t=0; t<POLL_COUNT; t++){
  611. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
  612. break;
  613. udelay(1);
  614. }
  615. /* wait for a SAFE time to write addr/data and then do it, dammit */
  616. for (t=0; t<POLL_COUNT; t++){
  617. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
  618. break;
  619. udelay(1);
  620. }
  621. outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) |
  622. ((data << CODEC_PODAT_SHIFT) & CODEC_PODAT_MASK), s->io+ES1371_REG_CODEC);
  623. /* restore SRC reg */
  624. wait_src_ready(s);
  625. outl(x, s->io+ES1371_REG_SRCONV);
  626. spin_unlock_irqrestore(&s->lock, flags);
  627. }
  628. static u16 rdcodec(struct ac97_codec *codec, u8 addr)
  629. {
  630. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  631. unsigned long flags;
  632. unsigned t, x;
  633. spin_lock_irqsave(&s->lock, flags);
  634. /* wait for WIP to go away */
  635. for (t = 0; t < 0x1000; t++)
  636. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  637. break;
  638. /* save the current state for later */
  639. x = (wait_src_ready(s) & (SRC_DIS | SRC_DDAC1 | SRC_DDAC2 | SRC_DADC));
  640. /* enable SRC state data in SRC mux */
  641. outl( x | 0x00010000,
  642. s->io+ES1371_REG_SRCONV);
  643. /* wait for not busy (state 0) first to avoid
  644. transition states */
  645. for (t=0; t<POLL_COUNT; t++){
  646. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0 )
  647. break;
  648. udelay(1);
  649. }
  650. /* wait for a SAFE time to write addr/data and then do it, dammit */
  651. for (t=0; t<POLL_COUNT; t++){
  652. if((inl(s->io+ES1371_REG_SRCONV) & 0x00870000) ==0x00010000)
  653. break;
  654. udelay(1);
  655. }
  656. outl(((addr << CODEC_POADD_SHIFT) & CODEC_POADD_MASK) | CODEC_PORD, s->io+ES1371_REG_CODEC);
  657. /* restore SRC reg */
  658. wait_src_ready(s);
  659. outl(x, s->io+ES1371_REG_SRCONV);
  660. /* wait for WIP again */
  661. for (t = 0; t < 0x1000; t++)
  662. if (!(inl(s->io+ES1371_REG_CODEC) & CODEC_WIP))
  663. break;
  664. /* now wait for the stinkin' data (RDY) */
  665. for (t = 0; t < POLL_COUNT; t++)
  666. if ((x = inl(s->io+ES1371_REG_CODEC)) & CODEC_RDY)
  667. break;
  668. spin_unlock_irqrestore(&s->lock, flags);
  669. return ((x & CODEC_PIDAT_MASK) >> CODEC_PIDAT_SHIFT);
  670. }
  671. /* --------------------------------------------------------------------- */
  672. static inline void stop_adc(struct es1371_state *s)
  673. {
  674. unsigned long flags;
  675. spin_lock_irqsave(&s->lock, flags);
  676. s->ctrl &= ~CTRL_ADC_EN;
  677. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  678. spin_unlock_irqrestore(&s->lock, flags);
  679. }
  680. static inline void stop_dac1(struct es1371_state *s)
  681. {
  682. unsigned long flags;
  683. spin_lock_irqsave(&s->lock, flags);
  684. s->ctrl &= ~CTRL_DAC1_EN;
  685. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  686. spin_unlock_irqrestore(&s->lock, flags);
  687. }
  688. static inline void stop_dac2(struct es1371_state *s)
  689. {
  690. unsigned long flags;
  691. spin_lock_irqsave(&s->lock, flags);
  692. s->ctrl &= ~CTRL_DAC2_EN;
  693. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  694. spin_unlock_irqrestore(&s->lock, flags);
  695. }
  696. static void start_dac1(struct es1371_state *s)
  697. {
  698. unsigned long flags;
  699. unsigned fragremain, fshift;
  700. spin_lock_irqsave(&s->lock, flags);
  701. if (!(s->ctrl & CTRL_DAC1_EN) && (s->dma_dac1.mapped || s->dma_dac1.count > 0)
  702. && s->dma_dac1.ready) {
  703. s->ctrl |= CTRL_DAC1_EN;
  704. s->sctrl = (s->sctrl & ~(SCTRL_P1LOOPSEL | SCTRL_P1PAUSE | SCTRL_P1SCTRLD)) | SCTRL_P1INTEN;
  705. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  706. fragremain = ((- s->dma_dac1.hwptr) & (s->dma_dac1.fragsize-1));
  707. fshift = sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
  708. if (fragremain < 2*fshift)
  709. fragremain = s->dma_dac1.fragsize;
  710. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
  711. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  712. outl((s->dma_dac1.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC1_SCOUNT);
  713. }
  714. spin_unlock_irqrestore(&s->lock, flags);
  715. }
  716. static void start_dac2(struct es1371_state *s)
  717. {
  718. unsigned long flags;
  719. unsigned fragremain, fshift;
  720. spin_lock_irqsave(&s->lock, flags);
  721. if (!(s->ctrl & CTRL_DAC2_EN) && (s->dma_dac2.mapped || s->dma_dac2.count > 0)
  722. && s->dma_dac2.ready) {
  723. s->ctrl |= CTRL_DAC2_EN;
  724. s->sctrl = (s->sctrl & ~(SCTRL_P2LOOPSEL | SCTRL_P2PAUSE | SCTRL_P2DACSEN |
  725. SCTRL_P2ENDINC | SCTRL_P2STINC)) | SCTRL_P2INTEN |
  726. (((s->sctrl & SCTRL_P2FMT) ? 2 : 1) << SCTRL_SH_P2ENDINC) |
  727. (0 << SCTRL_SH_P2STINC);
  728. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  729. fragremain = ((- s->dma_dac2.hwptr) & (s->dma_dac2.fragsize-1));
  730. fshift = sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
  731. if (fragremain < 2*fshift)
  732. fragremain = s->dma_dac2.fragsize;
  733. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
  734. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  735. outl((s->dma_dac2.fragsize >> fshift) - 1, s->io+ES1371_REG_DAC2_SCOUNT);
  736. }
  737. spin_unlock_irqrestore(&s->lock, flags);
  738. }
  739. static void start_adc(struct es1371_state *s)
  740. {
  741. unsigned long flags;
  742. unsigned fragremain, fshift;
  743. spin_lock_irqsave(&s->lock, flags);
  744. if (!(s->ctrl & CTRL_ADC_EN) && (s->dma_adc.mapped || s->dma_adc.count < (signed)(s->dma_adc.dmasize - 2*s->dma_adc.fragsize))
  745. && s->dma_adc.ready) {
  746. s->ctrl |= CTRL_ADC_EN;
  747. s->sctrl = (s->sctrl & ~SCTRL_R1LOOPSEL) | SCTRL_R1INTEN;
  748. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  749. fragremain = ((- s->dma_adc.hwptr) & (s->dma_adc.fragsize-1));
  750. fshift = sample_shift[(s->sctrl & SCTRL_R1FMT) >> SCTRL_SH_R1FMT];
  751. if (fragremain < 2*fshift)
  752. fragremain = s->dma_adc.fragsize;
  753. outl((fragremain >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
  754. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  755. outl((s->dma_adc.fragsize >> fshift) - 1, s->io+ES1371_REG_ADC_SCOUNT);
  756. }
  757. spin_unlock_irqrestore(&s->lock, flags);
  758. }
  759. /* --------------------------------------------------------------------- */
  760. #define DMABUF_DEFAULTORDER (17-PAGE_SHIFT)
  761. #define DMABUF_MINORDER 1
  762. static inline void dealloc_dmabuf(struct es1371_state *s, struct dmabuf *db)
  763. {
  764. struct page *page, *pend;
  765. if (db->rawbuf) {
  766. /* undo marking the pages as reserved */
  767. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  768. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  769. ClearPageReserved(page);
  770. pci_free_consistent(s->dev, PAGE_SIZE << db->buforder, db->rawbuf, db->dmaaddr);
  771. }
  772. db->rawbuf = NULL;
  773. db->mapped = db->ready = 0;
  774. }
  775. static int prog_dmabuf(struct es1371_state *s, struct dmabuf *db, unsigned rate, unsigned fmt, unsigned reg)
  776. {
  777. int order;
  778. unsigned bytepersec;
  779. unsigned bufs;
  780. struct page *page, *pend;
  781. db->hwptr = db->swptr = db->total_bytes = db->count = db->error = db->endcleared = 0;
  782. if (!db->rawbuf) {
  783. db->ready = db->mapped = 0;
  784. for (order = DMABUF_DEFAULTORDER; order >= DMABUF_MINORDER; order--)
  785. if ((db->rawbuf = pci_alloc_consistent(s->dev, PAGE_SIZE << order, &db->dmaaddr)))
  786. break;
  787. if (!db->rawbuf)
  788. return -ENOMEM;
  789. db->buforder = order;
  790. /* now mark the pages as reserved; otherwise remap_pfn_range doesn't do what we want */
  791. pend = virt_to_page(db->rawbuf + (PAGE_SIZE << db->buforder) - 1);
  792. for (page = virt_to_page(db->rawbuf); page <= pend; page++)
  793. SetPageReserved(page);
  794. }
  795. fmt &= ES1371_FMT_MASK;
  796. bytepersec = rate << sample_shift[fmt];
  797. bufs = PAGE_SIZE << db->buforder;
  798. if (db->ossfragshift) {
  799. if ((1000 << db->ossfragshift) < bytepersec)
  800. db->fragshift = ld2(bytepersec/1000);
  801. else
  802. db->fragshift = db->ossfragshift;
  803. } else {
  804. db->fragshift = ld2(bytepersec/100/(db->subdivision ? db->subdivision : 1));
  805. if (db->fragshift < 3)
  806. db->fragshift = 3;
  807. }
  808. db->numfrag = bufs >> db->fragshift;
  809. while (db->numfrag < 4 && db->fragshift > 3) {
  810. db->fragshift--;
  811. db->numfrag = bufs >> db->fragshift;
  812. }
  813. db->fragsize = 1 << db->fragshift;
  814. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  815. db->numfrag = db->ossmaxfrags;
  816. db->fragsamples = db->fragsize >> sample_shift[fmt];
  817. db->dmasize = db->numfrag << db->fragshift;
  818. memset(db->rawbuf, (fmt & ES1371_FMT_S16) ? 0 : 0x80, db->dmasize);
  819. outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
  820. outl(db->dmaaddr, s->io+(reg & 0xff));
  821. outl((db->dmasize >> 2)-1, s->io+((reg + 4) & 0xff));
  822. db->enabled = 1;
  823. db->ready = 1;
  824. return 0;
  825. }
  826. static inline int prog_dmabuf_adc(struct es1371_state *s)
  827. {
  828. stop_adc(s);
  829. return prog_dmabuf(s, &s->dma_adc, s->adcrate, (s->sctrl >> SCTRL_SH_R1FMT) & ES1371_FMT_MASK,
  830. ES1371_REG_ADC_FRAMEADR);
  831. }
  832. static inline int prog_dmabuf_dac2(struct es1371_state *s)
  833. {
  834. stop_dac2(s);
  835. return prog_dmabuf(s, &s->dma_dac2, s->dac2rate, (s->sctrl >> SCTRL_SH_P2FMT) & ES1371_FMT_MASK,
  836. ES1371_REG_DAC2_FRAMEADR);
  837. }
  838. static inline int prog_dmabuf_dac1(struct es1371_state *s)
  839. {
  840. stop_dac1(s);
  841. return prog_dmabuf(s, &s->dma_dac1, s->dac1rate, (s->sctrl >> SCTRL_SH_P1FMT) & ES1371_FMT_MASK,
  842. ES1371_REG_DAC1_FRAMEADR);
  843. }
  844. static inline unsigned get_hwptr(struct es1371_state *s, struct dmabuf *db, unsigned reg)
  845. {
  846. unsigned hwptr, diff;
  847. outl((reg >> 8) & 15, s->io+ES1371_REG_MEMPAGE);
  848. hwptr = (inl(s->io+(reg & 0xff)) >> 14) & 0x3fffc;
  849. diff = (db->dmasize + hwptr - db->hwptr) % db->dmasize;
  850. db->hwptr = hwptr;
  851. return diff;
  852. }
  853. static inline void clear_advance(void *buf, unsigned bsize, unsigned bptr, unsigned len, unsigned char c)
  854. {
  855. if (bptr + len > bsize) {
  856. unsigned x = bsize - bptr;
  857. memset(((char *)buf) + bptr, c, x);
  858. bptr = 0;
  859. len -= x;
  860. }
  861. memset(((char *)buf) + bptr, c, len);
  862. }
  863. /* call with spinlock held! */
  864. static void es1371_update_ptr(struct es1371_state *s)
  865. {
  866. int diff;
  867. /* update ADC pointer */
  868. if (s->ctrl & CTRL_ADC_EN) {
  869. diff = get_hwptr(s, &s->dma_adc, ES1371_REG_ADC_FRAMECNT);
  870. s->dma_adc.total_bytes += diff;
  871. s->dma_adc.count += diff;
  872. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  873. wake_up(&s->dma_adc.wait);
  874. if (!s->dma_adc.mapped) {
  875. if (s->dma_adc.count > (signed)(s->dma_adc.dmasize - ((3 * s->dma_adc.fragsize) >> 1))) {
  876. s->ctrl &= ~CTRL_ADC_EN;
  877. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  878. s->dma_adc.error++;
  879. }
  880. }
  881. }
  882. /* update DAC1 pointer */
  883. if (s->ctrl & CTRL_DAC1_EN) {
  884. diff = get_hwptr(s, &s->dma_dac1, ES1371_REG_DAC1_FRAMECNT);
  885. s->dma_dac1.total_bytes += diff;
  886. if (s->dma_dac1.mapped) {
  887. s->dma_dac1.count += diff;
  888. if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
  889. wake_up(&s->dma_dac1.wait);
  890. } else {
  891. s->dma_dac1.count -= diff;
  892. if (s->dma_dac1.count <= 0) {
  893. s->ctrl &= ~CTRL_DAC1_EN;
  894. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  895. s->dma_dac1.error++;
  896. } else if (s->dma_dac1.count <= (signed)s->dma_dac1.fragsize && !s->dma_dac1.endcleared) {
  897. clear_advance(s->dma_dac1.rawbuf, s->dma_dac1.dmasize, s->dma_dac1.swptr,
  898. s->dma_dac1.fragsize, (s->sctrl & SCTRL_P1SEB) ? 0 : 0x80);
  899. s->dma_dac1.endcleared = 1;
  900. }
  901. if (s->dma_dac1.count + (signed)s->dma_dac1.fragsize <= (signed)s->dma_dac1.dmasize)
  902. wake_up(&s->dma_dac1.wait);
  903. }
  904. }
  905. /* update DAC2 pointer */
  906. if (s->ctrl & CTRL_DAC2_EN) {
  907. diff = get_hwptr(s, &s->dma_dac2, ES1371_REG_DAC2_FRAMECNT);
  908. s->dma_dac2.total_bytes += diff;
  909. if (s->dma_dac2.mapped) {
  910. s->dma_dac2.count += diff;
  911. if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
  912. wake_up(&s->dma_dac2.wait);
  913. } else {
  914. s->dma_dac2.count -= diff;
  915. if (s->dma_dac2.count <= 0) {
  916. s->ctrl &= ~CTRL_DAC2_EN;
  917. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  918. s->dma_dac2.error++;
  919. } else if (s->dma_dac2.count <= (signed)s->dma_dac2.fragsize && !s->dma_dac2.endcleared) {
  920. clear_advance(s->dma_dac2.rawbuf, s->dma_dac2.dmasize, s->dma_dac2.swptr,
  921. s->dma_dac2.fragsize, (s->sctrl & SCTRL_P2SEB) ? 0 : 0x80);
  922. s->dma_dac2.endcleared = 1;
  923. }
  924. if (s->dma_dac2.count + (signed)s->dma_dac2.fragsize <= (signed)s->dma_dac2.dmasize)
  925. wake_up(&s->dma_dac2.wait);
  926. }
  927. }
  928. }
  929. /* hold spinlock for the following! */
  930. static void es1371_handle_midi(struct es1371_state *s)
  931. {
  932. unsigned char ch;
  933. int wake;
  934. if (!(s->ctrl & CTRL_UART_EN))
  935. return;
  936. wake = 0;
  937. while (inb(s->io+ES1371_REG_UART_STATUS) & USTAT_RXRDY) {
  938. ch = inb(s->io+ES1371_REG_UART_DATA);
  939. if (s->midi.icnt < MIDIINBUF) {
  940. s->midi.ibuf[s->midi.iwr] = ch;
  941. s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
  942. s->midi.icnt++;
  943. }
  944. wake = 1;
  945. }
  946. if (wake)
  947. wake_up(&s->midi.iwait);
  948. wake = 0;
  949. while ((inb(s->io+ES1371_REG_UART_STATUS) & USTAT_TXRDY) && s->midi.ocnt > 0) {
  950. outb(s->midi.obuf[s->midi.ord], s->io+ES1371_REG_UART_DATA);
  951. s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
  952. s->midi.ocnt--;
  953. if (s->midi.ocnt < MIDIOUTBUF-16)
  954. wake = 1;
  955. }
  956. if (wake)
  957. wake_up(&s->midi.owait);
  958. outb((s->midi.ocnt > 0) ? UCTRL_RXINTEN | UCTRL_ENA_TXINT : UCTRL_RXINTEN, s->io+ES1371_REG_UART_CONTROL);
  959. }
  960. static irqreturn_t es1371_interrupt(int irq, void *dev_id)
  961. {
  962. struct es1371_state *s = dev_id;
  963. unsigned int intsrc, sctl;
  964. /* fastpath out, to ease interrupt sharing */
  965. intsrc = inl(s->io+ES1371_REG_STATUS);
  966. if (!(intsrc & 0x80000000))
  967. return IRQ_NONE;
  968. spin_lock(&s->lock);
  969. /* clear audio interrupts first */
  970. sctl = s->sctrl;
  971. if (intsrc & STAT_ADC)
  972. sctl &= ~SCTRL_R1INTEN;
  973. if (intsrc & STAT_DAC1)
  974. sctl &= ~SCTRL_P1INTEN;
  975. if (intsrc & STAT_DAC2)
  976. sctl &= ~SCTRL_P2INTEN;
  977. outl(sctl, s->io+ES1371_REG_SERIAL_CONTROL);
  978. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  979. es1371_update_ptr(s);
  980. es1371_handle_midi(s);
  981. spin_unlock(&s->lock);
  982. return IRQ_HANDLED;
  983. }
  984. /* --------------------------------------------------------------------- */
  985. static const char invalid_magic[] = KERN_CRIT PFX "invalid magic value\n";
  986. #define VALIDATE_STATE(s) \
  987. ({ \
  988. if (!(s) || (s)->magic != ES1371_MAGIC) { \
  989. printk(invalid_magic); \
  990. return -ENXIO; \
  991. } \
  992. })
  993. /* --------------------------------------------------------------------- */
  994. /* Conversion table for S/PDIF PCM volume emulation through the SRC */
  995. /* dB-linear table of DAC vol values; -0dB to -46.5dB with mute */
  996. static const unsigned short DACVolTable[101] =
  997. {
  998. 0x1000, 0x0f2a, 0x0e60, 0x0da0, 0x0cea, 0x0c3e, 0x0b9a, 0x0aff,
  999. 0x0a6d, 0x09e1, 0x095e, 0x08e1, 0x086a, 0x07fa, 0x078f, 0x072a,
  1000. 0x06cb, 0x0670, 0x061a, 0x05c9, 0x057b, 0x0532, 0x04ed, 0x04ab,
  1001. 0x046d, 0x0432, 0x03fa, 0x03c5, 0x0392, 0x0363, 0x0335, 0x030b,
  1002. 0x02e2, 0x02bc, 0x0297, 0x0275, 0x0254, 0x0235, 0x0217, 0x01fb,
  1003. 0x01e1, 0x01c8, 0x01b0, 0x0199, 0x0184, 0x0170, 0x015d, 0x014b,
  1004. 0x0139, 0x0129, 0x0119, 0x010b, 0x00fd, 0x00f0, 0x00e3, 0x00d7,
  1005. 0x00cc, 0x00c1, 0x00b7, 0x00ae, 0x00a5, 0x009c, 0x0094, 0x008c,
  1006. 0x0085, 0x007e, 0x0077, 0x0071, 0x006b, 0x0066, 0x0060, 0x005b,
  1007. 0x0057, 0x0052, 0x004e, 0x004a, 0x0046, 0x0042, 0x003f, 0x003c,
  1008. 0x0038, 0x0036, 0x0033, 0x0030, 0x002e, 0x002b, 0x0029, 0x0027,
  1009. 0x0025, 0x0023, 0x0021, 0x001f, 0x001e, 0x001c, 0x001b, 0x0019,
  1010. 0x0018, 0x0017, 0x0016, 0x0014, 0x0000
  1011. };
  1012. /*
  1013. * when we are in S/PDIF mode, we want to disable any analog output so
  1014. * we filter the mixer ioctls
  1015. */
  1016. static int mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd, unsigned long arg)
  1017. {
  1018. struct es1371_state *s = (struct es1371_state *)codec->private_data;
  1019. int val;
  1020. unsigned long flags;
  1021. unsigned int left, right;
  1022. VALIDATE_STATE(s);
  1023. /* filter mixer ioctls to catch PCM and MASTER volume when in S/PDIF mode */
  1024. if (s->spdif_volume == -1)
  1025. return codec->mixer_ioctl(codec, cmd, arg);
  1026. switch (cmd) {
  1027. case SOUND_MIXER_WRITE_VOLUME:
  1028. return 0;
  1029. case SOUND_MIXER_WRITE_PCM: /* use SRC for PCM volume */
  1030. if (get_user(val, (int __user *)arg))
  1031. return -EFAULT;
  1032. right = ((val >> 8) & 0xff);
  1033. left = (val & 0xff);
  1034. if (right > 100)
  1035. right = 100;
  1036. if (left > 100)
  1037. left = 100;
  1038. s->spdif_volume = (right << 8) | left;
  1039. spin_lock_irqsave(&s->lock, flags);
  1040. src_write(s, SRCREG_VOL_DAC2, DACVolTable[100 - left]);
  1041. src_write(s, SRCREG_VOL_DAC2+1, DACVolTable[100 - right]);
  1042. spin_unlock_irqrestore(&s->lock, flags);
  1043. return 0;
  1044. case SOUND_MIXER_READ_PCM:
  1045. return put_user(s->spdif_volume, (int __user *)arg);
  1046. }
  1047. return codec->mixer_ioctl(codec, cmd, arg);
  1048. }
  1049. /* --------------------------------------------------------------------- */
  1050. /*
  1051. * AC97 Mixer Register to Connections mapping of the Concert 97 board
  1052. *
  1053. * AC97_MASTER_VOL_STEREO Line Out
  1054. * AC97_MASTER_VOL_MONO TAD Output
  1055. * AC97_PCBEEP_VOL none
  1056. * AC97_PHONE_VOL TAD Input (mono)
  1057. * AC97_MIC_VOL MIC Input (mono)
  1058. * AC97_LINEIN_VOL Line Input (stereo)
  1059. * AC97_CD_VOL CD Input (stereo)
  1060. * AC97_VIDEO_VOL none
  1061. * AC97_AUX_VOL Aux Input (stereo)
  1062. * AC97_PCMOUT_VOL Wave Output (stereo)
  1063. */
  1064. static int es1371_open_mixdev(struct inode *inode, struct file *file)
  1065. {
  1066. int minor = iminor(inode);
  1067. struct list_head *list;
  1068. struct es1371_state *s;
  1069. for (list = devs.next; ; list = list->next) {
  1070. if (list == &devs)
  1071. return -ENODEV;
  1072. s = list_entry(list, struct es1371_state, devs);
  1073. if (s->codec->dev_mixer == minor)
  1074. break;
  1075. }
  1076. VALIDATE_STATE(s);
  1077. file->private_data = s;
  1078. return nonseekable_open(inode, file);
  1079. }
  1080. static int es1371_release_mixdev(struct inode *inode, struct file *file)
  1081. {
  1082. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1083. VALIDATE_STATE(s);
  1084. return 0;
  1085. }
  1086. static int es1371_ioctl_mixdev(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1087. {
  1088. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1089. struct ac97_codec *codec = s->codec;
  1090. return mixdev_ioctl(codec, cmd, arg);
  1091. }
  1092. static /*const*/ struct file_operations es1371_mixer_fops = {
  1093. .owner = THIS_MODULE,
  1094. .llseek = no_llseek,
  1095. .ioctl = es1371_ioctl_mixdev,
  1096. .open = es1371_open_mixdev,
  1097. .release = es1371_release_mixdev,
  1098. };
  1099. /* --------------------------------------------------------------------- */
  1100. static int drain_dac1(struct es1371_state *s, int nonblock)
  1101. {
  1102. DECLARE_WAITQUEUE(wait, current);
  1103. unsigned long flags;
  1104. int count, tmo;
  1105. if (s->dma_dac1.mapped || !s->dma_dac1.ready)
  1106. return 0;
  1107. add_wait_queue(&s->dma_dac1.wait, &wait);
  1108. for (;;) {
  1109. __set_current_state(TASK_INTERRUPTIBLE);
  1110. spin_lock_irqsave(&s->lock, flags);
  1111. count = s->dma_dac1.count;
  1112. spin_unlock_irqrestore(&s->lock, flags);
  1113. if (count <= 0)
  1114. break;
  1115. if (signal_pending(current))
  1116. break;
  1117. if (nonblock) {
  1118. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1119. set_current_state(TASK_RUNNING);
  1120. return -EBUSY;
  1121. }
  1122. tmo = 3 * HZ * (count + s->dma_dac1.fragsize) / 2 / s->dac1rate;
  1123. tmo >>= sample_shift[(s->sctrl & SCTRL_P1FMT) >> SCTRL_SH_P1FMT];
  1124. if (!schedule_timeout(tmo + 1))
  1125. DBG(printk(KERN_DEBUG PFX "dac1 dma timed out??\n");)
  1126. }
  1127. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1128. set_current_state(TASK_RUNNING);
  1129. if (signal_pending(current))
  1130. return -ERESTARTSYS;
  1131. return 0;
  1132. }
  1133. static int drain_dac2(struct es1371_state *s, int nonblock)
  1134. {
  1135. DECLARE_WAITQUEUE(wait, current);
  1136. unsigned long flags;
  1137. int count, tmo;
  1138. if (s->dma_dac2.mapped || !s->dma_dac2.ready)
  1139. return 0;
  1140. add_wait_queue(&s->dma_dac2.wait, &wait);
  1141. for (;;) {
  1142. __set_current_state(TASK_UNINTERRUPTIBLE);
  1143. spin_lock_irqsave(&s->lock, flags);
  1144. count = s->dma_dac2.count;
  1145. spin_unlock_irqrestore(&s->lock, flags);
  1146. if (count <= 0)
  1147. break;
  1148. if (signal_pending(current))
  1149. break;
  1150. if (nonblock) {
  1151. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1152. set_current_state(TASK_RUNNING);
  1153. return -EBUSY;
  1154. }
  1155. tmo = 3 * HZ * (count + s->dma_dac2.fragsize) / 2 / s->dac2rate;
  1156. tmo >>= sample_shift[(s->sctrl & SCTRL_P2FMT) >> SCTRL_SH_P2FMT];
  1157. if (!schedule_timeout(tmo + 1))
  1158. DBG(printk(KERN_DEBUG PFX "dac2 dma timed out??\n");)
  1159. }
  1160. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1161. set_current_state(TASK_RUNNING);
  1162. if (signal_pending(current))
  1163. return -ERESTARTSYS;
  1164. return 0;
  1165. }
  1166. /* --------------------------------------------------------------------- */
  1167. static ssize_t es1371_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  1168. {
  1169. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1170. DECLARE_WAITQUEUE(wait, current);
  1171. ssize_t ret = 0;
  1172. unsigned long flags;
  1173. unsigned swptr;
  1174. int cnt;
  1175. VALIDATE_STATE(s);
  1176. if (s->dma_adc.mapped)
  1177. return -ENXIO;
  1178. if (!access_ok(VERIFY_WRITE, buffer, count))
  1179. return -EFAULT;
  1180. mutex_lock(&s->sem);
  1181. if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
  1182. goto out2;
  1183. add_wait_queue(&s->dma_adc.wait, &wait);
  1184. while (count > 0) {
  1185. spin_lock_irqsave(&s->lock, flags);
  1186. swptr = s->dma_adc.swptr;
  1187. cnt = s->dma_adc.dmasize-swptr;
  1188. if (s->dma_adc.count < cnt)
  1189. cnt = s->dma_adc.count;
  1190. if (cnt <= 0)
  1191. __set_current_state(TASK_INTERRUPTIBLE);
  1192. spin_unlock_irqrestore(&s->lock, flags);
  1193. if (cnt > count)
  1194. cnt = count;
  1195. if (cnt <= 0) {
  1196. if (s->dma_adc.enabled)
  1197. start_adc(s);
  1198. if (file->f_flags & O_NONBLOCK) {
  1199. if (!ret)
  1200. ret = -EAGAIN;
  1201. goto out;
  1202. }
  1203. mutex_unlock(&s->sem);
  1204. schedule();
  1205. if (signal_pending(current)) {
  1206. if (!ret)
  1207. ret = -ERESTARTSYS;
  1208. goto out2;
  1209. }
  1210. mutex_lock(&s->sem);
  1211. if (s->dma_adc.mapped)
  1212. {
  1213. ret = -ENXIO;
  1214. goto out;
  1215. }
  1216. continue;
  1217. }
  1218. if (copy_to_user(buffer, s->dma_adc.rawbuf + swptr, cnt)) {
  1219. if (!ret)
  1220. ret = -EFAULT;
  1221. goto out;
  1222. }
  1223. swptr = (swptr + cnt) % s->dma_adc.dmasize;
  1224. spin_lock_irqsave(&s->lock, flags);
  1225. s->dma_adc.swptr = swptr;
  1226. s->dma_adc.count -= cnt;
  1227. spin_unlock_irqrestore(&s->lock, flags);
  1228. count -= cnt;
  1229. buffer += cnt;
  1230. ret += cnt;
  1231. if (s->dma_adc.enabled)
  1232. start_adc(s);
  1233. }
  1234. out:
  1235. mutex_unlock(&s->sem);
  1236. out2:
  1237. remove_wait_queue(&s->dma_adc.wait, &wait);
  1238. set_current_state(TASK_RUNNING);
  1239. return ret;
  1240. }
  1241. static ssize_t es1371_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1242. {
  1243. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1244. DECLARE_WAITQUEUE(wait, current);
  1245. ssize_t ret;
  1246. unsigned long flags;
  1247. unsigned swptr;
  1248. int cnt;
  1249. VALIDATE_STATE(s);
  1250. if (s->dma_dac2.mapped)
  1251. return -ENXIO;
  1252. if (!access_ok(VERIFY_READ, buffer, count))
  1253. return -EFAULT;
  1254. mutex_lock(&s->sem);
  1255. if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
  1256. goto out3;
  1257. ret = 0;
  1258. add_wait_queue(&s->dma_dac2.wait, &wait);
  1259. while (count > 0) {
  1260. spin_lock_irqsave(&s->lock, flags);
  1261. if (s->dma_dac2.count < 0) {
  1262. s->dma_dac2.count = 0;
  1263. s->dma_dac2.swptr = s->dma_dac2.hwptr;
  1264. }
  1265. swptr = s->dma_dac2.swptr;
  1266. cnt = s->dma_dac2.dmasize-swptr;
  1267. if (s->dma_dac2.count + cnt > s->dma_dac2.dmasize)
  1268. cnt = s->dma_dac2.dmasize - s->dma_dac2.count;
  1269. if (cnt <= 0)
  1270. __set_current_state(TASK_INTERRUPTIBLE);
  1271. spin_unlock_irqrestore(&s->lock, flags);
  1272. if (cnt > count)
  1273. cnt = count;
  1274. if (cnt <= 0) {
  1275. if (s->dma_dac2.enabled)
  1276. start_dac2(s);
  1277. if (file->f_flags & O_NONBLOCK) {
  1278. if (!ret)
  1279. ret = -EAGAIN;
  1280. goto out;
  1281. }
  1282. mutex_unlock(&s->sem);
  1283. schedule();
  1284. if (signal_pending(current)) {
  1285. if (!ret)
  1286. ret = -ERESTARTSYS;
  1287. goto out2;
  1288. }
  1289. mutex_lock(&s->sem);
  1290. if (s->dma_dac2.mapped)
  1291. {
  1292. ret = -ENXIO;
  1293. goto out;
  1294. }
  1295. continue;
  1296. }
  1297. if (copy_from_user(s->dma_dac2.rawbuf + swptr, buffer, cnt)) {
  1298. if (!ret)
  1299. ret = -EFAULT;
  1300. goto out;
  1301. }
  1302. swptr = (swptr + cnt) % s->dma_dac2.dmasize;
  1303. spin_lock_irqsave(&s->lock, flags);
  1304. s->dma_dac2.swptr = swptr;
  1305. s->dma_dac2.count += cnt;
  1306. s->dma_dac2.endcleared = 0;
  1307. spin_unlock_irqrestore(&s->lock, flags);
  1308. count -= cnt;
  1309. buffer += cnt;
  1310. ret += cnt;
  1311. if (s->dma_dac2.enabled)
  1312. start_dac2(s);
  1313. }
  1314. out:
  1315. mutex_unlock(&s->sem);
  1316. out2:
  1317. remove_wait_queue(&s->dma_dac2.wait, &wait);
  1318. out3:
  1319. set_current_state(TASK_RUNNING);
  1320. return ret;
  1321. }
  1322. /* No kernel lock - we have our own spinlock */
  1323. static unsigned int es1371_poll(struct file *file, struct poll_table_struct *wait)
  1324. {
  1325. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1326. unsigned long flags;
  1327. unsigned int mask = 0;
  1328. VALIDATE_STATE(s);
  1329. if (file->f_mode & FMODE_WRITE) {
  1330. if (!s->dma_dac2.ready && prog_dmabuf_dac2(s))
  1331. return 0;
  1332. poll_wait(file, &s->dma_dac2.wait, wait);
  1333. }
  1334. if (file->f_mode & FMODE_READ) {
  1335. if (!s->dma_adc.ready && prog_dmabuf_adc(s))
  1336. return 0;
  1337. poll_wait(file, &s->dma_adc.wait, wait);
  1338. }
  1339. spin_lock_irqsave(&s->lock, flags);
  1340. es1371_update_ptr(s);
  1341. if (file->f_mode & FMODE_READ) {
  1342. if (s->dma_adc.count >= (signed)s->dma_adc.fragsize)
  1343. mask |= POLLIN | POLLRDNORM;
  1344. }
  1345. if (file->f_mode & FMODE_WRITE) {
  1346. if (s->dma_dac2.mapped) {
  1347. if (s->dma_dac2.count >= (signed)s->dma_dac2.fragsize)
  1348. mask |= POLLOUT | POLLWRNORM;
  1349. } else {
  1350. if ((signed)s->dma_dac2.dmasize >= s->dma_dac2.count + (signed)s->dma_dac2.fragsize)
  1351. mask |= POLLOUT | POLLWRNORM;
  1352. }
  1353. }
  1354. spin_unlock_irqrestore(&s->lock, flags);
  1355. return mask;
  1356. }
  1357. static int es1371_mmap(struct file *file, struct vm_area_struct *vma)
  1358. {
  1359. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1360. struct dmabuf *db;
  1361. int ret = 0;
  1362. unsigned long size;
  1363. VALIDATE_STATE(s);
  1364. lock_kernel();
  1365. mutex_lock(&s->sem);
  1366. if (vma->vm_flags & VM_WRITE) {
  1367. if ((ret = prog_dmabuf_dac2(s)) != 0) {
  1368. goto out;
  1369. }
  1370. db = &s->dma_dac2;
  1371. } else if (vma->vm_flags & VM_READ) {
  1372. if ((ret = prog_dmabuf_adc(s)) != 0) {
  1373. goto out;
  1374. }
  1375. db = &s->dma_adc;
  1376. } else {
  1377. ret = -EINVAL;
  1378. goto out;
  1379. }
  1380. if (vma->vm_pgoff != 0) {
  1381. ret = -EINVAL;
  1382. goto out;
  1383. }
  1384. size = vma->vm_end - vma->vm_start;
  1385. if (size > (PAGE_SIZE << db->buforder)) {
  1386. ret = -EINVAL;
  1387. goto out;
  1388. }
  1389. if (remap_pfn_range(vma, vma->vm_start,
  1390. virt_to_phys(db->rawbuf) >> PAGE_SHIFT,
  1391. size, vma->vm_page_prot)) {
  1392. ret = -EAGAIN;
  1393. goto out;
  1394. }
  1395. db->mapped = 1;
  1396. out:
  1397. mutex_unlock(&s->sem);
  1398. unlock_kernel();
  1399. return ret;
  1400. }
  1401. static int es1371_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1402. {
  1403. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1404. unsigned long flags;
  1405. audio_buf_info abinfo;
  1406. count_info cinfo;
  1407. int count;
  1408. int val, mapped, ret;
  1409. void __user *argp = (void __user *)arg;
  1410. int __user *p = argp;
  1411. VALIDATE_STATE(s);
  1412. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac2.mapped) ||
  1413. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1414. switch (cmd) {
  1415. case OSS_GETVERSION:
  1416. return put_user(SOUND_VERSION, p);
  1417. case SNDCTL_DSP_SYNC:
  1418. if (file->f_mode & FMODE_WRITE)
  1419. return drain_dac2(s, 0/*file->f_flags & O_NONBLOCK*/);
  1420. return 0;
  1421. case SNDCTL_DSP_SETDUPLEX:
  1422. return 0;
  1423. case SNDCTL_DSP_GETCAPS:
  1424. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1425. case SNDCTL_DSP_RESET:
  1426. if (file->f_mode & FMODE_WRITE) {
  1427. stop_dac2(s);
  1428. synchronize_irq(s->irq);
  1429. s->dma_dac2.swptr = s->dma_dac2.hwptr = s->dma_dac2.count = s->dma_dac2.total_bytes = 0;
  1430. }
  1431. if (file->f_mode & FMODE_READ) {
  1432. stop_adc(s);
  1433. synchronize_irq(s->irq);
  1434. s->dma_adc.swptr = s->dma_adc.hwptr = s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1435. }
  1436. return 0;
  1437. case SNDCTL_DSP_SPEED:
  1438. if (get_user(val, p))
  1439. return -EFAULT;
  1440. if (val >= 0) {
  1441. if (file->f_mode & FMODE_READ) {
  1442. stop_adc(s);
  1443. s->dma_adc.ready = 0;
  1444. set_adc_rate(s, val);
  1445. }
  1446. if (file->f_mode & FMODE_WRITE) {
  1447. stop_dac2(s);
  1448. s->dma_dac2.ready = 0;
  1449. set_dac2_rate(s, val);
  1450. }
  1451. }
  1452. return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
  1453. case SNDCTL_DSP_STEREO:
  1454. if (get_user(val, p))
  1455. return -EFAULT;
  1456. if (file->f_mode & FMODE_READ) {
  1457. stop_adc(s);
  1458. s->dma_adc.ready = 0;
  1459. spin_lock_irqsave(&s->lock, flags);
  1460. if (val)
  1461. s->sctrl |= SCTRL_R1SMB;
  1462. else
  1463. s->sctrl &= ~SCTRL_R1SMB;
  1464. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1465. spin_unlock_irqrestore(&s->lock, flags);
  1466. }
  1467. if (file->f_mode & FMODE_WRITE) {
  1468. stop_dac2(s);
  1469. s->dma_dac2.ready = 0;
  1470. spin_lock_irqsave(&s->lock, flags);
  1471. if (val)
  1472. s->sctrl |= SCTRL_P2SMB;
  1473. else
  1474. s->sctrl &= ~SCTRL_P2SMB;
  1475. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1476. spin_unlock_irqrestore(&s->lock, flags);
  1477. }
  1478. return 0;
  1479. case SNDCTL_DSP_CHANNELS:
  1480. if (get_user(val, p))
  1481. return -EFAULT;
  1482. if (val != 0) {
  1483. if (file->f_mode & FMODE_READ) {
  1484. stop_adc(s);
  1485. s->dma_adc.ready = 0;
  1486. spin_lock_irqsave(&s->lock, flags);
  1487. if (val >= 2)
  1488. s->sctrl |= SCTRL_R1SMB;
  1489. else
  1490. s->sctrl &= ~SCTRL_R1SMB;
  1491. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1492. spin_unlock_irqrestore(&s->lock, flags);
  1493. }
  1494. if (file->f_mode & FMODE_WRITE) {
  1495. stop_dac2(s);
  1496. s->dma_dac2.ready = 0;
  1497. spin_lock_irqsave(&s->lock, flags);
  1498. if (val >= 2)
  1499. s->sctrl |= SCTRL_P2SMB;
  1500. else
  1501. s->sctrl &= ~SCTRL_P2SMB;
  1502. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1503. spin_unlock_irqrestore(&s->lock, flags);
  1504. }
  1505. }
  1506. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
  1507. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1508. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1509. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1510. if (get_user(val, p))
  1511. return -EFAULT;
  1512. if (val != AFMT_QUERY) {
  1513. if (file->f_mode & FMODE_READ) {
  1514. stop_adc(s);
  1515. s->dma_adc.ready = 0;
  1516. spin_lock_irqsave(&s->lock, flags);
  1517. if (val == AFMT_S16_LE)
  1518. s->sctrl |= SCTRL_R1SEB;
  1519. else
  1520. s->sctrl &= ~SCTRL_R1SEB;
  1521. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1522. spin_unlock_irqrestore(&s->lock, flags);
  1523. }
  1524. if (file->f_mode & FMODE_WRITE) {
  1525. stop_dac2(s);
  1526. s->dma_dac2.ready = 0;
  1527. spin_lock_irqsave(&s->lock, flags);
  1528. if (val == AFMT_S16_LE)
  1529. s->sctrl |= SCTRL_P2SEB;
  1530. else
  1531. s->sctrl &= ~SCTRL_P2SEB;
  1532. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1533. spin_unlock_irqrestore(&s->lock, flags);
  1534. }
  1535. }
  1536. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ?
  1537. AFMT_S16_LE : AFMT_U8, p);
  1538. case SNDCTL_DSP_POST:
  1539. return 0;
  1540. case SNDCTL_DSP_GETTRIGGER:
  1541. val = 0;
  1542. if (file->f_mode & FMODE_READ && s->ctrl & CTRL_ADC_EN)
  1543. val |= PCM_ENABLE_INPUT;
  1544. if (file->f_mode & FMODE_WRITE && s->ctrl & CTRL_DAC2_EN)
  1545. val |= PCM_ENABLE_OUTPUT;
  1546. return put_user(val, p);
  1547. case SNDCTL_DSP_SETTRIGGER:
  1548. if (get_user(val, p))
  1549. return -EFAULT;
  1550. if (file->f_mode & FMODE_READ) {
  1551. if (val & PCM_ENABLE_INPUT) {
  1552. if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
  1553. return ret;
  1554. s->dma_adc.enabled = 1;
  1555. start_adc(s);
  1556. } else {
  1557. s->dma_adc.enabled = 0;
  1558. stop_adc(s);
  1559. }
  1560. }
  1561. if (file->f_mode & FMODE_WRITE) {
  1562. if (val & PCM_ENABLE_OUTPUT) {
  1563. if (!s->dma_dac2.ready && (ret = prog_dmabuf_dac2(s)))
  1564. return ret;
  1565. s->dma_dac2.enabled = 1;
  1566. start_dac2(s);
  1567. } else {
  1568. s->dma_dac2.enabled = 0;
  1569. stop_dac2(s);
  1570. }
  1571. }
  1572. return 0;
  1573. case SNDCTL_DSP_GETOSPACE:
  1574. if (!(file->f_mode & FMODE_WRITE))
  1575. return -EINVAL;
  1576. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1577. return val;
  1578. spin_lock_irqsave(&s->lock, flags);
  1579. es1371_update_ptr(s);
  1580. abinfo.fragsize = s->dma_dac2.fragsize;
  1581. count = s->dma_dac2.count;
  1582. if (count < 0)
  1583. count = 0;
  1584. abinfo.bytes = s->dma_dac2.dmasize - count;
  1585. abinfo.fragstotal = s->dma_dac2.numfrag;
  1586. abinfo.fragments = abinfo.bytes >> s->dma_dac2.fragshift;
  1587. spin_unlock_irqrestore(&s->lock, flags);
  1588. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1589. case SNDCTL_DSP_GETISPACE:
  1590. if (!(file->f_mode & FMODE_READ))
  1591. return -EINVAL;
  1592. if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
  1593. return val;
  1594. spin_lock_irqsave(&s->lock, flags);
  1595. es1371_update_ptr(s);
  1596. abinfo.fragsize = s->dma_adc.fragsize;
  1597. count = s->dma_adc.count;
  1598. if (count < 0)
  1599. count = 0;
  1600. abinfo.bytes = count;
  1601. abinfo.fragstotal = s->dma_adc.numfrag;
  1602. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1603. spin_unlock_irqrestore(&s->lock, flags);
  1604. return copy_to_user(argp, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  1605. case SNDCTL_DSP_NONBLOCK:
  1606. file->f_flags |= O_NONBLOCK;
  1607. return 0;
  1608. case SNDCTL_DSP_GETODELAY:
  1609. if (!(file->f_mode & FMODE_WRITE))
  1610. return -EINVAL;
  1611. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1612. return val;
  1613. spin_lock_irqsave(&s->lock, flags);
  1614. es1371_update_ptr(s);
  1615. count = s->dma_dac2.count;
  1616. spin_unlock_irqrestore(&s->lock, flags);
  1617. if (count < 0)
  1618. count = 0;
  1619. return put_user(count, p);
  1620. case SNDCTL_DSP_GETIPTR:
  1621. if (!(file->f_mode & FMODE_READ))
  1622. return -EINVAL;
  1623. if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)) != 0)
  1624. return val;
  1625. spin_lock_irqsave(&s->lock, flags);
  1626. es1371_update_ptr(s);
  1627. cinfo.bytes = s->dma_adc.total_bytes;
  1628. count = s->dma_adc.count;
  1629. if (count < 0)
  1630. count = 0;
  1631. cinfo.blocks = count >> s->dma_adc.fragshift;
  1632. cinfo.ptr = s->dma_adc.hwptr;
  1633. if (s->dma_adc.mapped)
  1634. s->dma_adc.count &= s->dma_adc.fragsize-1;
  1635. spin_unlock_irqrestore(&s->lock, flags);
  1636. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1637. return -EFAULT;
  1638. return 0;
  1639. case SNDCTL_DSP_GETOPTR:
  1640. if (!(file->f_mode & FMODE_WRITE))
  1641. return -EINVAL;
  1642. if (!s->dma_dac2.ready && (val = prog_dmabuf_dac2(s)) != 0)
  1643. return val;
  1644. spin_lock_irqsave(&s->lock, flags);
  1645. es1371_update_ptr(s);
  1646. cinfo.bytes = s->dma_dac2.total_bytes;
  1647. count = s->dma_dac2.count;
  1648. if (count < 0)
  1649. count = 0;
  1650. cinfo.blocks = count >> s->dma_dac2.fragshift;
  1651. cinfo.ptr = s->dma_dac2.hwptr;
  1652. if (s->dma_dac2.mapped)
  1653. s->dma_dac2.count &= s->dma_dac2.fragsize-1;
  1654. spin_unlock_irqrestore(&s->lock, flags);
  1655. if (copy_to_user(argp, &cinfo, sizeof(cinfo)))
  1656. return -EFAULT;
  1657. return 0;
  1658. case SNDCTL_DSP_GETBLKSIZE:
  1659. if (file->f_mode & FMODE_WRITE) {
  1660. if ((val = prog_dmabuf_dac2(s)))
  1661. return val;
  1662. return put_user(s->dma_dac2.fragsize, p);
  1663. }
  1664. if ((val = prog_dmabuf_adc(s)))
  1665. return val;
  1666. return put_user(s->dma_adc.fragsize, p);
  1667. case SNDCTL_DSP_SETFRAGMENT:
  1668. if (get_user(val, p))
  1669. return -EFAULT;
  1670. if (file->f_mode & FMODE_READ) {
  1671. s->dma_adc.ossfragshift = val & 0xffff;
  1672. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1673. if (s->dma_adc.ossfragshift < 4)
  1674. s->dma_adc.ossfragshift = 4;
  1675. if (s->dma_adc.ossfragshift > 15)
  1676. s->dma_adc.ossfragshift = 15;
  1677. if (s->dma_adc.ossmaxfrags < 4)
  1678. s->dma_adc.ossmaxfrags = 4;
  1679. }
  1680. if (file->f_mode & FMODE_WRITE) {
  1681. s->dma_dac2.ossfragshift = val & 0xffff;
  1682. s->dma_dac2.ossmaxfrags = (val >> 16) & 0xffff;
  1683. if (s->dma_dac2.ossfragshift < 4)
  1684. s->dma_dac2.ossfragshift = 4;
  1685. if (s->dma_dac2.ossfragshift > 15)
  1686. s->dma_dac2.ossfragshift = 15;
  1687. if (s->dma_dac2.ossmaxfrags < 4)
  1688. s->dma_dac2.ossmaxfrags = 4;
  1689. }
  1690. return 0;
  1691. case SNDCTL_DSP_SUBDIVIDE:
  1692. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1693. (file->f_mode & FMODE_WRITE && s->dma_dac2.subdivision))
  1694. return -EINVAL;
  1695. if (get_user(val, p))
  1696. return -EFAULT;
  1697. if (val != 1 && val != 2 && val != 4)
  1698. return -EINVAL;
  1699. if (file->f_mode & FMODE_READ)
  1700. s->dma_adc.subdivision = val;
  1701. if (file->f_mode & FMODE_WRITE)
  1702. s->dma_dac2.subdivision = val;
  1703. return 0;
  1704. case SOUND_PCM_READ_RATE:
  1705. return put_user((file->f_mode & FMODE_READ) ? s->adcrate : s->dac2rate, p);
  1706. case SOUND_PCM_READ_CHANNELS:
  1707. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SMB : SCTRL_P2SMB)) ? 2 : 1, p);
  1708. case SOUND_PCM_READ_BITS:
  1709. return put_user((s->sctrl & ((file->f_mode & FMODE_READ) ? SCTRL_R1SEB : SCTRL_P2SEB)) ? 16 : 8, p);
  1710. case SOUND_PCM_WRITE_FILTER:
  1711. case SNDCTL_DSP_SETSYNCRO:
  1712. case SOUND_PCM_READ_FILTER:
  1713. return -EINVAL;
  1714. }
  1715. return mixdev_ioctl(s->codec, cmd, arg);
  1716. }
  1717. static int es1371_open(struct inode *inode, struct file *file)
  1718. {
  1719. int minor = iminor(inode);
  1720. DECLARE_WAITQUEUE(wait, current);
  1721. unsigned long flags;
  1722. struct list_head *list;
  1723. struct es1371_state *s;
  1724. for (list = devs.next; ; list = list->next) {
  1725. if (list == &devs)
  1726. return -ENODEV;
  1727. s = list_entry(list, struct es1371_state, devs);
  1728. if (!((s->dev_audio ^ minor) & ~0xf))
  1729. break;
  1730. }
  1731. VALIDATE_STATE(s);
  1732. file->private_data = s;
  1733. /* wait for device to become free */
  1734. mutex_lock(&s->open_mutex);
  1735. while (s->open_mode & file->f_mode) {
  1736. if (file->f_flags & O_NONBLOCK) {
  1737. mutex_unlock(&s->open_mutex);
  1738. return -EBUSY;
  1739. }
  1740. add_wait_queue(&s->open_wait, &wait);
  1741. __set_current_state(TASK_INTERRUPTIBLE);
  1742. mutex_unlock(&s->open_mutex);
  1743. schedule();
  1744. remove_wait_queue(&s->open_wait, &wait);
  1745. set_current_state(TASK_RUNNING);
  1746. if (signal_pending(current))
  1747. return -ERESTARTSYS;
  1748. mutex_lock(&s->open_mutex);
  1749. }
  1750. if (file->f_mode & FMODE_READ) {
  1751. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = s->dma_adc.subdivision = 0;
  1752. s->dma_adc.enabled = 1;
  1753. set_adc_rate(s, 8000);
  1754. }
  1755. if (file->f_mode & FMODE_WRITE) {
  1756. s->dma_dac2.ossfragshift = s->dma_dac2.ossmaxfrags = s->dma_dac2.subdivision = 0;
  1757. s->dma_dac2.enabled = 1;
  1758. set_dac2_rate(s, 8000);
  1759. }
  1760. spin_lock_irqsave(&s->lock, flags);
  1761. if (file->f_mode & FMODE_READ) {
  1762. s->sctrl &= ~SCTRL_R1FMT;
  1763. if ((minor & 0xf) == SND_DEV_DSP16)
  1764. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_R1FMT;
  1765. else
  1766. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_R1FMT;
  1767. }
  1768. if (file->f_mode & FMODE_WRITE) {
  1769. s->sctrl &= ~SCTRL_P2FMT;
  1770. if ((minor & 0xf) == SND_DEV_DSP16)
  1771. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P2FMT;
  1772. else
  1773. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P2FMT;
  1774. }
  1775. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1776. spin_unlock_irqrestore(&s->lock, flags);
  1777. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1778. mutex_unlock(&s->open_mutex);
  1779. mutex_init(&s->sem);
  1780. return nonseekable_open(inode, file);
  1781. }
  1782. static int es1371_release(struct inode *inode, struct file *file)
  1783. {
  1784. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1785. VALIDATE_STATE(s);
  1786. lock_kernel();
  1787. if (file->f_mode & FMODE_WRITE)
  1788. drain_dac2(s, file->f_flags & O_NONBLOCK);
  1789. mutex_lock(&s->open_mutex);
  1790. if (file->f_mode & FMODE_WRITE) {
  1791. stop_dac2(s);
  1792. dealloc_dmabuf(s, &s->dma_dac2);
  1793. }
  1794. if (file->f_mode & FMODE_READ) {
  1795. stop_adc(s);
  1796. dealloc_dmabuf(s, &s->dma_adc);
  1797. }
  1798. s->open_mode &= ~(file->f_mode & (FMODE_READ|FMODE_WRITE));
  1799. mutex_unlock(&s->open_mutex);
  1800. wake_up(&s->open_wait);
  1801. unlock_kernel();
  1802. return 0;
  1803. }
  1804. static /*const*/ struct file_operations es1371_audio_fops = {
  1805. .owner = THIS_MODULE,
  1806. .llseek = no_llseek,
  1807. .read = es1371_read,
  1808. .write = es1371_write,
  1809. .poll = es1371_poll,
  1810. .ioctl = es1371_ioctl,
  1811. .mmap = es1371_mmap,
  1812. .open = es1371_open,
  1813. .release = es1371_release,
  1814. };
  1815. /* --------------------------------------------------------------------- */
  1816. static ssize_t es1371_write_dac(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  1817. {
  1818. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1819. DECLARE_WAITQUEUE(wait, current);
  1820. ssize_t ret = 0;
  1821. unsigned long flags;
  1822. unsigned swptr;
  1823. int cnt;
  1824. VALIDATE_STATE(s);
  1825. if (s->dma_dac1.mapped)
  1826. return -ENXIO;
  1827. if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
  1828. return ret;
  1829. if (!access_ok(VERIFY_READ, buffer, count))
  1830. return -EFAULT;
  1831. add_wait_queue(&s->dma_dac1.wait, &wait);
  1832. while (count > 0) {
  1833. spin_lock_irqsave(&s->lock, flags);
  1834. if (s->dma_dac1.count < 0) {
  1835. s->dma_dac1.count = 0;
  1836. s->dma_dac1.swptr = s->dma_dac1.hwptr;
  1837. }
  1838. swptr = s->dma_dac1.swptr;
  1839. cnt = s->dma_dac1.dmasize-swptr;
  1840. if (s->dma_dac1.count + cnt > s->dma_dac1.dmasize)
  1841. cnt = s->dma_dac1.dmasize - s->dma_dac1.count;
  1842. if (cnt <= 0)
  1843. __set_current_state(TASK_INTERRUPTIBLE);
  1844. spin_unlock_irqrestore(&s->lock, flags);
  1845. if (cnt > count)
  1846. cnt = count;
  1847. if (cnt <= 0) {
  1848. if (s->dma_dac1.enabled)
  1849. start_dac1(s);
  1850. if (file->f_flags & O_NONBLOCK) {
  1851. if (!ret)
  1852. ret = -EAGAIN;
  1853. break;
  1854. }
  1855. schedule();
  1856. if (signal_pending(current)) {
  1857. if (!ret)
  1858. ret = -ERESTARTSYS;
  1859. break;
  1860. }
  1861. continue;
  1862. }
  1863. if (copy_from_user(s->dma_dac1.rawbuf + swptr, buffer, cnt)) {
  1864. if (!ret)
  1865. ret = -EFAULT;
  1866. break;
  1867. }
  1868. swptr = (swptr + cnt) % s->dma_dac1.dmasize;
  1869. spin_lock_irqsave(&s->lock, flags);
  1870. s->dma_dac1.swptr = swptr;
  1871. s->dma_dac1.count += cnt;
  1872. s->dma_dac1.endcleared = 0;
  1873. spin_unlock_irqrestore(&s->lock, flags);
  1874. count -= cnt;
  1875. buffer += cnt;
  1876. ret += cnt;
  1877. if (s->dma_dac1.enabled)
  1878. start_dac1(s);
  1879. }
  1880. remove_wait_queue(&s->dma_dac1.wait, &wait);
  1881. set_current_state(TASK_RUNNING);
  1882. return ret;
  1883. }
  1884. /* No kernel lock - we have our own spinlock */
  1885. static unsigned int es1371_poll_dac(struct file *file, struct poll_table_struct *wait)
  1886. {
  1887. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1888. unsigned long flags;
  1889. unsigned int mask = 0;
  1890. VALIDATE_STATE(s);
  1891. if (!s->dma_dac1.ready && prog_dmabuf_dac1(s))
  1892. return 0;
  1893. poll_wait(file, &s->dma_dac1.wait, wait);
  1894. spin_lock_irqsave(&s->lock, flags);
  1895. es1371_update_ptr(s);
  1896. if (s->dma_dac1.mapped) {
  1897. if (s->dma_dac1.count >= (signed)s->dma_dac1.fragsize)
  1898. mask |= POLLOUT | POLLWRNORM;
  1899. } else {
  1900. if ((signed)s->dma_dac1.dmasize >= s->dma_dac1.count + (signed)s->dma_dac1.fragsize)
  1901. mask |= POLLOUT | POLLWRNORM;
  1902. }
  1903. spin_unlock_irqrestore(&s->lock, flags);
  1904. return mask;
  1905. }
  1906. static int es1371_mmap_dac(struct file *file, struct vm_area_struct *vma)
  1907. {
  1908. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1909. int ret;
  1910. unsigned long size;
  1911. VALIDATE_STATE(s);
  1912. if (!(vma->vm_flags & VM_WRITE))
  1913. return -EINVAL;
  1914. lock_kernel();
  1915. if ((ret = prog_dmabuf_dac1(s)) != 0)
  1916. goto out;
  1917. ret = -EINVAL;
  1918. if (vma->vm_pgoff != 0)
  1919. goto out;
  1920. size = vma->vm_end - vma->vm_start;
  1921. if (size > (PAGE_SIZE << s->dma_dac1.buforder))
  1922. goto out;
  1923. ret = -EAGAIN;
  1924. if (remap_pfn_range(vma, vma->vm_start,
  1925. virt_to_phys(s->dma_dac1.rawbuf) >> PAGE_SHIFT,
  1926. size, vma->vm_page_prot))
  1927. goto out;
  1928. s->dma_dac1.mapped = 1;
  1929. ret = 0;
  1930. out:
  1931. unlock_kernel();
  1932. return ret;
  1933. }
  1934. static int es1371_ioctl_dac(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  1935. {
  1936. struct es1371_state *s = (struct es1371_state *)file->private_data;
  1937. unsigned long flags;
  1938. audio_buf_info abinfo;
  1939. count_info cinfo;
  1940. int count;
  1941. int val, ret;
  1942. int __user *p = (int __user *)arg;
  1943. VALIDATE_STATE(s);
  1944. switch (cmd) {
  1945. case OSS_GETVERSION:
  1946. return put_user(SOUND_VERSION, p);
  1947. case SNDCTL_DSP_SYNC:
  1948. return drain_dac1(s, 0/*file->f_flags & O_NONBLOCK*/);
  1949. case SNDCTL_DSP_SETDUPLEX:
  1950. return -EINVAL;
  1951. case SNDCTL_DSP_GETCAPS:
  1952. return put_user(DSP_CAP_REALTIME | DSP_CAP_TRIGGER | DSP_CAP_MMAP, p);
  1953. case SNDCTL_DSP_RESET:
  1954. stop_dac1(s);
  1955. synchronize_irq(s->irq);
  1956. s->dma_dac1.swptr = s->dma_dac1.hwptr = s->dma_dac1.count = s->dma_dac1.total_bytes = 0;
  1957. return 0;
  1958. case SNDCTL_DSP_SPEED:
  1959. if (get_user(val, p))
  1960. return -EFAULT;
  1961. if (val >= 0) {
  1962. stop_dac1(s);
  1963. s->dma_dac1.ready = 0;
  1964. set_dac1_rate(s, val);
  1965. }
  1966. return put_user(s->dac1rate, p);
  1967. case SNDCTL_DSP_STEREO:
  1968. if (get_user(val, p))
  1969. return -EFAULT;
  1970. stop_dac1(s);
  1971. s->dma_dac1.ready = 0;
  1972. spin_lock_irqsave(&s->lock, flags);
  1973. if (val)
  1974. s->sctrl |= SCTRL_P1SMB;
  1975. else
  1976. s->sctrl &= ~SCTRL_P1SMB;
  1977. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1978. spin_unlock_irqrestore(&s->lock, flags);
  1979. return 0;
  1980. case SNDCTL_DSP_CHANNELS:
  1981. if (get_user(val, p))
  1982. return -EFAULT;
  1983. if (val != 0) {
  1984. stop_dac1(s);
  1985. s->dma_dac1.ready = 0;
  1986. spin_lock_irqsave(&s->lock, flags);
  1987. if (val >= 2)
  1988. s->sctrl |= SCTRL_P1SMB;
  1989. else
  1990. s->sctrl &= ~SCTRL_P1SMB;
  1991. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  1992. spin_unlock_irqrestore(&s->lock, flags);
  1993. }
  1994. return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
  1995. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1996. return put_user(AFMT_S16_LE|AFMT_U8, p);
  1997. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt*/
  1998. if (get_user(val, p))
  1999. return -EFAULT;
  2000. if (val != AFMT_QUERY) {
  2001. stop_dac1(s);
  2002. s->dma_dac1.ready = 0;
  2003. spin_lock_irqsave(&s->lock, flags);
  2004. if (val == AFMT_S16_LE)
  2005. s->sctrl |= SCTRL_P1SEB;
  2006. else
  2007. s->sctrl &= ~SCTRL_P1SEB;
  2008. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2009. spin_unlock_irqrestore(&s->lock, flags);
  2010. }
  2011. return put_user((s->sctrl & SCTRL_P1SEB) ? AFMT_S16_LE : AFMT_U8, p);
  2012. case SNDCTL_DSP_POST:
  2013. return 0;
  2014. case SNDCTL_DSP_GETTRIGGER:
  2015. return put_user((s->ctrl & CTRL_DAC1_EN) ? PCM_ENABLE_OUTPUT : 0, p);
  2016. case SNDCTL_DSP_SETTRIGGER:
  2017. if (get_user(val, p))
  2018. return -EFAULT;
  2019. if (val & PCM_ENABLE_OUTPUT) {
  2020. if (!s->dma_dac1.ready && (ret = prog_dmabuf_dac1(s)))
  2021. return ret;
  2022. s->dma_dac1.enabled = 1;
  2023. start_dac1(s);
  2024. } else {
  2025. s->dma_dac1.enabled = 0;
  2026. stop_dac1(s);
  2027. }
  2028. return 0;
  2029. case SNDCTL_DSP_GETOSPACE:
  2030. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2031. return val;
  2032. spin_lock_irqsave(&s->lock, flags);
  2033. es1371_update_ptr(s);
  2034. abinfo.fragsize = s->dma_dac1.fragsize;
  2035. count = s->dma_dac1.count;
  2036. if (count < 0)
  2037. count = 0;
  2038. abinfo.bytes = s->dma_dac1.dmasize - count;
  2039. abinfo.fragstotal = s->dma_dac1.numfrag;
  2040. abinfo.fragments = abinfo.bytes >> s->dma_dac1.fragshift;
  2041. spin_unlock_irqrestore(&s->lock, flags);
  2042. return copy_to_user((void __user *)arg, &abinfo, sizeof(abinfo)) ? -EFAULT : 0;
  2043. case SNDCTL_DSP_NONBLOCK:
  2044. file->f_flags |= O_NONBLOCK;
  2045. return 0;
  2046. case SNDCTL_DSP_GETODELAY:
  2047. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2048. return val;
  2049. spin_lock_irqsave(&s->lock, flags);
  2050. es1371_update_ptr(s);
  2051. count = s->dma_dac1.count;
  2052. spin_unlock_irqrestore(&s->lock, flags);
  2053. if (count < 0)
  2054. count = 0;
  2055. return put_user(count, p);
  2056. case SNDCTL_DSP_GETOPTR:
  2057. if (!s->dma_dac1.ready && (val = prog_dmabuf_dac1(s)) != 0)
  2058. return val;
  2059. spin_lock_irqsave(&s->lock, flags);
  2060. es1371_update_ptr(s);
  2061. cinfo.bytes = s->dma_dac1.total_bytes;
  2062. count = s->dma_dac1.count;
  2063. if (count < 0)
  2064. count = 0;
  2065. cinfo.blocks = count >> s->dma_dac1.fragshift;
  2066. cinfo.ptr = s->dma_dac1.hwptr;
  2067. if (s->dma_dac1.mapped)
  2068. s->dma_dac1.count &= s->dma_dac1.fragsize-1;
  2069. spin_unlock_irqrestore(&s->lock, flags);
  2070. if (copy_to_user((void __user *)arg, &cinfo, sizeof(cinfo)))
  2071. return -EFAULT;
  2072. return 0;
  2073. case SNDCTL_DSP_GETBLKSIZE:
  2074. if ((val = prog_dmabuf_dac1(s)))
  2075. return val;
  2076. return put_user(s->dma_dac1.fragsize, p);
  2077. case SNDCTL_DSP_SETFRAGMENT:
  2078. if (get_user(val, p))
  2079. return -EFAULT;
  2080. s->dma_dac1.ossfragshift = val & 0xffff;
  2081. s->dma_dac1.ossmaxfrags = (val >> 16) & 0xffff;
  2082. if (s->dma_dac1.ossfragshift < 4)
  2083. s->dma_dac1.ossfragshift = 4;
  2084. if (s->dma_dac1.ossfragshift > 15)
  2085. s->dma_dac1.ossfragshift = 15;
  2086. if (s->dma_dac1.ossmaxfrags < 4)
  2087. s->dma_dac1.ossmaxfrags = 4;
  2088. return 0;
  2089. case SNDCTL_DSP_SUBDIVIDE:
  2090. if (s->dma_dac1.subdivision)
  2091. return -EINVAL;
  2092. if (get_user(val, p))
  2093. return -EFAULT;
  2094. if (val != 1 && val != 2 && val != 4)
  2095. return -EINVAL;
  2096. s->dma_dac1.subdivision = val;
  2097. return 0;
  2098. case SOUND_PCM_READ_RATE:
  2099. return put_user(s->dac1rate, p);
  2100. case SOUND_PCM_READ_CHANNELS:
  2101. return put_user((s->sctrl & SCTRL_P1SMB) ? 2 : 1, p);
  2102. case SOUND_PCM_READ_BITS:
  2103. return put_user((s->sctrl & SCTRL_P1SEB) ? 16 : 8, p);
  2104. case SOUND_PCM_WRITE_FILTER:
  2105. case SNDCTL_DSP_SETSYNCRO:
  2106. case SOUND_PCM_READ_FILTER:
  2107. return -EINVAL;
  2108. }
  2109. return mixdev_ioctl(s->codec, cmd, arg);
  2110. }
  2111. static int es1371_open_dac(struct inode *inode, struct file *file)
  2112. {
  2113. int minor = iminor(inode);
  2114. DECLARE_WAITQUEUE(wait, current);
  2115. unsigned long flags;
  2116. struct list_head *list;
  2117. struct es1371_state *s;
  2118. for (list = devs.next; ; list = list->next) {
  2119. if (list == &devs)
  2120. return -ENODEV;
  2121. s = list_entry(list, struct es1371_state, devs);
  2122. if (!((s->dev_dac ^ minor) & ~0xf))
  2123. break;
  2124. }
  2125. VALIDATE_STATE(s);
  2126. /* we allow opening with O_RDWR, most programs do it although they will only write */
  2127. #if 0
  2128. if (file->f_mode & FMODE_READ)
  2129. return -EPERM;
  2130. #endif
  2131. if (!(file->f_mode & FMODE_WRITE))
  2132. return -EINVAL;
  2133. file->private_data = s;
  2134. /* wait for device to become free */
  2135. mutex_lock(&s->open_mutex);
  2136. while (s->open_mode & FMODE_DAC) {
  2137. if (file->f_flags & O_NONBLOCK) {
  2138. mutex_unlock(&s->open_mutex);
  2139. return -EBUSY;
  2140. }
  2141. add_wait_queue(&s->open_wait, &wait);
  2142. __set_current_state(TASK_INTERRUPTIBLE);
  2143. mutex_unlock(&s->open_mutex);
  2144. schedule();
  2145. remove_wait_queue(&s->open_wait, &wait);
  2146. set_current_state(TASK_RUNNING);
  2147. if (signal_pending(current))
  2148. return -ERESTARTSYS;
  2149. mutex_lock(&s->open_mutex);
  2150. }
  2151. s->dma_dac1.ossfragshift = s->dma_dac1.ossmaxfrags = s->dma_dac1.subdivision = 0;
  2152. s->dma_dac1.enabled = 1;
  2153. set_dac1_rate(s, 8000);
  2154. spin_lock_irqsave(&s->lock, flags);
  2155. s->sctrl &= ~SCTRL_P1FMT;
  2156. if ((minor & 0xf) == SND_DEV_DSP16)
  2157. s->sctrl |= ES1371_FMT_S16_MONO << SCTRL_SH_P1FMT;
  2158. else
  2159. s->sctrl |= ES1371_FMT_U8_MONO << SCTRL_SH_P1FMT;
  2160. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2161. spin_unlock_irqrestore(&s->lock, flags);
  2162. s->open_mode |= FMODE_DAC;
  2163. mutex_unlock(&s->open_mutex);
  2164. return nonseekable_open(inode, file);
  2165. }
  2166. static int es1371_release_dac(struct inode *inode, struct file *file)
  2167. {
  2168. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2169. VALIDATE_STATE(s);
  2170. lock_kernel();
  2171. drain_dac1(s, file->f_flags & O_NONBLOCK);
  2172. mutex_lock(&s->open_mutex);
  2173. stop_dac1(s);
  2174. dealloc_dmabuf(s, &s->dma_dac1);
  2175. s->open_mode &= ~FMODE_DAC;
  2176. mutex_unlock(&s->open_mutex);
  2177. wake_up(&s->open_wait);
  2178. unlock_kernel();
  2179. return 0;
  2180. }
  2181. static /*const*/ struct file_operations es1371_dac_fops = {
  2182. .owner = THIS_MODULE,
  2183. .llseek = no_llseek,
  2184. .write = es1371_write_dac,
  2185. .poll = es1371_poll_dac,
  2186. .ioctl = es1371_ioctl_dac,
  2187. .mmap = es1371_mmap_dac,
  2188. .open = es1371_open_dac,
  2189. .release = es1371_release_dac,
  2190. };
  2191. /* --------------------------------------------------------------------- */
  2192. static ssize_t es1371_midi_read(struct file *file, char __user *buffer, size_t count, loff_t *ppos)
  2193. {
  2194. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2195. DECLARE_WAITQUEUE(wait, current);
  2196. ssize_t ret;
  2197. unsigned long flags;
  2198. unsigned ptr;
  2199. int cnt;
  2200. VALIDATE_STATE(s);
  2201. if (!access_ok(VERIFY_WRITE, buffer, count))
  2202. return -EFAULT;
  2203. if (count == 0)
  2204. return 0;
  2205. ret = 0;
  2206. add_wait_queue(&s->midi.iwait, &wait);
  2207. while (count > 0) {
  2208. spin_lock_irqsave(&s->lock, flags);
  2209. ptr = s->midi.ird;
  2210. cnt = MIDIINBUF - ptr;
  2211. if (s->midi.icnt < cnt)
  2212. cnt = s->midi.icnt;
  2213. if (cnt <= 0)
  2214. __set_current_state(TASK_INTERRUPTIBLE);
  2215. spin_unlock_irqrestore(&s->lock, flags);
  2216. if (cnt > count)
  2217. cnt = count;
  2218. if (cnt <= 0) {
  2219. if (file->f_flags & O_NONBLOCK) {
  2220. if (!ret)
  2221. ret = -EAGAIN;
  2222. break;
  2223. }
  2224. schedule();
  2225. if (signal_pending(current)) {
  2226. if (!ret)
  2227. ret = -ERESTARTSYS;
  2228. break;
  2229. }
  2230. continue;
  2231. }
  2232. if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt)) {
  2233. if (!ret)
  2234. ret = -EFAULT;
  2235. break;
  2236. }
  2237. ptr = (ptr + cnt) % MIDIINBUF;
  2238. spin_lock_irqsave(&s->lock, flags);
  2239. s->midi.ird = ptr;
  2240. s->midi.icnt -= cnt;
  2241. spin_unlock_irqrestore(&s->lock, flags);
  2242. count -= cnt;
  2243. buffer += cnt;
  2244. ret += cnt;
  2245. break;
  2246. }
  2247. __set_current_state(TASK_RUNNING);
  2248. remove_wait_queue(&s->midi.iwait, &wait);
  2249. return ret;
  2250. }
  2251. static ssize_t es1371_midi_write(struct file *file, const char __user *buffer, size_t count, loff_t *ppos)
  2252. {
  2253. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2254. DECLARE_WAITQUEUE(wait, current);
  2255. ssize_t ret;
  2256. unsigned long flags;
  2257. unsigned ptr;
  2258. int cnt;
  2259. VALIDATE_STATE(s);
  2260. if (!access_ok(VERIFY_READ, buffer, count))
  2261. return -EFAULT;
  2262. if (count == 0)
  2263. return 0;
  2264. ret = 0;
  2265. add_wait_queue(&s->midi.owait, &wait);
  2266. while (count > 0) {
  2267. spin_lock_irqsave(&s->lock, flags);
  2268. ptr = s->midi.owr;
  2269. cnt = MIDIOUTBUF - ptr;
  2270. if (s->midi.ocnt + cnt > MIDIOUTBUF)
  2271. cnt = MIDIOUTBUF - s->midi.ocnt;
  2272. if (cnt <= 0) {
  2273. __set_current_state(TASK_INTERRUPTIBLE);
  2274. es1371_handle_midi(s);
  2275. }
  2276. spin_unlock_irqrestore(&s->lock, flags);
  2277. if (cnt > count)
  2278. cnt = count;
  2279. if (cnt <= 0) {
  2280. if (file->f_flags & O_NONBLOCK) {
  2281. if (!ret)
  2282. ret = -EAGAIN;
  2283. break;
  2284. }
  2285. schedule();
  2286. if (signal_pending(current)) {
  2287. if (!ret)
  2288. ret = -ERESTARTSYS;
  2289. break;
  2290. }
  2291. continue;
  2292. }
  2293. if (copy_from_user(s->midi.obuf + ptr, buffer, cnt)) {
  2294. if (!ret)
  2295. ret = -EFAULT;
  2296. break;
  2297. }
  2298. ptr = (ptr + cnt) % MIDIOUTBUF;
  2299. spin_lock_irqsave(&s->lock, flags);
  2300. s->midi.owr = ptr;
  2301. s->midi.ocnt += cnt;
  2302. spin_unlock_irqrestore(&s->lock, flags);
  2303. count -= cnt;
  2304. buffer += cnt;
  2305. ret += cnt;
  2306. spin_lock_irqsave(&s->lock, flags);
  2307. es1371_handle_midi(s);
  2308. spin_unlock_irqrestore(&s->lock, flags);
  2309. }
  2310. __set_current_state(TASK_RUNNING);
  2311. remove_wait_queue(&s->midi.owait, &wait);
  2312. return ret;
  2313. }
  2314. /* No kernel lock - we have our own spinlock */
  2315. static unsigned int es1371_midi_poll(struct file *file, struct poll_table_struct *wait)
  2316. {
  2317. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2318. unsigned long flags;
  2319. unsigned int mask = 0;
  2320. VALIDATE_STATE(s);
  2321. if (file->f_mode & FMODE_WRITE)
  2322. poll_wait(file, &s->midi.owait, wait);
  2323. if (file->f_mode & FMODE_READ)
  2324. poll_wait(file, &s->midi.iwait, wait);
  2325. spin_lock_irqsave(&s->lock, flags);
  2326. if (file->f_mode & FMODE_READ) {
  2327. if (s->midi.icnt > 0)
  2328. mask |= POLLIN | POLLRDNORM;
  2329. }
  2330. if (file->f_mode & FMODE_WRITE) {
  2331. if (s->midi.ocnt < MIDIOUTBUF)
  2332. mask |= POLLOUT | POLLWRNORM;
  2333. }
  2334. spin_unlock_irqrestore(&s->lock, flags);
  2335. return mask;
  2336. }
  2337. static int es1371_midi_open(struct inode *inode, struct file *file)
  2338. {
  2339. int minor = iminor(inode);
  2340. DECLARE_WAITQUEUE(wait, current);
  2341. unsigned long flags;
  2342. struct list_head *list;
  2343. struct es1371_state *s;
  2344. for (list = devs.next; ; list = list->next) {
  2345. if (list == &devs)
  2346. return -ENODEV;
  2347. s = list_entry(list, struct es1371_state, devs);
  2348. if (s->dev_midi == minor)
  2349. break;
  2350. }
  2351. VALIDATE_STATE(s);
  2352. file->private_data = s;
  2353. /* wait for device to become free */
  2354. mutex_lock(&s->open_mutex);
  2355. while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
  2356. if (file->f_flags & O_NONBLOCK) {
  2357. mutex_unlock(&s->open_mutex);
  2358. return -EBUSY;
  2359. }
  2360. add_wait_queue(&s->open_wait, &wait);
  2361. __set_current_state(TASK_INTERRUPTIBLE);
  2362. mutex_unlock(&s->open_mutex);
  2363. schedule();
  2364. remove_wait_queue(&s->open_wait, &wait);
  2365. set_current_state(TASK_RUNNING);
  2366. if (signal_pending(current))
  2367. return -ERESTARTSYS;
  2368. mutex_lock(&s->open_mutex);
  2369. }
  2370. spin_lock_irqsave(&s->lock, flags);
  2371. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2372. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2373. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2374. outb(UCTRL_CNTRL_SWR, s->io+ES1371_REG_UART_CONTROL);
  2375. outb(0, s->io+ES1371_REG_UART_CONTROL);
  2376. outb(0, s->io+ES1371_REG_UART_TEST);
  2377. }
  2378. if (file->f_mode & FMODE_READ) {
  2379. s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
  2380. }
  2381. if (file->f_mode & FMODE_WRITE) {
  2382. s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
  2383. }
  2384. s->ctrl |= CTRL_UART_EN;
  2385. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2386. es1371_handle_midi(s);
  2387. spin_unlock_irqrestore(&s->lock, flags);
  2388. s->open_mode |= (file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ | FMODE_MIDI_WRITE);
  2389. mutex_unlock(&s->open_mutex);
  2390. return nonseekable_open(inode, file);
  2391. }
  2392. static int es1371_midi_release(struct inode *inode, struct file *file)
  2393. {
  2394. struct es1371_state *s = (struct es1371_state *)file->private_data;
  2395. DECLARE_WAITQUEUE(wait, current);
  2396. unsigned long flags;
  2397. unsigned count, tmo;
  2398. VALIDATE_STATE(s);
  2399. lock_kernel();
  2400. if (file->f_mode & FMODE_WRITE) {
  2401. add_wait_queue(&s->midi.owait, &wait);
  2402. for (;;) {
  2403. __set_current_state(TASK_INTERRUPTIBLE);
  2404. spin_lock_irqsave(&s->lock, flags);
  2405. count = s->midi.ocnt;
  2406. spin_unlock_irqrestore(&s->lock, flags);
  2407. if (count <= 0)
  2408. break;
  2409. if (signal_pending(current))
  2410. break;
  2411. if (file->f_flags & O_NONBLOCK)
  2412. break;
  2413. tmo = (count * HZ) / 3100;
  2414. if (!schedule_timeout(tmo ? : 1) && tmo)
  2415. printk(KERN_DEBUG PFX "midi timed out??\n");
  2416. }
  2417. remove_wait_queue(&s->midi.owait, &wait);
  2418. set_current_state(TASK_RUNNING);
  2419. }
  2420. mutex_lock(&s->open_mutex);
  2421. s->open_mode &= ~((file->f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ|FMODE_MIDI_WRITE));
  2422. spin_lock_irqsave(&s->lock, flags);
  2423. if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
  2424. s->ctrl &= ~CTRL_UART_EN;
  2425. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2426. }
  2427. spin_unlock_irqrestore(&s->lock, flags);
  2428. mutex_unlock(&s->open_mutex);
  2429. wake_up(&s->open_wait);
  2430. unlock_kernel();
  2431. return 0;
  2432. }
  2433. static /*const*/ struct file_operations es1371_midi_fops = {
  2434. .owner = THIS_MODULE,
  2435. .llseek = no_llseek,
  2436. .read = es1371_midi_read,
  2437. .write = es1371_midi_write,
  2438. .poll = es1371_midi_poll,
  2439. .open = es1371_midi_open,
  2440. .release = es1371_midi_release,
  2441. };
  2442. /* --------------------------------------------------------------------- */
  2443. /*
  2444. * for debugging purposes, we'll create a proc device that dumps the
  2445. * CODEC chipstate
  2446. */
  2447. #ifdef ES1371_DEBUG
  2448. static int proc_es1371_dump (char *buf, char **start, off_t fpos, int length, int *eof, void *data)
  2449. {
  2450. struct es1371_state *s;
  2451. int cnt, len = 0;
  2452. if (list_empty(&devs))
  2453. return 0;
  2454. s = list_entry(devs.next, struct es1371_state, devs);
  2455. /* print out header */
  2456. len += sprintf(buf + len, "\t\tCreative ES137x Debug Dump-o-matic\n");
  2457. /* print out CODEC state */
  2458. len += sprintf (buf + len, "AC97 CODEC state\n");
  2459. for (cnt=0; cnt <= 0x7e; cnt = cnt +2)
  2460. len+= sprintf (buf + len, "reg:0x%02x val:0x%04x\n", cnt, rdcodec(s->codec, cnt));
  2461. if (fpos >=len){
  2462. *start = buf;
  2463. *eof =1;
  2464. return 0;
  2465. }
  2466. *start = buf + fpos;
  2467. if ((len -= fpos) > length)
  2468. return length;
  2469. *eof =1;
  2470. return len;
  2471. }
  2472. #endif /* ES1371_DEBUG */
  2473. /* --------------------------------------------------------------------- */
  2474. /* maximum number of devices; only used for command line params */
  2475. #define NR_DEVICE 5
  2476. static int spdif[NR_DEVICE];
  2477. static int nomix[NR_DEVICE];
  2478. static int amplifier[NR_DEVICE];
  2479. static unsigned int devindex;
  2480. module_param_array(spdif, bool, NULL, 0);
  2481. MODULE_PARM_DESC(spdif, "if 1 the output is in S/PDIF digital mode");
  2482. module_param_array(nomix, bool, NULL, 0);
  2483. MODULE_PARM_DESC(nomix, "if 1 no analog audio is mixed to the digital output");
  2484. module_param_array(amplifier, bool, NULL, 0);
  2485. MODULE_PARM_DESC(amplifier, "Set to 1 if the machine needs the amp control enabling (many laptops)");
  2486. MODULE_AUTHOR("Thomas M. Sailer, sailer@ife.ee.ethz.ch, hb9jnx@hb9w.che.eu");
  2487. MODULE_DESCRIPTION("ES1371 AudioPCI97 Driver");
  2488. MODULE_LICENSE("GPL");
  2489. /* --------------------------------------------------------------------- */
  2490. static struct initvol {
  2491. int mixch;
  2492. int vol;
  2493. } initvol[] __devinitdata = {
  2494. { SOUND_MIXER_WRITE_LINE, 0x4040 },
  2495. { SOUND_MIXER_WRITE_CD, 0x4040 },
  2496. { MIXER_WRITE(SOUND_MIXER_VIDEO), 0x4040 },
  2497. { SOUND_MIXER_WRITE_LINE1, 0x4040 },
  2498. { SOUND_MIXER_WRITE_PCM, 0x4040 },
  2499. { SOUND_MIXER_WRITE_VOLUME, 0x4040 },
  2500. { MIXER_WRITE(SOUND_MIXER_PHONEOUT), 0x4040 },
  2501. { SOUND_MIXER_WRITE_OGAIN, 0x4040 },
  2502. { MIXER_WRITE(SOUND_MIXER_PHONEIN), 0x4040 },
  2503. { SOUND_MIXER_WRITE_SPEAKER, 0x4040 },
  2504. { SOUND_MIXER_WRITE_MIC, 0x4040 },
  2505. { SOUND_MIXER_WRITE_RECLEV, 0x4040 },
  2506. { SOUND_MIXER_WRITE_IGAIN, 0x4040 }
  2507. };
  2508. static struct
  2509. {
  2510. short svid, sdid;
  2511. } amplifier_needed[] =
  2512. {
  2513. { 0x107B, 0x2150 }, /* Gateway Solo 2150 */
  2514. { 0x13BD, 0x100C }, /* Mebius PC-MJ100V */
  2515. { 0x1102, 0x5938 }, /* Targa Xtender 300 */
  2516. { 0x1102, 0x8938 }, /* IPC notebook */
  2517. { PCI_ANY_ID, PCI_ANY_ID }
  2518. };
  2519. #ifdef SUPPORT_JOYSTICK
  2520. static int __devinit es1371_register_gameport(struct es1371_state *s)
  2521. {
  2522. struct gameport *gp;
  2523. int gpio;
  2524. for (gpio = 0x218; gpio >= 0x200; gpio -= 0x08)
  2525. if (request_region(gpio, JOY_EXTENT, "es1371"))
  2526. break;
  2527. if (gpio < 0x200) {
  2528. printk(KERN_ERR PFX "no free joystick address found\n");
  2529. return -EBUSY;
  2530. }
  2531. s->gameport = gp = gameport_allocate_port();
  2532. if (!gp) {
  2533. printk(KERN_ERR PFX "can not allocate memory for gameport\n");
  2534. release_region(gpio, JOY_EXTENT);
  2535. return -ENOMEM;
  2536. }
  2537. gameport_set_name(gp, "ESS1371 Gameport");
  2538. gameport_set_phys(gp, "isa%04x/gameport0", gpio);
  2539. gp->dev.parent = &s->dev->dev;
  2540. gp->io = gpio;
  2541. s->ctrl |= CTRL_JYSTK_EN | (((gpio >> 3) & CTRL_JOY_MASK) << CTRL_JOY_SHIFT);
  2542. outl(s->ctrl, s->io + ES1371_REG_CONTROL);
  2543. gameport_register_port(gp);
  2544. return 0;
  2545. }
  2546. static inline void es1371_unregister_gameport(struct es1371_state *s)
  2547. {
  2548. if (s->gameport) {
  2549. int gpio = s->gameport->io;
  2550. gameport_unregister_port(s->gameport);
  2551. release_region(gpio, JOY_EXTENT);
  2552. }
  2553. }
  2554. #else
  2555. static inline int es1371_register_gameport(struct es1371_state *s) { return -ENOSYS; }
  2556. static inline void es1371_unregister_gameport(struct es1371_state *s) { }
  2557. #endif /* SUPPORT_JOYSTICK */
  2558. static int __devinit es1371_probe(struct pci_dev *pcidev, const struct pci_device_id *pciid)
  2559. {
  2560. struct es1371_state *s;
  2561. mm_segment_t fs;
  2562. int i, val, res = -1;
  2563. int idx;
  2564. unsigned long tmo;
  2565. signed long tmo2;
  2566. unsigned int cssr;
  2567. if ((res=pci_enable_device(pcidev)))
  2568. return res;
  2569. if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_IO))
  2570. return -ENODEV;
  2571. if (pcidev->irq == 0)
  2572. return -ENODEV;
  2573. i = pci_set_dma_mask(pcidev, DMA_32BIT_MASK);
  2574. if (i) {
  2575. printk(KERN_WARNING "es1371: architecture does not support 32bit PCI busmaster DMA\n");
  2576. return i;
  2577. }
  2578. if (!(s = kzalloc(sizeof(struct es1371_state), GFP_KERNEL))) {
  2579. printk(KERN_WARNING PFX "out of memory\n");
  2580. return -ENOMEM;
  2581. }
  2582. s->codec = ac97_alloc_codec();
  2583. if(s->codec == NULL)
  2584. goto err_codec;
  2585. init_waitqueue_head(&s->dma_adc.wait);
  2586. init_waitqueue_head(&s->dma_dac1.wait);
  2587. init_waitqueue_head(&s->dma_dac2.wait);
  2588. init_waitqueue_head(&s->open_wait);
  2589. init_waitqueue_head(&s->midi.iwait);
  2590. init_waitqueue_head(&s->midi.owait);
  2591. mutex_init(&s->open_mutex);
  2592. spin_lock_init(&s->lock);
  2593. s->magic = ES1371_MAGIC;
  2594. s->dev = pcidev;
  2595. s->io = pci_resource_start(pcidev, 0);
  2596. s->irq = pcidev->irq;
  2597. s->vendor = pcidev->vendor;
  2598. s->device = pcidev->device;
  2599. pci_read_config_byte(pcidev, PCI_REVISION_ID, &s->rev);
  2600. s->codec->private_data = s;
  2601. s->codec->id = 0;
  2602. s->codec->codec_read = rdcodec;
  2603. s->codec->codec_write = wrcodec;
  2604. printk(KERN_INFO PFX "found chip, vendor id 0x%04x device id 0x%04x revision 0x%02x\n",
  2605. s->vendor, s->device, s->rev);
  2606. if (!request_region(s->io, ES1371_EXTENT, "es1371")) {
  2607. printk(KERN_ERR PFX "io ports %#lx-%#lx in use\n", s->io, s->io+ES1371_EXTENT-1);
  2608. res = -EBUSY;
  2609. goto err_region;
  2610. }
  2611. if ((res=request_irq(s->irq, es1371_interrupt, IRQF_SHARED, "es1371",s))) {
  2612. printk(KERN_ERR PFX "irq %u in use\n", s->irq);
  2613. goto err_irq;
  2614. }
  2615. printk(KERN_INFO PFX "found es1371 rev %d at io %#lx irq %u\n",
  2616. s->rev, s->io, s->irq);
  2617. /* register devices */
  2618. if ((res=(s->dev_audio = register_sound_dsp(&es1371_audio_fops,-1)))<0)
  2619. goto err_dev1;
  2620. if ((res=(s->codec->dev_mixer = register_sound_mixer(&es1371_mixer_fops, -1))) < 0)
  2621. goto err_dev2;
  2622. if ((res=(s->dev_dac = register_sound_dsp(&es1371_dac_fops, -1))) < 0)
  2623. goto err_dev3;
  2624. if ((res=(s->dev_midi = register_sound_midi(&es1371_midi_fops, -1)))<0 )
  2625. goto err_dev4;
  2626. #ifdef ES1371_DEBUG
  2627. /* initialize the debug proc device */
  2628. s->ps = create_proc_read_entry("es1371",0,NULL,proc_es1371_dump,NULL);
  2629. #endif /* ES1371_DEBUG */
  2630. /* initialize codec registers */
  2631. s->ctrl = 0;
  2632. /* Check amplifier requirements */
  2633. if (amplifier[devindex])
  2634. s->ctrl |= CTRL_GPIO_OUT0;
  2635. else for(idx = 0; amplifier_needed[idx].svid != PCI_ANY_ID; idx++)
  2636. {
  2637. if(pcidev->subsystem_vendor == amplifier_needed[idx].svid &&
  2638. pcidev->subsystem_device == amplifier_needed[idx].sdid)
  2639. {
  2640. s->ctrl |= CTRL_GPIO_OUT0; /* turn internal amplifier on */
  2641. printk(KERN_INFO PFX "Enabling internal amplifier.\n");
  2642. }
  2643. }
  2644. s->sctrl = 0;
  2645. cssr = 0;
  2646. s->spdif_volume = -1;
  2647. /* check to see if s/pdif mode is being requested */
  2648. if (spdif[devindex]) {
  2649. if (s->rev >= 4) {
  2650. printk(KERN_INFO PFX "enabling S/PDIF output\n");
  2651. s->spdif_volume = 0;
  2652. cssr |= STAT_EN_SPDIF;
  2653. s->ctrl |= CTRL_SPDIFEN_B;
  2654. if (nomix[devindex]) /* don't mix analog inputs to s/pdif output */
  2655. s->ctrl |= CTRL_RECEN_B;
  2656. } else {
  2657. printk(KERN_ERR PFX "revision %d does not support S/PDIF\n", s->rev);
  2658. }
  2659. }
  2660. /* initialize the chips */
  2661. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2662. outl(s->sctrl, s->io+ES1371_REG_SERIAL_CONTROL);
  2663. outl(LEGACY_JFAST, s->io+ES1371_REG_LEGACY);
  2664. pci_set_master(pcidev); /* enable bus mastering */
  2665. /* if we are a 5880 turn on the AC97 */
  2666. if (s->vendor == PCI_VENDOR_ID_ENSONIQ &&
  2667. ((s->device == PCI_DEVICE_ID_ENSONIQ_CT5880 && s->rev >= CT5880REV_CT5880_C) ||
  2668. (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_CT5880_A) ||
  2669. (s->device == PCI_DEVICE_ID_ENSONIQ_ES1371 && s->rev == ES1371REV_ES1373_8))) {
  2670. cssr |= CSTAT_5880_AC97_RST;
  2671. outl(cssr, s->io+ES1371_REG_STATUS);
  2672. /* need to delay around 20ms(bleech) to give
  2673. some CODECs enough time to wakeup */
  2674. tmo = jiffies + (HZ / 50) + 1;
  2675. for (;;) {
  2676. tmo2 = tmo - jiffies;
  2677. if (tmo2 <= 0)
  2678. break;
  2679. schedule_timeout(tmo2);
  2680. }
  2681. }
  2682. /* AC97 warm reset to start the bitclk */
  2683. outl(s->ctrl | CTRL_SYNCRES, s->io+ES1371_REG_CONTROL);
  2684. udelay(2);
  2685. outl(s->ctrl, s->io+ES1371_REG_CONTROL);
  2686. /* init the sample rate converter */
  2687. src_init(s);
  2688. /* codec init */
  2689. if (!ac97_probe_codec(s->codec)) {
  2690. res = -ENODEV;
  2691. goto err_gp;
  2692. }
  2693. /* set default values */
  2694. fs = get_fs();
  2695. set_fs(KERNEL_DS);
  2696. val = SOUND_MASK_LINE;
  2697. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC, (unsigned long)&val);
  2698. for (i = 0; i < ARRAY_SIZE(initvol); i++) {
  2699. val = initvol[i].vol;
  2700. mixdev_ioctl(s->codec, initvol[i].mixch, (unsigned long)&val);
  2701. }
  2702. /* mute master and PCM when in S/PDIF mode */
  2703. if (s->spdif_volume != -1) {
  2704. val = 0x0000;
  2705. s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_VOLUME, (unsigned long)&val);
  2706. s->codec->mixer_ioctl(s->codec, SOUND_MIXER_WRITE_PCM, (unsigned long)&val);
  2707. }
  2708. set_fs(fs);
  2709. /* turn on S/PDIF output driver if requested */
  2710. outl(cssr, s->io+ES1371_REG_STATUS);
  2711. es1371_register_gameport(s);
  2712. /* store it in the driver field */
  2713. pci_set_drvdata(pcidev, s);
  2714. /* put it into driver list */
  2715. list_add_tail(&s->devs, &devs);
  2716. /* increment devindex */
  2717. if (devindex < NR_DEVICE-1)
  2718. devindex++;
  2719. return 0;
  2720. err_gp:
  2721. #ifdef ES1371_DEBUG
  2722. if (s->ps)
  2723. remove_proc_entry("es1371", NULL);
  2724. #endif
  2725. unregister_sound_midi(s->dev_midi);
  2726. err_dev4:
  2727. unregister_sound_dsp(s->dev_dac);
  2728. err_dev3:
  2729. unregister_sound_mixer(s->codec->dev_mixer);
  2730. err_dev2:
  2731. unregister_sound_dsp(s->dev_audio);
  2732. err_dev1:
  2733. printk(KERN_ERR PFX "cannot register misc device\n");
  2734. free_irq(s->irq, s);
  2735. err_irq:
  2736. release_region(s->io, ES1371_EXTENT);
  2737. err_region:
  2738. err_codec:
  2739. ac97_release_codec(s->codec);
  2740. kfree(s);
  2741. return res;
  2742. }
  2743. static void __devexit es1371_remove(struct pci_dev *dev)
  2744. {
  2745. struct es1371_state *s = pci_get_drvdata(dev);
  2746. if (!s)
  2747. return;
  2748. list_del(&s->devs);
  2749. #ifdef ES1371_DEBUG
  2750. if (s->ps)
  2751. remove_proc_entry("es1371", NULL);
  2752. #endif /* ES1371_DEBUG */
  2753. outl(0, s->io+ES1371_REG_CONTROL); /* switch everything off */
  2754. outl(0, s->io+ES1371_REG_SERIAL_CONTROL); /* clear serial interrupts */
  2755. synchronize_irq(s->irq);
  2756. free_irq(s->irq, s);
  2757. es1371_unregister_gameport(s);
  2758. release_region(s->io, ES1371_EXTENT);
  2759. unregister_sound_dsp(s->dev_audio);
  2760. unregister_sound_mixer(s->codec->dev_mixer);
  2761. unregister_sound_dsp(s->dev_dac);
  2762. unregister_sound_midi(s->dev_midi);
  2763. ac97_release_codec(s->codec);
  2764. kfree(s);
  2765. pci_set_drvdata(dev, NULL);
  2766. }
  2767. static struct pci_device_id id_table[] = {
  2768. { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_ES1371, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2769. { PCI_VENDOR_ID_ENSONIQ, PCI_DEVICE_ID_ENSONIQ_CT5880, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2770. { PCI_VENDOR_ID_ECTIVA, PCI_DEVICE_ID_ECTIVA_EV1938, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
  2771. { 0, }
  2772. };
  2773. MODULE_DEVICE_TABLE(pci, id_table);
  2774. static struct pci_driver es1371_driver = {
  2775. .name = "es1371",
  2776. .id_table = id_table,
  2777. .probe = es1371_probe,
  2778. .remove = __devexit_p(es1371_remove),
  2779. };
  2780. static int __init init_es1371(void)
  2781. {
  2782. printk(KERN_INFO PFX "version v0.32 time " __TIME__ " " __DATE__ "\n");
  2783. return pci_register_driver(&es1371_driver);
  2784. }
  2785. static void __exit cleanup_es1371(void)
  2786. {
  2787. printk(KERN_INFO PFX "unloading\n");
  2788. pci_unregister_driver(&es1371_driver);
  2789. }
  2790. module_init(init_es1371);
  2791. module_exit(cleanup_es1371);
  2792. /* --------------------------------------------------------------------- */
  2793. #ifndef MODULE
  2794. /* format is: es1371=[spdif,[nomix,[amplifier]]] */
  2795. static int __init es1371_setup(char *str)
  2796. {
  2797. static unsigned __initdata nr_dev = 0;
  2798. if (nr_dev >= NR_DEVICE)
  2799. return 0;
  2800. (void)
  2801. ((get_option(&str, &spdif[nr_dev]) == 2)
  2802. && (get_option(&str, &nomix[nr_dev]) == 2)
  2803. && (get_option(&str, &amplifier[nr_dev])));
  2804. nr_dev++;
  2805. return 1;
  2806. }
  2807. __setup("es1371=", es1371_setup);
  2808. #endif /* MODULE */