awacs_defs.h 9.3 KB

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  1. /*********************************************************/
  2. /* This file was written by someone, somewhere, sometime */
  3. /* And is released into the Public Domain */
  4. /*********************************************************/
  5. #ifndef _AWACS_DEFS_H_
  6. #define _AWACS_DEFS_H_
  7. /*******************************/
  8. /* AWACs Audio Register Layout */
  9. /*******************************/
  10. struct awacs_regs {
  11. unsigned control; /* Audio control register */
  12. unsigned pad0[3];
  13. unsigned codec_ctrl; /* Codec control register */
  14. unsigned pad1[3];
  15. unsigned codec_stat; /* Codec status register */
  16. unsigned pad2[3];
  17. unsigned clip_count; /* Clipping count register */
  18. unsigned pad3[3];
  19. unsigned byteswap; /* Data is little-endian if 1 */
  20. };
  21. /*******************/
  22. /* Audio Bit Masks */
  23. /*******************/
  24. /* Audio Control Reg Bit Masks */
  25. /* ----- ------- --- --- ----- */
  26. #define MASK_ISFSEL (0xf) /* Input SubFrame Select */
  27. #define MASK_OSFSEL (0xf << 4) /* Output SubFrame Select */
  28. #define MASK_RATE (0x7 << 8) /* Sound Rate */
  29. #define MASK_CNTLERR (0x1 << 11) /* Error */
  30. #define MASK_PORTCHG (0x1 << 12) /* Port Change */
  31. #define MASK_IEE (0x1 << 13) /* Enable Interrupt on Error */
  32. #define MASK_IEPC (0x1 << 14) /* Enable Interrupt on Port Change */
  33. #define MASK_SSFSEL (0x3 << 15) /* Status SubFrame Select */
  34. /* Audio Codec Control Reg Bit Masks */
  35. /* ----- ----- ------- --- --- ----- */
  36. #define MASK_NEWECMD (0x1 << 24) /* Lock: don't write to reg when 1 */
  37. #define MASK_EMODESEL (0x3 << 22) /* Send info out on which frame? */
  38. #define MASK_EXMODEADDR (0x3ff << 12) /* Extended Mode Address -- 10 bits */
  39. #define MASK_EXMODEDATA (0xfff) /* Extended Mode Data -- 12 bits */
  40. /* Audio Codec Control Address Values / Masks */
  41. /* ----- ----- ------- ------- ------ - ----- */
  42. #define MASK_ADDR0 (0x0 << 12) /* Expanded Data Mode Address 0 */
  43. #define MASK_ADDR_MUX MASK_ADDR0 /* Mux Control */
  44. #define MASK_ADDR_GAIN MASK_ADDR0
  45. #define MASK_ADDR1 (0x1 << 12) /* Expanded Data Mode Address 1 */
  46. #define MASK_ADDR_MUTE MASK_ADDR1
  47. #define MASK_ADDR_RATE MASK_ADDR1
  48. #define MASK_ADDR2 (0x2 << 12) /* Expanded Data Mode Address 2 */
  49. #define MASK_ADDR_VOLA MASK_ADDR2 /* Volume Control A -- Headphones */
  50. #define MASK_ADDR_VOLHD MASK_ADDR2
  51. #define MASK_ADDR4 (0x4 << 12) /* Expanded Data Mode Address 4 */
  52. #define MASK_ADDR_VOLC MASK_ADDR4 /* Volume Control C -- Speaker */
  53. #define MASK_ADDR_VOLSPK MASK_ADDR4
  54. /* additional registers of screamer */
  55. #define MASK_ADDR5 (0x5 << 12) /* Expanded Data Mode Address 5 */
  56. #define MASK_ADDR6 (0x6 << 12) /* Expanded Data Mode Address 6 */
  57. #define MASK_ADDR7 (0x7 << 12) /* Expanded Data Mode Address 7 */
  58. /* Address 0 Bit Masks & Macros */
  59. /* ------- - --- ----- - ------ */
  60. #define MASK_GAINRIGHT (0xf) /* Gain Right Mask */
  61. #define MASK_GAINLEFT (0xf << 4) /* Gain Left Mask */
  62. #define MASK_GAINLINE (0x1 << 8) /* Disable Mic preamp */
  63. #define MASK_GAINMIC (0x0 << 8) /* Enable Mic preamp */
  64. #define MASK_MUX_CD (0x1 << 9) /* Select CD in MUX */
  65. #define MASK_MUX_MIC (0x1 << 10) /* Select Mic in MUX */
  66. #define MASK_MUX_AUDIN (0x1 << 11) /* Select Audio In in MUX */
  67. #define MASK_MUX_LINE MASK_MUX_AUDIN
  68. #define GAINRIGHT(x) ((x) & MASK_GAINRIGHT)
  69. #define GAINLEFT(x) (((x) << 4) & MASK_GAINLEFT)
  70. #define DEF_CD_GAIN 0x00bb
  71. #define DEF_MIC_GAIN 0x00cc
  72. /* Address 1 Bit Masks */
  73. /* ------- - --- ----- */
  74. #define MASK_ADDR1RES1 (0x3) /* Reserved */
  75. #define MASK_RECALIBRATE (0x1 << 2) /* Recalibrate */
  76. #define MASK_SAMPLERATE (0x7 << 3) /* Sample Rate: */
  77. #define MASK_LOOPTHRU (0x1 << 6) /* Loopthrough Enable */
  78. #define MASK_CMUTE (0x1 << 7) /* Output C (Speaker) Mute when 1 */
  79. #define MASK_SPKMUTE MASK_CMUTE
  80. #define MASK_ADDR1RES2 (0x1 << 8) /* Reserved */
  81. #define MASK_AMUTE (0x1 << 9) /* Output A (Headphone) Mute when 1 */
  82. #define MASK_HDMUTE MASK_AMUTE
  83. #define MASK_PAROUT0 (0x1 << 10) /* Parallel Output 0 */
  84. #define MASK_PAROUT1 (0x2 << 10) /* Parallel Output 1 */
  85. #define MASK_MIC_BOOST (0x4) /* screamer mic boost */
  86. #define SAMPLERATE_48000 (0x0 << 3) /* 48 or 44.1 kHz */
  87. #define SAMPLERATE_32000 (0x1 << 3) /* 32 or 29.4 kHz */
  88. #define SAMPLERATE_24000 (0x2 << 3) /* 24 or 22.05 kHz */
  89. #define SAMPLERATE_19200 (0x3 << 3) /* 19.2 or 17.64 kHz */
  90. #define SAMPLERATE_16000 (0x4 << 3) /* 16 or 14.7 kHz */
  91. #define SAMPLERATE_12000 (0x5 << 3) /* 12 or 11.025 kHz */
  92. #define SAMPLERATE_9600 (0x6 << 3) /* 9.6 or 8.82 kHz */
  93. #define SAMPLERATE_8000 (0x7 << 3) /* 8 or 7.35 kHz */
  94. /* Address 2 & 4 Bit Masks & Macros */
  95. /* ------- - - - --- ----- - ------ */
  96. #define MASK_OUTVOLRIGHT (0xf) /* Output Right Volume */
  97. #define MASK_ADDR2RES1 (0x2 << 4) /* Reserved */
  98. #define MASK_ADDR4RES1 MASK_ADDR2RES1
  99. #define MASK_OUTVOLLEFT (0xf << 6) /* Output Left Volume */
  100. #define MASK_ADDR2RES2 (0x2 << 10) /* Reserved */
  101. #define MASK_ADDR4RES2 MASK_ADDR2RES2
  102. #define VOLRIGHT(x) (((~(x)) & MASK_OUTVOLRIGHT))
  103. #define VOLLEFT(x) (((~(x)) << 6) & MASK_OUTVOLLEFT)
  104. /* Audio Codec Status Reg Bit Masks */
  105. /* ----- ----- ------ --- --- ----- */
  106. #define MASK_EXTEND (0x1 << 23) /* Extend */
  107. #define MASK_VALID (0x1 << 22) /* Valid Data? */
  108. #define MASK_OFLEFT (0x1 << 21) /* Overflow Left */
  109. #define MASK_OFRIGHT (0x1 << 20) /* Overflow Right */
  110. #define MASK_ERRCODE (0xf << 16) /* Error Code */
  111. #define MASK_REVISION (0xf << 12) /* Revision Number */
  112. #define MASK_MFGID (0xf << 8) /* Mfg. ID */
  113. #define MASK_CODSTATRES (0xf << 4) /* bits 4 - 7 reserved */
  114. #define MASK_INPPORT (0xf) /* Input Port */
  115. #define MASK_HDPCONN 8 /* headphone plugged in */
  116. /* Clipping Count Reg Bit Masks */
  117. /* -------- ----- --- --- ----- */
  118. #define MASK_CLIPLEFT (0xff << 7) /* Clipping Count, Left Channel */
  119. #define MASK_CLIPRIGHT (0xff) /* Clipping Count, Right Channel */
  120. /* DBDMA ChannelStatus Bit Masks */
  121. /* ----- ------------- --- ----- */
  122. #define MASK_CSERR (0x1 << 7) /* Error */
  123. #define MASK_EOI (0x1 << 6) /* End of Input -- only for Input Channel */
  124. #define MASK_CSUNUSED (0x1f << 1) /* bits 1-5 not used */
  125. #define MASK_WAIT (0x1) /* Wait */
  126. /* Various Rates */
  127. /* ------- ----- */
  128. #define RATE_48000 (0x0 << 8) /* 48 kHz */
  129. #define RATE_44100 (0x0 << 8) /* 44.1 kHz */
  130. #define RATE_32000 (0x1 << 8) /* 32 kHz */
  131. #define RATE_29400 (0x1 << 8) /* 29.4 kHz */
  132. #define RATE_24000 (0x2 << 8) /* 24 kHz */
  133. #define RATE_22050 (0x2 << 8) /* 22.05 kHz */
  134. #define RATE_19200 (0x3 << 8) /* 19.2 kHz */
  135. #define RATE_17640 (0x3 << 8) /* 17.64 kHz */
  136. #define RATE_16000 (0x4 << 8) /* 16 kHz */
  137. #define RATE_14700 (0x4 << 8) /* 14.7 kHz */
  138. #define RATE_12000 (0x5 << 8) /* 12 kHz */
  139. #define RATE_11025 (0x5 << 8) /* 11.025 kHz */
  140. #define RATE_9600 (0x6 << 8) /* 9.6 kHz */
  141. #define RATE_8820 (0x6 << 8) /* 8.82 kHz */
  142. #define RATE_8000 (0x7 << 8) /* 8 kHz */
  143. #define RATE_7350 (0x7 << 8) /* 7.35 kHz */
  144. #define RATE_LOW 1 /* HIGH = 48kHz, etc; LOW = 44.1kHz, etc. */
  145. /*******************/
  146. /* Burgundy values */
  147. /*******************/
  148. #define MASK_ADDR_BURGUNDY_INPSEL21 (0x11 << 12)
  149. #define MASK_ADDR_BURGUNDY_INPSEL3 (0x12 << 12)
  150. #define MASK_ADDR_BURGUNDY_GAINCH1 (0x13 << 12)
  151. #define MASK_ADDR_BURGUNDY_GAINCH2 (0x14 << 12)
  152. #define MASK_ADDR_BURGUNDY_GAINCH3 (0x15 << 12)
  153. #define MASK_ADDR_BURGUNDY_GAINCH4 (0x16 << 12)
  154. #define MASK_ADDR_BURGUNDY_VOLCH1 (0x20 << 12)
  155. #define MASK_ADDR_BURGUNDY_VOLCH2 (0x21 << 12)
  156. #define MASK_ADDR_BURGUNDY_VOLCH3 (0x22 << 12)
  157. #define MASK_ADDR_BURGUNDY_VOLCH4 (0x23 << 12)
  158. #define MASK_ADDR_BURGUNDY_OUTPUTSELECTS (0x2B << 12)
  159. #define MASK_ADDR_BURGUNDY_OUTPUTENABLES (0x2F << 12)
  160. #define MASK_ADDR_BURGUNDY_MASTER_VOLUME (0x30 << 12)
  161. #define MASK_ADDR_BURGUNDY_MORE_OUTPUTENABLES (0x60 << 12)
  162. #define MASK_ADDR_BURGUNDY_ATTENSPEAKER (0x62 << 12)
  163. #define MASK_ADDR_BURGUNDY_ATTENLINEOUT (0x63 << 12)
  164. #define MASK_ADDR_BURGUNDY_ATTENHP (0x64 << 12)
  165. #define MASK_ADDR_BURGUNDY_VOLCD (MASK_ADDR_BURGUNDY_VOLCH1)
  166. #define MASK_ADDR_BURGUNDY_VOLLINE (MASK_ADDR_BURGUNDY_VOLCH2)
  167. #define MASK_ADDR_BURGUNDY_VOLMIC (MASK_ADDR_BURGUNDY_VOLCH3)
  168. #define MASK_ADDR_BURGUNDY_VOLMODEM (MASK_ADDR_BURGUNDY_VOLCH4)
  169. #define MASK_ADDR_BURGUNDY_GAINCD (MASK_ADDR_BURGUNDY_GAINCH1)
  170. #define MASK_ADDR_BURGUNDY_GAINLINE (MASK_ADDR_BURGUNDY_GAINCH2)
  171. #define MASK_ADDR_BURGUNDY_GAINMIC (MASK_ADDR_BURGUNDY_GAINCH3)
  172. #define MASK_ADDR_BURGUNDY_GAINMODEM (MASK_ADDR_BURGUNDY_VOLCH4)
  173. /* These are all default values for the burgundy */
  174. #define DEF_BURGUNDY_INPSEL21 (0xAA)
  175. #define DEF_BURGUNDY_INPSEL3 (0x0A)
  176. #define DEF_BURGUNDY_GAINCD (0x33)
  177. #define DEF_BURGUNDY_GAINLINE (0x44)
  178. #define DEF_BURGUNDY_GAINMIC (0x44)
  179. #define DEF_BURGUNDY_GAINMODEM (0x06)
  180. /* Remember: lowest volume here is 0x9b */
  181. #define DEF_BURGUNDY_VOLCD (0xCCCCCCCC)
  182. #define DEF_BURGUNDY_VOLLINE (0x00000000)
  183. #define DEF_BURGUNDY_VOLMIC (0x00000000)
  184. #define DEF_BURGUNDY_VOLMODEM (0xCCCCCCCC)
  185. #define DEF_BURGUNDY_OUTPUTSELECTS (0x010f010f)
  186. #define DEF_BURGUNDY_OUTPUTENABLES (0x0A)
  187. #define DEF_BURGUNDY_MASTER_VOLUME (0xFFFFFFFF)
  188. #define DEF_BURGUNDY_MORE_OUTPUTENABLES (0x7E)
  189. #define DEF_BURGUNDY_ATTENSPEAKER (0x44)
  190. #define DEF_BURGUNDY_ATTENLINEOUT (0xCC)
  191. #define DEF_BURGUNDY_ATTENHP (0xCC)
  192. /*********************/
  193. /* i2s layout values */
  194. /*********************/
  195. #define I2S_REG_INT_CTL 0x00
  196. #define I2S_REG_SERIAL_FORMAT 0x10
  197. #define I2S_REG_CODEC_MSG_OUT 0x20
  198. #define I2S_REG_CODEC_MSG_IN 0x30
  199. #define I2S_REG_FRAME_COUNT 0x40
  200. #define I2S_REG_FRAME_MATCH 0x50
  201. #define I2S_REG_DATAWORD_SIZES 0x60
  202. #define I2S_REG_PEAKLEVEL_SEL 0x70
  203. #define I2S_REG_PEAKLEVEL_IN0 0x80
  204. #define I2S_REG_PEAKLEVEL_IN1 0x90
  205. #endif /* _AWACS_DEFS_H_ */