cs461x.h 73 KB

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  1. #ifndef __CS461X_H
  2. #define __CS461X_H
  3. /*
  4. * Copyright (c) by Cirrus Logic Corporation <pcaudio@crystal.cirrus.com>
  5. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  6. * Definitions for Cirrus Logic CS461x chips
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. */
  24. #ifndef PCI_VENDOR_ID_CIRRUS
  25. #define PCI_VENDOR_ID_CIRRUS 0x1013
  26. #endif
  27. #ifndef PCI_DEVICE_ID_CIRRUS_4610
  28. #define PCI_DEVICE_ID_CIRRUS_4610 0x6001
  29. #endif
  30. #ifndef PCI_DEVICE_ID_CIRRUS_4612
  31. #define PCI_DEVICE_ID_CIRRUS_4612 0x6003
  32. #endif
  33. #ifndef PCI_DEVICE_ID_CIRRUS_4615
  34. #define PCI_DEVICE_ID_CIRRUS_4615 0x6004
  35. #endif
  36. /*
  37. * Direct registers
  38. */
  39. /*
  40. * The following define the offsets of the registers accessed via base address
  41. * register zero on the CS461x part.
  42. */
  43. #define BA0_HISR 0x00000000
  44. #define BA0_HSR0 0x00000004
  45. #define BA0_HICR 0x00000008
  46. #define BA0_DMSR 0x00000100
  47. #define BA0_HSAR 0x00000110
  48. #define BA0_HDAR 0x00000114
  49. #define BA0_HDMR 0x00000118
  50. #define BA0_HDCR 0x0000011C
  51. #define BA0_PFMC 0x00000200
  52. #define BA0_PFCV1 0x00000204
  53. #define BA0_PFCV2 0x00000208
  54. #define BA0_PCICFG00 0x00000300
  55. #define BA0_PCICFG04 0x00000304
  56. #define BA0_PCICFG08 0x00000308
  57. #define BA0_PCICFG0C 0x0000030C
  58. #define BA0_PCICFG10 0x00000310
  59. #define BA0_PCICFG14 0x00000314
  60. #define BA0_PCICFG18 0x00000318
  61. #define BA0_PCICFG1C 0x0000031C
  62. #define BA0_PCICFG20 0x00000320
  63. #define BA0_PCICFG24 0x00000324
  64. #define BA0_PCICFG28 0x00000328
  65. #define BA0_PCICFG2C 0x0000032C
  66. #define BA0_PCICFG30 0x00000330
  67. #define BA0_PCICFG34 0x00000334
  68. #define BA0_PCICFG38 0x00000338
  69. #define BA0_PCICFG3C 0x0000033C
  70. #define BA0_CLKCR1 0x00000400
  71. #define BA0_CLKCR2 0x00000404
  72. #define BA0_PLLM 0x00000408
  73. #define BA0_PLLCC 0x0000040C
  74. #define BA0_FRR 0x00000410
  75. #define BA0_CFL1 0x00000414
  76. #define BA0_CFL2 0x00000418
  77. #define BA0_SERMC1 0x00000420
  78. #define BA0_SERMC2 0x00000424
  79. #define BA0_SERC1 0x00000428
  80. #define BA0_SERC2 0x0000042C
  81. #define BA0_SERC3 0x00000430
  82. #define BA0_SERC4 0x00000434
  83. #define BA0_SERC5 0x00000438
  84. #define BA0_SERBSP 0x0000043C
  85. #define BA0_SERBST 0x00000440
  86. #define BA0_SERBCM 0x00000444
  87. #define BA0_SERBAD 0x00000448
  88. #define BA0_SERBCF 0x0000044C
  89. #define BA0_SERBWP 0x00000450
  90. #define BA0_SERBRP 0x00000454
  91. #ifndef NO_CS4612
  92. #define BA0_ASER_FADDR 0x00000458
  93. #endif
  94. #define BA0_ACCTL 0x00000460
  95. #define BA0_ACSTS 0x00000464
  96. #define BA0_ACOSV 0x00000468
  97. #define BA0_ACCAD 0x0000046C
  98. #define BA0_ACCDA 0x00000470
  99. #define BA0_ACISV 0x00000474
  100. #define BA0_ACSAD 0x00000478
  101. #define BA0_ACSDA 0x0000047C
  102. #define BA0_JSPT 0x00000480
  103. #define BA0_JSCTL 0x00000484
  104. #define BA0_JSC1 0x00000488
  105. #define BA0_JSC2 0x0000048C
  106. #define BA0_MIDCR 0x00000490
  107. #define BA0_MIDSR 0x00000494
  108. #define BA0_MIDWP 0x00000498
  109. #define BA0_MIDRP 0x0000049C
  110. #define BA0_JSIO 0x000004A0
  111. #ifndef NO_CS4612
  112. #define BA0_ASER_MASTER 0x000004A4
  113. #endif
  114. #define BA0_CFGI 0x000004B0
  115. #define BA0_SSVID 0x000004B4
  116. #define BA0_GPIOR 0x000004B8
  117. #ifndef NO_CS4612
  118. #define BA0_EGPIODR 0x000004BC
  119. #define BA0_EGPIOPTR 0x000004C0
  120. #define BA0_EGPIOTR 0x000004C4
  121. #define BA0_EGPIOWR 0x000004C8
  122. #define BA0_EGPIOSR 0x000004CC
  123. #define BA0_SERC6 0x000004D0
  124. #define BA0_SERC7 0x000004D4
  125. #define BA0_SERACC 0x000004D8
  126. #define BA0_ACCTL2 0x000004E0
  127. #define BA0_ACSTS2 0x000004E4
  128. #define BA0_ACOSV2 0x000004E8
  129. #define BA0_ACCAD2 0x000004EC
  130. #define BA0_ACCDA2 0x000004F0
  131. #define BA0_ACISV2 0x000004F4
  132. #define BA0_ACSAD2 0x000004F8
  133. #define BA0_ACSDA2 0x000004FC
  134. #define BA0_IOTAC0 0x00000500
  135. #define BA0_IOTAC1 0x00000504
  136. #define BA0_IOTAC2 0x00000508
  137. #define BA0_IOTAC3 0x0000050C
  138. #define BA0_IOTAC4 0x00000510
  139. #define BA0_IOTAC5 0x00000514
  140. #define BA0_IOTAC6 0x00000518
  141. #define BA0_IOTAC7 0x0000051C
  142. #define BA0_IOTAC8 0x00000520
  143. #define BA0_IOTAC9 0x00000524
  144. #define BA0_IOTAC10 0x00000528
  145. #define BA0_IOTAC11 0x0000052C
  146. #define BA0_IOTFR0 0x00000540
  147. #define BA0_IOTFR1 0x00000544
  148. #define BA0_IOTFR2 0x00000548
  149. #define BA0_IOTFR3 0x0000054C
  150. #define BA0_IOTFR4 0x00000550
  151. #define BA0_IOTFR5 0x00000554
  152. #define BA0_IOTFR6 0x00000558
  153. #define BA0_IOTFR7 0x0000055C
  154. #define BA0_IOTFIFO 0x00000580
  155. #define BA0_IOTRRD 0x00000584
  156. #define BA0_IOTFP 0x00000588
  157. #define BA0_IOTCR 0x0000058C
  158. #define BA0_DPCID 0x00000590
  159. #define BA0_DPCIA 0x00000594
  160. #define BA0_DPCIC 0x00000598
  161. #define BA0_PCPCIR 0x00000600
  162. #define BA0_PCPCIG 0x00000604
  163. #define BA0_PCPCIEN 0x00000608
  164. #define BA0_EPCIPMC 0x00000610
  165. #endif
  166. /*
  167. * The following define the offsets of the registers and memories accessed via
  168. * base address register one on the CS461x part.
  169. */
  170. #define BA1_SP_DMEM0 0x00000000
  171. #define BA1_SP_DMEM1 0x00010000
  172. #define BA1_SP_PMEM 0x00020000
  173. #define BA1_SP_REG 0x00030000
  174. #define BA1_SPCR 0x00030000
  175. #define BA1_DREG 0x00030004
  176. #define BA1_DSRWP 0x00030008
  177. #define BA1_TWPR 0x0003000C
  178. #define BA1_SPWR 0x00030010
  179. #define BA1_SPIR 0x00030014
  180. #define BA1_FGR1 0x00030020
  181. #define BA1_SPCS 0x00030028
  182. #define BA1_SDSR 0x0003002C
  183. #define BA1_FRMT 0x00030030
  184. #define BA1_FRCC 0x00030034
  185. #define BA1_FRSC 0x00030038
  186. #define BA1_OMNI_MEM 0x000E0000
  187. /*
  188. * The following defines are for the flags in the host interrupt status
  189. * register.
  190. */
  191. #define HISR_VC_MASK 0x0000FFFF
  192. #define HISR_VC0 0x00000001
  193. #define HISR_VC1 0x00000002
  194. #define HISR_VC2 0x00000004
  195. #define HISR_VC3 0x00000008
  196. #define HISR_VC4 0x00000010
  197. #define HISR_VC5 0x00000020
  198. #define HISR_VC6 0x00000040
  199. #define HISR_VC7 0x00000080
  200. #define HISR_VC8 0x00000100
  201. #define HISR_VC9 0x00000200
  202. #define HISR_VC10 0x00000400
  203. #define HISR_VC11 0x00000800
  204. #define HISR_VC12 0x00001000
  205. #define HISR_VC13 0x00002000
  206. #define HISR_VC14 0x00004000
  207. #define HISR_VC15 0x00008000
  208. #define HISR_INT0 0x00010000
  209. #define HISR_INT1 0x00020000
  210. #define HISR_DMAI 0x00040000
  211. #define HISR_FROVR 0x00080000
  212. #define HISR_MIDI 0x00100000
  213. #ifdef NO_CS4612
  214. #define HISR_RESERVED 0x0FE00000
  215. #else
  216. #define HISR_SBINT 0x00200000
  217. #define HISR_RESERVED 0x0FC00000
  218. #endif
  219. #define HISR_H0P 0x40000000
  220. #define HISR_INTENA 0x80000000
  221. /*
  222. * The following defines are for the flags in the host signal register 0.
  223. */
  224. #define HSR0_VC_MASK 0xFFFFFFFF
  225. #define HSR0_VC16 0x00000001
  226. #define HSR0_VC17 0x00000002
  227. #define HSR0_VC18 0x00000004
  228. #define HSR0_VC19 0x00000008
  229. #define HSR0_VC20 0x00000010
  230. #define HSR0_VC21 0x00000020
  231. #define HSR0_VC22 0x00000040
  232. #define HSR0_VC23 0x00000080
  233. #define HSR0_VC24 0x00000100
  234. #define HSR0_VC25 0x00000200
  235. #define HSR0_VC26 0x00000400
  236. #define HSR0_VC27 0x00000800
  237. #define HSR0_VC28 0x00001000
  238. #define HSR0_VC29 0x00002000
  239. #define HSR0_VC30 0x00004000
  240. #define HSR0_VC31 0x00008000
  241. #define HSR0_VC32 0x00010000
  242. #define HSR0_VC33 0x00020000
  243. #define HSR0_VC34 0x00040000
  244. #define HSR0_VC35 0x00080000
  245. #define HSR0_VC36 0x00100000
  246. #define HSR0_VC37 0x00200000
  247. #define HSR0_VC38 0x00400000
  248. #define HSR0_VC39 0x00800000
  249. #define HSR0_VC40 0x01000000
  250. #define HSR0_VC41 0x02000000
  251. #define HSR0_VC42 0x04000000
  252. #define HSR0_VC43 0x08000000
  253. #define HSR0_VC44 0x10000000
  254. #define HSR0_VC45 0x20000000
  255. #define HSR0_VC46 0x40000000
  256. #define HSR0_VC47 0x80000000
  257. /*
  258. * The following defines are for the flags in the host interrupt control
  259. * register.
  260. */
  261. #define HICR_IEV 0x00000001
  262. #define HICR_CHGM 0x00000002
  263. /*
  264. * The following defines are for the flags in the DMA status register.
  265. */
  266. #define DMSR_HP 0x00000001
  267. #define DMSR_HR 0x00000002
  268. #define DMSR_SP 0x00000004
  269. #define DMSR_SR 0x00000008
  270. /*
  271. * The following defines are for the flags in the host DMA source address
  272. * register.
  273. */
  274. #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
  275. #define HSAR_DSP_ADDR_MASK 0x0000FFFF
  276. #define HSAR_MEMID_MASK 0x000F0000
  277. #define HSAR_MEMID_SP_DMEM0 0x00000000
  278. #define HSAR_MEMID_SP_DMEM1 0x00010000
  279. #define HSAR_MEMID_SP_PMEM 0x00020000
  280. #define HSAR_MEMID_SP_DEBUG 0x00030000
  281. #define HSAR_MEMID_OMNI_MEM 0x000E0000
  282. #define HSAR_END 0x40000000
  283. #define HSAR_ERR 0x80000000
  284. /*
  285. * The following defines are for the flags in the host DMA destination address
  286. * register.
  287. */
  288. #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
  289. #define HDAR_DSP_ADDR_MASK 0x0000FFFF
  290. #define HDAR_MEMID_MASK 0x000F0000
  291. #define HDAR_MEMID_SP_DMEM0 0x00000000
  292. #define HDAR_MEMID_SP_DMEM1 0x00010000
  293. #define HDAR_MEMID_SP_PMEM 0x00020000
  294. #define HDAR_MEMID_SP_DEBUG 0x00030000
  295. #define HDAR_MEMID_OMNI_MEM 0x000E0000
  296. #define HDAR_END 0x40000000
  297. #define HDAR_ERR 0x80000000
  298. /*
  299. * The following defines are for the flags in the host DMA control register.
  300. */
  301. #define HDMR_AC_MASK 0x0000F000
  302. #define HDMR_AC_8_16 0x00001000
  303. #define HDMR_AC_M_S 0x00002000
  304. #define HDMR_AC_B_L 0x00004000
  305. #define HDMR_AC_S_U 0x00008000
  306. /*
  307. * The following defines are for the flags in the host DMA control register.
  308. */
  309. #define HDCR_COUNT_MASK 0x000003FF
  310. #define HDCR_DONE 0x00004000
  311. #define HDCR_OPT 0x00008000
  312. #define HDCR_WBD 0x00400000
  313. #define HDCR_WBS 0x00800000
  314. #define HDCR_DMS_MASK 0x07000000
  315. #define HDCR_DMS_LINEAR 0x00000000
  316. #define HDCR_DMS_16_DWORDS 0x01000000
  317. #define HDCR_DMS_32_DWORDS 0x02000000
  318. #define HDCR_DMS_64_DWORDS 0x03000000
  319. #define HDCR_DMS_128_DWORDS 0x04000000
  320. #define HDCR_DMS_256_DWORDS 0x05000000
  321. #define HDCR_DMS_512_DWORDS 0x06000000
  322. #define HDCR_DMS_1024_DWORDS 0x07000000
  323. #define HDCR_DH 0x08000000
  324. #define HDCR_SMS_MASK 0x70000000
  325. #define HDCR_SMS_LINEAR 0x00000000
  326. #define HDCR_SMS_16_DWORDS 0x10000000
  327. #define HDCR_SMS_32_DWORDS 0x20000000
  328. #define HDCR_SMS_64_DWORDS 0x30000000
  329. #define HDCR_SMS_128_DWORDS 0x40000000
  330. #define HDCR_SMS_256_DWORDS 0x50000000
  331. #define HDCR_SMS_512_DWORDS 0x60000000
  332. #define HDCR_SMS_1024_DWORDS 0x70000000
  333. #define HDCR_SH 0x80000000
  334. #define HDCR_COUNT_SHIFT 0
  335. /*
  336. * The following defines are for the flags in the performance monitor control
  337. * register.
  338. */
  339. #define PFMC_C1SS_MASK 0x0000001F
  340. #define PFMC_C1EV 0x00000020
  341. #define PFMC_C1RS 0x00008000
  342. #define PFMC_C2SS_MASK 0x001F0000
  343. #define PFMC_C2EV 0x00200000
  344. #define PFMC_C2RS 0x80000000
  345. #define PFMC_C1SS_SHIFT 0
  346. #define PFMC_C2SS_SHIFT 16
  347. #define PFMC_BUS_GRANT 0
  348. #define PFMC_GRANT_AFTER_REQ 1
  349. #define PFMC_TRANSACTION 2
  350. #define PFMC_DWORD_TRANSFER 3
  351. #define PFMC_SLAVE_READ 4
  352. #define PFMC_SLAVE_WRITE 5
  353. #define PFMC_PREEMPTION 6
  354. #define PFMC_DISCONNECT_RETRY 7
  355. #define PFMC_INTERRUPT 8
  356. #define PFMC_BUS_OWNERSHIP 9
  357. #define PFMC_TRANSACTION_LAG 10
  358. #define PFMC_PCI_CLOCK 11
  359. #define PFMC_SERIAL_CLOCK 12
  360. #define PFMC_SP_CLOCK 13
  361. /*
  362. * The following defines are for the flags in the performance counter value 1
  363. * register.
  364. */
  365. #define PFCV1_PC1V_MASK 0xFFFFFFFF
  366. #define PFCV1_PC1V_SHIFT 0
  367. /*
  368. * The following defines are for the flags in the performance counter value 2
  369. * register.
  370. */
  371. #define PFCV2_PC2V_MASK 0xFFFFFFFF
  372. #define PFCV2_PC2V_SHIFT 0
  373. /*
  374. * The following defines are for the flags in the clock control register 1.
  375. */
  376. #define CLKCR1_OSCS 0x00000001
  377. #define CLKCR1_OSCP 0x00000002
  378. #define CLKCR1_PLLSS_MASK 0x0000000C
  379. #define CLKCR1_PLLSS_SERIAL 0x00000000
  380. #define CLKCR1_PLLSS_CRYSTAL 0x00000004
  381. #define CLKCR1_PLLSS_PCI 0x00000008
  382. #define CLKCR1_PLLSS_RESERVED 0x0000000C
  383. #define CLKCR1_PLLP 0x00000010
  384. #define CLKCR1_SWCE 0x00000020
  385. #define CLKCR1_PLLOS 0x00000040
  386. /*
  387. * The following defines are for the flags in the clock control register 2.
  388. */
  389. #define CLKCR2_PDIVS_MASK 0x0000000F
  390. #define CLKCR2_PDIVS_1 0x00000001
  391. #define CLKCR2_PDIVS_2 0x00000002
  392. #define CLKCR2_PDIVS_4 0x00000004
  393. #define CLKCR2_PDIVS_7 0x00000007
  394. #define CLKCR2_PDIVS_8 0x00000008
  395. #define CLKCR2_PDIVS_16 0x00000000
  396. /*
  397. * The following defines are for the flags in the PLL multiplier register.
  398. */
  399. #define PLLM_MASK 0x000000FF
  400. #define PLLM_SHIFT 0
  401. /*
  402. * The following defines are for the flags in the PLL capacitor coefficient
  403. * register.
  404. */
  405. #define PLLCC_CDR_MASK 0x00000007
  406. #ifndef NO_CS4610
  407. #define PLLCC_CDR_240_350_MHZ 0x00000000
  408. #define PLLCC_CDR_184_265_MHZ 0x00000001
  409. #define PLLCC_CDR_144_205_MHZ 0x00000002
  410. #define PLLCC_CDR_111_160_MHZ 0x00000003
  411. #define PLLCC_CDR_87_123_MHZ 0x00000004
  412. #define PLLCC_CDR_67_96_MHZ 0x00000005
  413. #define PLLCC_CDR_52_74_MHZ 0x00000006
  414. #define PLLCC_CDR_45_58_MHZ 0x00000007
  415. #endif
  416. #ifndef NO_CS4612
  417. #define PLLCC_CDR_271_398_MHZ 0x00000000
  418. #define PLLCC_CDR_227_330_MHZ 0x00000001
  419. #define PLLCC_CDR_167_239_MHZ 0x00000002
  420. #define PLLCC_CDR_150_215_MHZ 0x00000003
  421. #define PLLCC_CDR_107_154_MHZ 0x00000004
  422. #define PLLCC_CDR_98_140_MHZ 0x00000005
  423. #define PLLCC_CDR_73_104_MHZ 0x00000006
  424. #define PLLCC_CDR_63_90_MHZ 0x00000007
  425. #endif
  426. #define PLLCC_LPF_MASK 0x000000F8
  427. #ifndef NO_CS4610
  428. #define PLLCC_LPF_23850_60000_KHZ 0x00000000
  429. #define PLLCC_LPF_7960_26290_KHZ 0x00000008
  430. #define PLLCC_LPF_4160_10980_KHZ 0x00000018
  431. #define PLLCC_LPF_1740_4580_KHZ 0x00000038
  432. #define PLLCC_LPF_724_1910_KHZ 0x00000078
  433. #define PLLCC_LPF_317_798_KHZ 0x000000F8
  434. #endif
  435. #ifndef NO_CS4612
  436. #define PLLCC_LPF_25580_64530_KHZ 0x00000000
  437. #define PLLCC_LPF_14360_37270_KHZ 0x00000008
  438. #define PLLCC_LPF_6100_16020_KHZ 0x00000018
  439. #define PLLCC_LPF_2540_6690_KHZ 0x00000038
  440. #define PLLCC_LPF_1050_2780_KHZ 0x00000078
  441. #define PLLCC_LPF_450_1160_KHZ 0x000000F8
  442. #endif
  443. /*
  444. * The following defines are for the flags in the feature reporting register.
  445. */
  446. #define FRR_FAB_MASK 0x00000003
  447. #define FRR_MASK_MASK 0x0000001C
  448. #ifdef NO_CS4612
  449. #define FRR_CFOP_MASK 0x000000E0
  450. #else
  451. #define FRR_CFOP_MASK 0x00000FE0
  452. #endif
  453. #define FRR_CFOP_NOT_DVD 0x00000020
  454. #define FRR_CFOP_A3D 0x00000040
  455. #define FRR_CFOP_128_PIN 0x00000080
  456. #ifndef NO_CS4612
  457. #define FRR_CFOP_CS4280 0x00000800
  458. #endif
  459. #define FRR_FAB_SHIFT 0
  460. #define FRR_MASK_SHIFT 2
  461. #define FRR_CFOP_SHIFT 5
  462. /*
  463. * The following defines are for the flags in the configuration load 1
  464. * register.
  465. */
  466. #define CFL1_CLOCK_SOURCE_MASK 0x00000003
  467. #define CFL1_CLOCK_SOURCE_CS423X 0x00000000
  468. #define CFL1_CLOCK_SOURCE_AC97 0x00000001
  469. #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
  470. #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
  471. #define CFL1_VALID_DATA_MASK 0x000000FF
  472. /*
  473. * The following defines are for the flags in the configuration load 2
  474. * register.
  475. */
  476. #define CFL2_VALID_DATA_MASK 0x000000FF
  477. /*
  478. * The following defines are for the flags in the serial port master control
  479. * register 1.
  480. */
  481. #define SERMC1_MSPE 0x00000001
  482. #define SERMC1_PTC_MASK 0x0000000E
  483. #define SERMC1_PTC_CS423X 0x00000000
  484. #define SERMC1_PTC_AC97 0x00000002
  485. #define SERMC1_PTC_DAC 0x00000004
  486. #define SERMC1_PLB 0x00000010
  487. #define SERMC1_XLB 0x00000020
  488. /*
  489. * The following defines are for the flags in the serial port master control
  490. * register 2.
  491. */
  492. #define SERMC2_LROE 0x00000001
  493. #define SERMC2_MCOE 0x00000002
  494. #define SERMC2_MCDIV 0x00000004
  495. /*
  496. * The following defines are for the flags in the serial port 1 configuration
  497. * register.
  498. */
  499. #define SERC1_SO1EN 0x00000001
  500. #define SERC1_SO1F_MASK 0x0000000E
  501. #define SERC1_SO1F_CS423X 0x00000000
  502. #define SERC1_SO1F_AC97 0x00000002
  503. #define SERC1_SO1F_DAC 0x00000004
  504. #define SERC1_SO1F_SPDIF 0x00000006
  505. /*
  506. * The following defines are for the flags in the serial port 2 configuration
  507. * register.
  508. */
  509. #define SERC2_SI1EN 0x00000001
  510. #define SERC2_SI1F_MASK 0x0000000E
  511. #define SERC2_SI1F_CS423X 0x00000000
  512. #define SERC2_SI1F_AC97 0x00000002
  513. #define SERC2_SI1F_ADC 0x00000004
  514. #define SERC2_SI1F_SPDIF 0x00000006
  515. /*
  516. * The following defines are for the flags in the serial port 3 configuration
  517. * register.
  518. */
  519. #define SERC3_SO2EN 0x00000001
  520. #define SERC3_SO2F_MASK 0x00000006
  521. #define SERC3_SO2F_DAC 0x00000000
  522. #define SERC3_SO2F_SPDIF 0x00000002
  523. /*
  524. * The following defines are for the flags in the serial port 4 configuration
  525. * register.
  526. */
  527. #define SERC4_SO3EN 0x00000001
  528. #define SERC4_SO3F_MASK 0x00000006
  529. #define SERC4_SO3F_DAC 0x00000000
  530. #define SERC4_SO3F_SPDIF 0x00000002
  531. /*
  532. * The following defines are for the flags in the serial port 5 configuration
  533. * register.
  534. */
  535. #define SERC5_SI2EN 0x00000001
  536. #define SERC5_SI2F_MASK 0x00000006
  537. #define SERC5_SI2F_ADC 0x00000000
  538. #define SERC5_SI2F_SPDIF 0x00000002
  539. /*
  540. * The following defines are for the flags in the serial port backdoor sample
  541. * pointer register.
  542. */
  543. #define SERBSP_FSP_MASK 0x0000000F
  544. #define SERBSP_FSP_SHIFT 0
  545. /*
  546. * The following defines are for the flags in the serial port backdoor status
  547. * register.
  548. */
  549. #define SERBST_RRDY 0x00000001
  550. #define SERBST_WBSY 0x00000002
  551. /*
  552. * The following defines are for the flags in the serial port backdoor command
  553. * register.
  554. */
  555. #define SERBCM_RDC 0x00000001
  556. #define SERBCM_WRC 0x00000002
  557. /*
  558. * The following defines are for the flags in the serial port backdoor address
  559. * register.
  560. */
  561. #ifdef NO_CS4612
  562. #define SERBAD_FAD_MASK 0x000000FF
  563. #else
  564. #define SERBAD_FAD_MASK 0x000001FF
  565. #endif
  566. #define SERBAD_FAD_SHIFT 0
  567. /*
  568. * The following defines are for the flags in the serial port backdoor
  569. * configuration register.
  570. */
  571. #define SERBCF_HBP 0x00000001
  572. /*
  573. * The following defines are for the flags in the serial port backdoor write
  574. * port register.
  575. */
  576. #define SERBWP_FWD_MASK 0x000FFFFF
  577. #define SERBWP_FWD_SHIFT 0
  578. /*
  579. * The following defines are for the flags in the serial port backdoor read
  580. * port register.
  581. */
  582. #define SERBRP_FRD_MASK 0x000FFFFF
  583. #define SERBRP_FRD_SHIFT 0
  584. /*
  585. * The following defines are for the flags in the async FIFO address register.
  586. */
  587. #ifndef NO_CS4612
  588. #define ASER_FADDR_A1_MASK 0x000001FF
  589. #define ASER_FADDR_EN1 0x00008000
  590. #define ASER_FADDR_A2_MASK 0x01FF0000
  591. #define ASER_FADDR_EN2 0x80000000
  592. #define ASER_FADDR_A1_SHIFT 0
  593. #define ASER_FADDR_A2_SHIFT 16
  594. #endif
  595. /*
  596. * The following defines are for the flags in the AC97 control register.
  597. */
  598. #define ACCTL_RSTN 0x00000001
  599. #define ACCTL_ESYN 0x00000002
  600. #define ACCTL_VFRM 0x00000004
  601. #define ACCTL_DCV 0x00000008
  602. #define ACCTL_CRW 0x00000010
  603. #define ACCTL_ASYN 0x00000020
  604. #ifndef NO_CS4612
  605. #define ACCTL_TC 0x00000040
  606. #endif
  607. /*
  608. * The following defines are for the flags in the AC97 status register.
  609. */
  610. #define ACSTS_CRDY 0x00000001
  611. #define ACSTS_VSTS 0x00000002
  612. #ifndef NO_CS4612
  613. #define ACSTS_WKUP 0x00000004
  614. #endif
  615. /*
  616. * The following defines are for the flags in the AC97 output slot valid
  617. * register.
  618. */
  619. #define ACOSV_SLV3 0x00000001
  620. #define ACOSV_SLV4 0x00000002
  621. #define ACOSV_SLV5 0x00000004
  622. #define ACOSV_SLV6 0x00000008
  623. #define ACOSV_SLV7 0x00000010
  624. #define ACOSV_SLV8 0x00000020
  625. #define ACOSV_SLV9 0x00000040
  626. #define ACOSV_SLV10 0x00000080
  627. #define ACOSV_SLV11 0x00000100
  628. #define ACOSV_SLV12 0x00000200
  629. /*
  630. * The following defines are for the flags in the AC97 command address
  631. * register.
  632. */
  633. #define ACCAD_CI_MASK 0x0000007F
  634. #define ACCAD_CI_SHIFT 0
  635. /*
  636. * The following defines are for the flags in the AC97 command data register.
  637. */
  638. #define ACCDA_CD_MASK 0x0000FFFF
  639. #define ACCDA_CD_SHIFT 0
  640. /*
  641. * The following defines are for the flags in the AC97 input slot valid
  642. * register.
  643. */
  644. #define ACISV_ISV3 0x00000001
  645. #define ACISV_ISV4 0x00000002
  646. #define ACISV_ISV5 0x00000004
  647. #define ACISV_ISV6 0x00000008
  648. #define ACISV_ISV7 0x00000010
  649. #define ACISV_ISV8 0x00000020
  650. #define ACISV_ISV9 0x00000040
  651. #define ACISV_ISV10 0x00000080
  652. #define ACISV_ISV11 0x00000100
  653. #define ACISV_ISV12 0x00000200
  654. /*
  655. * The following defines are for the flags in the AC97 status address
  656. * register.
  657. */
  658. #define ACSAD_SI_MASK 0x0000007F
  659. #define ACSAD_SI_SHIFT 0
  660. /*
  661. * The following defines are for the flags in the AC97 status data register.
  662. */
  663. #define ACSDA_SD_MASK 0x0000FFFF
  664. #define ACSDA_SD_SHIFT 0
  665. /*
  666. * The following defines are for the flags in the joystick poll/trigger
  667. * register.
  668. */
  669. #define JSPT_CAX 0x00000001
  670. #define JSPT_CAY 0x00000002
  671. #define JSPT_CBX 0x00000004
  672. #define JSPT_CBY 0x00000008
  673. #define JSPT_BA1 0x00000010
  674. #define JSPT_BA2 0x00000020
  675. #define JSPT_BB1 0x00000040
  676. #define JSPT_BB2 0x00000080
  677. /*
  678. * The following defines are for the flags in the joystick control register.
  679. */
  680. #define JSCTL_SP_MASK 0x00000003
  681. #define JSCTL_SP_SLOW 0x00000000
  682. #define JSCTL_SP_MEDIUM_SLOW 0x00000001
  683. #define JSCTL_SP_MEDIUM_FAST 0x00000002
  684. #define JSCTL_SP_FAST 0x00000003
  685. #define JSCTL_ARE 0x00000004
  686. /*
  687. * The following defines are for the flags in the joystick coordinate pair 1
  688. * readback register.
  689. */
  690. #define JSC1_Y1V_MASK 0x0000FFFF
  691. #define JSC1_X1V_MASK 0xFFFF0000
  692. #define JSC1_Y1V_SHIFT 0
  693. #define JSC1_X1V_SHIFT 16
  694. /*
  695. * The following defines are for the flags in the joystick coordinate pair 2
  696. * readback register.
  697. */
  698. #define JSC2_Y2V_MASK 0x0000FFFF
  699. #define JSC2_X2V_MASK 0xFFFF0000
  700. #define JSC2_Y2V_SHIFT 0
  701. #define JSC2_X2V_SHIFT 16
  702. /*
  703. * The following defines are for the flags in the MIDI control register.
  704. */
  705. #define MIDCR_TXE 0x00000001 /* Enable transmitting. */
  706. #define MIDCR_RXE 0x00000002 /* Enable receiving. */
  707. #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
  708. #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
  709. #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
  710. #define MIDCR_MRST 0x00000020 /* Reset interface. */
  711. /*
  712. * The following defines are for the flags in the MIDI status register.
  713. */
  714. #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
  715. #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
  716. /*
  717. * The following defines are for the flags in the MIDI write port register.
  718. */
  719. #define MIDWP_MWD_MASK 0x000000FF
  720. #define MIDWP_MWD_SHIFT 0
  721. /*
  722. * The following defines are for the flags in the MIDI read port register.
  723. */
  724. #define MIDRP_MRD_MASK 0x000000FF
  725. #define MIDRP_MRD_SHIFT 0
  726. /*
  727. * The following defines are for the flags in the joystick GPIO register.
  728. */
  729. #define JSIO_DAX 0x00000001
  730. #define JSIO_DAY 0x00000002
  731. #define JSIO_DBX 0x00000004
  732. #define JSIO_DBY 0x00000008
  733. #define JSIO_AXOE 0x00000010
  734. #define JSIO_AYOE 0x00000020
  735. #define JSIO_BXOE 0x00000040
  736. #define JSIO_BYOE 0x00000080
  737. /*
  738. * The following defines are for the flags in the master async/sync serial
  739. * port enable register.
  740. */
  741. #ifndef NO_CS4612
  742. #define ASER_MASTER_ME 0x00000001
  743. #endif
  744. /*
  745. * The following defines are for the flags in the configuration interface
  746. * register.
  747. */
  748. #define CFGI_CLK 0x00000001
  749. #define CFGI_DOUT 0x00000002
  750. #define CFGI_DIN_EEN 0x00000004
  751. #define CFGI_EELD 0x00000008
  752. /*
  753. * The following defines are for the flags in the subsystem ID and vendor ID
  754. * register.
  755. */
  756. #define SSVID_VID_MASK 0x0000FFFF
  757. #define SSVID_SID_MASK 0xFFFF0000
  758. #define SSVID_VID_SHIFT 0
  759. #define SSVID_SID_SHIFT 16
  760. /*
  761. * The following defines are for the flags in the GPIO pin interface register.
  762. */
  763. #define GPIOR_VOLDN 0x00000001
  764. #define GPIOR_VOLUP 0x00000002
  765. #define GPIOR_SI2D 0x00000004
  766. #define GPIOR_SI2OE 0x00000008
  767. /*
  768. * The following defines are for the flags in the extended GPIO pin direction
  769. * register.
  770. */
  771. #ifndef NO_CS4612
  772. #define EGPIODR_GPOE0 0x00000001
  773. #define EGPIODR_GPOE1 0x00000002
  774. #define EGPIODR_GPOE2 0x00000004
  775. #define EGPIODR_GPOE3 0x00000008
  776. #define EGPIODR_GPOE4 0x00000010
  777. #define EGPIODR_GPOE5 0x00000020
  778. #define EGPIODR_GPOE6 0x00000040
  779. #define EGPIODR_GPOE7 0x00000080
  780. #define EGPIODR_GPOE8 0x00000100
  781. #endif
  782. /*
  783. * The following defines are for the flags in the extended GPIO pin polarity/
  784. * type register.
  785. */
  786. #ifndef NO_CS4612
  787. #define EGPIOPTR_GPPT0 0x00000001
  788. #define EGPIOPTR_GPPT1 0x00000002
  789. #define EGPIOPTR_GPPT2 0x00000004
  790. #define EGPIOPTR_GPPT3 0x00000008
  791. #define EGPIOPTR_GPPT4 0x00000010
  792. #define EGPIOPTR_GPPT5 0x00000020
  793. #define EGPIOPTR_GPPT6 0x00000040
  794. #define EGPIOPTR_GPPT7 0x00000080
  795. #define EGPIOPTR_GPPT8 0x00000100
  796. #endif
  797. /*
  798. * The following defines are for the flags in the extended GPIO pin sticky
  799. * register.
  800. */
  801. #ifndef NO_CS4612
  802. #define EGPIOTR_GPS0 0x00000001
  803. #define EGPIOTR_GPS1 0x00000002
  804. #define EGPIOTR_GPS2 0x00000004
  805. #define EGPIOTR_GPS3 0x00000008
  806. #define EGPIOTR_GPS4 0x00000010
  807. #define EGPIOTR_GPS5 0x00000020
  808. #define EGPIOTR_GPS6 0x00000040
  809. #define EGPIOTR_GPS7 0x00000080
  810. #define EGPIOTR_GPS8 0x00000100
  811. #endif
  812. /*
  813. * The following defines are for the flags in the extended GPIO ping wakeup
  814. * register.
  815. */
  816. #ifndef NO_CS4612
  817. #define EGPIOWR_GPW0 0x00000001
  818. #define EGPIOWR_GPW1 0x00000002
  819. #define EGPIOWR_GPW2 0x00000004
  820. #define EGPIOWR_GPW3 0x00000008
  821. #define EGPIOWR_GPW4 0x00000010
  822. #define EGPIOWR_GPW5 0x00000020
  823. #define EGPIOWR_GPW6 0x00000040
  824. #define EGPIOWR_GPW7 0x00000080
  825. #define EGPIOWR_GPW8 0x00000100
  826. #endif
  827. /*
  828. * The following defines are for the flags in the extended GPIO pin status
  829. * register.
  830. */
  831. #ifndef NO_CS4612
  832. #define EGPIOSR_GPS0 0x00000001
  833. #define EGPIOSR_GPS1 0x00000002
  834. #define EGPIOSR_GPS2 0x00000004
  835. #define EGPIOSR_GPS3 0x00000008
  836. #define EGPIOSR_GPS4 0x00000010
  837. #define EGPIOSR_GPS5 0x00000020
  838. #define EGPIOSR_GPS6 0x00000040
  839. #define EGPIOSR_GPS7 0x00000080
  840. #define EGPIOSR_GPS8 0x00000100
  841. #endif
  842. /*
  843. * The following defines are for the flags in the serial port 6 configuration
  844. * register.
  845. */
  846. #ifndef NO_CS4612
  847. #define SERC6_ASDO2EN 0x00000001
  848. #endif
  849. /*
  850. * The following defines are for the flags in the serial port 7 configuration
  851. * register.
  852. */
  853. #ifndef NO_CS4612
  854. #define SERC7_ASDI2EN 0x00000001
  855. #define SERC7_POSILB 0x00000002
  856. #define SERC7_SIPOLB 0x00000004
  857. #define SERC7_SOSILB 0x00000008
  858. #define SERC7_SISOLB 0x00000010
  859. #endif
  860. /*
  861. * The following defines are for the flags in the serial port AC link
  862. * configuration register.
  863. */
  864. #ifndef NO_CS4612
  865. #define SERACC_CODEC_TYPE_MASK 0x00000001
  866. #define SERACC_CODEC_TYPE_1_03 0x00000000
  867. #define SERACC_CODEC_TYPE_2_0 0x00000001
  868. #define SERACC_TWO_CODECS 0x00000002
  869. #define SERACC_MDM 0x00000004
  870. #define SERACC_HSP 0x00000008
  871. #endif
  872. /*
  873. * The following defines are for the flags in the AC97 control register 2.
  874. */
  875. #ifndef NO_CS4612
  876. #define ACCTL2_RSTN 0x00000001
  877. #define ACCTL2_ESYN 0x00000002
  878. #define ACCTL2_VFRM 0x00000004
  879. #define ACCTL2_DCV 0x00000008
  880. #define ACCTL2_CRW 0x00000010
  881. #define ACCTL2_ASYN 0x00000020
  882. #endif
  883. /*
  884. * The following defines are for the flags in the AC97 status register 2.
  885. */
  886. #ifndef NO_CS4612
  887. #define ACSTS2_CRDY 0x00000001
  888. #define ACSTS2_VSTS 0x00000002
  889. #endif
  890. /*
  891. * The following defines are for the flags in the AC97 output slot valid
  892. * register 2.
  893. */
  894. #ifndef NO_CS4612
  895. #define ACOSV2_SLV3 0x00000001
  896. #define ACOSV2_SLV4 0x00000002
  897. #define ACOSV2_SLV5 0x00000004
  898. #define ACOSV2_SLV6 0x00000008
  899. #define ACOSV2_SLV7 0x00000010
  900. #define ACOSV2_SLV8 0x00000020
  901. #define ACOSV2_SLV9 0x00000040
  902. #define ACOSV2_SLV10 0x00000080
  903. #define ACOSV2_SLV11 0x00000100
  904. #define ACOSV2_SLV12 0x00000200
  905. #endif
  906. /*
  907. * The following defines are for the flags in the AC97 command address
  908. * register 2.
  909. */
  910. #ifndef NO_CS4612
  911. #define ACCAD2_CI_MASK 0x0000007F
  912. #define ACCAD2_CI_SHIFT 0
  913. #endif
  914. /*
  915. * The following defines are for the flags in the AC97 command data register
  916. * 2.
  917. */
  918. #ifndef NO_CS4612
  919. #define ACCDA2_CD_MASK 0x0000FFFF
  920. #define ACCDA2_CD_SHIFT 0
  921. #endif
  922. /*
  923. * The following defines are for the flags in the AC97 input slot valid
  924. * register 2.
  925. */
  926. #ifndef NO_CS4612
  927. #define ACISV2_ISV3 0x00000001
  928. #define ACISV2_ISV4 0x00000002
  929. #define ACISV2_ISV5 0x00000004
  930. #define ACISV2_ISV6 0x00000008
  931. #define ACISV2_ISV7 0x00000010
  932. #define ACISV2_ISV8 0x00000020
  933. #define ACISV2_ISV9 0x00000040
  934. #define ACISV2_ISV10 0x00000080
  935. #define ACISV2_ISV11 0x00000100
  936. #define ACISV2_ISV12 0x00000200
  937. #endif
  938. /*
  939. * The following defines are for the flags in the AC97 status address
  940. * register 2.
  941. */
  942. #ifndef NO_CS4612
  943. #define ACSAD2_SI_MASK 0x0000007F
  944. #define ACSAD2_SI_SHIFT 0
  945. #endif
  946. /*
  947. * The following defines are for the flags in the AC97 status data register 2.
  948. */
  949. #ifndef NO_CS4612
  950. #define ACSDA2_SD_MASK 0x0000FFFF
  951. #define ACSDA2_SD_SHIFT 0
  952. #endif
  953. /*
  954. * The following defines are for the flags in the I/O trap address and control
  955. * registers (all 12).
  956. */
  957. #ifndef NO_CS4612
  958. #define IOTAC_SA_MASK 0x0000FFFF
  959. #define IOTAC_MSK_MASK 0x000F0000
  960. #define IOTAC_IODC_MASK 0x06000000
  961. #define IOTAC_IODC_16_BIT 0x00000000
  962. #define IOTAC_IODC_10_BIT 0x02000000
  963. #define IOTAC_IODC_12_BIT 0x04000000
  964. #define IOTAC_WSPI 0x08000000
  965. #define IOTAC_RSPI 0x10000000
  966. #define IOTAC_WSE 0x20000000
  967. #define IOTAC_WE 0x40000000
  968. #define IOTAC_RE 0x80000000
  969. #define IOTAC_SA_SHIFT 0
  970. #define IOTAC_MSK_SHIFT 16
  971. #endif
  972. /*
  973. * The following defines are for the flags in the I/O trap fast read registers
  974. * (all 8).
  975. */
  976. #ifndef NO_CS4612
  977. #define IOTFR_D_MASK 0x0000FFFF
  978. #define IOTFR_A_MASK 0x000F0000
  979. #define IOTFR_R_MASK 0x0F000000
  980. #define IOTFR_ALL 0x40000000
  981. #define IOTFR_VL 0x80000000
  982. #define IOTFR_D_SHIFT 0
  983. #define IOTFR_A_SHIFT 16
  984. #define IOTFR_R_SHIFT 24
  985. #endif
  986. /*
  987. * The following defines are for the flags in the I/O trap FIFO register.
  988. */
  989. #ifndef NO_CS4612
  990. #define IOTFIFO_BA_MASK 0x00003FFF
  991. #define IOTFIFO_S_MASK 0x00FF0000
  992. #define IOTFIFO_OF 0x40000000
  993. #define IOTFIFO_SPIOF 0x80000000
  994. #define IOTFIFO_BA_SHIFT 0
  995. #define IOTFIFO_S_SHIFT 16
  996. #endif
  997. /*
  998. * The following defines are for the flags in the I/O trap retry read data
  999. * register.
  1000. */
  1001. #ifndef NO_CS4612
  1002. #define IOTRRD_D_MASK 0x0000FFFF
  1003. #define IOTRRD_RDV 0x80000000
  1004. #define IOTRRD_D_SHIFT 0
  1005. #endif
  1006. /*
  1007. * The following defines are for the flags in the I/O trap FIFO pointer
  1008. * register.
  1009. */
  1010. #ifndef NO_CS4612
  1011. #define IOTFP_CA_MASK 0x00003FFF
  1012. #define IOTFP_PA_MASK 0x3FFF0000
  1013. #define IOTFP_CA_SHIFT 0
  1014. #define IOTFP_PA_SHIFT 16
  1015. #endif
  1016. /*
  1017. * The following defines are for the flags in the I/O trap control register.
  1018. */
  1019. #ifndef NO_CS4612
  1020. #define IOTCR_ITD 0x00000001
  1021. #define IOTCR_HRV 0x00000002
  1022. #define IOTCR_SRV 0x00000004
  1023. #define IOTCR_DTI 0x00000008
  1024. #define IOTCR_DFI 0x00000010
  1025. #define IOTCR_DDP 0x00000020
  1026. #define IOTCR_JTE 0x00000040
  1027. #define IOTCR_PPE 0x00000080
  1028. #endif
  1029. /*
  1030. * The following defines are for the flags in the direct PCI data register.
  1031. */
  1032. #ifndef NO_CS4612
  1033. #define DPCID_D_MASK 0xFFFFFFFF
  1034. #define DPCID_D_SHIFT 0
  1035. #endif
  1036. /*
  1037. * The following defines are for the flags in the direct PCI address register.
  1038. */
  1039. #ifndef NO_CS4612
  1040. #define DPCIA_A_MASK 0xFFFFFFFF
  1041. #define DPCIA_A_SHIFT 0
  1042. #endif
  1043. /*
  1044. * The following defines are for the flags in the direct PCI command register.
  1045. */
  1046. #ifndef NO_CS4612
  1047. #define DPCIC_C_MASK 0x0000000F
  1048. #define DPCIC_C_IOREAD 0x00000002
  1049. #define DPCIC_C_IOWRITE 0x00000003
  1050. #define DPCIC_BE_MASK 0x000000F0
  1051. #endif
  1052. /*
  1053. * The following defines are for the flags in the PC/PCI request register.
  1054. */
  1055. #ifndef NO_CS4612
  1056. #define PCPCIR_RDC_MASK 0x00000007
  1057. #define PCPCIR_C_MASK 0x00007000
  1058. #define PCPCIR_REQ 0x00008000
  1059. #define PCPCIR_RDC_SHIFT 0
  1060. #define PCPCIR_C_SHIFT 12
  1061. #endif
  1062. /*
  1063. * The following defines are for the flags in the PC/PCI grant register.
  1064. */
  1065. #ifndef NO_CS4612
  1066. #define PCPCIG_GDC_MASK 0x00000007
  1067. #define PCPCIG_VL 0x00008000
  1068. #define PCPCIG_GDC_SHIFT 0
  1069. #endif
  1070. /*
  1071. * The following defines are for the flags in the PC/PCI master enable
  1072. * register.
  1073. */
  1074. #ifndef NO_CS4612
  1075. #define PCPCIEN_EN 0x00000001
  1076. #endif
  1077. /*
  1078. * The following defines are for the flags in the extended PCI power
  1079. * management control register.
  1080. */
  1081. #ifndef NO_CS4612
  1082. #define EPCIPMC_GWU 0x00000001
  1083. #define EPCIPMC_FSPC 0x00000002
  1084. #endif
  1085. /*
  1086. * The following defines are for the flags in the SP control register.
  1087. */
  1088. #define SPCR_RUN 0x00000001
  1089. #define SPCR_STPFR 0x00000002
  1090. #define SPCR_RUNFR 0x00000004
  1091. #define SPCR_TICK 0x00000008
  1092. #define SPCR_DRQEN 0x00000020
  1093. #define SPCR_RSTSP 0x00000040
  1094. #define SPCR_OREN 0x00000080
  1095. #ifndef NO_CS4612
  1096. #define SPCR_PCIINT 0x00000100
  1097. #define SPCR_OINTD 0x00000200
  1098. #define SPCR_CRE 0x00008000
  1099. #endif
  1100. /*
  1101. * The following defines are for the flags in the debug index register.
  1102. */
  1103. #define DREG_REGID_MASK 0x0000007F
  1104. #define DREG_DEBUG 0x00000080
  1105. #define DREG_RGBK_MASK 0x00000700
  1106. #define DREG_TRAP 0x00000800
  1107. #if !defined(NO_CS4612)
  1108. #if !defined(NO_CS4615)
  1109. #define DREG_TRAPX 0x00001000
  1110. #endif
  1111. #endif
  1112. #define DREG_REGID_SHIFT 0
  1113. #define DREG_RGBK_SHIFT 8
  1114. #define DREG_RGBK_REGID_MASK 0x0000077F
  1115. #define DREG_REGID_R0 0x00000010
  1116. #define DREG_REGID_R1 0x00000011
  1117. #define DREG_REGID_R2 0x00000012
  1118. #define DREG_REGID_R3 0x00000013
  1119. #define DREG_REGID_R4 0x00000014
  1120. #define DREG_REGID_R5 0x00000015
  1121. #define DREG_REGID_R6 0x00000016
  1122. #define DREG_REGID_R7 0x00000017
  1123. #define DREG_REGID_R8 0x00000018
  1124. #define DREG_REGID_R9 0x00000019
  1125. #define DREG_REGID_RA 0x0000001A
  1126. #define DREG_REGID_RB 0x0000001B
  1127. #define DREG_REGID_RC 0x0000001C
  1128. #define DREG_REGID_RD 0x0000001D
  1129. #define DREG_REGID_RE 0x0000001E
  1130. #define DREG_REGID_RF 0x0000001F
  1131. #define DREG_REGID_RA_BUS_LOW 0x00000020
  1132. #define DREG_REGID_RA_BUS_HIGH 0x00000038
  1133. #define DREG_REGID_YBUS_LOW 0x00000050
  1134. #define DREG_REGID_YBUS_HIGH 0x00000058
  1135. #define DREG_REGID_TRAP_0 0x00000100
  1136. #define DREG_REGID_TRAP_1 0x00000101
  1137. #define DREG_REGID_TRAP_2 0x00000102
  1138. #define DREG_REGID_TRAP_3 0x00000103
  1139. #define DREG_REGID_TRAP_4 0x00000104
  1140. #define DREG_REGID_TRAP_5 0x00000105
  1141. #define DREG_REGID_TRAP_6 0x00000106
  1142. #define DREG_REGID_TRAP_7 0x00000107
  1143. #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
  1144. #define DREG_REGID_TOP_OF_STACK 0x0000010F
  1145. #if !defined(NO_CS4612)
  1146. #if !defined(NO_CS4615)
  1147. #define DREG_REGID_TRAP_8 0x00000110
  1148. #define DREG_REGID_TRAP_9 0x00000111
  1149. #define DREG_REGID_TRAP_10 0x00000112
  1150. #define DREG_REGID_TRAP_11 0x00000113
  1151. #define DREG_REGID_TRAP_12 0x00000114
  1152. #define DREG_REGID_TRAP_13 0x00000115
  1153. #define DREG_REGID_TRAP_14 0x00000116
  1154. #define DREG_REGID_TRAP_15 0x00000117
  1155. #define DREG_REGID_TRAP_16 0x00000118
  1156. #define DREG_REGID_TRAP_17 0x00000119
  1157. #define DREG_REGID_TRAP_18 0x0000011A
  1158. #define DREG_REGID_TRAP_19 0x0000011B
  1159. #define DREG_REGID_TRAP_20 0x0000011C
  1160. #define DREG_REGID_TRAP_21 0x0000011D
  1161. #define DREG_REGID_TRAP_22 0x0000011E
  1162. #define DREG_REGID_TRAP_23 0x0000011F
  1163. #endif
  1164. #endif
  1165. #define DREG_REGID_RSA0_LOW 0x00000200
  1166. #define DREG_REGID_RSA0_HIGH 0x00000201
  1167. #define DREG_REGID_RSA1_LOW 0x00000202
  1168. #define DREG_REGID_RSA1_HIGH 0x00000203
  1169. #define DREG_REGID_RSA2 0x00000204
  1170. #define DREG_REGID_RSA3 0x00000205
  1171. #define DREG_REGID_RSI0_LOW 0x00000206
  1172. #define DREG_REGID_RSI0_HIGH 0x00000207
  1173. #define DREG_REGID_RSI1 0x00000208
  1174. #define DREG_REGID_RSI2 0x00000209
  1175. #define DREG_REGID_SAGUSTATUS 0x0000020A
  1176. #define DREG_REGID_RSCONFIG01_LOW 0x0000020B
  1177. #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
  1178. #define DREG_REGID_RSCONFIG23_LOW 0x0000020D
  1179. #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
  1180. #define DREG_REGID_RSDMA01E 0x0000020F
  1181. #define DREG_REGID_RSDMA23E 0x00000210
  1182. #define DREG_REGID_RSD0_LOW 0x00000211
  1183. #define DREG_REGID_RSD0_HIGH 0x00000212
  1184. #define DREG_REGID_RSD1_LOW 0x00000213
  1185. #define DREG_REGID_RSD1_HIGH 0x00000214
  1186. #define DREG_REGID_RSD2_LOW 0x00000215
  1187. #define DREG_REGID_RSD2_HIGH 0x00000216
  1188. #define DREG_REGID_RSD3_LOW 0x00000217
  1189. #define DREG_REGID_RSD3_HIGH 0x00000218
  1190. #define DREG_REGID_SRAR_HIGH 0x0000021A
  1191. #define DREG_REGID_SRAR_LOW 0x0000021B
  1192. #define DREG_REGID_DMA_STATE 0x0000021C
  1193. #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
  1194. #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
  1195. #define DREG_REGID_CPU_STATUS 0x00000300
  1196. #define DREG_REGID_MAC_MODE 0x00000301
  1197. #define DREG_REGID_STACK_AND_REPEAT 0x00000302
  1198. #define DREG_REGID_INDEX0 0x00000304
  1199. #define DREG_REGID_INDEX1 0x00000305
  1200. #define DREG_REGID_DMA_STATE_0_3 0x00000400
  1201. #define DREG_REGID_DMA_STATE_4_7 0x00000404
  1202. #define DREG_REGID_DMA_STATE_8_11 0x00000408
  1203. #define DREG_REGID_DMA_STATE_12_15 0x0000040C
  1204. #define DREG_REGID_DMA_STATE_16_19 0x00000410
  1205. #define DREG_REGID_DMA_STATE_20_23 0x00000414
  1206. #define DREG_REGID_DMA_STATE_24_27 0x00000418
  1207. #define DREG_REGID_DMA_STATE_28_31 0x0000041C
  1208. #define DREG_REGID_DMA_STATE_32_35 0x00000420
  1209. #define DREG_REGID_DMA_STATE_36_39 0x00000424
  1210. #define DREG_REGID_DMA_STATE_40_43 0x00000428
  1211. #define DREG_REGID_DMA_STATE_44_47 0x0000042C
  1212. #define DREG_REGID_DMA_STATE_48_51 0x00000430
  1213. #define DREG_REGID_DMA_STATE_52_55 0x00000434
  1214. #define DREG_REGID_DMA_STATE_56_59 0x00000438
  1215. #define DREG_REGID_DMA_STATE_60_63 0x0000043C
  1216. #define DREG_REGID_DMA_STATE_64_67 0x00000440
  1217. #define DREG_REGID_DMA_STATE_68_71 0x00000444
  1218. #define DREG_REGID_DMA_STATE_72_75 0x00000448
  1219. #define DREG_REGID_DMA_STATE_76_79 0x0000044C
  1220. #define DREG_REGID_DMA_STATE_80_83 0x00000450
  1221. #define DREG_REGID_DMA_STATE_84_87 0x00000454
  1222. #define DREG_REGID_DMA_STATE_88_91 0x00000458
  1223. #define DREG_REGID_DMA_STATE_92_95 0x0000045C
  1224. #define DREG_REGID_TRAP_SELECT 0x00000500
  1225. #define DREG_REGID_TRAP_WRITE_0 0x00000500
  1226. #define DREG_REGID_TRAP_WRITE_1 0x00000501
  1227. #define DREG_REGID_TRAP_WRITE_2 0x00000502
  1228. #define DREG_REGID_TRAP_WRITE_3 0x00000503
  1229. #define DREG_REGID_TRAP_WRITE_4 0x00000504
  1230. #define DREG_REGID_TRAP_WRITE_5 0x00000505
  1231. #define DREG_REGID_TRAP_WRITE_6 0x00000506
  1232. #define DREG_REGID_TRAP_WRITE_7 0x00000507
  1233. #if !defined(NO_CS4612)
  1234. #if !defined(NO_CS4615)
  1235. #define DREG_REGID_TRAP_WRITE_8 0x00000510
  1236. #define DREG_REGID_TRAP_WRITE_9 0x00000511
  1237. #define DREG_REGID_TRAP_WRITE_10 0x00000512
  1238. #define DREG_REGID_TRAP_WRITE_11 0x00000513
  1239. #define DREG_REGID_TRAP_WRITE_12 0x00000514
  1240. #define DREG_REGID_TRAP_WRITE_13 0x00000515
  1241. #define DREG_REGID_TRAP_WRITE_14 0x00000516
  1242. #define DREG_REGID_TRAP_WRITE_15 0x00000517
  1243. #define DREG_REGID_TRAP_WRITE_16 0x00000518
  1244. #define DREG_REGID_TRAP_WRITE_17 0x00000519
  1245. #define DREG_REGID_TRAP_WRITE_18 0x0000051A
  1246. #define DREG_REGID_TRAP_WRITE_19 0x0000051B
  1247. #define DREG_REGID_TRAP_WRITE_20 0x0000051C
  1248. #define DREG_REGID_TRAP_WRITE_21 0x0000051D
  1249. #define DREG_REGID_TRAP_WRITE_22 0x0000051E
  1250. #define DREG_REGID_TRAP_WRITE_23 0x0000051F
  1251. #endif
  1252. #endif
  1253. #define DREG_REGID_MAC0_ACC0_LOW 0x00000600
  1254. #define DREG_REGID_MAC0_ACC1_LOW 0x00000601
  1255. #define DREG_REGID_MAC0_ACC2_LOW 0x00000602
  1256. #define DREG_REGID_MAC0_ACC3_LOW 0x00000603
  1257. #define DREG_REGID_MAC1_ACC0_LOW 0x00000604
  1258. #define DREG_REGID_MAC1_ACC1_LOW 0x00000605
  1259. #define DREG_REGID_MAC1_ACC2_LOW 0x00000606
  1260. #define DREG_REGID_MAC1_ACC3_LOW 0x00000607
  1261. #define DREG_REGID_MAC0_ACC0_MID 0x00000608
  1262. #define DREG_REGID_MAC0_ACC1_MID 0x00000609
  1263. #define DREG_REGID_MAC0_ACC2_MID 0x0000060A
  1264. #define DREG_REGID_MAC0_ACC3_MID 0x0000060B
  1265. #define DREG_REGID_MAC1_ACC0_MID 0x0000060C
  1266. #define DREG_REGID_MAC1_ACC1_MID 0x0000060D
  1267. #define DREG_REGID_MAC1_ACC2_MID 0x0000060E
  1268. #define DREG_REGID_MAC1_ACC3_MID 0x0000060F
  1269. #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
  1270. #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
  1271. #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
  1272. #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
  1273. #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
  1274. #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
  1275. #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
  1276. #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
  1277. #define DREG_REGID_RSHOUT_LOW 0x00000620
  1278. #define DREG_REGID_RSHOUT_MID 0x00000628
  1279. #define DREG_REGID_RSHOUT_HIGH 0x00000630
  1280. /*
  1281. * The following defines are for the flags in the DMA stream requestor write
  1282. */
  1283. #define DSRWP_DSR_MASK 0x0000000F
  1284. #define DSRWP_DSR_BG_RQ 0x00000001
  1285. #define DSRWP_DSR_PRIORITY_MASK 0x00000006
  1286. #define DSRWP_DSR_PRIORITY_0 0x00000000
  1287. #define DSRWP_DSR_PRIORITY_1 0x00000002
  1288. #define DSRWP_DSR_PRIORITY_2 0x00000004
  1289. #define DSRWP_DSR_PRIORITY_3 0x00000006
  1290. #define DSRWP_DSR_RQ_PENDING 0x00000008
  1291. /*
  1292. * The following defines are for the flags in the trap write port register.
  1293. */
  1294. #define TWPR_TW_MASK 0x0000FFFF
  1295. #define TWPR_TW_SHIFT 0
  1296. /*
  1297. * The following defines are for the flags in the stack pointer write
  1298. * register.
  1299. */
  1300. #define SPWR_STKP_MASK 0x0000000F
  1301. #define SPWR_STKP_SHIFT 0
  1302. /*
  1303. * The following defines are for the flags in the SP interrupt register.
  1304. */
  1305. #define SPIR_FRI 0x00000001
  1306. #define SPIR_DOI 0x00000002
  1307. #define SPIR_GPI2 0x00000004
  1308. #define SPIR_GPI3 0x00000008
  1309. #define SPIR_IP0 0x00000010
  1310. #define SPIR_IP1 0x00000020
  1311. #define SPIR_IP2 0x00000040
  1312. #define SPIR_IP3 0x00000080
  1313. /*
  1314. * The following defines are for the flags in the functional group 1 register.
  1315. */
  1316. #define FGR1_F1S_MASK 0x0000FFFF
  1317. #define FGR1_F1S_SHIFT 0
  1318. /*
  1319. * The following defines are for the flags in the SP clock status register.
  1320. */
  1321. #define SPCS_FRI 0x00000001
  1322. #define SPCS_DOI 0x00000002
  1323. #define SPCS_GPI2 0x00000004
  1324. #define SPCS_GPI3 0x00000008
  1325. #define SPCS_IP0 0x00000010
  1326. #define SPCS_IP1 0x00000020
  1327. #define SPCS_IP2 0x00000040
  1328. #define SPCS_IP3 0x00000080
  1329. #define SPCS_SPRUN 0x00000100
  1330. #define SPCS_SLEEP 0x00000200
  1331. #define SPCS_FG 0x00000400
  1332. #define SPCS_ORUN 0x00000800
  1333. #define SPCS_IRQ 0x00001000
  1334. #define SPCS_FGN_MASK 0x0000E000
  1335. #define SPCS_FGN_SHIFT 13
  1336. /*
  1337. * The following defines are for the flags in the SP DMA requestor status
  1338. * register.
  1339. */
  1340. #define SDSR_DCS_MASK 0x000000FF
  1341. #define SDSR_DCS_SHIFT 0
  1342. #define SDSR_DCS_NONE 0x00000007
  1343. /*
  1344. * The following defines are for the flags in the frame timer register.
  1345. */
  1346. #define FRMT_FTV_MASK 0x0000FFFF
  1347. #define FRMT_FTV_SHIFT 0
  1348. /*
  1349. * The following defines are for the flags in the frame timer current count
  1350. * register.
  1351. */
  1352. #define FRCC_FCC_MASK 0x0000FFFF
  1353. #define FRCC_FCC_SHIFT 0
  1354. /*
  1355. * The following defines are for the flags in the frame timer save count
  1356. * register.
  1357. */
  1358. #define FRSC_FCS_MASK 0x0000FFFF
  1359. #define FRSC_FCS_SHIFT 0
  1360. /*
  1361. * The following define the various flags stored in the scatter/gather
  1362. * descriptors.
  1363. */
  1364. #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
  1365. #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
  1366. #define DMA_SG_SAMPLE_END_FLAG 0x10000000
  1367. #define DMA_SG_LOOP_END_FLAG 0x20000000
  1368. #define DMA_SG_SIGNAL_END_FLAG 0x40000000
  1369. #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
  1370. #define DMA_SG_NEXT_ENTRY_SHIFT 3
  1371. #define DMA_SG_SAMPLE_END_SHIFT 16
  1372. /*
  1373. * The following define the offsets of the fields within the on-chip generic
  1374. * DMA requestor.
  1375. */
  1376. #define DMA_RQ_CONTROL1 0x00000000
  1377. #define DMA_RQ_CONTROL2 0x00000004
  1378. #define DMA_RQ_SOURCE_ADDR 0x00000008
  1379. #define DMA_RQ_DESTINATION_ADDR 0x0000000C
  1380. #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
  1381. #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
  1382. #define DMA_RQ_LOOP_START_ADDR 0x00000018
  1383. #define DMA_RQ_POST_LOOP_ADDR 0x0000001C
  1384. #define DMA_RQ_PAGE_MAP_ADDR 0x00000020
  1385. /*
  1386. * The following defines are for the flags in the first control word of the
  1387. * on-chip generic DMA requestor.
  1388. */
  1389. #define DMA_RQ_C1_COUNT_MASK 0x000003FF
  1390. #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
  1391. #define DMA_RQ_C1_SOURCE_GATHER 0x00002000
  1392. #define DMA_RQ_C1_DONE_FLAG 0x00004000
  1393. #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
  1394. #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
  1395. #define DMA_RQ_C1_FULL_PAGE 0x00000000
  1396. #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
  1397. #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
  1398. #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
  1399. #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
  1400. #define DMA_RQ_C1_NOT_LOOP_END 0x00000000
  1401. #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
  1402. #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
  1403. #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
  1404. #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
  1405. #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
  1406. #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
  1407. #define DMA_RQ_C1_PM_RESERVED 0x00200000
  1408. #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
  1409. #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
  1410. #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
  1411. #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
  1412. #define DMA_RQ_C1_DEST_LINEAR 0x00000000
  1413. #define DMA_RQ_C1_DEST_MOD16 0x01000000
  1414. #define DMA_RQ_C1_DEST_MOD32 0x02000000
  1415. #define DMA_RQ_C1_DEST_MOD64 0x03000000
  1416. #define DMA_RQ_C1_DEST_MOD128 0x04000000
  1417. #define DMA_RQ_C1_DEST_MOD256 0x05000000
  1418. #define DMA_RQ_C1_DEST_MOD512 0x06000000
  1419. #define DMA_RQ_C1_DEST_MOD1024 0x07000000
  1420. #define DMA_RQ_C1_DEST_ON_HOST 0x08000000
  1421. #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
  1422. #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
  1423. #define DMA_RQ_C1_SOURCE_MOD16 0x10000000
  1424. #define DMA_RQ_C1_SOURCE_MOD32 0x20000000
  1425. #define DMA_RQ_C1_SOURCE_MOD64 0x30000000
  1426. #define DMA_RQ_C1_SOURCE_MOD128 0x40000000
  1427. #define DMA_RQ_C1_SOURCE_MOD256 0x50000000
  1428. #define DMA_RQ_C1_SOURCE_MOD512 0x60000000
  1429. #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
  1430. #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
  1431. #define DMA_RQ_C1_COUNT_SHIFT 0
  1432. /*
  1433. * The following defines are for the flags in the second control word of the
  1434. * on-chip generic DMA requestor.
  1435. */
  1436. #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
  1437. #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
  1438. #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
  1439. #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
  1440. #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
  1441. #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
  1442. #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
  1443. #define DMA_RQ_C2_AC_NONE 0x00000000
  1444. #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
  1445. #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
  1446. #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
  1447. #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
  1448. #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
  1449. #define DMA_RQ_C2_LOOP_MASK 0x30000000
  1450. #define DMA_RQ_C2_NO_LOOP 0x00000000
  1451. #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
  1452. #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
  1453. #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
  1454. #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
  1455. #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
  1456. #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
  1457. #define DMA_RQ_C2_LOOP_END_SHIFT 16
  1458. /*
  1459. * The following defines are for the flags in the source and destination words
  1460. * of the on-chip generic DMA requestor.
  1461. */
  1462. #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
  1463. #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
  1464. #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
  1465. #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
  1466. #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
  1467. #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
  1468. #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
  1469. #define DMA_RQ_SD_END_FLAG 0x40000000
  1470. #define DMA_RQ_SD_ERROR_FLAG 0x80000000
  1471. #define DMA_RQ_SD_ADDRESS_SHIFT 0
  1472. /*
  1473. * The following defines are for the flags in the page map address word of the
  1474. * on-chip generic DMA requestor.
  1475. */
  1476. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
  1477. #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
  1478. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
  1479. #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
  1480. #define BA1_VARIDEC_BUF_1 0x000
  1481. #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
  1482. #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
  1483. #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
  1484. #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
  1485. #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
  1486. #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
  1487. #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
  1488. #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
  1489. #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
  1490. #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
  1491. #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
  1492. #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
  1493. #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
  1494. #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
  1495. #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
  1496. #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
  1497. #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
  1498. #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
  1499. #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
  1500. /*
  1501. *
  1502. */
  1503. #define CS461X_MODE_OUTPUT (1<<0) /* MIDI UART - output */
  1504. #define CS461X_MODE_INPUT (1<<1) /* MIDI UART - input */
  1505. //****************************************************************************
  1506. //
  1507. // The following define the offsets of the AC97 shadow registers, which appear
  1508. // as a virtual extension to the base address register zero memory range.
  1509. //
  1510. //****************************************************************************
  1511. #define AC97_REG_OFFSET_MASK 0x0000007EL
  1512. #define AC97_CODEC_NUMBER_MASK 0x00003000L
  1513. #define BA0_AC97_RESET 0x00001000L
  1514. #define BA0_AC97_MASTER_VOLUME 0x00001002L
  1515. #define BA0_AC97_HEADPHONE_VOLUME 0x00001004L
  1516. #define BA0_AC97_MASTER_VOLUME_MONO 0x00001006L
  1517. #define BA0_AC97_MASTER_TONE 0x00001008L
  1518. #define BA0_AC97_PC_BEEP_VOLUME 0x0000100AL
  1519. #define BA0_AC97_PHONE_VOLUME 0x0000100CL
  1520. #define BA0_AC97_MIC_VOLUME 0x0000100EL
  1521. #define BA0_AC97_LINE_IN_VOLUME 0x00001010L
  1522. #define BA0_AC97_CD_VOLUME 0x00001012L
  1523. #define BA0_AC97_VIDEO_VOLUME 0x00001014L
  1524. #define BA0_AC97_AUX_VOLUME 0x00001016L
  1525. #define BA0_AC97_PCM_OUT_VOLUME 0x00001018L
  1526. #define BA0_AC97_RECORD_SELECT 0x0000101AL
  1527. #define BA0_AC97_RECORD_GAIN 0x0000101CL
  1528. #define BA0_AC97_RECORD_GAIN_MIC 0x0000101EL
  1529. #define BA0_AC97_GENERAL_PURPOSE 0x00001020L
  1530. #define BA0_AC97_3D_CONTROL 0x00001022L
  1531. #define BA0_AC97_MODEM_RATE 0x00001024L
  1532. #define BA0_AC97_POWERDOWN 0x00001026L
  1533. #define BA0_AC97_EXT_AUDIO_ID 0x00001028L
  1534. #define BA0_AC97_EXT_AUDIO_POWER 0x0000102AL
  1535. #define BA0_AC97_PCM_FRONT_DAC_RATE 0x0000102CL
  1536. #define BA0_AC97_PCM_SURR_DAC_RATE 0x0000102EL
  1537. #define BA0_AC97_PCM_LFE_DAC_RATE 0x00001030L
  1538. #define BA0_AC97_PCM_LR_ADC_RATE 0x00001032L
  1539. #define BA0_AC97_MIC_ADC_RATE 0x00001034L
  1540. #define BA0_AC97_6CH_VOL_C_LFE 0x00001036L
  1541. #define BA0_AC97_6CH_VOL_SURROUND 0x00001038L
  1542. #define BA0_AC97_RESERVED_3A 0x0000103AL
  1543. #define BA0_AC97_EXT_MODEM_ID 0x0000103CL
  1544. #define BA0_AC97_EXT_MODEM_POWER 0x0000103EL
  1545. #define BA0_AC97_LINE1_CODEC_RATE 0x00001040L
  1546. #define BA0_AC97_LINE2_CODEC_RATE 0x00001042L
  1547. #define BA0_AC97_HANDSET_CODEC_RATE 0x00001044L
  1548. #define BA0_AC97_LINE1_CODEC_LEVEL 0x00001046L
  1549. #define BA0_AC97_LINE2_CODEC_LEVEL 0x00001048L
  1550. #define BA0_AC97_HANDSET_CODEC_LEVEL 0x0000104AL
  1551. #define BA0_AC97_GPIO_PIN_CONFIG 0x0000104CL
  1552. #define BA0_AC97_GPIO_PIN_TYPE 0x0000104EL
  1553. #define BA0_AC97_GPIO_PIN_STICKY 0x00001050L
  1554. #define BA0_AC97_GPIO_PIN_WAKEUP 0x00001052L
  1555. #define BA0_AC97_GPIO_PIN_STATUS 0x00001054L
  1556. #define BA0_AC97_MISC_MODEM_AFE_STAT 0x00001056L
  1557. #define BA0_AC97_RESERVED_58 0x00001058L
  1558. #define BA0_AC97_CRYSTAL_REV_N_FAB_ID 0x0000105AL
  1559. #define BA0_AC97_TEST_AND_MISC_CTRL 0x0000105CL
  1560. #define BA0_AC97_AC_MODE 0x0000105EL
  1561. #define BA0_AC97_MISC_CRYSTAL_CONTROL 0x00001060L
  1562. #define BA0_AC97_LINE1_HYPRID_CTRL 0x00001062L
  1563. #define BA0_AC97_VENDOR_RESERVED_64 0x00001064L
  1564. #define BA0_AC97_VENDOR_RESERVED_66 0x00001066L
  1565. #define BA0_AC97_SPDIF_CONTROL 0x00001068L
  1566. #define BA0_AC97_VENDOR_RESERVED_6A 0x0000106AL
  1567. #define BA0_AC97_VENDOR_RESERVED_6C 0x0000106CL
  1568. #define BA0_AC97_VENDOR_RESERVED_6E 0x0000106EL
  1569. #define BA0_AC97_VENDOR_RESERVED_70 0x00001070L
  1570. #define BA0_AC97_VENDOR_RESERVED_72 0x00001072L
  1571. #define BA0_AC97_VENDOR_RESERVED_74 0x00001074L
  1572. #define BA0_AC97_CAL_ADDRESS 0x00001076L
  1573. #define BA0_AC97_CAL_DATA 0x00001078L
  1574. #define BA0_AC97_VENDOR_RESERVED_7A 0x0000107AL
  1575. #define BA0_AC97_VENDOR_ID1 0x0000107CL
  1576. #define BA0_AC97_VENDOR_ID2 0x0000107EL
  1577. #endif /* __CS461X_H */