au1550_ac97.c 50 KB

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  1. /*
  2. * au1550_ac97.c -- Sound driver for Alchemy Au1550 MIPS Internet Edge
  3. * Processor.
  4. *
  5. * Copyright 2004 Embedded Edge, LLC
  6. * dan@embeddededge.com
  7. *
  8. * Mostly copied from the au1000.c driver and some from the
  9. * PowerMac dbdma driver.
  10. * We assume the processor can do memory coherent DMA.
  11. *
  12. * Ported to 2.6 by Matt Porter <mporter@kernel.crashing.org>
  13. *
  14. * This program is free software; you can redistribute it and/or modify it
  15. * under the terms of the GNU General Public License as published by the
  16. * Free Software Foundation; either version 2 of the License, or (at your
  17. * option) any later version.
  18. *
  19. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  20. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  21. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  22. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  23. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  24. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  25. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  26. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  27. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  28. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  29. *
  30. * You should have received a copy of the GNU General Public License along
  31. * with this program; if not, write to the Free Software Foundation, Inc.,
  32. * 675 Mass Ave, Cambridge, MA 02139, USA.
  33. *
  34. */
  35. #undef DEBUG
  36. #include <linux/module.h>
  37. #include <linux/string.h>
  38. #include <linux/ioport.h>
  39. #include <linux/sched.h>
  40. #include <linux/delay.h>
  41. #include <linux/sound.h>
  42. #include <linux/slab.h>
  43. #include <linux/soundcard.h>
  44. #include <linux/init.h>
  45. #include <linux/interrupt.h>
  46. #include <linux/kernel.h>
  47. #include <linux/poll.h>
  48. #include <linux/pci.h>
  49. #include <linux/bitops.h>
  50. #include <linux/spinlock.h>
  51. #include <linux/smp_lock.h>
  52. #include <linux/ac97_codec.h>
  53. #include <linux/mutex.h>
  54. #include <asm/io.h>
  55. #include <asm/uaccess.h>
  56. #include <asm/hardirq.h>
  57. #include <asm/mach-au1x00/au1xxx_psc.h>
  58. #include <asm/mach-au1x00/au1xxx_dbdma.h>
  59. #include <asm/mach-au1x00/au1xxx.h>
  60. #undef OSS_DOCUMENTED_MIXER_SEMANTICS
  61. /* misc stuff */
  62. #define POLL_COUNT 0x50000
  63. #define AC97_EXT_DACS (AC97_EXTID_SDAC | AC97_EXTID_CDAC | AC97_EXTID_LDAC)
  64. /* The number of DBDMA ring descriptors to allocate. No sense making
  65. * this too large....if you can't keep up with a few you aren't likely
  66. * to be able to with lots of them, either.
  67. */
  68. #define NUM_DBDMA_DESCRIPTORS 4
  69. #define err(format, arg...) printk(KERN_ERR format "\n" , ## arg)
  70. /* Boot options
  71. * 0 = no VRA, 1 = use VRA if codec supports it
  72. */
  73. static int vra = 1;
  74. module_param(vra, bool, 0);
  75. MODULE_PARM_DESC(vra, "if 1 use VRA if codec supports it");
  76. static struct au1550_state {
  77. /* soundcore stuff */
  78. int dev_audio;
  79. struct ac97_codec *codec;
  80. unsigned codec_base_caps; /* AC'97 reg 00h, "Reset Register" */
  81. unsigned codec_ext_caps; /* AC'97 reg 28h, "Extended Audio ID" */
  82. int no_vra; /* do not use VRA */
  83. spinlock_t lock;
  84. struct mutex open_mutex;
  85. struct mutex sem;
  86. mode_t open_mode;
  87. wait_queue_head_t open_wait;
  88. struct dmabuf {
  89. u32 dmanr;
  90. unsigned sample_rate;
  91. unsigned src_factor;
  92. unsigned sample_size;
  93. int num_channels;
  94. int dma_bytes_per_sample;
  95. int user_bytes_per_sample;
  96. int cnt_factor;
  97. void *rawbuf;
  98. unsigned buforder;
  99. unsigned numfrag;
  100. unsigned fragshift;
  101. void *nextIn;
  102. void *nextOut;
  103. int count;
  104. unsigned total_bytes;
  105. unsigned error;
  106. wait_queue_head_t wait;
  107. /* redundant, but makes calculations easier */
  108. unsigned fragsize;
  109. unsigned dma_fragsize;
  110. unsigned dmasize;
  111. unsigned dma_qcount;
  112. /* OSS stuff */
  113. unsigned mapped:1;
  114. unsigned ready:1;
  115. unsigned stopped:1;
  116. unsigned ossfragshift;
  117. int ossmaxfrags;
  118. unsigned subdivision;
  119. } dma_dac, dma_adc;
  120. } au1550_state;
  121. static unsigned
  122. ld2(unsigned int x)
  123. {
  124. unsigned r = 0;
  125. if (x >= 0x10000) {
  126. x >>= 16;
  127. r += 16;
  128. }
  129. if (x >= 0x100) {
  130. x >>= 8;
  131. r += 8;
  132. }
  133. if (x >= 0x10) {
  134. x >>= 4;
  135. r += 4;
  136. }
  137. if (x >= 4) {
  138. x >>= 2;
  139. r += 2;
  140. }
  141. if (x >= 2)
  142. r++;
  143. return r;
  144. }
  145. static void
  146. au1550_delay(int msec)
  147. {
  148. unsigned long tmo;
  149. signed long tmo2;
  150. if (in_interrupt())
  151. return;
  152. tmo = jiffies + (msec * HZ) / 1000;
  153. for (;;) {
  154. tmo2 = tmo - jiffies;
  155. if (tmo2 <= 0)
  156. break;
  157. schedule_timeout(tmo2);
  158. }
  159. }
  160. static u16
  161. rdcodec(struct ac97_codec *codec, u8 addr)
  162. {
  163. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  164. unsigned long flags;
  165. u32 cmd, val;
  166. u16 data;
  167. int i;
  168. spin_lock_irqsave(&s->lock, flags);
  169. for (i = 0; i < POLL_COUNT; i++) {
  170. val = au_readl(PSC_AC97STAT);
  171. au_sync();
  172. if (!(val & PSC_AC97STAT_CP))
  173. break;
  174. }
  175. if (i == POLL_COUNT)
  176. err("rdcodec: codec cmd pending expired!");
  177. cmd = (u32)PSC_AC97CDC_INDX(addr);
  178. cmd |= PSC_AC97CDC_RD; /* read command */
  179. au_writel(cmd, PSC_AC97CDC);
  180. au_sync();
  181. /* now wait for the data
  182. */
  183. for (i = 0; i < POLL_COUNT; i++) {
  184. val = au_readl(PSC_AC97STAT);
  185. au_sync();
  186. if (!(val & PSC_AC97STAT_CP))
  187. break;
  188. }
  189. if (i == POLL_COUNT) {
  190. err("rdcodec: read poll expired!");
  191. data = 0;
  192. goto out;
  193. }
  194. /* wait for command done?
  195. */
  196. for (i = 0; i < POLL_COUNT; i++) {
  197. val = au_readl(PSC_AC97EVNT);
  198. au_sync();
  199. if (val & PSC_AC97EVNT_CD)
  200. break;
  201. }
  202. if (i == POLL_COUNT) {
  203. err("rdcodec: read cmdwait expired!");
  204. data = 0;
  205. goto out;
  206. }
  207. data = au_readl(PSC_AC97CDC) & 0xffff;
  208. au_sync();
  209. /* Clear command done event.
  210. */
  211. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  212. au_sync();
  213. out:
  214. spin_unlock_irqrestore(&s->lock, flags);
  215. return data;
  216. }
  217. static void
  218. wrcodec(struct ac97_codec *codec, u8 addr, u16 data)
  219. {
  220. struct au1550_state *s = (struct au1550_state *)codec->private_data;
  221. unsigned long flags;
  222. u32 cmd, val;
  223. int i;
  224. spin_lock_irqsave(&s->lock, flags);
  225. for (i = 0; i < POLL_COUNT; i++) {
  226. val = au_readl(PSC_AC97STAT);
  227. au_sync();
  228. if (!(val & PSC_AC97STAT_CP))
  229. break;
  230. }
  231. if (i == POLL_COUNT)
  232. err("wrcodec: codec cmd pending expired!");
  233. cmd = (u32)PSC_AC97CDC_INDX(addr);
  234. cmd |= (u32)data;
  235. au_writel(cmd, PSC_AC97CDC);
  236. au_sync();
  237. for (i = 0; i < POLL_COUNT; i++) {
  238. val = au_readl(PSC_AC97STAT);
  239. au_sync();
  240. if (!(val & PSC_AC97STAT_CP))
  241. break;
  242. }
  243. if (i == POLL_COUNT)
  244. err("wrcodec: codec cmd pending expired!");
  245. for (i = 0; i < POLL_COUNT; i++) {
  246. val = au_readl(PSC_AC97EVNT);
  247. au_sync();
  248. if (val & PSC_AC97EVNT_CD)
  249. break;
  250. }
  251. if (i == POLL_COUNT)
  252. err("wrcodec: read cmdwait expired!");
  253. /* Clear command done event.
  254. */
  255. au_writel(PSC_AC97EVNT_CD, PSC_AC97EVNT);
  256. au_sync();
  257. spin_unlock_irqrestore(&s->lock, flags);
  258. }
  259. static void
  260. waitcodec(struct ac97_codec *codec)
  261. {
  262. u16 temp;
  263. u32 val;
  264. int i;
  265. /* codec_wait is used to wait for a ready state after
  266. * an AC97C_RESET.
  267. */
  268. au1550_delay(10);
  269. /* first poll the CODEC_READY tag bit
  270. */
  271. for (i = 0; i < POLL_COUNT; i++) {
  272. val = au_readl(PSC_AC97STAT);
  273. au_sync();
  274. if (val & PSC_AC97STAT_CR)
  275. break;
  276. }
  277. if (i == POLL_COUNT) {
  278. err("waitcodec: CODEC_READY poll expired!");
  279. return;
  280. }
  281. /* get AC'97 powerdown control/status register
  282. */
  283. temp = rdcodec(codec, AC97_POWER_CONTROL);
  284. /* If anything is powered down, power'em up
  285. */
  286. if (temp & 0x7f00) {
  287. /* Power on
  288. */
  289. wrcodec(codec, AC97_POWER_CONTROL, 0);
  290. au1550_delay(100);
  291. /* Reread
  292. */
  293. temp = rdcodec(codec, AC97_POWER_CONTROL);
  294. }
  295. /* Check if Codec REF,ANL,DAC,ADC ready
  296. */
  297. if ((temp & 0x7f0f) != 0x000f)
  298. err("codec reg 26 status (0x%x) not ready!!", temp);
  299. }
  300. /* stop the ADC before calling */
  301. static void
  302. set_adc_rate(struct au1550_state *s, unsigned rate)
  303. {
  304. struct dmabuf *adc = &s->dma_adc;
  305. struct dmabuf *dac = &s->dma_dac;
  306. unsigned adc_rate, dac_rate;
  307. u16 ac97_extstat;
  308. if (s->no_vra) {
  309. /* calc SRC factor
  310. */
  311. adc->src_factor = ((96000 / rate) + 1) >> 1;
  312. adc->sample_rate = 48000 / adc->src_factor;
  313. return;
  314. }
  315. adc->src_factor = 1;
  316. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  317. rate = rate > 48000 ? 48000 : rate;
  318. /* enable VRA
  319. */
  320. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  321. ac97_extstat | AC97_EXTSTAT_VRA);
  322. /* now write the sample rate
  323. */
  324. wrcodec(s->codec, AC97_PCM_LR_ADC_RATE, (u16) rate);
  325. /* read it back for actual supported rate
  326. */
  327. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  328. pr_debug("set_adc_rate: set to %d Hz\n", adc_rate);
  329. /* some codec's don't allow unequal DAC and ADC rates, in which case
  330. * writing one rate reg actually changes both.
  331. */
  332. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  333. if (dac->num_channels > 2)
  334. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, dac_rate);
  335. if (dac->num_channels > 4)
  336. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, dac_rate);
  337. adc->sample_rate = adc_rate;
  338. dac->sample_rate = dac_rate;
  339. }
  340. /* stop the DAC before calling */
  341. static void
  342. set_dac_rate(struct au1550_state *s, unsigned rate)
  343. {
  344. struct dmabuf *dac = &s->dma_dac;
  345. struct dmabuf *adc = &s->dma_adc;
  346. unsigned adc_rate, dac_rate;
  347. u16 ac97_extstat;
  348. if (s->no_vra) {
  349. /* calc SRC factor
  350. */
  351. dac->src_factor = ((96000 / rate) + 1) >> 1;
  352. dac->sample_rate = 48000 / dac->src_factor;
  353. return;
  354. }
  355. dac->src_factor = 1;
  356. ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  357. rate = rate > 48000 ? 48000 : rate;
  358. /* enable VRA
  359. */
  360. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  361. ac97_extstat | AC97_EXTSTAT_VRA);
  362. /* now write the sample rate
  363. */
  364. wrcodec(s->codec, AC97_PCM_FRONT_DAC_RATE, (u16) rate);
  365. /* I don't support different sample rates for multichannel,
  366. * so make these channels the same.
  367. */
  368. if (dac->num_channels > 2)
  369. wrcodec(s->codec, AC97_PCM_SURR_DAC_RATE, (u16) rate);
  370. if (dac->num_channels > 4)
  371. wrcodec(s->codec, AC97_PCM_LFE_DAC_RATE, (u16) rate);
  372. /* read it back for actual supported rate
  373. */
  374. dac_rate = rdcodec(s->codec, AC97_PCM_FRONT_DAC_RATE);
  375. pr_debug("set_dac_rate: set to %d Hz\n", dac_rate);
  376. /* some codec's don't allow unequal DAC and ADC rates, in which case
  377. * writing one rate reg actually changes both.
  378. */
  379. adc_rate = rdcodec(s->codec, AC97_PCM_LR_ADC_RATE);
  380. dac->sample_rate = dac_rate;
  381. adc->sample_rate = adc_rate;
  382. }
  383. static void
  384. stop_dac(struct au1550_state *s)
  385. {
  386. struct dmabuf *db = &s->dma_dac;
  387. u32 stat;
  388. unsigned long flags;
  389. if (db->stopped)
  390. return;
  391. spin_lock_irqsave(&s->lock, flags);
  392. au_writel(PSC_AC97PCR_TP, PSC_AC97PCR);
  393. au_sync();
  394. /* Wait for Transmit Busy to show disabled.
  395. */
  396. do {
  397. stat = au_readl(PSC_AC97STAT);
  398. au_sync();
  399. } while ((stat & PSC_AC97STAT_TB) != 0);
  400. au1xxx_dbdma_reset(db->dmanr);
  401. db->stopped = 1;
  402. spin_unlock_irqrestore(&s->lock, flags);
  403. }
  404. static void
  405. stop_adc(struct au1550_state *s)
  406. {
  407. struct dmabuf *db = &s->dma_adc;
  408. unsigned long flags;
  409. u32 stat;
  410. if (db->stopped)
  411. return;
  412. spin_lock_irqsave(&s->lock, flags);
  413. au_writel(PSC_AC97PCR_RP, PSC_AC97PCR);
  414. au_sync();
  415. /* Wait for Receive Busy to show disabled.
  416. */
  417. do {
  418. stat = au_readl(PSC_AC97STAT);
  419. au_sync();
  420. } while ((stat & PSC_AC97STAT_RB) != 0);
  421. au1xxx_dbdma_reset(db->dmanr);
  422. db->stopped = 1;
  423. spin_unlock_irqrestore(&s->lock, flags);
  424. }
  425. static void
  426. set_xmit_slots(int num_channels)
  427. {
  428. u32 ac97_config, stat;
  429. ac97_config = au_readl(PSC_AC97CFG);
  430. au_sync();
  431. ac97_config &= ~(PSC_AC97CFG_TXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  432. au_writel(ac97_config, PSC_AC97CFG);
  433. au_sync();
  434. switch (num_channels) {
  435. case 6: /* stereo with surround and center/LFE,
  436. * slots 3,4,6,7,8,9
  437. */
  438. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(6);
  439. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(9);
  440. case 4: /* stereo with surround, slots 3,4,7,8 */
  441. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(7);
  442. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(8);
  443. case 2: /* stereo, slots 3,4 */
  444. case 1: /* mono */
  445. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(3);
  446. ac97_config |= PSC_AC97CFG_TXSLOT_ENA(4);
  447. }
  448. au_writel(ac97_config, PSC_AC97CFG);
  449. au_sync();
  450. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  451. au_writel(ac97_config, PSC_AC97CFG);
  452. au_sync();
  453. /* Wait for Device ready.
  454. */
  455. do {
  456. stat = au_readl(PSC_AC97STAT);
  457. au_sync();
  458. } while ((stat & PSC_AC97STAT_DR) == 0);
  459. }
  460. static void
  461. set_recv_slots(int num_channels)
  462. {
  463. u32 ac97_config, stat;
  464. ac97_config = au_readl(PSC_AC97CFG);
  465. au_sync();
  466. ac97_config &= ~(PSC_AC97CFG_RXSLOT_MASK | PSC_AC97CFG_DE_ENABLE);
  467. au_writel(ac97_config, PSC_AC97CFG);
  468. au_sync();
  469. /* Always enable slots 3 and 4 (stereo). Slot 6 is
  470. * optional Mic ADC, which we don't support yet.
  471. */
  472. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(3);
  473. ac97_config |= PSC_AC97CFG_RXSLOT_ENA(4);
  474. au_writel(ac97_config, PSC_AC97CFG);
  475. au_sync();
  476. ac97_config |= PSC_AC97CFG_DE_ENABLE;
  477. au_writel(ac97_config, PSC_AC97CFG);
  478. au_sync();
  479. /* Wait for Device ready.
  480. */
  481. do {
  482. stat = au_readl(PSC_AC97STAT);
  483. au_sync();
  484. } while ((stat & PSC_AC97STAT_DR) == 0);
  485. }
  486. /* Hold spinlock for both start_dac() and start_adc() calls */
  487. static void
  488. start_dac(struct au1550_state *s)
  489. {
  490. struct dmabuf *db = &s->dma_dac;
  491. if (!db->stopped)
  492. return;
  493. set_xmit_slots(db->num_channels);
  494. au_writel(PSC_AC97PCR_TC, PSC_AC97PCR);
  495. au_sync();
  496. au_writel(PSC_AC97PCR_TS, PSC_AC97PCR);
  497. au_sync();
  498. au1xxx_dbdma_start(db->dmanr);
  499. db->stopped = 0;
  500. }
  501. static void
  502. start_adc(struct au1550_state *s)
  503. {
  504. struct dmabuf *db = &s->dma_adc;
  505. int i;
  506. if (!db->stopped)
  507. return;
  508. /* Put two buffers on the ring to get things started.
  509. */
  510. for (i=0; i<2; i++) {
  511. au1xxx_dbdma_put_dest(db->dmanr, db->nextIn, db->dma_fragsize);
  512. db->nextIn += db->dma_fragsize;
  513. if (db->nextIn >= db->rawbuf + db->dmasize)
  514. db->nextIn -= db->dmasize;
  515. }
  516. set_recv_slots(db->num_channels);
  517. au1xxx_dbdma_start(db->dmanr);
  518. au_writel(PSC_AC97PCR_RC, PSC_AC97PCR);
  519. au_sync();
  520. au_writel(PSC_AC97PCR_RS, PSC_AC97PCR);
  521. au_sync();
  522. db->stopped = 0;
  523. }
  524. static int
  525. prog_dmabuf(struct au1550_state *s, struct dmabuf *db)
  526. {
  527. unsigned user_bytes_per_sec;
  528. unsigned bufs;
  529. unsigned rate = db->sample_rate;
  530. if (!db->rawbuf) {
  531. db->ready = db->mapped = 0;
  532. db->buforder = 5; /* 32 * PAGE_SIZE */
  533. db->rawbuf = kmalloc((PAGE_SIZE << db->buforder), GFP_KERNEL);
  534. if (!db->rawbuf)
  535. return -ENOMEM;
  536. }
  537. db->cnt_factor = 1;
  538. if (db->sample_size == 8)
  539. db->cnt_factor *= 2;
  540. if (db->num_channels == 1)
  541. db->cnt_factor *= 2;
  542. db->cnt_factor *= db->src_factor;
  543. db->count = 0;
  544. db->dma_qcount = 0;
  545. db->nextIn = db->nextOut = db->rawbuf;
  546. db->user_bytes_per_sample = (db->sample_size>>3) * db->num_channels;
  547. db->dma_bytes_per_sample = 2 * ((db->num_channels == 1) ?
  548. 2 : db->num_channels);
  549. user_bytes_per_sec = rate * db->user_bytes_per_sample;
  550. bufs = PAGE_SIZE << db->buforder;
  551. if (db->ossfragshift) {
  552. if ((1000 << db->ossfragshift) < user_bytes_per_sec)
  553. db->fragshift = ld2(user_bytes_per_sec/1000);
  554. else
  555. db->fragshift = db->ossfragshift;
  556. } else {
  557. db->fragshift = ld2(user_bytes_per_sec / 100 /
  558. (db->subdivision ? db->subdivision : 1));
  559. if (db->fragshift < 3)
  560. db->fragshift = 3;
  561. }
  562. db->fragsize = 1 << db->fragshift;
  563. db->dma_fragsize = db->fragsize * db->cnt_factor;
  564. db->numfrag = bufs / db->dma_fragsize;
  565. while (db->numfrag < 4 && db->fragshift > 3) {
  566. db->fragshift--;
  567. db->fragsize = 1 << db->fragshift;
  568. db->dma_fragsize = db->fragsize * db->cnt_factor;
  569. db->numfrag = bufs / db->dma_fragsize;
  570. }
  571. if (db->ossmaxfrags >= 4 && db->ossmaxfrags < db->numfrag)
  572. db->numfrag = db->ossmaxfrags;
  573. db->dmasize = db->dma_fragsize * db->numfrag;
  574. memset(db->rawbuf, 0, bufs);
  575. pr_debug("prog_dmabuf: rate=%d, samplesize=%d, channels=%d\n",
  576. rate, db->sample_size, db->num_channels);
  577. pr_debug("prog_dmabuf: fragsize=%d, cnt_factor=%d, dma_fragsize=%d\n",
  578. db->fragsize, db->cnt_factor, db->dma_fragsize);
  579. pr_debug("prog_dmabuf: numfrag=%d, dmasize=%d\n", db->numfrag, db->dmasize);
  580. db->ready = 1;
  581. return 0;
  582. }
  583. static int
  584. prog_dmabuf_adc(struct au1550_state *s)
  585. {
  586. stop_adc(s);
  587. return prog_dmabuf(s, &s->dma_adc);
  588. }
  589. static int
  590. prog_dmabuf_dac(struct au1550_state *s)
  591. {
  592. stop_dac(s);
  593. return prog_dmabuf(s, &s->dma_dac);
  594. }
  595. static void dac_dma_interrupt(int irq, void *dev_id)
  596. {
  597. struct au1550_state *s = (struct au1550_state *) dev_id;
  598. struct dmabuf *db = &s->dma_dac;
  599. u32 ac97c_stat;
  600. spin_lock(&s->lock);
  601. ac97c_stat = au_readl(PSC_AC97STAT);
  602. if (ac97c_stat & (AC97C_XU | AC97C_XO | AC97C_TE))
  603. pr_debug("AC97C status = 0x%08x\n", ac97c_stat);
  604. db->dma_qcount--;
  605. if (db->count >= db->fragsize) {
  606. if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
  607. db->fragsize) == 0) {
  608. err("qcount < 2 and no ring room!");
  609. }
  610. db->nextOut += db->fragsize;
  611. if (db->nextOut >= db->rawbuf + db->dmasize)
  612. db->nextOut -= db->dmasize;
  613. db->count -= db->fragsize;
  614. db->total_bytes += db->dma_fragsize;
  615. db->dma_qcount++;
  616. }
  617. /* wake up anybody listening */
  618. if (waitqueue_active(&db->wait))
  619. wake_up(&db->wait);
  620. spin_unlock(&s->lock);
  621. }
  622. static void adc_dma_interrupt(int irq, void *dev_id)
  623. {
  624. struct au1550_state *s = (struct au1550_state *)dev_id;
  625. struct dmabuf *dp = &s->dma_adc;
  626. u32 obytes;
  627. char *obuf;
  628. spin_lock(&s->lock);
  629. /* Pull the buffer from the dma queue.
  630. */
  631. au1xxx_dbdma_get_dest(dp->dmanr, (void *)(&obuf), &obytes);
  632. if ((dp->count + obytes) > dp->dmasize) {
  633. /* Overrun. Stop ADC and log the error
  634. */
  635. spin_unlock(&s->lock);
  636. stop_adc(s);
  637. dp->error++;
  638. err("adc overrun");
  639. return;
  640. }
  641. /* Put a new empty buffer on the destination DMA.
  642. */
  643. au1xxx_dbdma_put_dest(dp->dmanr, dp->nextIn, dp->dma_fragsize);
  644. dp->nextIn += dp->dma_fragsize;
  645. if (dp->nextIn >= dp->rawbuf + dp->dmasize)
  646. dp->nextIn -= dp->dmasize;
  647. dp->count += obytes;
  648. dp->total_bytes += obytes;
  649. /* wake up anybody listening
  650. */
  651. if (waitqueue_active(&dp->wait))
  652. wake_up(&dp->wait);
  653. spin_unlock(&s->lock);
  654. }
  655. static loff_t
  656. au1550_llseek(struct file *file, loff_t offset, int origin)
  657. {
  658. return -ESPIPE;
  659. }
  660. static int
  661. au1550_open_mixdev(struct inode *inode, struct file *file)
  662. {
  663. file->private_data = &au1550_state;
  664. return 0;
  665. }
  666. static int
  667. au1550_release_mixdev(struct inode *inode, struct file *file)
  668. {
  669. return 0;
  670. }
  671. static int
  672. mixdev_ioctl(struct ac97_codec *codec, unsigned int cmd,
  673. unsigned long arg)
  674. {
  675. return codec->mixer_ioctl(codec, cmd, arg);
  676. }
  677. static int
  678. au1550_ioctl_mixdev(struct inode *inode, struct file *file,
  679. unsigned int cmd, unsigned long arg)
  680. {
  681. struct au1550_state *s = (struct au1550_state *)file->private_data;
  682. struct ac97_codec *codec = s->codec;
  683. return mixdev_ioctl(codec, cmd, arg);
  684. }
  685. static /*const */ struct file_operations au1550_mixer_fops = {
  686. owner:THIS_MODULE,
  687. llseek:au1550_llseek,
  688. ioctl:au1550_ioctl_mixdev,
  689. open:au1550_open_mixdev,
  690. release:au1550_release_mixdev,
  691. };
  692. static int
  693. drain_dac(struct au1550_state *s, int nonblock)
  694. {
  695. unsigned long flags;
  696. int count, tmo;
  697. if (s->dma_dac.mapped || !s->dma_dac.ready || s->dma_dac.stopped)
  698. return 0;
  699. for (;;) {
  700. spin_lock_irqsave(&s->lock, flags);
  701. count = s->dma_dac.count;
  702. spin_unlock_irqrestore(&s->lock, flags);
  703. if (count <= s->dma_dac.fragsize)
  704. break;
  705. if (signal_pending(current))
  706. break;
  707. if (nonblock)
  708. return -EBUSY;
  709. tmo = 1000 * count / (s->no_vra ?
  710. 48000 : s->dma_dac.sample_rate);
  711. tmo /= s->dma_dac.dma_bytes_per_sample;
  712. au1550_delay(tmo);
  713. }
  714. if (signal_pending(current))
  715. return -ERESTARTSYS;
  716. return 0;
  717. }
  718. static inline u8 S16_TO_U8(s16 ch)
  719. {
  720. return (u8) (ch >> 8) + 0x80;
  721. }
  722. static inline s16 U8_TO_S16(u8 ch)
  723. {
  724. return (s16) (ch - 0x80) << 8;
  725. }
  726. /*
  727. * Translates user samples to dma buffer suitable for AC'97 DAC data:
  728. * If mono, copy left channel to right channel in dma buffer.
  729. * If 8 bit samples, cvt to 16-bit before writing to dma buffer.
  730. * If interpolating (no VRA), duplicate every audio frame src_factor times.
  731. */
  732. static int
  733. translate_from_user(struct dmabuf *db, char* dmabuf, char* userbuf,
  734. int dmacount)
  735. {
  736. int sample, i;
  737. int interp_bytes_per_sample;
  738. int num_samples;
  739. int mono = (db->num_channels == 1);
  740. char usersample[12];
  741. s16 ch, dmasample[6];
  742. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  743. /* no translation necessary, just copy
  744. */
  745. if (copy_from_user(dmabuf, userbuf, dmacount))
  746. return -EFAULT;
  747. return dmacount;
  748. }
  749. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  750. num_samples = dmacount / interp_bytes_per_sample;
  751. for (sample = 0; sample < num_samples; sample++) {
  752. if (copy_from_user(usersample, userbuf,
  753. db->user_bytes_per_sample)) {
  754. return -EFAULT;
  755. }
  756. for (i = 0; i < db->num_channels; i++) {
  757. if (db->sample_size == 8)
  758. ch = U8_TO_S16(usersample[i]);
  759. else
  760. ch = *((s16 *) (&usersample[i * 2]));
  761. dmasample[i] = ch;
  762. if (mono)
  763. dmasample[i + 1] = ch; /* right channel */
  764. }
  765. /* duplicate every audio frame src_factor times
  766. */
  767. for (i = 0; i < db->src_factor; i++)
  768. memcpy(dmabuf, dmasample, db->dma_bytes_per_sample);
  769. userbuf += db->user_bytes_per_sample;
  770. dmabuf += interp_bytes_per_sample;
  771. }
  772. return num_samples * interp_bytes_per_sample;
  773. }
  774. /*
  775. * Translates AC'97 ADC samples to user buffer:
  776. * If mono, send only left channel to user buffer.
  777. * If 8 bit samples, cvt from 16 to 8 bit before writing to user buffer.
  778. * If decimating (no VRA), skip over src_factor audio frames.
  779. */
  780. static int
  781. translate_to_user(struct dmabuf *db, char* userbuf, char* dmabuf,
  782. int dmacount)
  783. {
  784. int sample, i;
  785. int interp_bytes_per_sample;
  786. int num_samples;
  787. int mono = (db->num_channels == 1);
  788. char usersample[12];
  789. if (db->sample_size == 16 && !mono && db->src_factor == 1) {
  790. /* no translation necessary, just copy
  791. */
  792. if (copy_to_user(userbuf, dmabuf, dmacount))
  793. return -EFAULT;
  794. return dmacount;
  795. }
  796. interp_bytes_per_sample = db->dma_bytes_per_sample * db->src_factor;
  797. num_samples = dmacount / interp_bytes_per_sample;
  798. for (sample = 0; sample < num_samples; sample++) {
  799. for (i = 0; i < db->num_channels; i++) {
  800. if (db->sample_size == 8)
  801. usersample[i] =
  802. S16_TO_U8(*((s16 *) (&dmabuf[i * 2])));
  803. else
  804. *((s16 *) (&usersample[i * 2])) =
  805. *((s16 *) (&dmabuf[i * 2]));
  806. }
  807. if (copy_to_user(userbuf, usersample,
  808. db->user_bytes_per_sample)) {
  809. return -EFAULT;
  810. }
  811. userbuf += db->user_bytes_per_sample;
  812. dmabuf += interp_bytes_per_sample;
  813. }
  814. return num_samples * interp_bytes_per_sample;
  815. }
  816. /*
  817. * Copy audio data to/from user buffer from/to dma buffer, taking care
  818. * that we wrap when reading/writing the dma buffer. Returns actual byte
  819. * count written to or read from the dma buffer.
  820. */
  821. static int
  822. copy_dmabuf_user(struct dmabuf *db, char* userbuf, int count, int to_user)
  823. {
  824. char *bufptr = to_user ? db->nextOut : db->nextIn;
  825. char *bufend = db->rawbuf + db->dmasize;
  826. int cnt, ret;
  827. if (bufptr + count > bufend) {
  828. int partial = (int) (bufend - bufptr);
  829. if (to_user) {
  830. if ((cnt = translate_to_user(db, userbuf,
  831. bufptr, partial)) < 0)
  832. return cnt;
  833. ret = cnt;
  834. if ((cnt = translate_to_user(db, userbuf + partial,
  835. db->rawbuf,
  836. count - partial)) < 0)
  837. return cnt;
  838. ret += cnt;
  839. } else {
  840. if ((cnt = translate_from_user(db, bufptr, userbuf,
  841. partial)) < 0)
  842. return cnt;
  843. ret = cnt;
  844. if ((cnt = translate_from_user(db, db->rawbuf,
  845. userbuf + partial,
  846. count - partial)) < 0)
  847. return cnt;
  848. ret += cnt;
  849. }
  850. } else {
  851. if (to_user)
  852. ret = translate_to_user(db, userbuf, bufptr, count);
  853. else
  854. ret = translate_from_user(db, bufptr, userbuf, count);
  855. }
  856. return ret;
  857. }
  858. static ssize_t
  859. au1550_read(struct file *file, char *buffer, size_t count, loff_t *ppos)
  860. {
  861. struct au1550_state *s = (struct au1550_state *)file->private_data;
  862. struct dmabuf *db = &s->dma_adc;
  863. DECLARE_WAITQUEUE(wait, current);
  864. ssize_t ret;
  865. unsigned long flags;
  866. int cnt, usercnt, avail;
  867. if (db->mapped)
  868. return -ENXIO;
  869. if (!access_ok(VERIFY_WRITE, buffer, count))
  870. return -EFAULT;
  871. ret = 0;
  872. count *= db->cnt_factor;
  873. mutex_lock(&s->sem);
  874. add_wait_queue(&db->wait, &wait);
  875. while (count > 0) {
  876. /* wait for samples in ADC dma buffer
  877. */
  878. do {
  879. spin_lock_irqsave(&s->lock, flags);
  880. if (db->stopped)
  881. start_adc(s);
  882. avail = db->count;
  883. if (avail <= 0)
  884. __set_current_state(TASK_INTERRUPTIBLE);
  885. spin_unlock_irqrestore(&s->lock, flags);
  886. if (avail <= 0) {
  887. if (file->f_flags & O_NONBLOCK) {
  888. if (!ret)
  889. ret = -EAGAIN;
  890. goto out;
  891. }
  892. mutex_unlock(&s->sem);
  893. schedule();
  894. if (signal_pending(current)) {
  895. if (!ret)
  896. ret = -ERESTARTSYS;
  897. goto out2;
  898. }
  899. mutex_lock(&s->sem);
  900. }
  901. } while (avail <= 0);
  902. /* copy from nextOut to user
  903. */
  904. if ((cnt = copy_dmabuf_user(db, buffer,
  905. count > avail ?
  906. avail : count, 1)) < 0) {
  907. if (!ret)
  908. ret = -EFAULT;
  909. goto out;
  910. }
  911. spin_lock_irqsave(&s->lock, flags);
  912. db->count -= cnt;
  913. db->nextOut += cnt;
  914. if (db->nextOut >= db->rawbuf + db->dmasize)
  915. db->nextOut -= db->dmasize;
  916. spin_unlock_irqrestore(&s->lock, flags);
  917. count -= cnt;
  918. usercnt = cnt / db->cnt_factor;
  919. buffer += usercnt;
  920. ret += usercnt;
  921. } /* while (count > 0) */
  922. out:
  923. mutex_unlock(&s->sem);
  924. out2:
  925. remove_wait_queue(&db->wait, &wait);
  926. set_current_state(TASK_RUNNING);
  927. return ret;
  928. }
  929. static ssize_t
  930. au1550_write(struct file *file, const char *buffer, size_t count, loff_t * ppos)
  931. {
  932. struct au1550_state *s = (struct au1550_state *)file->private_data;
  933. struct dmabuf *db = &s->dma_dac;
  934. DECLARE_WAITQUEUE(wait, current);
  935. ssize_t ret = 0;
  936. unsigned long flags;
  937. int cnt, usercnt, avail;
  938. pr_debug("write: count=%d\n", count);
  939. if (db->mapped)
  940. return -ENXIO;
  941. if (!access_ok(VERIFY_READ, buffer, count))
  942. return -EFAULT;
  943. count *= db->cnt_factor;
  944. mutex_lock(&s->sem);
  945. add_wait_queue(&db->wait, &wait);
  946. while (count > 0) {
  947. /* wait for space in playback buffer
  948. */
  949. do {
  950. spin_lock_irqsave(&s->lock, flags);
  951. avail = (int) db->dmasize - db->count;
  952. if (avail <= 0)
  953. __set_current_state(TASK_INTERRUPTIBLE);
  954. spin_unlock_irqrestore(&s->lock, flags);
  955. if (avail <= 0) {
  956. if (file->f_flags & O_NONBLOCK) {
  957. if (!ret)
  958. ret = -EAGAIN;
  959. goto out;
  960. }
  961. mutex_unlock(&s->sem);
  962. schedule();
  963. if (signal_pending(current)) {
  964. if (!ret)
  965. ret = -ERESTARTSYS;
  966. goto out2;
  967. }
  968. mutex_lock(&s->sem);
  969. }
  970. } while (avail <= 0);
  971. /* copy from user to nextIn
  972. */
  973. if ((cnt = copy_dmabuf_user(db, (char *) buffer,
  974. count > avail ?
  975. avail : count, 0)) < 0) {
  976. if (!ret)
  977. ret = -EFAULT;
  978. goto out;
  979. }
  980. spin_lock_irqsave(&s->lock, flags);
  981. db->count += cnt;
  982. db->nextIn += cnt;
  983. if (db->nextIn >= db->rawbuf + db->dmasize)
  984. db->nextIn -= db->dmasize;
  985. /* If the data is available, we want to keep two buffers
  986. * on the dma queue. If the queue count reaches zero,
  987. * we know the dma has stopped.
  988. */
  989. while ((db->dma_qcount < 2) && (db->count >= db->fragsize)) {
  990. if (au1xxx_dbdma_put_source(db->dmanr, db->nextOut,
  991. db->fragsize) == 0) {
  992. err("qcount < 2 and no ring room!");
  993. }
  994. db->nextOut += db->fragsize;
  995. if (db->nextOut >= db->rawbuf + db->dmasize)
  996. db->nextOut -= db->dmasize;
  997. db->total_bytes += db->dma_fragsize;
  998. if (db->dma_qcount == 0)
  999. start_dac(s);
  1000. db->dma_qcount++;
  1001. }
  1002. spin_unlock_irqrestore(&s->lock, flags);
  1003. count -= cnt;
  1004. usercnt = cnt / db->cnt_factor;
  1005. buffer += usercnt;
  1006. ret += usercnt;
  1007. } /* while (count > 0) */
  1008. out:
  1009. mutex_unlock(&s->sem);
  1010. out2:
  1011. remove_wait_queue(&db->wait, &wait);
  1012. set_current_state(TASK_RUNNING);
  1013. return ret;
  1014. }
  1015. /* No kernel lock - we have our own spinlock */
  1016. static unsigned int
  1017. au1550_poll(struct file *file, struct poll_table_struct *wait)
  1018. {
  1019. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1020. unsigned long flags;
  1021. unsigned int mask = 0;
  1022. if (file->f_mode & FMODE_WRITE) {
  1023. if (!s->dma_dac.ready)
  1024. return 0;
  1025. poll_wait(file, &s->dma_dac.wait, wait);
  1026. }
  1027. if (file->f_mode & FMODE_READ) {
  1028. if (!s->dma_adc.ready)
  1029. return 0;
  1030. poll_wait(file, &s->dma_adc.wait, wait);
  1031. }
  1032. spin_lock_irqsave(&s->lock, flags);
  1033. if (file->f_mode & FMODE_READ) {
  1034. if (s->dma_adc.count >= (signed)s->dma_adc.dma_fragsize)
  1035. mask |= POLLIN | POLLRDNORM;
  1036. }
  1037. if (file->f_mode & FMODE_WRITE) {
  1038. if (s->dma_dac.mapped) {
  1039. if (s->dma_dac.count >=
  1040. (signed)s->dma_dac.dma_fragsize)
  1041. mask |= POLLOUT | POLLWRNORM;
  1042. } else {
  1043. if ((signed) s->dma_dac.dmasize >=
  1044. s->dma_dac.count + (signed)s->dma_dac.dma_fragsize)
  1045. mask |= POLLOUT | POLLWRNORM;
  1046. }
  1047. }
  1048. spin_unlock_irqrestore(&s->lock, flags);
  1049. return mask;
  1050. }
  1051. static int
  1052. au1550_mmap(struct file *file, struct vm_area_struct *vma)
  1053. {
  1054. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1055. struct dmabuf *db;
  1056. unsigned long size;
  1057. int ret = 0;
  1058. lock_kernel();
  1059. mutex_lock(&s->sem);
  1060. if (vma->vm_flags & VM_WRITE)
  1061. db = &s->dma_dac;
  1062. else if (vma->vm_flags & VM_READ)
  1063. db = &s->dma_adc;
  1064. else {
  1065. ret = -EINVAL;
  1066. goto out;
  1067. }
  1068. if (vma->vm_pgoff != 0) {
  1069. ret = -EINVAL;
  1070. goto out;
  1071. }
  1072. size = vma->vm_end - vma->vm_start;
  1073. if (size > (PAGE_SIZE << db->buforder)) {
  1074. ret = -EINVAL;
  1075. goto out;
  1076. }
  1077. if (remap_pfn_range(vma, vma->vm_start, page_to_pfn(virt_to_page(db->rawbuf)),
  1078. size, vma->vm_page_prot)) {
  1079. ret = -EAGAIN;
  1080. goto out;
  1081. }
  1082. vma->vm_flags &= ~VM_IO;
  1083. db->mapped = 1;
  1084. out:
  1085. mutex_unlock(&s->sem);
  1086. unlock_kernel();
  1087. return ret;
  1088. }
  1089. #ifdef DEBUG
  1090. static struct ioctl_str_t {
  1091. unsigned int cmd;
  1092. const char *str;
  1093. } ioctl_str[] = {
  1094. {SNDCTL_DSP_RESET, "SNDCTL_DSP_RESET"},
  1095. {SNDCTL_DSP_SYNC, "SNDCTL_DSP_SYNC"},
  1096. {SNDCTL_DSP_SPEED, "SNDCTL_DSP_SPEED"},
  1097. {SNDCTL_DSP_STEREO, "SNDCTL_DSP_STEREO"},
  1098. {SNDCTL_DSP_GETBLKSIZE, "SNDCTL_DSP_GETBLKSIZE"},
  1099. {SNDCTL_DSP_SAMPLESIZE, "SNDCTL_DSP_SAMPLESIZE"},
  1100. {SNDCTL_DSP_CHANNELS, "SNDCTL_DSP_CHANNELS"},
  1101. {SOUND_PCM_WRITE_CHANNELS, "SOUND_PCM_WRITE_CHANNELS"},
  1102. {SOUND_PCM_WRITE_FILTER, "SOUND_PCM_WRITE_FILTER"},
  1103. {SNDCTL_DSP_POST, "SNDCTL_DSP_POST"},
  1104. {SNDCTL_DSP_SUBDIVIDE, "SNDCTL_DSP_SUBDIVIDE"},
  1105. {SNDCTL_DSP_SETFRAGMENT, "SNDCTL_DSP_SETFRAGMENT"},
  1106. {SNDCTL_DSP_GETFMTS, "SNDCTL_DSP_GETFMTS"},
  1107. {SNDCTL_DSP_SETFMT, "SNDCTL_DSP_SETFMT"},
  1108. {SNDCTL_DSP_GETOSPACE, "SNDCTL_DSP_GETOSPACE"},
  1109. {SNDCTL_DSP_GETISPACE, "SNDCTL_DSP_GETISPACE"},
  1110. {SNDCTL_DSP_NONBLOCK, "SNDCTL_DSP_NONBLOCK"},
  1111. {SNDCTL_DSP_GETCAPS, "SNDCTL_DSP_GETCAPS"},
  1112. {SNDCTL_DSP_GETTRIGGER, "SNDCTL_DSP_GETTRIGGER"},
  1113. {SNDCTL_DSP_SETTRIGGER, "SNDCTL_DSP_SETTRIGGER"},
  1114. {SNDCTL_DSP_GETIPTR, "SNDCTL_DSP_GETIPTR"},
  1115. {SNDCTL_DSP_GETOPTR, "SNDCTL_DSP_GETOPTR"},
  1116. {SNDCTL_DSP_MAPINBUF, "SNDCTL_DSP_MAPINBUF"},
  1117. {SNDCTL_DSP_MAPOUTBUF, "SNDCTL_DSP_MAPOUTBUF"},
  1118. {SNDCTL_DSP_SETSYNCRO, "SNDCTL_DSP_SETSYNCRO"},
  1119. {SNDCTL_DSP_SETDUPLEX, "SNDCTL_DSP_SETDUPLEX"},
  1120. {SNDCTL_DSP_GETODELAY, "SNDCTL_DSP_GETODELAY"},
  1121. {SNDCTL_DSP_GETCHANNELMASK, "SNDCTL_DSP_GETCHANNELMASK"},
  1122. {SNDCTL_DSP_BIND_CHANNEL, "SNDCTL_DSP_BIND_CHANNEL"},
  1123. {OSS_GETVERSION, "OSS_GETVERSION"},
  1124. {SOUND_PCM_READ_RATE, "SOUND_PCM_READ_RATE"},
  1125. {SOUND_PCM_READ_CHANNELS, "SOUND_PCM_READ_CHANNELS"},
  1126. {SOUND_PCM_READ_BITS, "SOUND_PCM_READ_BITS"},
  1127. {SOUND_PCM_READ_FILTER, "SOUND_PCM_READ_FILTER"}
  1128. };
  1129. #endif
  1130. static int
  1131. dma_count_done(struct dmabuf *db)
  1132. {
  1133. if (db->stopped)
  1134. return 0;
  1135. return db->dma_fragsize - au1xxx_get_dma_residue(db->dmanr);
  1136. }
  1137. static int
  1138. au1550_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
  1139. unsigned long arg)
  1140. {
  1141. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1142. unsigned long flags;
  1143. audio_buf_info abinfo;
  1144. count_info cinfo;
  1145. int count;
  1146. int val, mapped, ret, diff;
  1147. mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
  1148. ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
  1149. #ifdef DEBUG
  1150. for (count = 0; count < ARRAY_SIZE(ioctl_str); count++) {
  1151. if (ioctl_str[count].cmd == cmd)
  1152. break;
  1153. }
  1154. if (count < ARRAY_SIZE(ioctl_str))
  1155. pr_debug("ioctl %s, arg=0x%lxn", ioctl_str[count].str, arg);
  1156. else
  1157. pr_debug("ioctl 0x%x unknown, arg=0x%lx\n", cmd, arg);
  1158. #endif
  1159. switch (cmd) {
  1160. case OSS_GETVERSION:
  1161. return put_user(SOUND_VERSION, (int *) arg);
  1162. case SNDCTL_DSP_SYNC:
  1163. if (file->f_mode & FMODE_WRITE)
  1164. return drain_dac(s, file->f_flags & O_NONBLOCK);
  1165. return 0;
  1166. case SNDCTL_DSP_SETDUPLEX:
  1167. return 0;
  1168. case SNDCTL_DSP_GETCAPS:
  1169. return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
  1170. DSP_CAP_TRIGGER | DSP_CAP_MMAP, (int *)arg);
  1171. case SNDCTL_DSP_RESET:
  1172. if (file->f_mode & FMODE_WRITE) {
  1173. stop_dac(s);
  1174. synchronize_irq();
  1175. s->dma_dac.count = s->dma_dac.total_bytes = 0;
  1176. s->dma_dac.nextIn = s->dma_dac.nextOut =
  1177. s->dma_dac.rawbuf;
  1178. }
  1179. if (file->f_mode & FMODE_READ) {
  1180. stop_adc(s);
  1181. synchronize_irq();
  1182. s->dma_adc.count = s->dma_adc.total_bytes = 0;
  1183. s->dma_adc.nextIn = s->dma_adc.nextOut =
  1184. s->dma_adc.rawbuf;
  1185. }
  1186. return 0;
  1187. case SNDCTL_DSP_SPEED:
  1188. if (get_user(val, (int *) arg))
  1189. return -EFAULT;
  1190. if (val >= 0) {
  1191. if (file->f_mode & FMODE_READ) {
  1192. stop_adc(s);
  1193. set_adc_rate(s, val);
  1194. }
  1195. if (file->f_mode & FMODE_WRITE) {
  1196. stop_dac(s);
  1197. set_dac_rate(s, val);
  1198. }
  1199. if (s->open_mode & FMODE_READ)
  1200. if ((ret = prog_dmabuf_adc(s)))
  1201. return ret;
  1202. if (s->open_mode & FMODE_WRITE)
  1203. if ((ret = prog_dmabuf_dac(s)))
  1204. return ret;
  1205. }
  1206. return put_user((file->f_mode & FMODE_READ) ?
  1207. s->dma_adc.sample_rate :
  1208. s->dma_dac.sample_rate,
  1209. (int *)arg);
  1210. case SNDCTL_DSP_STEREO:
  1211. if (get_user(val, (int *) arg))
  1212. return -EFAULT;
  1213. if (file->f_mode & FMODE_READ) {
  1214. stop_adc(s);
  1215. s->dma_adc.num_channels = val ? 2 : 1;
  1216. if ((ret = prog_dmabuf_adc(s)))
  1217. return ret;
  1218. }
  1219. if (file->f_mode & FMODE_WRITE) {
  1220. stop_dac(s);
  1221. s->dma_dac.num_channels = val ? 2 : 1;
  1222. if (s->codec_ext_caps & AC97_EXT_DACS) {
  1223. /* disable surround and center/lfe in AC'97
  1224. */
  1225. u16 ext_stat = rdcodec(s->codec,
  1226. AC97_EXTENDED_STATUS);
  1227. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1228. ext_stat | (AC97_EXTSTAT_PRI |
  1229. AC97_EXTSTAT_PRJ |
  1230. AC97_EXTSTAT_PRK));
  1231. }
  1232. if ((ret = prog_dmabuf_dac(s)))
  1233. return ret;
  1234. }
  1235. return 0;
  1236. case SNDCTL_DSP_CHANNELS:
  1237. if (get_user(val, (int *) arg))
  1238. return -EFAULT;
  1239. if (val != 0) {
  1240. if (file->f_mode & FMODE_READ) {
  1241. if (val < 0 || val > 2)
  1242. return -EINVAL;
  1243. stop_adc(s);
  1244. s->dma_adc.num_channels = val;
  1245. if ((ret = prog_dmabuf_adc(s)))
  1246. return ret;
  1247. }
  1248. if (file->f_mode & FMODE_WRITE) {
  1249. switch (val) {
  1250. case 1:
  1251. case 2:
  1252. break;
  1253. case 3:
  1254. case 5:
  1255. return -EINVAL;
  1256. case 4:
  1257. if (!(s->codec_ext_caps &
  1258. AC97_EXTID_SDAC))
  1259. return -EINVAL;
  1260. break;
  1261. case 6:
  1262. if ((s->codec_ext_caps &
  1263. AC97_EXT_DACS) != AC97_EXT_DACS)
  1264. return -EINVAL;
  1265. break;
  1266. default:
  1267. return -EINVAL;
  1268. }
  1269. stop_dac(s);
  1270. if (val <= 2 &&
  1271. (s->codec_ext_caps & AC97_EXT_DACS)) {
  1272. /* disable surround and center/lfe
  1273. * channels in AC'97
  1274. */
  1275. u16 ext_stat =
  1276. rdcodec(s->codec,
  1277. AC97_EXTENDED_STATUS);
  1278. wrcodec(s->codec,
  1279. AC97_EXTENDED_STATUS,
  1280. ext_stat | (AC97_EXTSTAT_PRI |
  1281. AC97_EXTSTAT_PRJ |
  1282. AC97_EXTSTAT_PRK));
  1283. } else if (val >= 4) {
  1284. /* enable surround, center/lfe
  1285. * channels in AC'97
  1286. */
  1287. u16 ext_stat =
  1288. rdcodec(s->codec,
  1289. AC97_EXTENDED_STATUS);
  1290. ext_stat &= ~AC97_EXTSTAT_PRJ;
  1291. if (val == 6)
  1292. ext_stat &=
  1293. ~(AC97_EXTSTAT_PRI |
  1294. AC97_EXTSTAT_PRK);
  1295. wrcodec(s->codec,
  1296. AC97_EXTENDED_STATUS,
  1297. ext_stat);
  1298. }
  1299. s->dma_dac.num_channels = val;
  1300. if ((ret = prog_dmabuf_dac(s)))
  1301. return ret;
  1302. }
  1303. }
  1304. return put_user(val, (int *) arg);
  1305. case SNDCTL_DSP_GETFMTS: /* Returns a mask */
  1306. return put_user(AFMT_S16_LE | AFMT_U8, (int *) arg);
  1307. case SNDCTL_DSP_SETFMT: /* Selects ONE fmt */
  1308. if (get_user(val, (int *) arg))
  1309. return -EFAULT;
  1310. if (val != AFMT_QUERY) {
  1311. if (file->f_mode & FMODE_READ) {
  1312. stop_adc(s);
  1313. if (val == AFMT_S16_LE)
  1314. s->dma_adc.sample_size = 16;
  1315. else {
  1316. val = AFMT_U8;
  1317. s->dma_adc.sample_size = 8;
  1318. }
  1319. if ((ret = prog_dmabuf_adc(s)))
  1320. return ret;
  1321. }
  1322. if (file->f_mode & FMODE_WRITE) {
  1323. stop_dac(s);
  1324. if (val == AFMT_S16_LE)
  1325. s->dma_dac.sample_size = 16;
  1326. else {
  1327. val = AFMT_U8;
  1328. s->dma_dac.sample_size = 8;
  1329. }
  1330. if ((ret = prog_dmabuf_dac(s)))
  1331. return ret;
  1332. }
  1333. } else {
  1334. if (file->f_mode & FMODE_READ)
  1335. val = (s->dma_adc.sample_size == 16) ?
  1336. AFMT_S16_LE : AFMT_U8;
  1337. else
  1338. val = (s->dma_dac.sample_size == 16) ?
  1339. AFMT_S16_LE : AFMT_U8;
  1340. }
  1341. return put_user(val, (int *) arg);
  1342. case SNDCTL_DSP_POST:
  1343. return 0;
  1344. case SNDCTL_DSP_GETTRIGGER:
  1345. val = 0;
  1346. spin_lock_irqsave(&s->lock, flags);
  1347. if (file->f_mode & FMODE_READ && !s->dma_adc.stopped)
  1348. val |= PCM_ENABLE_INPUT;
  1349. if (file->f_mode & FMODE_WRITE && !s->dma_dac.stopped)
  1350. val |= PCM_ENABLE_OUTPUT;
  1351. spin_unlock_irqrestore(&s->lock, flags);
  1352. return put_user(val, (int *) arg);
  1353. case SNDCTL_DSP_SETTRIGGER:
  1354. if (get_user(val, (int *) arg))
  1355. return -EFAULT;
  1356. if (file->f_mode & FMODE_READ) {
  1357. if (val & PCM_ENABLE_INPUT) {
  1358. spin_lock_irqsave(&s->lock, flags);
  1359. start_adc(s);
  1360. spin_unlock_irqrestore(&s->lock, flags);
  1361. } else
  1362. stop_adc(s);
  1363. }
  1364. if (file->f_mode & FMODE_WRITE) {
  1365. if (val & PCM_ENABLE_OUTPUT) {
  1366. spin_lock_irqsave(&s->lock, flags);
  1367. start_dac(s);
  1368. spin_unlock_irqrestore(&s->lock, flags);
  1369. } else
  1370. stop_dac(s);
  1371. }
  1372. return 0;
  1373. case SNDCTL_DSP_GETOSPACE:
  1374. if (!(file->f_mode & FMODE_WRITE))
  1375. return -EINVAL;
  1376. abinfo.fragsize = s->dma_dac.fragsize;
  1377. spin_lock_irqsave(&s->lock, flags);
  1378. count = s->dma_dac.count;
  1379. count -= dma_count_done(&s->dma_dac);
  1380. spin_unlock_irqrestore(&s->lock, flags);
  1381. if (count < 0)
  1382. count = 0;
  1383. abinfo.bytes = (s->dma_dac.dmasize - count) /
  1384. s->dma_dac.cnt_factor;
  1385. abinfo.fragstotal = s->dma_dac.numfrag;
  1386. abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
  1387. pr_debug("ioctl SNDCTL_DSP_GETOSPACE: bytes=%d, fragments=%d\n", abinfo.bytes, abinfo.fragments);
  1388. return copy_to_user((void *) arg, &abinfo,
  1389. sizeof(abinfo)) ? -EFAULT : 0;
  1390. case SNDCTL_DSP_GETISPACE:
  1391. if (!(file->f_mode & FMODE_READ))
  1392. return -EINVAL;
  1393. abinfo.fragsize = s->dma_adc.fragsize;
  1394. spin_lock_irqsave(&s->lock, flags);
  1395. count = s->dma_adc.count;
  1396. count += dma_count_done(&s->dma_adc);
  1397. spin_unlock_irqrestore(&s->lock, flags);
  1398. if (count < 0)
  1399. count = 0;
  1400. abinfo.bytes = count / s->dma_adc.cnt_factor;
  1401. abinfo.fragstotal = s->dma_adc.numfrag;
  1402. abinfo.fragments = abinfo.bytes >> s->dma_adc.fragshift;
  1403. return copy_to_user((void *) arg, &abinfo,
  1404. sizeof(abinfo)) ? -EFAULT : 0;
  1405. case SNDCTL_DSP_NONBLOCK:
  1406. file->f_flags |= O_NONBLOCK;
  1407. return 0;
  1408. case SNDCTL_DSP_GETODELAY:
  1409. if (!(file->f_mode & FMODE_WRITE))
  1410. return -EINVAL;
  1411. spin_lock_irqsave(&s->lock, flags);
  1412. count = s->dma_dac.count;
  1413. count -= dma_count_done(&s->dma_dac);
  1414. spin_unlock_irqrestore(&s->lock, flags);
  1415. if (count < 0)
  1416. count = 0;
  1417. count /= s->dma_dac.cnt_factor;
  1418. return put_user(count, (int *) arg);
  1419. case SNDCTL_DSP_GETIPTR:
  1420. if (!(file->f_mode & FMODE_READ))
  1421. return -EINVAL;
  1422. spin_lock_irqsave(&s->lock, flags);
  1423. cinfo.bytes = s->dma_adc.total_bytes;
  1424. count = s->dma_adc.count;
  1425. if (!s->dma_adc.stopped) {
  1426. diff = dma_count_done(&s->dma_adc);
  1427. count += diff;
  1428. cinfo.bytes += diff;
  1429. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) + diff -
  1430. virt_to_phys(s->dma_adc.rawbuf);
  1431. } else
  1432. cinfo.ptr = virt_to_phys(s->dma_adc.nextIn) -
  1433. virt_to_phys(s->dma_adc.rawbuf);
  1434. if (s->dma_adc.mapped)
  1435. s->dma_adc.count &= (s->dma_adc.dma_fragsize-1);
  1436. spin_unlock_irqrestore(&s->lock, flags);
  1437. if (count < 0)
  1438. count = 0;
  1439. cinfo.blocks = count >> s->dma_adc.fragshift;
  1440. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1441. case SNDCTL_DSP_GETOPTR:
  1442. if (!(file->f_mode & FMODE_READ))
  1443. return -EINVAL;
  1444. spin_lock_irqsave(&s->lock, flags);
  1445. cinfo.bytes = s->dma_dac.total_bytes;
  1446. count = s->dma_dac.count;
  1447. if (!s->dma_dac.stopped) {
  1448. diff = dma_count_done(&s->dma_dac);
  1449. count -= diff;
  1450. cinfo.bytes += diff;
  1451. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) + diff -
  1452. virt_to_phys(s->dma_dac.rawbuf);
  1453. } else
  1454. cinfo.ptr = virt_to_phys(s->dma_dac.nextOut) -
  1455. virt_to_phys(s->dma_dac.rawbuf);
  1456. if (s->dma_dac.mapped)
  1457. s->dma_dac.count &= (s->dma_dac.dma_fragsize-1);
  1458. spin_unlock_irqrestore(&s->lock, flags);
  1459. if (count < 0)
  1460. count = 0;
  1461. cinfo.blocks = count >> s->dma_dac.fragshift;
  1462. return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
  1463. case SNDCTL_DSP_GETBLKSIZE:
  1464. if (file->f_mode & FMODE_WRITE)
  1465. return put_user(s->dma_dac.fragsize, (int *) arg);
  1466. else
  1467. return put_user(s->dma_adc.fragsize, (int *) arg);
  1468. case SNDCTL_DSP_SETFRAGMENT:
  1469. if (get_user(val, (int *) arg))
  1470. return -EFAULT;
  1471. if (file->f_mode & FMODE_READ) {
  1472. stop_adc(s);
  1473. s->dma_adc.ossfragshift = val & 0xffff;
  1474. s->dma_adc.ossmaxfrags = (val >> 16) & 0xffff;
  1475. if (s->dma_adc.ossfragshift < 4)
  1476. s->dma_adc.ossfragshift = 4;
  1477. if (s->dma_adc.ossfragshift > 15)
  1478. s->dma_adc.ossfragshift = 15;
  1479. if (s->dma_adc.ossmaxfrags < 4)
  1480. s->dma_adc.ossmaxfrags = 4;
  1481. if ((ret = prog_dmabuf_adc(s)))
  1482. return ret;
  1483. }
  1484. if (file->f_mode & FMODE_WRITE) {
  1485. stop_dac(s);
  1486. s->dma_dac.ossfragshift = val & 0xffff;
  1487. s->dma_dac.ossmaxfrags = (val >> 16) & 0xffff;
  1488. if (s->dma_dac.ossfragshift < 4)
  1489. s->dma_dac.ossfragshift = 4;
  1490. if (s->dma_dac.ossfragshift > 15)
  1491. s->dma_dac.ossfragshift = 15;
  1492. if (s->dma_dac.ossmaxfrags < 4)
  1493. s->dma_dac.ossmaxfrags = 4;
  1494. if ((ret = prog_dmabuf_dac(s)))
  1495. return ret;
  1496. }
  1497. return 0;
  1498. case SNDCTL_DSP_SUBDIVIDE:
  1499. if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) ||
  1500. (file->f_mode & FMODE_WRITE && s->dma_dac.subdivision))
  1501. return -EINVAL;
  1502. if (get_user(val, (int *) arg))
  1503. return -EFAULT;
  1504. if (val != 1 && val != 2 && val != 4)
  1505. return -EINVAL;
  1506. if (file->f_mode & FMODE_READ) {
  1507. stop_adc(s);
  1508. s->dma_adc.subdivision = val;
  1509. if ((ret = prog_dmabuf_adc(s)))
  1510. return ret;
  1511. }
  1512. if (file->f_mode & FMODE_WRITE) {
  1513. stop_dac(s);
  1514. s->dma_dac.subdivision = val;
  1515. if ((ret = prog_dmabuf_dac(s)))
  1516. return ret;
  1517. }
  1518. return 0;
  1519. case SOUND_PCM_READ_RATE:
  1520. return put_user((file->f_mode & FMODE_READ) ?
  1521. s->dma_adc.sample_rate :
  1522. s->dma_dac.sample_rate,
  1523. (int *)arg);
  1524. case SOUND_PCM_READ_CHANNELS:
  1525. if (file->f_mode & FMODE_READ)
  1526. return put_user(s->dma_adc.num_channels, (int *)arg);
  1527. else
  1528. return put_user(s->dma_dac.num_channels, (int *)arg);
  1529. case SOUND_PCM_READ_BITS:
  1530. if (file->f_mode & FMODE_READ)
  1531. return put_user(s->dma_adc.sample_size, (int *)arg);
  1532. else
  1533. return put_user(s->dma_dac.sample_size, (int *)arg);
  1534. case SOUND_PCM_WRITE_FILTER:
  1535. case SNDCTL_DSP_SETSYNCRO:
  1536. case SOUND_PCM_READ_FILTER:
  1537. return -EINVAL;
  1538. }
  1539. return mixdev_ioctl(s->codec, cmd, arg);
  1540. }
  1541. static int
  1542. au1550_open(struct inode *inode, struct file *file)
  1543. {
  1544. int minor = MINOR(inode->i_rdev);
  1545. DECLARE_WAITQUEUE(wait, current);
  1546. struct au1550_state *s = &au1550_state;
  1547. int ret;
  1548. #ifdef DEBUG
  1549. if (file->f_flags & O_NONBLOCK)
  1550. pr_debug("open: non-blocking\n");
  1551. else
  1552. pr_debug("open: blocking\n");
  1553. #endif
  1554. file->private_data = s;
  1555. /* wait for device to become free */
  1556. mutex_lock(&s->open_mutex);
  1557. while (s->open_mode & file->f_mode) {
  1558. if (file->f_flags & O_NONBLOCK) {
  1559. mutex_unlock(&s->open_mutex);
  1560. return -EBUSY;
  1561. }
  1562. add_wait_queue(&s->open_wait, &wait);
  1563. __set_current_state(TASK_INTERRUPTIBLE);
  1564. mutex_unlock(&s->open_mutex);
  1565. schedule();
  1566. remove_wait_queue(&s->open_wait, &wait);
  1567. set_current_state(TASK_RUNNING);
  1568. if (signal_pending(current))
  1569. return -ERESTARTSYS;
  1570. mutex_lock(&s->open_mutex);
  1571. }
  1572. stop_dac(s);
  1573. stop_adc(s);
  1574. if (file->f_mode & FMODE_READ) {
  1575. s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
  1576. s->dma_adc.subdivision = s->dma_adc.total_bytes = 0;
  1577. s->dma_adc.num_channels = 1;
  1578. s->dma_adc.sample_size = 8;
  1579. set_adc_rate(s, 8000);
  1580. if ((minor & 0xf) == SND_DEV_DSP16)
  1581. s->dma_adc.sample_size = 16;
  1582. }
  1583. if (file->f_mode & FMODE_WRITE) {
  1584. s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
  1585. s->dma_dac.subdivision = s->dma_dac.total_bytes = 0;
  1586. s->dma_dac.num_channels = 1;
  1587. s->dma_dac.sample_size = 8;
  1588. set_dac_rate(s, 8000);
  1589. if ((minor & 0xf) == SND_DEV_DSP16)
  1590. s->dma_dac.sample_size = 16;
  1591. }
  1592. if (file->f_mode & FMODE_READ) {
  1593. if ((ret = prog_dmabuf_adc(s)))
  1594. return ret;
  1595. }
  1596. if (file->f_mode & FMODE_WRITE) {
  1597. if ((ret = prog_dmabuf_dac(s)))
  1598. return ret;
  1599. }
  1600. s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
  1601. mutex_unlock(&s->open_mutex);
  1602. mutex_init(&s->sem);
  1603. return 0;
  1604. }
  1605. static int
  1606. au1550_release(struct inode *inode, struct file *file)
  1607. {
  1608. struct au1550_state *s = (struct au1550_state *)file->private_data;
  1609. lock_kernel();
  1610. if (file->f_mode & FMODE_WRITE) {
  1611. unlock_kernel();
  1612. drain_dac(s, file->f_flags & O_NONBLOCK);
  1613. lock_kernel();
  1614. }
  1615. mutex_lock(&s->open_mutex);
  1616. if (file->f_mode & FMODE_WRITE) {
  1617. stop_dac(s);
  1618. kfree(s->dma_dac.rawbuf);
  1619. s->dma_dac.rawbuf = NULL;
  1620. }
  1621. if (file->f_mode & FMODE_READ) {
  1622. stop_adc(s);
  1623. kfree(s->dma_adc.rawbuf);
  1624. s->dma_adc.rawbuf = NULL;
  1625. }
  1626. s->open_mode &= ((~file->f_mode) & (FMODE_READ|FMODE_WRITE));
  1627. mutex_unlock(&s->open_mutex);
  1628. wake_up(&s->open_wait);
  1629. unlock_kernel();
  1630. return 0;
  1631. }
  1632. static /*const */ struct file_operations au1550_audio_fops = {
  1633. owner: THIS_MODULE,
  1634. llseek: au1550_llseek,
  1635. read: au1550_read,
  1636. write: au1550_write,
  1637. poll: au1550_poll,
  1638. ioctl: au1550_ioctl,
  1639. mmap: au1550_mmap,
  1640. open: au1550_open,
  1641. release: au1550_release,
  1642. };
  1643. MODULE_AUTHOR("Advanced Micro Devices (AMD), dan@embeddededge.com");
  1644. MODULE_DESCRIPTION("Au1550 AC97 Audio Driver");
  1645. MODULE_LICENSE("GPL");
  1646. static int __devinit
  1647. au1550_probe(void)
  1648. {
  1649. struct au1550_state *s = &au1550_state;
  1650. int val;
  1651. memset(s, 0, sizeof(struct au1550_state));
  1652. init_waitqueue_head(&s->dma_adc.wait);
  1653. init_waitqueue_head(&s->dma_dac.wait);
  1654. init_waitqueue_head(&s->open_wait);
  1655. mutex_init(&s->open_mutex);
  1656. spin_lock_init(&s->lock);
  1657. s->codec = ac97_alloc_codec();
  1658. if(s->codec == NULL) {
  1659. err("Out of memory");
  1660. return -1;
  1661. }
  1662. s->codec->private_data = s;
  1663. s->codec->id = 0;
  1664. s->codec->codec_read = rdcodec;
  1665. s->codec->codec_write = wrcodec;
  1666. s->codec->codec_wait = waitcodec;
  1667. if (!request_mem_region(CPHYSADDR(AC97_PSC_SEL),
  1668. 0x30, "Au1550 AC97")) {
  1669. err("AC'97 ports in use");
  1670. }
  1671. /* Allocate the DMA Channels
  1672. */
  1673. if ((s->dma_dac.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_MEM_CHAN,
  1674. DBDMA_AC97_TX_CHAN, dac_dma_interrupt, (void *)s)) == 0) {
  1675. err("Can't get DAC DMA");
  1676. goto err_dma1;
  1677. }
  1678. au1xxx_dbdma_set_devwidth(s->dma_dac.dmanr, 16);
  1679. if (au1xxx_dbdma_ring_alloc(s->dma_dac.dmanr,
  1680. NUM_DBDMA_DESCRIPTORS) == 0) {
  1681. err("Can't get DAC DMA descriptors");
  1682. goto err_dma1;
  1683. }
  1684. if ((s->dma_adc.dmanr = au1xxx_dbdma_chan_alloc(DBDMA_AC97_RX_CHAN,
  1685. DBDMA_MEM_CHAN, adc_dma_interrupt, (void *)s)) == 0) {
  1686. err("Can't get ADC DMA");
  1687. goto err_dma2;
  1688. }
  1689. au1xxx_dbdma_set_devwidth(s->dma_adc.dmanr, 16);
  1690. if (au1xxx_dbdma_ring_alloc(s->dma_adc.dmanr,
  1691. NUM_DBDMA_DESCRIPTORS) == 0) {
  1692. err("Can't get ADC DMA descriptors");
  1693. goto err_dma2;
  1694. }
  1695. pr_info("DAC: DMA%d, ADC: DMA%d", DBDMA_AC97_TX_CHAN, DBDMA_AC97_RX_CHAN);
  1696. /* register devices */
  1697. if ((s->dev_audio = register_sound_dsp(&au1550_audio_fops, -1)) < 0)
  1698. goto err_dev1;
  1699. if ((s->codec->dev_mixer =
  1700. register_sound_mixer(&au1550_mixer_fops, -1)) < 0)
  1701. goto err_dev2;
  1702. /* The GPIO for the appropriate PSC was configured by the
  1703. * board specific start up.
  1704. *
  1705. * configure PSC for AC'97
  1706. */
  1707. au_writel(0, AC97_PSC_CTRL); /* Disable PSC */
  1708. au_sync();
  1709. au_writel((PSC_SEL_CLK_SERCLK | PSC_SEL_PS_AC97MODE), AC97_PSC_SEL);
  1710. au_sync();
  1711. /* cold reset the AC'97
  1712. */
  1713. au_writel(PSC_AC97RST_RST, PSC_AC97RST);
  1714. au_sync();
  1715. au1550_delay(10);
  1716. au_writel(0, PSC_AC97RST);
  1717. au_sync();
  1718. /* need to delay around 500msec(bleech) to give
  1719. some CODECs enough time to wakeup */
  1720. au1550_delay(500);
  1721. /* warm reset the AC'97 to start the bitclk
  1722. */
  1723. au_writel(PSC_AC97RST_SNC, PSC_AC97RST);
  1724. au_sync();
  1725. udelay(100);
  1726. au_writel(0, PSC_AC97RST);
  1727. au_sync();
  1728. /* Enable PSC
  1729. */
  1730. au_writel(PSC_CTRL_ENABLE, AC97_PSC_CTRL);
  1731. au_sync();
  1732. /* Wait for PSC ready.
  1733. */
  1734. do {
  1735. val = au_readl(PSC_AC97STAT);
  1736. au_sync();
  1737. } while ((val & PSC_AC97STAT_SR) == 0);
  1738. /* Configure AC97 controller.
  1739. * Deep FIFO, 16-bit sample, DMA, make sure DMA matches fifo size.
  1740. */
  1741. val = PSC_AC97CFG_SET_LEN(16);
  1742. val |= PSC_AC97CFG_RT_FIFO8 | PSC_AC97CFG_TT_FIFO8;
  1743. /* Enable device so we can at least
  1744. * talk over the AC-link.
  1745. */
  1746. au_writel(val, PSC_AC97CFG);
  1747. au_writel(PSC_AC97MSK_ALLMASK, PSC_AC97MSK);
  1748. au_sync();
  1749. val |= PSC_AC97CFG_DE_ENABLE;
  1750. au_writel(val, PSC_AC97CFG);
  1751. au_sync();
  1752. /* Wait for Device ready.
  1753. */
  1754. do {
  1755. val = au_readl(PSC_AC97STAT);
  1756. au_sync();
  1757. } while ((val & PSC_AC97STAT_DR) == 0);
  1758. /* codec init */
  1759. if (!ac97_probe_codec(s->codec))
  1760. goto err_dev3;
  1761. s->codec_base_caps = rdcodec(s->codec, AC97_RESET);
  1762. s->codec_ext_caps = rdcodec(s->codec, AC97_EXTENDED_ID);
  1763. pr_info("AC'97 Base/Extended ID = %04x/%04x",
  1764. s->codec_base_caps, s->codec_ext_caps);
  1765. if (!(s->codec_ext_caps & AC97_EXTID_VRA)) {
  1766. /* codec does not support VRA
  1767. */
  1768. s->no_vra = 1;
  1769. } else if (!vra) {
  1770. /* Boot option says disable VRA
  1771. */
  1772. u16 ac97_extstat = rdcodec(s->codec, AC97_EXTENDED_STATUS);
  1773. wrcodec(s->codec, AC97_EXTENDED_STATUS,
  1774. ac97_extstat & ~AC97_EXTSTAT_VRA);
  1775. s->no_vra = 1;
  1776. }
  1777. if (s->no_vra)
  1778. pr_info("no VRA, interpolating and decimating");
  1779. /* set mic to be the recording source */
  1780. val = SOUND_MASK_MIC;
  1781. mixdev_ioctl(s->codec, SOUND_MIXER_WRITE_RECSRC,
  1782. (unsigned long) &val);
  1783. return 0;
  1784. err_dev3:
  1785. unregister_sound_mixer(s->codec->dev_mixer);
  1786. err_dev2:
  1787. unregister_sound_dsp(s->dev_audio);
  1788. err_dev1:
  1789. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1790. err_dma2:
  1791. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1792. err_dma1:
  1793. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1794. ac97_release_codec(s->codec);
  1795. return -1;
  1796. }
  1797. static void __devinit
  1798. au1550_remove(void)
  1799. {
  1800. struct au1550_state *s = &au1550_state;
  1801. if (!s)
  1802. return;
  1803. synchronize_irq();
  1804. au1xxx_dbdma_chan_free(s->dma_adc.dmanr);
  1805. au1xxx_dbdma_chan_free(s->dma_dac.dmanr);
  1806. release_mem_region(CPHYSADDR(AC97_PSC_SEL), 0x30);
  1807. unregister_sound_dsp(s->dev_audio);
  1808. unregister_sound_mixer(s->codec->dev_mixer);
  1809. ac97_release_codec(s->codec);
  1810. }
  1811. static int __init
  1812. init_au1550(void)
  1813. {
  1814. return au1550_probe();
  1815. }
  1816. static void __exit
  1817. cleanup_au1550(void)
  1818. {
  1819. au1550_remove();
  1820. }
  1821. module_init(init_au1550);
  1822. module_exit(cleanup_au1550);
  1823. #ifndef MODULE
  1824. static int __init
  1825. au1550_setup(char *options)
  1826. {
  1827. char *this_opt;
  1828. if (!options || !*options)
  1829. return 0;
  1830. while ((this_opt = strsep(&options, ","))) {
  1831. if (!*this_opt)
  1832. continue;
  1833. if (!strncmp(this_opt, "vra", 3)) {
  1834. vra = 1;
  1835. }
  1836. }
  1837. return 1;
  1838. }
  1839. __setup("au1550_audio=", au1550_setup);
  1840. #endif /* MODULE */