emu8000.c 36 KB

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  1. /*
  2. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  3. * and (c) 1999 Steve Ratcliffe <steve@parabola.demon.co.uk>
  4. * Copyright (C) 1999-2000 Takashi Iwai <tiwai@suse.de>
  5. *
  6. * Routines for control of EMU8000 chip
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <sound/driver.h>
  23. #include <linux/wait.h>
  24. #include <linux/sched.h>
  25. #include <linux/slab.h>
  26. #include <linux/ioport.h>
  27. #include <linux/delay.h>
  28. #include <sound/core.h>
  29. #include <sound/emu8000.h>
  30. #include <sound/emu8000_reg.h>
  31. #include <asm/io.h>
  32. #include <asm/uaccess.h>
  33. #include <linux/init.h>
  34. #include <sound/control.h>
  35. #include <sound/initval.h>
  36. /*
  37. * emu8000 register controls
  38. */
  39. /*
  40. * The following routines read and write registers on the emu8000. They
  41. * should always be called via the EMU8000*READ/WRITE macros and never
  42. * directly. The macros handle the port number and command word.
  43. */
  44. /* Write a word */
  45. void snd_emu8000_poke(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val)
  46. {
  47. unsigned long flags;
  48. spin_lock_irqsave(&emu->reg_lock, flags);
  49. if (reg != emu->last_reg) {
  50. outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */
  51. emu->last_reg = reg;
  52. }
  53. outw((unsigned short)val, port); /* Send data */
  54. spin_unlock_irqrestore(&emu->reg_lock, flags);
  55. }
  56. /* Read a word */
  57. unsigned short snd_emu8000_peek(struct snd_emu8000 *emu, unsigned int port, unsigned int reg)
  58. {
  59. unsigned short res;
  60. unsigned long flags;
  61. spin_lock_irqsave(&emu->reg_lock, flags);
  62. if (reg != emu->last_reg) {
  63. outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */
  64. emu->last_reg = reg;
  65. }
  66. res = inw(port); /* Read data */
  67. spin_unlock_irqrestore(&emu->reg_lock, flags);
  68. return res;
  69. }
  70. /* Write a double word */
  71. void snd_emu8000_poke_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg, unsigned int val)
  72. {
  73. unsigned long flags;
  74. spin_lock_irqsave(&emu->reg_lock, flags);
  75. if (reg != emu->last_reg) {
  76. outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */
  77. emu->last_reg = reg;
  78. }
  79. outw((unsigned short)val, port); /* Send low word of data */
  80. outw((unsigned short)(val>>16), port+2); /* Send high word of data */
  81. spin_unlock_irqrestore(&emu->reg_lock, flags);
  82. }
  83. /* Read a double word */
  84. unsigned int snd_emu8000_peek_dw(struct snd_emu8000 *emu, unsigned int port, unsigned int reg)
  85. {
  86. unsigned short low;
  87. unsigned int res;
  88. unsigned long flags;
  89. spin_lock_irqsave(&emu->reg_lock, flags);
  90. if (reg != emu->last_reg) {
  91. outw((unsigned short)reg, EMU8000_PTR(emu)); /* Set register */
  92. emu->last_reg = reg;
  93. }
  94. low = inw(port); /* Read low word of data */
  95. res = low + (inw(port+2) << 16);
  96. spin_unlock_irqrestore(&emu->reg_lock, flags);
  97. return res;
  98. }
  99. /*
  100. * Set up / close a channel to be used for DMA.
  101. */
  102. /*exported*/ void
  103. snd_emu8000_dma_chan(struct snd_emu8000 *emu, int ch, int mode)
  104. {
  105. unsigned right_bit = (mode & EMU8000_RAM_RIGHT) ? 0x01000000 : 0;
  106. mode &= EMU8000_RAM_MODE_MASK;
  107. if (mode == EMU8000_RAM_CLOSE) {
  108. EMU8000_CCCA_WRITE(emu, ch, 0);
  109. EMU8000_DCYSUSV_WRITE(emu, ch, 0x807F);
  110. return;
  111. }
  112. EMU8000_DCYSUSV_WRITE(emu, ch, 0x80);
  113. EMU8000_VTFT_WRITE(emu, ch, 0);
  114. EMU8000_CVCF_WRITE(emu, ch, 0);
  115. EMU8000_PTRX_WRITE(emu, ch, 0x40000000);
  116. EMU8000_CPF_WRITE(emu, ch, 0x40000000);
  117. EMU8000_PSST_WRITE(emu, ch, 0);
  118. EMU8000_CSL_WRITE(emu, ch, 0);
  119. if (mode == EMU8000_RAM_WRITE) /* DMA write */
  120. EMU8000_CCCA_WRITE(emu, ch, 0x06000000 | right_bit);
  121. else /* DMA read */
  122. EMU8000_CCCA_WRITE(emu, ch, 0x04000000 | right_bit);
  123. }
  124. /*
  125. */
  126. static void __devinit
  127. snd_emu8000_read_wait(struct snd_emu8000 *emu)
  128. {
  129. while ((EMU8000_SMALR_READ(emu) & 0x80000000) != 0) {
  130. schedule_timeout_interruptible(1);
  131. if (signal_pending(current))
  132. break;
  133. }
  134. }
  135. /*
  136. */
  137. static void __devinit
  138. snd_emu8000_write_wait(struct snd_emu8000 *emu)
  139. {
  140. while ((EMU8000_SMALW_READ(emu) & 0x80000000) != 0) {
  141. schedule_timeout_interruptible(1);
  142. if (signal_pending(current))
  143. break;
  144. }
  145. }
  146. /*
  147. * detect a card at the given port
  148. */
  149. static int __devinit
  150. snd_emu8000_detect(struct snd_emu8000 *emu)
  151. {
  152. /* Initialise */
  153. EMU8000_HWCF1_WRITE(emu, 0x0059);
  154. EMU8000_HWCF2_WRITE(emu, 0x0020);
  155. EMU8000_HWCF3_WRITE(emu, 0x0000);
  156. /* Check for a recognisable emu8000 */
  157. /*
  158. if ((EMU8000_U1_READ(emu) & 0x000f) != 0x000c)
  159. return -ENODEV;
  160. */
  161. if ((EMU8000_HWCF1_READ(emu) & 0x007e) != 0x0058)
  162. return -ENODEV;
  163. if ((EMU8000_HWCF2_READ(emu) & 0x0003) != 0x0003)
  164. return -ENODEV;
  165. snd_printdd("EMU8000 [0x%lx]: Synth chip found\n",
  166. emu->port1);
  167. return 0;
  168. }
  169. /*
  170. * intiailize audio channels
  171. */
  172. static void __devinit
  173. init_audio(struct snd_emu8000 *emu)
  174. {
  175. int ch;
  176. /* turn off envelope engines */
  177. for (ch = 0; ch < EMU8000_CHANNELS; ch++)
  178. EMU8000_DCYSUSV_WRITE(emu, ch, 0x80);
  179. /* reset all other parameters to zero */
  180. for (ch = 0; ch < EMU8000_CHANNELS; ch++) {
  181. EMU8000_ENVVOL_WRITE(emu, ch, 0);
  182. EMU8000_ENVVAL_WRITE(emu, ch, 0);
  183. EMU8000_DCYSUS_WRITE(emu, ch, 0);
  184. EMU8000_ATKHLDV_WRITE(emu, ch, 0);
  185. EMU8000_LFO1VAL_WRITE(emu, ch, 0);
  186. EMU8000_ATKHLD_WRITE(emu, ch, 0);
  187. EMU8000_LFO2VAL_WRITE(emu, ch, 0);
  188. EMU8000_IP_WRITE(emu, ch, 0);
  189. EMU8000_IFATN_WRITE(emu, ch, 0);
  190. EMU8000_PEFE_WRITE(emu, ch, 0);
  191. EMU8000_FMMOD_WRITE(emu, ch, 0);
  192. EMU8000_TREMFRQ_WRITE(emu, ch, 0);
  193. EMU8000_FM2FRQ2_WRITE(emu, ch, 0);
  194. EMU8000_PTRX_WRITE(emu, ch, 0);
  195. EMU8000_VTFT_WRITE(emu, ch, 0);
  196. EMU8000_PSST_WRITE(emu, ch, 0);
  197. EMU8000_CSL_WRITE(emu, ch, 0);
  198. EMU8000_CCCA_WRITE(emu, ch, 0);
  199. }
  200. for (ch = 0; ch < EMU8000_CHANNELS; ch++) {
  201. EMU8000_CPF_WRITE(emu, ch, 0);
  202. EMU8000_CVCF_WRITE(emu, ch, 0);
  203. }
  204. }
  205. /*
  206. * initialize DMA address
  207. */
  208. static void __devinit
  209. init_dma(struct snd_emu8000 *emu)
  210. {
  211. EMU8000_SMALR_WRITE(emu, 0);
  212. EMU8000_SMARR_WRITE(emu, 0);
  213. EMU8000_SMALW_WRITE(emu, 0);
  214. EMU8000_SMARW_WRITE(emu, 0);
  215. }
  216. /*
  217. * initialization arrays; from ADIP
  218. */
  219. static unsigned short init1[128] /*__devinitdata*/ = {
  220. 0x03ff, 0x0030, 0x07ff, 0x0130, 0x0bff, 0x0230, 0x0fff, 0x0330,
  221. 0x13ff, 0x0430, 0x17ff, 0x0530, 0x1bff, 0x0630, 0x1fff, 0x0730,
  222. 0x23ff, 0x0830, 0x27ff, 0x0930, 0x2bff, 0x0a30, 0x2fff, 0x0b30,
  223. 0x33ff, 0x0c30, 0x37ff, 0x0d30, 0x3bff, 0x0e30, 0x3fff, 0x0f30,
  224. 0x43ff, 0x0030, 0x47ff, 0x0130, 0x4bff, 0x0230, 0x4fff, 0x0330,
  225. 0x53ff, 0x0430, 0x57ff, 0x0530, 0x5bff, 0x0630, 0x5fff, 0x0730,
  226. 0x63ff, 0x0830, 0x67ff, 0x0930, 0x6bff, 0x0a30, 0x6fff, 0x0b30,
  227. 0x73ff, 0x0c30, 0x77ff, 0x0d30, 0x7bff, 0x0e30, 0x7fff, 0x0f30,
  228. 0x83ff, 0x0030, 0x87ff, 0x0130, 0x8bff, 0x0230, 0x8fff, 0x0330,
  229. 0x93ff, 0x0430, 0x97ff, 0x0530, 0x9bff, 0x0630, 0x9fff, 0x0730,
  230. 0xa3ff, 0x0830, 0xa7ff, 0x0930, 0xabff, 0x0a30, 0xafff, 0x0b30,
  231. 0xb3ff, 0x0c30, 0xb7ff, 0x0d30, 0xbbff, 0x0e30, 0xbfff, 0x0f30,
  232. 0xc3ff, 0x0030, 0xc7ff, 0x0130, 0xcbff, 0x0230, 0xcfff, 0x0330,
  233. 0xd3ff, 0x0430, 0xd7ff, 0x0530, 0xdbff, 0x0630, 0xdfff, 0x0730,
  234. 0xe3ff, 0x0830, 0xe7ff, 0x0930, 0xebff, 0x0a30, 0xefff, 0x0b30,
  235. 0xf3ff, 0x0c30, 0xf7ff, 0x0d30, 0xfbff, 0x0e30, 0xffff, 0x0f30,
  236. };
  237. static unsigned short init2[128] /*__devinitdata*/ = {
  238. 0x03ff, 0x8030, 0x07ff, 0x8130, 0x0bff, 0x8230, 0x0fff, 0x8330,
  239. 0x13ff, 0x8430, 0x17ff, 0x8530, 0x1bff, 0x8630, 0x1fff, 0x8730,
  240. 0x23ff, 0x8830, 0x27ff, 0x8930, 0x2bff, 0x8a30, 0x2fff, 0x8b30,
  241. 0x33ff, 0x8c30, 0x37ff, 0x8d30, 0x3bff, 0x8e30, 0x3fff, 0x8f30,
  242. 0x43ff, 0x8030, 0x47ff, 0x8130, 0x4bff, 0x8230, 0x4fff, 0x8330,
  243. 0x53ff, 0x8430, 0x57ff, 0x8530, 0x5bff, 0x8630, 0x5fff, 0x8730,
  244. 0x63ff, 0x8830, 0x67ff, 0x8930, 0x6bff, 0x8a30, 0x6fff, 0x8b30,
  245. 0x73ff, 0x8c30, 0x77ff, 0x8d30, 0x7bff, 0x8e30, 0x7fff, 0x8f30,
  246. 0x83ff, 0x8030, 0x87ff, 0x8130, 0x8bff, 0x8230, 0x8fff, 0x8330,
  247. 0x93ff, 0x8430, 0x97ff, 0x8530, 0x9bff, 0x8630, 0x9fff, 0x8730,
  248. 0xa3ff, 0x8830, 0xa7ff, 0x8930, 0xabff, 0x8a30, 0xafff, 0x8b30,
  249. 0xb3ff, 0x8c30, 0xb7ff, 0x8d30, 0xbbff, 0x8e30, 0xbfff, 0x8f30,
  250. 0xc3ff, 0x8030, 0xc7ff, 0x8130, 0xcbff, 0x8230, 0xcfff, 0x8330,
  251. 0xd3ff, 0x8430, 0xd7ff, 0x8530, 0xdbff, 0x8630, 0xdfff, 0x8730,
  252. 0xe3ff, 0x8830, 0xe7ff, 0x8930, 0xebff, 0x8a30, 0xefff, 0x8b30,
  253. 0xf3ff, 0x8c30, 0xf7ff, 0x8d30, 0xfbff, 0x8e30, 0xffff, 0x8f30,
  254. };
  255. static unsigned short init3[128] /*__devinitdata*/ = {
  256. 0x0C10, 0x8470, 0x14FE, 0xB488, 0x167F, 0xA470, 0x18E7, 0x84B5,
  257. 0x1B6E, 0x842A, 0x1F1D, 0x852A, 0x0DA3, 0x8F7C, 0x167E, 0xF254,
  258. 0x0000, 0x842A, 0x0001, 0x852A, 0x18E6, 0x8BAA, 0x1B6D, 0xF234,
  259. 0x229F, 0x8429, 0x2746, 0x8529, 0x1F1C, 0x86E7, 0x229E, 0xF224,
  260. 0x0DA4, 0x8429, 0x2C29, 0x8529, 0x2745, 0x87F6, 0x2C28, 0xF254,
  261. 0x383B, 0x8428, 0x320F, 0x8528, 0x320E, 0x8F02, 0x1341, 0xF264,
  262. 0x3EB6, 0x8428, 0x3EB9, 0x8528, 0x383A, 0x8FA9, 0x3EB5, 0xF294,
  263. 0x3EB7, 0x8474, 0x3EBA, 0x8575, 0x3EB8, 0xC4C3, 0x3EBB, 0xC5C3,
  264. 0x0000, 0xA404, 0x0001, 0xA504, 0x141F, 0x8671, 0x14FD, 0x8287,
  265. 0x3EBC, 0xE610, 0x3EC8, 0x8C7B, 0x031A, 0x87E6, 0x3EC8, 0x86F7,
  266. 0x3EC0, 0x821E, 0x3EBE, 0xD208, 0x3EBD, 0x821F, 0x3ECA, 0x8386,
  267. 0x3EC1, 0x8C03, 0x3EC9, 0x831E, 0x3ECA, 0x8C4C, 0x3EBF, 0x8C55,
  268. 0x3EC9, 0xC208, 0x3EC4, 0xBC84, 0x3EC8, 0x8EAD, 0x3EC8, 0xD308,
  269. 0x3EC2, 0x8F7E, 0x3ECB, 0x8219, 0x3ECB, 0xD26E, 0x3EC5, 0x831F,
  270. 0x3EC6, 0xC308, 0x3EC3, 0xB2FF, 0x3EC9, 0x8265, 0x3EC9, 0x8319,
  271. 0x1342, 0xD36E, 0x3EC7, 0xB3FF, 0x0000, 0x8365, 0x1420, 0x9570,
  272. };
  273. static unsigned short init4[128] /*__devinitdata*/ = {
  274. 0x0C10, 0x8470, 0x14FE, 0xB488, 0x167F, 0xA470, 0x18E7, 0x84B5,
  275. 0x1B6E, 0x842A, 0x1F1D, 0x852A, 0x0DA3, 0x0F7C, 0x167E, 0x7254,
  276. 0x0000, 0x842A, 0x0001, 0x852A, 0x18E6, 0x0BAA, 0x1B6D, 0x7234,
  277. 0x229F, 0x8429, 0x2746, 0x8529, 0x1F1C, 0x06E7, 0x229E, 0x7224,
  278. 0x0DA4, 0x8429, 0x2C29, 0x8529, 0x2745, 0x07F6, 0x2C28, 0x7254,
  279. 0x383B, 0x8428, 0x320F, 0x8528, 0x320E, 0x0F02, 0x1341, 0x7264,
  280. 0x3EB6, 0x8428, 0x3EB9, 0x8528, 0x383A, 0x0FA9, 0x3EB5, 0x7294,
  281. 0x3EB7, 0x8474, 0x3EBA, 0x8575, 0x3EB8, 0x44C3, 0x3EBB, 0x45C3,
  282. 0x0000, 0xA404, 0x0001, 0xA504, 0x141F, 0x0671, 0x14FD, 0x0287,
  283. 0x3EBC, 0xE610, 0x3EC8, 0x0C7B, 0x031A, 0x07E6, 0x3EC8, 0x86F7,
  284. 0x3EC0, 0x821E, 0x3EBE, 0xD208, 0x3EBD, 0x021F, 0x3ECA, 0x0386,
  285. 0x3EC1, 0x0C03, 0x3EC9, 0x031E, 0x3ECA, 0x8C4C, 0x3EBF, 0x0C55,
  286. 0x3EC9, 0xC208, 0x3EC4, 0xBC84, 0x3EC8, 0x0EAD, 0x3EC8, 0xD308,
  287. 0x3EC2, 0x8F7E, 0x3ECB, 0x0219, 0x3ECB, 0xD26E, 0x3EC5, 0x031F,
  288. 0x3EC6, 0xC308, 0x3EC3, 0x32FF, 0x3EC9, 0x0265, 0x3EC9, 0x8319,
  289. 0x1342, 0xD36E, 0x3EC7, 0x33FF, 0x0000, 0x8365, 0x1420, 0x9570,
  290. };
  291. /* send an initialization array
  292. * Taken from the oss driver, not obvious from the doc how this
  293. * is meant to work
  294. */
  295. static void __devinit
  296. send_array(struct snd_emu8000 *emu, unsigned short *data, int size)
  297. {
  298. int i;
  299. unsigned short *p;
  300. p = data;
  301. for (i = 0; i < size; i++, p++)
  302. EMU8000_INIT1_WRITE(emu, i, *p);
  303. for (i = 0; i < size; i++, p++)
  304. EMU8000_INIT2_WRITE(emu, i, *p);
  305. for (i = 0; i < size; i++, p++)
  306. EMU8000_INIT3_WRITE(emu, i, *p);
  307. for (i = 0; i < size; i++, p++)
  308. EMU8000_INIT4_WRITE(emu, i, *p);
  309. }
  310. /*
  311. * Send initialization arrays to start up, this just follows the
  312. * initialisation sequence in the adip.
  313. */
  314. static void __devinit
  315. init_arrays(struct snd_emu8000 *emu)
  316. {
  317. send_array(emu, init1, ARRAY_SIZE(init1)/4);
  318. msleep((1024 * 1000) / 44100); /* wait for 1024 clocks */
  319. send_array(emu, init2, ARRAY_SIZE(init2)/4);
  320. send_array(emu, init3, ARRAY_SIZE(init3)/4);
  321. EMU8000_HWCF4_WRITE(emu, 0);
  322. EMU8000_HWCF5_WRITE(emu, 0x83);
  323. EMU8000_HWCF6_WRITE(emu, 0x8000);
  324. send_array(emu, init4, ARRAY_SIZE(init4)/4);
  325. }
  326. #define UNIQUE_ID1 0xa5b9
  327. #define UNIQUE_ID2 0x9d53
  328. /*
  329. * Size the onboard memory.
  330. * This is written so as not to need arbitary delays after the write. It
  331. * seems that the only way to do this is to use the one channel and keep
  332. * reallocating between read and write.
  333. */
  334. static void __devinit
  335. size_dram(struct snd_emu8000 *emu)
  336. {
  337. int i, size;
  338. if (emu->dram_checked)
  339. return;
  340. size = 0;
  341. /* write out a magic number */
  342. snd_emu8000_dma_chan(emu, 0, EMU8000_RAM_WRITE);
  343. snd_emu8000_dma_chan(emu, 1, EMU8000_RAM_READ);
  344. EMU8000_SMALW_WRITE(emu, EMU8000_DRAM_OFFSET);
  345. EMU8000_SMLD_WRITE(emu, UNIQUE_ID1);
  346. snd_emu8000_init_fm(emu); /* This must really be here and not 2 lines back even */
  347. while (size < EMU8000_MAX_DRAM) {
  348. size += 512 * 1024; /* increment 512kbytes */
  349. /* Write a unique data on the test address.
  350. * if the address is out of range, the data is written on
  351. * 0x200000(=EMU8000_DRAM_OFFSET). Then the id word is
  352. * changed by this data.
  353. */
  354. /*snd_emu8000_dma_chan(emu, 0, EMU8000_RAM_WRITE);*/
  355. EMU8000_SMALW_WRITE(emu, EMU8000_DRAM_OFFSET + (size>>1));
  356. EMU8000_SMLD_WRITE(emu, UNIQUE_ID2);
  357. snd_emu8000_write_wait(emu);
  358. /*
  359. * read the data on the just written DRAM address
  360. * if not the same then we have reached the end of ram.
  361. */
  362. /*snd_emu8000_dma_chan(emu, 0, EMU8000_RAM_READ);*/
  363. EMU8000_SMALR_WRITE(emu, EMU8000_DRAM_OFFSET + (size>>1));
  364. /*snd_emu8000_read_wait(emu);*/
  365. EMU8000_SMLD_READ(emu); /* discard stale data */
  366. if (EMU8000_SMLD_READ(emu) != UNIQUE_ID2)
  367. break; /* we must have wrapped around */
  368. snd_emu8000_read_wait(emu);
  369. /*
  370. * If it is the same it could be that the address just
  371. * wraps back to the beginning; so check to see if the
  372. * initial value has been overwritten.
  373. */
  374. EMU8000_SMALR_WRITE(emu, EMU8000_DRAM_OFFSET);
  375. EMU8000_SMLD_READ(emu); /* discard stale data */
  376. if (EMU8000_SMLD_READ(emu) != UNIQUE_ID1)
  377. break; /* we must have wrapped around */
  378. snd_emu8000_read_wait(emu);
  379. }
  380. /* wait until FULL bit in SMAxW register is false */
  381. for (i = 0; i < 10000; i++) {
  382. if ((EMU8000_SMALW_READ(emu) & 0x80000000) == 0)
  383. break;
  384. schedule_timeout_interruptible(1);
  385. if (signal_pending(current))
  386. break;
  387. }
  388. snd_emu8000_dma_chan(emu, 0, EMU8000_RAM_CLOSE);
  389. snd_emu8000_dma_chan(emu, 1, EMU8000_RAM_CLOSE);
  390. snd_printdd("EMU8000 [0x%lx]: %d Kb on-board memory detected\n",
  391. emu->port1, size/1024);
  392. emu->mem_size = size;
  393. emu->dram_checked = 1;
  394. }
  395. /*
  396. * Initiailise the FM section. You have to do this to use sample RAM
  397. * and therefore lose 2 voices.
  398. */
  399. /*exported*/ void
  400. snd_emu8000_init_fm(struct snd_emu8000 *emu)
  401. {
  402. unsigned long flags;
  403. /* Initialize the last two channels for DRAM refresh and producing
  404. the reverb and chorus effects for Yamaha OPL-3 synthesizer */
  405. /* 31: FM left channel, 0xffffe0-0xffffe8 */
  406. EMU8000_DCYSUSV_WRITE(emu, 30, 0x80);
  407. EMU8000_PSST_WRITE(emu, 30, 0xFFFFFFE0); /* full left */
  408. EMU8000_CSL_WRITE(emu, 30, 0x00FFFFE8 | (emu->fm_chorus_depth << 24));
  409. EMU8000_PTRX_WRITE(emu, 30, (emu->fm_reverb_depth << 8));
  410. EMU8000_CPF_WRITE(emu, 30, 0);
  411. EMU8000_CCCA_WRITE(emu, 30, 0x00FFFFE3);
  412. /* 32: FM right channel, 0xfffff0-0xfffff8 */
  413. EMU8000_DCYSUSV_WRITE(emu, 31, 0x80);
  414. EMU8000_PSST_WRITE(emu, 31, 0x00FFFFF0); /* full right */
  415. EMU8000_CSL_WRITE(emu, 31, 0x00FFFFF8 | (emu->fm_chorus_depth << 24));
  416. EMU8000_PTRX_WRITE(emu, 31, (emu->fm_reverb_depth << 8));
  417. EMU8000_CPF_WRITE(emu, 31, 0x8000);
  418. EMU8000_CCCA_WRITE(emu, 31, 0x00FFFFF3);
  419. snd_emu8000_poke((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (30)), 0);
  420. spin_lock_irqsave(&emu->reg_lock, flags);
  421. while (!(inw(EMU8000_PTR(emu)) & 0x1000))
  422. ;
  423. while ((inw(EMU8000_PTR(emu)) & 0x1000))
  424. ;
  425. spin_unlock_irqrestore(&emu->reg_lock, flags);
  426. snd_emu8000_poke((emu), EMU8000_DATA0(emu), EMU8000_CMD(1, (30)), 0x4828);
  427. /* this is really odd part.. */
  428. outb(0x3C, EMU8000_PTR(emu));
  429. outb(0, EMU8000_DATA1(emu));
  430. /* skew volume & cutoff */
  431. EMU8000_VTFT_WRITE(emu, 30, 0x8000FFFF);
  432. EMU8000_VTFT_WRITE(emu, 31, 0x8000FFFF);
  433. }
  434. /*
  435. * The main initialization routine.
  436. */
  437. static void __devinit
  438. snd_emu8000_init_hw(struct snd_emu8000 *emu)
  439. {
  440. int i;
  441. emu->last_reg = 0xffff; /* reset the last register index */
  442. /* initialize hardware configuration */
  443. EMU8000_HWCF1_WRITE(emu, 0x0059);
  444. EMU8000_HWCF2_WRITE(emu, 0x0020);
  445. /* disable audio; this seems to reduce a clicking noise a bit.. */
  446. EMU8000_HWCF3_WRITE(emu, 0);
  447. /* initialize audio channels */
  448. init_audio(emu);
  449. /* initialize DMA */
  450. init_dma(emu);
  451. /* initialize init arrays */
  452. init_arrays(emu);
  453. /*
  454. * Initialize the FM section of the AWE32, this is needed
  455. * for DRAM refresh as well
  456. */
  457. snd_emu8000_init_fm(emu);
  458. /* terminate all voices */
  459. for (i = 0; i < EMU8000_DRAM_VOICES; i++)
  460. EMU8000_DCYSUSV_WRITE(emu, 0, 0x807F);
  461. /* check DRAM memory size */
  462. size_dram(emu);
  463. /* enable audio */
  464. EMU8000_HWCF3_WRITE(emu, 0x4);
  465. /* set equzlier, chorus and reverb modes */
  466. snd_emu8000_update_equalizer(emu);
  467. snd_emu8000_update_chorus_mode(emu);
  468. snd_emu8000_update_reverb_mode(emu);
  469. }
  470. /*----------------------------------------------------------------
  471. * Bass/Treble Equalizer
  472. *----------------------------------------------------------------*/
  473. static unsigned short bass_parm[12][3] = {
  474. {0xD26A, 0xD36A, 0x0000}, /* -12 dB */
  475. {0xD25B, 0xD35B, 0x0000}, /* -8 */
  476. {0xD24C, 0xD34C, 0x0000}, /* -6 */
  477. {0xD23D, 0xD33D, 0x0000}, /* -4 */
  478. {0xD21F, 0xD31F, 0x0000}, /* -2 */
  479. {0xC208, 0xC308, 0x0001}, /* 0 (HW default) */
  480. {0xC219, 0xC319, 0x0001}, /* +2 */
  481. {0xC22A, 0xC32A, 0x0001}, /* +4 */
  482. {0xC24C, 0xC34C, 0x0001}, /* +6 */
  483. {0xC26E, 0xC36E, 0x0001}, /* +8 */
  484. {0xC248, 0xC384, 0x0002}, /* +10 */
  485. {0xC26A, 0xC36A, 0x0002}, /* +12 dB */
  486. };
  487. static unsigned short treble_parm[12][9] = {
  488. {0x821E, 0xC26A, 0x031E, 0xC36A, 0x021E, 0xD208, 0x831E, 0xD308, 0x0001}, /* -12 dB */
  489. {0x821E, 0xC25B, 0x031E, 0xC35B, 0x021E, 0xD208, 0x831E, 0xD308, 0x0001},
  490. {0x821E, 0xC24C, 0x031E, 0xC34C, 0x021E, 0xD208, 0x831E, 0xD308, 0x0001},
  491. {0x821E, 0xC23D, 0x031E, 0xC33D, 0x021E, 0xD208, 0x831E, 0xD308, 0x0001},
  492. {0x821E, 0xC21F, 0x031E, 0xC31F, 0x021E, 0xD208, 0x831E, 0xD308, 0x0001},
  493. {0x821E, 0xD208, 0x031E, 0xD308, 0x021E, 0xD208, 0x831E, 0xD308, 0x0002},
  494. {0x821E, 0xD208, 0x031E, 0xD308, 0x021D, 0xD219, 0x831D, 0xD319, 0x0002},
  495. {0x821E, 0xD208, 0x031E, 0xD308, 0x021C, 0xD22A, 0x831C, 0xD32A, 0x0002},
  496. {0x821E, 0xD208, 0x031E, 0xD308, 0x021A, 0xD24C, 0x831A, 0xD34C, 0x0002},
  497. {0x821E, 0xD208, 0x031E, 0xD308, 0x0219, 0xD26E, 0x8319, 0xD36E, 0x0002}, /* +8 (HW default) */
  498. {0x821D, 0xD219, 0x031D, 0xD319, 0x0219, 0xD26E, 0x8319, 0xD36E, 0x0002},
  499. {0x821C, 0xD22A, 0x031C, 0xD32A, 0x0219, 0xD26E, 0x8319, 0xD36E, 0x0002} /* +12 dB */
  500. };
  501. /*
  502. * set Emu8000 digital equalizer; from 0 to 11 [-12dB - 12dB]
  503. */
  504. /*exported*/ void
  505. snd_emu8000_update_equalizer(struct snd_emu8000 *emu)
  506. {
  507. unsigned short w;
  508. int bass = emu->bass_level;
  509. int treble = emu->treble_level;
  510. if (bass < 0 || bass > 11 || treble < 0 || treble > 11)
  511. return;
  512. EMU8000_INIT4_WRITE(emu, 0x01, bass_parm[bass][0]);
  513. EMU8000_INIT4_WRITE(emu, 0x11, bass_parm[bass][1]);
  514. EMU8000_INIT3_WRITE(emu, 0x11, treble_parm[treble][0]);
  515. EMU8000_INIT3_WRITE(emu, 0x13, treble_parm[treble][1]);
  516. EMU8000_INIT3_WRITE(emu, 0x1b, treble_parm[treble][2]);
  517. EMU8000_INIT4_WRITE(emu, 0x07, treble_parm[treble][3]);
  518. EMU8000_INIT4_WRITE(emu, 0x0b, treble_parm[treble][4]);
  519. EMU8000_INIT4_WRITE(emu, 0x0d, treble_parm[treble][5]);
  520. EMU8000_INIT4_WRITE(emu, 0x17, treble_parm[treble][6]);
  521. EMU8000_INIT4_WRITE(emu, 0x19, treble_parm[treble][7]);
  522. w = bass_parm[bass][2] + treble_parm[treble][8];
  523. EMU8000_INIT4_WRITE(emu, 0x15, (unsigned short)(w + 0x0262));
  524. EMU8000_INIT4_WRITE(emu, 0x1d, (unsigned short)(w + 0x8362));
  525. }
  526. /*----------------------------------------------------------------
  527. * Chorus mode control
  528. *----------------------------------------------------------------*/
  529. /*
  530. * chorus mode parameters
  531. */
  532. #define SNDRV_EMU8000_CHORUS_1 0
  533. #define SNDRV_EMU8000_CHORUS_2 1
  534. #define SNDRV_EMU8000_CHORUS_3 2
  535. #define SNDRV_EMU8000_CHORUS_4 3
  536. #define SNDRV_EMU8000_CHORUS_FEEDBACK 4
  537. #define SNDRV_EMU8000_CHORUS_FLANGER 5
  538. #define SNDRV_EMU8000_CHORUS_SHORTDELAY 6
  539. #define SNDRV_EMU8000_CHORUS_SHORTDELAY2 7
  540. #define SNDRV_EMU8000_CHORUS_PREDEFINED 8
  541. /* user can define chorus modes up to 32 */
  542. #define SNDRV_EMU8000_CHORUS_NUMBERS 32
  543. struct soundfont_chorus_fx {
  544. unsigned short feedback; /* feedback level (0xE600-0xE6FF) */
  545. unsigned short delay_offset; /* delay (0-0x0DA3) [1/44100 sec] */
  546. unsigned short lfo_depth; /* LFO depth (0xBC00-0xBCFF) */
  547. unsigned int delay; /* right delay (0-0xFFFFFFFF) [1/256/44100 sec] */
  548. unsigned int lfo_freq; /* LFO freq LFO freq (0-0xFFFFFFFF) */
  549. };
  550. /* 5 parameters for each chorus mode; 3 x 16bit, 2 x 32bit */
  551. static char chorus_defined[SNDRV_EMU8000_CHORUS_NUMBERS];
  552. static struct soundfont_chorus_fx chorus_parm[SNDRV_EMU8000_CHORUS_NUMBERS] = {
  553. {0xE600, 0x03F6, 0xBC2C ,0x00000000, 0x0000006D}, /* chorus 1 */
  554. {0xE608, 0x031A, 0xBC6E, 0x00000000, 0x0000017C}, /* chorus 2 */
  555. {0xE610, 0x031A, 0xBC84, 0x00000000, 0x00000083}, /* chorus 3 */
  556. {0xE620, 0x0269, 0xBC6E, 0x00000000, 0x0000017C}, /* chorus 4 */
  557. {0xE680, 0x04D3, 0xBCA6, 0x00000000, 0x0000005B}, /* feedback */
  558. {0xE6E0, 0x044E, 0xBC37, 0x00000000, 0x00000026}, /* flanger */
  559. {0xE600, 0x0B06, 0xBC00, 0x0006E000, 0x00000083}, /* short delay */
  560. {0xE6C0, 0x0B06, 0xBC00, 0x0006E000, 0x00000083}, /* short delay + feedback */
  561. };
  562. /*exported*/ int
  563. snd_emu8000_load_chorus_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len)
  564. {
  565. struct soundfont_chorus_fx rec;
  566. if (mode < SNDRV_EMU8000_CHORUS_PREDEFINED || mode >= SNDRV_EMU8000_CHORUS_NUMBERS) {
  567. snd_printk(KERN_WARNING "invalid chorus mode %d for uploading\n", mode);
  568. return -EINVAL;
  569. }
  570. if (len < (long)sizeof(rec) || copy_from_user(&rec, buf, sizeof(rec)))
  571. return -EFAULT;
  572. chorus_parm[mode] = rec;
  573. chorus_defined[mode] = 1;
  574. return 0;
  575. }
  576. /*exported*/ void
  577. snd_emu8000_update_chorus_mode(struct snd_emu8000 *emu)
  578. {
  579. int effect = emu->chorus_mode;
  580. if (effect < 0 || effect >= SNDRV_EMU8000_CHORUS_NUMBERS ||
  581. (effect >= SNDRV_EMU8000_CHORUS_PREDEFINED && !chorus_defined[effect]))
  582. return;
  583. EMU8000_INIT3_WRITE(emu, 0x09, chorus_parm[effect].feedback);
  584. EMU8000_INIT3_WRITE(emu, 0x0c, chorus_parm[effect].delay_offset);
  585. EMU8000_INIT4_WRITE(emu, 0x03, chorus_parm[effect].lfo_depth);
  586. EMU8000_HWCF4_WRITE(emu, chorus_parm[effect].delay);
  587. EMU8000_HWCF5_WRITE(emu, chorus_parm[effect].lfo_freq);
  588. EMU8000_HWCF6_WRITE(emu, 0x8000);
  589. EMU8000_HWCF7_WRITE(emu, 0x0000);
  590. }
  591. /*----------------------------------------------------------------
  592. * Reverb mode control
  593. *----------------------------------------------------------------*/
  594. /*
  595. * reverb mode parameters
  596. */
  597. #define SNDRV_EMU8000_REVERB_ROOM1 0
  598. #define SNDRV_EMU8000_REVERB_ROOM2 1
  599. #define SNDRV_EMU8000_REVERB_ROOM3 2
  600. #define SNDRV_EMU8000_REVERB_HALL1 3
  601. #define SNDRV_EMU8000_REVERB_HALL2 4
  602. #define SNDRV_EMU8000_REVERB_PLATE 5
  603. #define SNDRV_EMU8000_REVERB_DELAY 6
  604. #define SNDRV_EMU8000_REVERB_PANNINGDELAY 7
  605. #define SNDRV_EMU8000_REVERB_PREDEFINED 8
  606. /* user can define reverb modes up to 32 */
  607. #define SNDRV_EMU8000_REVERB_NUMBERS 32
  608. struct soundfont_reverb_fx {
  609. unsigned short parms[28];
  610. };
  611. /* reverb mode settings; write the following 28 data of 16 bit length
  612. * on the corresponding ports in the reverb_cmds array
  613. */
  614. static char reverb_defined[SNDRV_EMU8000_CHORUS_NUMBERS];
  615. static struct soundfont_reverb_fx reverb_parm[SNDRV_EMU8000_REVERB_NUMBERS] = {
  616. {{ /* room 1 */
  617. 0xB488, 0xA450, 0x9550, 0x84B5, 0x383A, 0x3EB5, 0x72F4,
  618. 0x72A4, 0x7254, 0x7204, 0x7204, 0x7204, 0x4416, 0x4516,
  619. 0xA490, 0xA590, 0x842A, 0x852A, 0x842A, 0x852A, 0x8429,
  620. 0x8529, 0x8429, 0x8529, 0x8428, 0x8528, 0x8428, 0x8528,
  621. }},
  622. {{ /* room 2 */
  623. 0xB488, 0xA458, 0x9558, 0x84B5, 0x383A, 0x3EB5, 0x7284,
  624. 0x7254, 0x7224, 0x7224, 0x7254, 0x7284, 0x4448, 0x4548,
  625. 0xA440, 0xA540, 0x842A, 0x852A, 0x842A, 0x852A, 0x8429,
  626. 0x8529, 0x8429, 0x8529, 0x8428, 0x8528, 0x8428, 0x8528,
  627. }},
  628. {{ /* room 3 */
  629. 0xB488, 0xA460, 0x9560, 0x84B5, 0x383A, 0x3EB5, 0x7284,
  630. 0x7254, 0x7224, 0x7224, 0x7254, 0x7284, 0x4416, 0x4516,
  631. 0xA490, 0xA590, 0x842C, 0x852C, 0x842C, 0x852C, 0x842B,
  632. 0x852B, 0x842B, 0x852B, 0x842A, 0x852A, 0x842A, 0x852A,
  633. }},
  634. {{ /* hall 1 */
  635. 0xB488, 0xA470, 0x9570, 0x84B5, 0x383A, 0x3EB5, 0x7284,
  636. 0x7254, 0x7224, 0x7224, 0x7254, 0x7284, 0x4448, 0x4548,
  637. 0xA440, 0xA540, 0x842B, 0x852B, 0x842B, 0x852B, 0x842A,
  638. 0x852A, 0x842A, 0x852A, 0x8429, 0x8529, 0x8429, 0x8529,
  639. }},
  640. {{ /* hall 2 */
  641. 0xB488, 0xA470, 0x9570, 0x84B5, 0x383A, 0x3EB5, 0x7254,
  642. 0x7234, 0x7224, 0x7254, 0x7264, 0x7294, 0x44C3, 0x45C3,
  643. 0xA404, 0xA504, 0x842A, 0x852A, 0x842A, 0x852A, 0x8429,
  644. 0x8529, 0x8429, 0x8529, 0x8428, 0x8528, 0x8428, 0x8528,
  645. }},
  646. {{ /* plate */
  647. 0xB4FF, 0xA470, 0x9570, 0x84B5, 0x383A, 0x3EB5, 0x7234,
  648. 0x7234, 0x7234, 0x7234, 0x7234, 0x7234, 0x4448, 0x4548,
  649. 0xA440, 0xA540, 0x842A, 0x852A, 0x842A, 0x852A, 0x8429,
  650. 0x8529, 0x8429, 0x8529, 0x8428, 0x8528, 0x8428, 0x8528,
  651. }},
  652. {{ /* delay */
  653. 0xB4FF, 0xA470, 0x9500, 0x84B5, 0x333A, 0x39B5, 0x7204,
  654. 0x7204, 0x7204, 0x7204, 0x7204, 0x72F4, 0x4400, 0x4500,
  655. 0xA4FF, 0xA5FF, 0x8420, 0x8520, 0x8420, 0x8520, 0x8420,
  656. 0x8520, 0x8420, 0x8520, 0x8420, 0x8520, 0x8420, 0x8520,
  657. }},
  658. {{ /* panning delay */
  659. 0xB4FF, 0xA490, 0x9590, 0x8474, 0x333A, 0x39B5, 0x7204,
  660. 0x7204, 0x7204, 0x7204, 0x7204, 0x72F4, 0x4400, 0x4500,
  661. 0xA4FF, 0xA5FF, 0x8420, 0x8520, 0x8420, 0x8520, 0x8420,
  662. 0x8520, 0x8420, 0x8520, 0x8420, 0x8520, 0x8420, 0x8520,
  663. }},
  664. };
  665. enum { DATA1, DATA2 };
  666. #define AWE_INIT1(c) EMU8000_CMD(2,c), DATA1
  667. #define AWE_INIT2(c) EMU8000_CMD(2,c), DATA2
  668. #define AWE_INIT3(c) EMU8000_CMD(3,c), DATA1
  669. #define AWE_INIT4(c) EMU8000_CMD(3,c), DATA2
  670. static struct reverb_cmd_pair {
  671. unsigned short cmd, port;
  672. } reverb_cmds[28] = {
  673. {AWE_INIT1(0x03)}, {AWE_INIT1(0x05)}, {AWE_INIT4(0x1F)}, {AWE_INIT1(0x07)},
  674. {AWE_INIT2(0x14)}, {AWE_INIT2(0x16)}, {AWE_INIT1(0x0F)}, {AWE_INIT1(0x17)},
  675. {AWE_INIT1(0x1F)}, {AWE_INIT2(0x07)}, {AWE_INIT2(0x0F)}, {AWE_INIT2(0x17)},
  676. {AWE_INIT2(0x1D)}, {AWE_INIT2(0x1F)}, {AWE_INIT3(0x01)}, {AWE_INIT3(0x03)},
  677. {AWE_INIT1(0x09)}, {AWE_INIT1(0x0B)}, {AWE_INIT1(0x11)}, {AWE_INIT1(0x13)},
  678. {AWE_INIT1(0x19)}, {AWE_INIT1(0x1B)}, {AWE_INIT2(0x01)}, {AWE_INIT2(0x03)},
  679. {AWE_INIT2(0x09)}, {AWE_INIT2(0x0B)}, {AWE_INIT2(0x11)}, {AWE_INIT2(0x13)},
  680. };
  681. /*exported*/ int
  682. snd_emu8000_load_reverb_fx(struct snd_emu8000 *emu, int mode, const void __user *buf, long len)
  683. {
  684. struct soundfont_reverb_fx rec;
  685. if (mode < SNDRV_EMU8000_REVERB_PREDEFINED || mode >= SNDRV_EMU8000_REVERB_NUMBERS) {
  686. snd_printk(KERN_WARNING "invalid reverb mode %d for uploading\n", mode);
  687. return -EINVAL;
  688. }
  689. if (len < (long)sizeof(rec) || copy_from_user(&rec, buf, sizeof(rec)))
  690. return -EFAULT;
  691. reverb_parm[mode] = rec;
  692. reverb_defined[mode] = 1;
  693. return 0;
  694. }
  695. /*exported*/ void
  696. snd_emu8000_update_reverb_mode(struct snd_emu8000 *emu)
  697. {
  698. int effect = emu->reverb_mode;
  699. int i;
  700. if (effect < 0 || effect >= SNDRV_EMU8000_REVERB_NUMBERS ||
  701. (effect >= SNDRV_EMU8000_REVERB_PREDEFINED && !reverb_defined[effect]))
  702. return;
  703. for (i = 0; i < 28; i++) {
  704. int port;
  705. if (reverb_cmds[i].port == DATA1)
  706. port = EMU8000_DATA1(emu);
  707. else
  708. port = EMU8000_DATA2(emu);
  709. snd_emu8000_poke(emu, port, reverb_cmds[i].cmd, reverb_parm[effect].parms[i]);
  710. }
  711. }
  712. /*----------------------------------------------------------------
  713. * mixer interface
  714. *----------------------------------------------------------------*/
  715. /*
  716. * bass/treble
  717. */
  718. static int mixer_bass_treble_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  719. {
  720. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  721. uinfo->count = 1;
  722. uinfo->value.integer.min = 0;
  723. uinfo->value.integer.max = 11;
  724. return 0;
  725. }
  726. static int mixer_bass_treble_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  727. {
  728. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  729. ucontrol->value.integer.value[0] = kcontrol->private_value ? emu->treble_level : emu->bass_level;
  730. return 0;
  731. }
  732. static int mixer_bass_treble_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  733. {
  734. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  735. unsigned long flags;
  736. int change;
  737. unsigned short val1;
  738. val1 = ucontrol->value.integer.value[0] % 12;
  739. spin_lock_irqsave(&emu->control_lock, flags);
  740. if (kcontrol->private_value) {
  741. change = val1 != emu->treble_level;
  742. emu->treble_level = val1;
  743. } else {
  744. change = val1 != emu->bass_level;
  745. emu->bass_level = val1;
  746. }
  747. spin_unlock_irqrestore(&emu->control_lock, flags);
  748. snd_emu8000_update_equalizer(emu);
  749. return change;
  750. }
  751. static struct snd_kcontrol_new mixer_bass_control =
  752. {
  753. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  754. .name = "Synth Tone Control - Bass",
  755. .info = mixer_bass_treble_info,
  756. .get = mixer_bass_treble_get,
  757. .put = mixer_bass_treble_put,
  758. .private_value = 0,
  759. };
  760. static struct snd_kcontrol_new mixer_treble_control =
  761. {
  762. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  763. .name = "Synth Tone Control - Treble",
  764. .info = mixer_bass_treble_info,
  765. .get = mixer_bass_treble_get,
  766. .put = mixer_bass_treble_put,
  767. .private_value = 1,
  768. };
  769. /*
  770. * chorus/reverb mode
  771. */
  772. static int mixer_chorus_reverb_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  773. {
  774. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  775. uinfo->count = 1;
  776. uinfo->value.integer.min = 0;
  777. uinfo->value.integer.max = kcontrol->private_value ? (SNDRV_EMU8000_CHORUS_NUMBERS-1) : (SNDRV_EMU8000_REVERB_NUMBERS-1);
  778. return 0;
  779. }
  780. static int mixer_chorus_reverb_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  781. {
  782. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  783. ucontrol->value.integer.value[0] = kcontrol->private_value ? emu->chorus_mode : emu->reverb_mode;
  784. return 0;
  785. }
  786. static int mixer_chorus_reverb_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  787. {
  788. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  789. unsigned long flags;
  790. int change;
  791. unsigned short val1;
  792. spin_lock_irqsave(&emu->control_lock, flags);
  793. if (kcontrol->private_value) {
  794. val1 = ucontrol->value.integer.value[0] % SNDRV_EMU8000_CHORUS_NUMBERS;
  795. change = val1 != emu->chorus_mode;
  796. emu->chorus_mode = val1;
  797. } else {
  798. val1 = ucontrol->value.integer.value[0] % SNDRV_EMU8000_REVERB_NUMBERS;
  799. change = val1 != emu->reverb_mode;
  800. emu->reverb_mode = val1;
  801. }
  802. spin_unlock_irqrestore(&emu->control_lock, flags);
  803. if (change) {
  804. if (kcontrol->private_value)
  805. snd_emu8000_update_chorus_mode(emu);
  806. else
  807. snd_emu8000_update_reverb_mode(emu);
  808. }
  809. return change;
  810. }
  811. static struct snd_kcontrol_new mixer_chorus_mode_control =
  812. {
  813. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  814. .name = "Chorus Mode",
  815. .info = mixer_chorus_reverb_info,
  816. .get = mixer_chorus_reverb_get,
  817. .put = mixer_chorus_reverb_put,
  818. .private_value = 1,
  819. };
  820. static struct snd_kcontrol_new mixer_reverb_mode_control =
  821. {
  822. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  823. .name = "Reverb Mode",
  824. .info = mixer_chorus_reverb_info,
  825. .get = mixer_chorus_reverb_get,
  826. .put = mixer_chorus_reverb_put,
  827. .private_value = 0,
  828. };
  829. /*
  830. * FM OPL3 chorus/reverb depth
  831. */
  832. static int mixer_fm_depth_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
  833. {
  834. uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
  835. uinfo->count = 1;
  836. uinfo->value.integer.min = 0;
  837. uinfo->value.integer.max = 255;
  838. return 0;
  839. }
  840. static int mixer_fm_depth_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  841. {
  842. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  843. ucontrol->value.integer.value[0] = kcontrol->private_value ? emu->fm_chorus_depth : emu->fm_reverb_depth;
  844. return 0;
  845. }
  846. static int mixer_fm_depth_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
  847. {
  848. struct snd_emu8000 *emu = snd_kcontrol_chip(kcontrol);
  849. unsigned long flags;
  850. int change;
  851. unsigned short val1;
  852. val1 = ucontrol->value.integer.value[0] % 256;
  853. spin_lock_irqsave(&emu->control_lock, flags);
  854. if (kcontrol->private_value) {
  855. change = val1 != emu->fm_chorus_depth;
  856. emu->fm_chorus_depth = val1;
  857. } else {
  858. change = val1 != emu->fm_reverb_depth;
  859. emu->fm_reverb_depth = val1;
  860. }
  861. spin_unlock_irqrestore(&emu->control_lock, flags);
  862. if (change)
  863. snd_emu8000_init_fm(emu);
  864. return change;
  865. }
  866. static struct snd_kcontrol_new mixer_fm_chorus_depth_control =
  867. {
  868. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  869. .name = "FM Chorus Depth",
  870. .info = mixer_fm_depth_info,
  871. .get = mixer_fm_depth_get,
  872. .put = mixer_fm_depth_put,
  873. .private_value = 1,
  874. };
  875. static struct snd_kcontrol_new mixer_fm_reverb_depth_control =
  876. {
  877. .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
  878. .name = "FM Reverb Depth",
  879. .info = mixer_fm_depth_info,
  880. .get = mixer_fm_depth_get,
  881. .put = mixer_fm_depth_put,
  882. .private_value = 0,
  883. };
  884. static struct snd_kcontrol_new *mixer_defs[EMU8000_NUM_CONTROLS] = {
  885. &mixer_bass_control,
  886. &mixer_treble_control,
  887. &mixer_chorus_mode_control,
  888. &mixer_reverb_mode_control,
  889. &mixer_fm_chorus_depth_control,
  890. &mixer_fm_reverb_depth_control,
  891. };
  892. /*
  893. * create and attach mixer elements for WaveTable treble/bass controls
  894. */
  895. static int __devinit
  896. snd_emu8000_create_mixer(struct snd_card *card, struct snd_emu8000 *emu)
  897. {
  898. int i, err = 0;
  899. snd_assert(emu != NULL && card != NULL, return -EINVAL);
  900. spin_lock_init(&emu->control_lock);
  901. memset(emu->controls, 0, sizeof(emu->controls));
  902. for (i = 0; i < EMU8000_NUM_CONTROLS; i++) {
  903. if ((err = snd_ctl_add(card, emu->controls[i] = snd_ctl_new1(mixer_defs[i], emu))) < 0)
  904. goto __error;
  905. }
  906. return 0;
  907. __error:
  908. for (i = 0; i < EMU8000_NUM_CONTROLS; i++) {
  909. down_write(&card->controls_rwsem);
  910. if (emu->controls[i])
  911. snd_ctl_remove(card, emu->controls[i]);
  912. up_write(&card->controls_rwsem);
  913. }
  914. return err;
  915. }
  916. /*
  917. * free resources
  918. */
  919. static int snd_emu8000_free(struct snd_emu8000 *hw)
  920. {
  921. release_and_free_resource(hw->res_port1);
  922. release_and_free_resource(hw->res_port2);
  923. release_and_free_resource(hw->res_port3);
  924. kfree(hw);
  925. return 0;
  926. }
  927. /*
  928. */
  929. static int snd_emu8000_dev_free(struct snd_device *device)
  930. {
  931. struct snd_emu8000 *hw = device->device_data;
  932. return snd_emu8000_free(hw);
  933. }
  934. /*
  935. * initialize and register emu8000 synth device.
  936. */
  937. int __devinit
  938. snd_emu8000_new(struct snd_card *card, int index, long port, int seq_ports,
  939. struct snd_seq_device **awe_ret)
  940. {
  941. struct snd_seq_device *awe;
  942. struct snd_emu8000 *hw;
  943. int err;
  944. static struct snd_device_ops ops = {
  945. .dev_free = snd_emu8000_dev_free,
  946. };
  947. if (awe_ret)
  948. *awe_ret = NULL;
  949. if (seq_ports <= 0)
  950. return 0;
  951. hw = kzalloc(sizeof(*hw), GFP_KERNEL);
  952. if (hw == NULL)
  953. return -ENOMEM;
  954. spin_lock_init(&hw->reg_lock);
  955. hw->index = index;
  956. hw->port1 = port;
  957. hw->port2 = port + 0x400;
  958. hw->port3 = port + 0x800;
  959. if (!(hw->res_port1 = request_region(hw->port1, 4, "Emu8000-1")) ||
  960. !(hw->res_port2 = request_region(hw->port2, 4, "Emu8000-2")) ||
  961. !(hw->res_port3 = request_region(hw->port3, 4, "Emu8000-3"))) {
  962. snd_printk(KERN_ERR "sbawe: can't grab ports 0x%lx, 0x%lx, 0x%lx\n", hw->port1, hw->port2, hw->port3);
  963. snd_emu8000_free(hw);
  964. return -EBUSY;
  965. }
  966. hw->mem_size = 0;
  967. hw->card = card;
  968. hw->seq_ports = seq_ports;
  969. hw->bass_level = 5;
  970. hw->treble_level = 9;
  971. hw->chorus_mode = 2;
  972. hw->reverb_mode = 4;
  973. hw->fm_chorus_depth = 0;
  974. hw->fm_reverb_depth = 0;
  975. if (snd_emu8000_detect(hw) < 0) {
  976. snd_emu8000_free(hw);
  977. return -ENODEV;
  978. }
  979. snd_emu8000_init_hw(hw);
  980. if ((err = snd_emu8000_create_mixer(card, hw)) < 0) {
  981. snd_emu8000_free(hw);
  982. return err;
  983. }
  984. if ((err = snd_device_new(card, SNDRV_DEV_CODEC, hw, &ops)) < 0) {
  985. snd_emu8000_free(hw);
  986. return err;
  987. }
  988. #if defined(CONFIG_SND_SEQUENCER) || (defined(MODULE) && defined(CONFIG_SND_SEQUENCER_MODULE))
  989. if (snd_seq_device_new(card, index, SNDRV_SEQ_DEV_ID_EMU8000,
  990. sizeof(struct snd_emu8000*), &awe) >= 0) {
  991. strcpy(awe->name, "EMU-8000");
  992. *(struct snd_emu8000 **)SNDRV_SEQ_DEVICE_ARGPTR(awe) = hw;
  993. }
  994. #else
  995. awe = NULL;
  996. #endif
  997. if (awe_ret)
  998. *awe_ret = awe;
  999. return 0;
  1000. }
  1001. /*
  1002. * exported stuff
  1003. */
  1004. EXPORT_SYMBOL(snd_emu8000_poke);
  1005. EXPORT_SYMBOL(snd_emu8000_peek);
  1006. EXPORT_SYMBOL(snd_emu8000_poke_dw);
  1007. EXPORT_SYMBOL(snd_emu8000_peek_dw);
  1008. EXPORT_SYMBOL(snd_emu8000_dma_chan);
  1009. EXPORT_SYMBOL(snd_emu8000_init_fm);
  1010. EXPORT_SYMBOL(snd_emu8000_load_chorus_fx);
  1011. EXPORT_SYMBOL(snd_emu8000_load_reverb_fx);
  1012. EXPORT_SYMBOL(snd_emu8000_update_chorus_mode);
  1013. EXPORT_SYMBOL(snd_emu8000_update_reverb_mode);
  1014. EXPORT_SYMBOL(snd_emu8000_update_equalizer);